Int. J. Electron. Commun.

(AEÜ) 122 (2020) 153243

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International Journal of Electronics and

Communications (AEÜ)
journal homepage: www.elsevier.com/locate/aeue

Regular paper

Analog and RF performance evaluation of negative capacitance SOI

junctionless transistor
Sandeep Moparthi a, Adarsh K.P. a, Pramod Kumar Tiwari b, Gopi Krishna Saramekala a,⇑
a
Department of Electronics and Communication Engineering, National Institute of Technology, Calicut, Kerala 673601, India
b
Department of Electrical Engineering, Indian Institute of Technology Patna, Bihar 801103, India

a r t i c l e i n f o a b s t r a c t

Article history: In this work, for the first time, the DC characteristics and Analog/RF performance of negative capacitance
Received 8 March 2020 (NC) Silicon-on-insulator (SOI) junctionless transistor (JLT) have been investigated including quantum
Accepted 3 May 2020 confinement effects. In NC transistors, ferroelectric materials are used in the gate-stack to improve the
switching characteristics. The Metal-Ferroelectric-Metal-Insulator-semiconductor (MFMIS) gate-stack
structure has been simulated with the help of 1D Landau Khalatnikov (LK) equation to incorporate the
Keywords: effect of negative capacitance with SOI JLT. The impact of varying the temperatures in the range 300–
Negative capacitance (NC)
380 K and ferroelectric layer thickness (t f ) of 0 to 4.5 nm on the device characteristics are studied. The
Silicon-on-insulator (SOI)
Junctionless transistor (JLT)
analog and RF characteristics such as transconductance (g m ) and cut-off frequency (f t ) of NC SOI JLT show
Metal-ferroelectric-metal–insulator-semi better performance over SOI JLT. A minimum subthreshold swing (SS) of 12.77 mV/decade and f t of
conductor (MFMIS) 590 GHz has been observed at 300 K for a channel length (L) of 14 nm with t f of 4.5 nm. The character-
Subthreshold swing (SS) istics of NC SOI JLT are evaluated by coupling the 1D LK equation with the simulated results of SOI JLT
which are obtained using 2D device simulator AtlasTM from Silvaco.
Ó 2020 Elsevier GmbH. All rights reserved.

1. Introduction duce sub-60 mV/decade with distinct carrier transport phenomena

called tunneling and avalanche multiplication, respectively [4].
Moore’s law on transistor packing density is struggling for its Although T-FET can deliver a sub-60 mV/decade SS, it suffers from
existence as the miniaturization of the device introduces poor drive current. On the other hand, despite sub-60 mV/decade
challenges regarding the performance of transistors such as high behavior, I-MOS has its limitations in channel shrinking to establish
leakage currents, high dynamic power dissipation and other avalanche multiplication within it. NEM FET [4] and NC FET are the
short-channel effects (SCEs) [1,2]. As the current state-of-the-art two other inventions in this line that come with the change in
applications are mostly backed by the battery; power dissipation device physics. NEMFET is not the preferred choice in many appli-
and leakage currents play a vital role in the performance of the cations due to its movable gate. Further, the germanene nanoribbon
device. Supply voltage scale-down is the key to suppress these SCEs field-effect transistor (GeNR-FET) is proposed in the literature to
and thereby the realization of low power devices. Though the scale attain better ION/IOFF ratio and improved analog performance by
down of supply voltage minimizes the power dissipation, Boltz- altering the bandgap of GeNR at different regions of the device [5]
mann’s limitation (SS of 60mv/decade) imposes a serious limitation and using uniaxial compressive strain[6].
on the further scale down. Researchers made rigorous efforts to NC FET is found to be a feasible option and considered in this
break this Boltzmann’s limit and succeeded with the invention of study among all due to ease of adaptability and structural similar-
new devices [2,3]. These efforts pave the path for the realization ity with conventional MOSFET [3,7]. The principle behind the
of low power devices with sub-60 mV/decade swing and ease the working of NCFET comes from the negative capacitance offered
challenges in further miniaturization of the device. Change in car- by ferroelectric material [7]. Ferroelectric exhibits spontaneous
rier transport and device physics are the two distinct concepts polarization under no electric field and alters its polarization under
involved in the above-said inventions. Tunnel FET (T-FET) and the influence of the electric field. During its phase transition, ferro-
Impact ionization FET (I-MOS) are two innovative devices that pro- electric offers negative capacitance nature which is the key princi-
ple involved in NCFET operation. It is required to stabilize the
negative capacitance property which is observed in the unstable
⇑ Corresponding author. state of ferroelectric by placing a positive capacitor in series with
E-mail address: [email protected] (G. Krishna Saramekala).

https://doi.org/10.1016/j.aeue.2020.153243
1434-8411/Ó 2020 Elsevier GmbH. All rights reserved.
2 S. Moparthi et al. / Int. J. Electron. Commun. (AEÜ) 122 (2020) 153243

a ferroelectric capacitor [3,8]. NC FET can be formed by placing a

ferroelectric negative capacitor within the gate stack of the con-
ventional MOSFET. The series network of underlying positive
MOS capacitance and ferroelectric negative capacitor results in
an effective gate capacitance which is larger than conventional
gate capacitance. This increase in gate capacitance, in turn
amplifies the surface potential of the MOSFET which produces
sub-60 mV/decade performance [8]. The concept of NC was
demonstrated and analyzed on many of the existing structures
[9–12]. Apart from NC FET which uses ferroelectric as a gate insu-
lator, a transistor with a ferromagnetic topological insulator as a
channel is proposed in the literature that offers a better ION/IOFF
ratio and negative differential conductance with a good peak to
valley ratio [13,14]. Among many ferroelectric materials found in
the literature, doped-HfO2 stands unique in the list as it is MOS
fabrication friendly [15]. Doped-HfO2 offers better controllability
of ferroelectric nature by its doping. With this motivation,
doped-HfO2 is opted as ferroelectric in this work.
With an emphasis on the lower short channel effects and para-
sitic capacitance reduction in short channel devices, SOI technol-
ogy was introduced [16,17]. To enhance the SS and ION/IOFF ratio
of the SOI device, a novel structure was reported with retrograde Fig. 1. NC SOI JLT device structure.
channel doping and placing a strip of graphene at the source side
of the channel [18]. Furthermore, as the size of the transistor
can be done by doping silicon with noble impurities such as
shrinks and reaches nanometer regime, the making of different
platinum and gold [22]. Ls and Lsd are the spacing between
doping regions becomes extremely difficult due to random doping
gate-source/drain electrodes and source/drain electrode length,
fluctuations. These random changes in doping cause larger vari-
respectively. Ls is a key parameter that influences the dynamic per-
ability in characteristics between adjacent transistors. As a general
formance of SOI JLT. Though minimum Ls certainly enhance the ON
solution to this problem, JLT was introduced [19]. Unlike conven-
current due to better tunneling efficiency, it deteriorates the OFF
tional depletion MOSFET, a JLT has a single type doped channel that
current and switching speed of the device because of high coupling
extent from source to drain electrodes. This avoids the necessity of
and parasitic capacitances [23,24]. An optimum Ls of 8 nm between
abrupt doped junctions at the source/drain to channel junctions at
gate and source/drain electrodes is considered in this study to
smaller dimensions. The JLT has been tried for many combinations
make a trade-off among important device parameters ION/IOFF ratio
like multi-gate and nanowire gate all around (GAA) structures
and subthreshold swing (SS). Moreover, Lsd is chosen as 12 nm.
[20,21]. But fabrication aspects of such combinations are still com-
However, the impact of Lsd on the device characteristics is negligi-
plex and expensive as compare to normal JLT structure even
ble on the considered device structure.
though JLT is considered to be an effective solution for doping
Further, to verify the accuracy of simulation models, SOI JLT is
irregularities in short channel devices. To grab the advantages of
calibrated with ref.[22] as shown in Fig. 2(a). The drain current
JLT and SOI structures and to attain the extent possible optimum
(Id ) versus gate voltage (V G ) is plotted using BTBT model with
subthreshold performance, this paper carried out an extensive
and without increased SRH recombination rate. It is seen that the
analysis of NC SOI JLT by incorporating quantum confinement
suppressed carrier recombination lifetime (10–15 s) greatly
effects. This structure can be a promising candidate for the current
improved the ON-OFF current ratio due to the increased SRH
short-channel and low-power era. Hence, in this work, the effect of
recombination rate. Hence, in this paper, a suppressed carrier
negative capacitance and the impact of temperature variations on
recombination lifetime of 10–15 s is considered for the entire anal-
NC SOI JLT have been studied at different temperatures and ferro-
ysis to ensure the improved ION/IOFF ratio. The various device
electric thicknesses.
parameters used in this analysis are shown in Table.1.
As per the literature, it is clear that the direct simulation of fer-
roelectric negative capacitance FET is not possible in any of the
2. Device structure and simulation model
state-of-the-art TCAD tools [25]. Hence the effect of negative
capacitance was solved by coupling 1D LK equation (1) with the
The cross-sectional view of an NC SOI JLT is shown in Fig. 1. The
simulation of underlying SOI JLT (excluding NC) [25]. In a ferroelec-
nonlocal band to band tunneling model, bandgap narrowing model
tric capacitor, the relation between the voltage across the ferro-
along with field-dependent mobility, concentration-dependent
electric (V f ) and charge density (Q) is given by LK equation as,
mobility, Shockley-Read-Hall (SRH) recombination, and auger
recombination models are used for simulations. The quantum V f ¼ 2atf Q þ 4bt f Q 3 þ 6ct f Q 5 ð1Þ
model is used to capture the confinement effects in the ultra-
thin channel region by solving the Schrodinger equation along with where, a ¼ a0 ðT  T c Þ. a0 , b and c are the ferroelectric parameters of
the Poisson equation. With the help of a nonlocal band to band Al-doped HfO2 as given in [12]. T C is the ferroelectric Curie temper-
tunneling model, the effect of tunneling current due to BJT action ature, which causes phase transformation in ferroelectric. It is seen
was taken into account for improved simulation accuracy as from eq. (1) that the NC of ferroelectric is temperature-dependent.
demonstrated by S. Gundapaneni et.al [22]. Since, OFF-state leak- NC property of ferroelectric weakens as it approaches T C and the NC
age due to band to band tunneling has a significant impact on property disappears as and when the material reaches T C [26]. In
the ION/IOFF of JLT, careful selection of device parameters such as this study, T C of 450 °C is considered from [15] which is for Al-
channel doping, channel thickness, drain voltage and optimization doped HfO2.
of carrier recombination lifetime need to be done to improve the The 1D LK equation (1) is coupled with underlying SOI JLT by
ION/IOFF ratio [22]. Optimization of carrier recombination lifetime replacing charge density (Q) of (1) with total gate charge density
 S. Moparthi et al. / Int. J. Electron. Commun. (AEÜ) 122 (2020) 153243 3

SOI JLT amplifies the gate voltage which produces amplified gate
voltage (V 0G ), which leads to higher drain current (Id ) at applied
gate voltage (V G ). This paves the path for low power design with
sub-60 mV/decade swing. The transfer characteristics of NC SOI
JLT are obtained by simulating SOI JLT with amplified gate voltage
(V 0G ). Silvaco AtlasTM 2D TCAD simulator [27] is used for the simu-
lation of the structure (SOI JLT) for extracting gate charge and drain
current (Id ). Metal-Ferroelectric-Metal-Insulator-semiconductor
(MFMIS) structure is taken here in which a suspended metal layer
is placed between ferroelectric and oxide layers. Intermediate
metal allows the independent study of SOI JLT and NC, by creating
a uniform distribution of potential between them [28,29]. More-
over, to verify the accuracy of the simulation procedure of the neg-
ative capacitance concept, a double gate (DG) NC FET from ref.[30]
is calibrated and the results are shown in Fig. 2(b). A very good
match between simulated and reference characteristics are
observed. Hence, by following the same simulation approach, for
the first time, a detailed analysis of temperature effect on NC SOI
JLT has been studied including quantum confinement effects.

3. Results and discussion

This section discusses the results obtained for NC SOI JLT

including quantum confinement effects. The DC and analog/RF
characteristics of the considered device are studied and compared
at 300 K, 340 K, and 380 K. With the inclusion of ferroelectric neg-
ative capacitance in gate stack, SOI JLT achieved a gate voltage
amplification (Av) of greater than unity which is shown in Fig. 3.
With a tf of 4.5 nm, the device has delivered an Av of 1.34 which
is significantly higher than the conventional SOI JLT. Fig. 4(a)
shows the effect of ferroelectric thickness variation on ferroelectric
charge and voltage characteristics. The negative slope in the char-
acteristics is a sign of NC which is varying withtf . It is also seen that
voltage across ferroelectric (V f ) is proportional to tf . As higher fer-
roelectric thickness leads to hysteresis [8], the maximum ferroelec-
tric thickness of 4.5 nm is used in the entire analysis to ensure
hysteresis free operation of the device. The variation of ferroelec-
tric charge with ferroelectric voltage for different temperatures is
depicted in Fig. 4(b). As the operating temperature of ferroelectric
increases, the magnitude of negative capacitance is found to dete-
riorate. This is due to the fact that the ferroelectric reaches its curie
point with a raise in temperature beyond which, the material no
longer exhibits negative capacitance nature [31].
Fig. 2. Calibration (a) SOI JLT, (b) NC effect using MFMIS on DG FET.

Table 1
Device parameters.

Parameters Values
Silicon channel thickness (t Si ) 5 nm
Gate oxide thickness (tox ) 1 nm
Buried oxide thickness (t box ) 50 nm
Channel length (L) 14 nm
Spacing between Gate - source/drain electrodes (Ls) 8 nm
Source/drain electrode length (Lsd) 12 nm
Gate workfunction (/M ) 5.1 eV
Channel doping (N d ) 0.5x1019 cm3
Substrate doping (N a ) 5  1018 cm3
Ferroelectric thickness (t f ) 0–4.5 nm
Drain voltage (V D ) 0.5 V
Gate voltage (V G ) 0.5 to 1.2 V
Temperature (T) 300 K – 380 K

(Qg) of underlying SOI JLT structure, which is extracted from TCAD

simulation. This is because the ferroelectric negative capacitor and
underlying MOS capacitor carry the same charge as they are in ser-
ies. The voltage induced by the ferroelectric capacitor (V f ) in NC Fig. 3. Gate voltage amplification of NC SOI JLT.
4 S. Moparthi et al. / Int. J. Electron. Commun. (AEÜ) 122 (2020) 153243

Fig. 4. (b) Change in ferroelectric charge density versus voltage with (a) ferroelec-
tric thickness, (b) Temperature.

The current–voltage transfer characteristics of the proposed

device were depicted in Fig. 5 (a), (b) and (c) at different tempera-
tures 300 K, 340 K, and 380 K respectively. It is observed that when
the tf increases, the device offers better subthreshold performance
owing to improved capacitance matching between NC and under-
lying MOS capacitance. The proposed device brings an improve-
ment in ION/IOFF by improvement in ON current at a range of
temperatures as demonstrated. A detailed discussion about ION/IOFF
variations is depicted in the description of Fig. 8. A notable
improvement in subthreshold swing and drive current of the
device is observed at high temperatures with NC effect.
Fig. 6 (a), (b), and (c) analyses the variation in SS with drain cur- Fig. 5. Transfer characteristics of SOI JLT and NC SOI JLT at (a)300 K, (b)340 K, (c)
rent at 300 K, 340 K, and 380 K, respectively. As shown in figures, 380 K.

there is a measurable improvement in the subthreshold perfor-

mance of the device with negative capacitance at any given tem- making SS of the device better at high temperatures. The device
perature. It is depicted that the negative capacitance effect delivers an excellent minimum SS of 12.77 mV/decade at 300 K.
 S. Moparthi et al. / Int. J. Electron. Commun. (AEÜ) 122 (2020) 153243 5

The device managed to get a minimum SS of 77.32 mV/decade ever, these values give a measurable improvement in the perfor-
and 92.75 mV/decade at 340 K and 380 K, respectively with a mance of the device at such a shorter channel length of 14 nm
t f of 4.5 nm despite the deterioration in negative capacitance. How- under the high-temperature regime.
Fig. 7 illustrates the variation in the minimum SS of the device
with varying t f at a given temperature range. It is noticed that at
higher tf , the device offers enhanced subthreshold performance
with betterment in the minimum SS. The Boltzmann’s limit of
60 mV/decade which limits the performance of conventional MOS-
FETs is indicated by the cut-line as shown in Fig. 7. It is seen from
the figure that the conventional SOI JLT (tf =0nm) delivered a min-
imum SS which is distant from 60 mV/decade at any given temper-
ature. At 300 K, the conventional SOI JLT offered a minimum SS
of ~ 90 mV/decade which is far above Boltzmann’s limit. However,
the proposed NC SOI JLT delivered a better minimum SS than SOI
JLT at any given temperature. It is also observed that with tf above
1.5 nm, the proposed device surpasses Boltzmann’s limit and deliv-
ered sub-60 mV/decade subthreshold performance. The minimum

120

Minimum subthreshold swing (mV/decade)

100

80

60

60 mV/decade cut-line
40
T=300K
T=340K
20 T=380K

0
0 0.5 1 1.5 2 2.5 3 3.5 4 4.5
Ferroelectric thickness, tf (nm)

Fig. 7. Effect of ferroelectric thickness on minimum subthreshold swing.

7
10

T=300K
6 VG (OFF) = -0.05V T=340K
10 VG (ON) = 0.8V T=380K
VD =0.5V
ION/IOFF

5
10

104 4 4.5
0 0.5 1 1.5 2 2.5 3 3.5
Ferroelectric thickness, tf (nm)
Fig. 6. Change in subthreshold swing versus drain current at (a)300 K, (b)340 K, (c)
380 K. Fig. 8. Variation of ION/ IOFF with ferroelectric thickness.
6 S. Moparthi et al. / Int. J. Electron. Commun. (AEÜ) 122 (2020) 153243

SS of NC SOI JLT is becoming much better with an increase in t f due

to improvement in capacitance matching between ferroelectric
negative capacitance and underlying MOS capacitance as tf
increases. However, tf is limited to below hysteresis operation of
the device. Though the performance of NC degrades with an
increase in temperature, comparatively better performance was
offered by the NC devices than its counterpart conventional SOI
JLT for all the temperatures.
Fig. 8 represents the variation in the figure of merit ION/IOFF with
the tf at given temperatures. The ON and OFF currents are taken at
gate voltages of 0.8 V and 0.05 V, respectively. Interestingly, there
is a significant improvement in ION/IOFF of the proposed device even
at higher temperatures with an increase in t f as observed. The ION/
IOFF of 5.36x106 is obtained for the t f of 4.5 nm at 300 K which is a
significant value for junctionless SOI devices. This feature makes
the device most promising for switching and low power applica-

Fig. 9. Variation in gate capacitance for (a) SOI JLT and (b) NC SOI JLT.

Fig. 11. Change in cut-off frequency versus (a) drain current and (b) ferroelectric
Fig. 10. Variation of transconductance with drain current. thickness.
 S. Moparthi et al. / Int. J. Electron. Commun. (AEÜ) 122 (2020) 153243 7

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