Majority Encoder with 3 inputs
module Majority_Circuit (output F, input x,y,z);
wire w1,w2,w3;
and Gl(w1,x,y); and G2 (w2,y,z);
and G3 (w3,z,x);
or G4 (F,w1,w2,w3);
endmodule
Test bench:-
module Majority_Circuit_tb;
// Inputs
reg x;
reg y:
reg z;
// Outputs
wire F;
Majority_Circuit M(F,x,y,z);
initial
begin
x = 1'b0; y = 1'b0; z = 1'b0;
repeat (7)
#100 x = x+1'bl; y = y+l'bl; z = z+l'bl;
end
endmodule
4:1 MUX (19/08/2024)
module mux41(I,S,Y);
input[0:3]I;
input[0:1]S;
output reg Y;
always @ (I or S)
begin
case(S)
2'b00:Y=I[0];
2'b01:Y=I[1];
2'b10:Y=I[2];
2'b11:Y=I[3];
endcase
end
endmodule
Testbench:-
module mux41_tb;
reg [0:3]I;
reg [0:1]S;
wire Y;
mux41 m1(I,S,Y);
initial
begin
I[0:3]=0111;
S[0:1]=10;
#5
I[0:3]=1000;
S[0:1]=01;
#4
I[0:3]=1100;
S[0:1]=01;
#3
I[0:3]=1111;
S[0:1]=00;
end
endmodule
Fulladder(21-8-2024)
module fulladd(a,b,cin,sum,cout);
input a,b,cin;
output sum,cout;
reg sum,cout;
initial
begin
assign sum=a^b^cin;
assign cout =(a&b)|(b&cin)|(a&cin);
end
endmodule
Test bench:-
module fulladd_tb;
reg a,b,cin;
wire sum,cout;
fulladd f1(a,b,cin,sum,cout);
initial begin
a=0;b=0;cin=0;
#2
a=0;b=0;cin=1;
#3
a=0;b=1;cin=1;
#4
a=1;b=1;cin=1;
end
endmodule
Half Adder (23-8-2024)
module hal(a,b,s,c);
input a,b;
output s,c;
xor1 x1(a,b,s);
and1 a1(a,b,c);
endmodule
module xor1(a,b,y);
input a,b;
output y;
assign y=(~a&b)|(a&~b);
endmodule
module and1(a,b,y);
input a,b;
output y;
assign y=a&b;
endmodule
Testbench:-
module hal_tb;
reg a,b;
wire s,c;
hal h1(a,b,s,c);
initial
begin
a=0;b=0;
#2
a=0;b=1;#3
a=1;b=1;
end
endmodule
8:1 Mux(30-8-2024)
module mux81(ip,sel,op);
input [0:7]ip;
input [2:0]sel;
wire w1,w2;
output op;
mux41 ml(ip[0:3],sel[1:0],wl);
mux41 m2(ip[4:7],sel[1:0],w2);
mux21 m3(wl,w2,sel[2],op);
endmodule
module mux21(ip[0],ip[1],sel,op);
input [0:1] ip;
input sel;
output op;
assign op=sel?ip[1]:ip[0];
endmodule
module mux41(ip,sel,op);
input [0:3] ip;
input [1:0] sel;
output op;
assign op=(~sel[0])&(~sel[1])&ip[0];
assign op=sel[0]&(~sel[1])&ip[1];
assign op=(~sel[0])&sel[1]&ip[2];
assign op=sel[0]&sel[1]&ip[3];
endmodule
Testbench:-
module mux81_tb();
reg [0:7] ip;
reg [2:0] sel;
wire op;
mux81 ml(ip,sel,op);
initial
begin
ip=8'b10101010; sel=3'b000;
#20
sel=3'b001;
#20
sel=3'b010;
#20
sel=3'b011;
#20
sel=3'b100;
#20
sel=3'b101;
#20
sel=3'b110;
#20
sel=3'b111;
#20 $finish;
end
endmodule
8:3 encoder:-
module enc83(I,Y0,Y1,Y2);
input[7:0]I;
output Y0,Y1,Y2;
assign Y0=I[4]+I[5]+I[6]+I[7];
assign Y1=I[2]+I[3]+I[6]+I[7];
assign Y2=I[1]+I[3]+I[5]+I[7];
endmodule
Priority Encoder:-
module PE1(I0,I1,I2,I3,Y1,Y2);
input I0,I1,I2,I3;
output Y1,Y2;
assign Y1=I3|I2;
assign Y2=I3|I1&(~I2);
endmodule
3:8 Decoder (30-8-24)
module dec38(en,ip,op);
input en;
input [2:0]ip;
output[0:7] op;
assign op[0]= en &(~ip[2])&(~ip[1])&(~ip[0]);
assign op[1]= en &(~ip[2])&(~ip[1])&(ip[0]);
assign op[2]= en &(~ip[2])&(ip[1])&(~ip[0]);
assign op[3]= en &(~ip[2])&(ip[1])&(ip[0]);
assign op[4]= en &(ip[2])&(~ip[1])&(~ip[0]);
assign op[5]= en &(ip[2])&(~ip[1])&(ip[0]);
assign op[6]= en &(ip[2])&(ip[1])&(~ip[0]);
assign op[7]= en &(ip[2])&(ip[1])&(ip[0]);
endmodule
TestBench:-
module dec38_tb();
reg en;
reg [2:0] ip;
wire [0:7] op;
dec38 d1(en , ip, op);
initial
begin
en=1'b0;ip=3'd0;
#20 en=1'b0;ip=3'd0;
#20 en=1'b0;ip=3'd3;
#20 en=1'b1;ip=3'd0;
#20 en=1'b1;ip=3'd1;
#20 en=1'b1;ip=3'd2;
#20 en=1'b1;ip=3'd3;
#20 en=1'b1;ip=3'd4;
#20 en=1'b1;ip=3'd5;
#20 en=1'b1;ip=3'd6;
#20 en=1'b1;ip=3'd7;
#20 $finish;
end
initial $monitor("en=%b ip=%b op=%b",en,ip,op);
endmodule
XDC FILE:-
##Switches
set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { ip[0] }];
#IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 } [get_ports { ip[1] }];
#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { ip[2] }];
#IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 } [get_ports { en }];
#IO_L13N_T2_MRCC_14 Sch=sw[3]
## LEDs
set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { op[0] }];
#IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { op[1] }];
#IO_L24P_T3_RS1_15 Sch=led[1]
set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { op[2] }];
#IO_L17N_T2_A25_15 Sch=led[2]
set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { op[3] }];
#IO_L8P_T1_D11_14 Sch=led[3]
set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { op[4] }];
#IO_L7P_T1_D09_14 Sch=led[4]
set_property -dict { PACKAGE_PIN W22 IOSTANDARD LVCMOS33 } [get_ports { op[5] }];
#IO_L18N_T2_A11_D27_14 Sch=led[5]
set_property -dict { PACKAGE_PIN U19 IOSTANDARD LVCMOS33 } [get_ports { op[6] }];
#IO_L17P_T2_A14_D30_14 Sch=led[6]
set_property -dict { PACKAGE_PIN U14 IOSTANDARD LVCMOS33 } [get_ports { op[7] }];
#IO_L18P_T2_A12_D28_14 Sch=led[7]
Seven Segment Decoder (30-8-2024)
module seg7decoder(input [3:0] data, output reg [6:0] segments);
parameter BLANK = 7'b000_0000;
parameter ZERO = 7'b111_1110;
parameter ONE = 7'b011_0000;
parameter TWO = 7'b110_1101;
parameter THREE = 7'b111_1001;
parameter FOUR = 7'b011_0011;
parameter FIVE = 7'b101_1011;
parameter SIX = 7'b101_1111;
parameter SEVEN = 7'b111_0000;
parameter EIGHT = 7'b111_1111;
parameter NINE = 7'b111_1011;
always @(*)
case(data)
0: segments = ZERO;
1: segments = ONE;
2: segments = TWO;
3: segments = THREE;
4: segments = FOUR;
5: segments = FIVE;
6: segments = SIX;
7: segments = SEVEN;
8: segments = EIGHT;
9: segments = NINE;
default: segments = BLANK;
endcase
endmodule
XDC file:- ee file example matrame deepu ni adagandi ela cheyyalo
##Switches
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { BLANK }];
#IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { ZERO }];
#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { ONE }];
#IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { TWO }];
#IO_L13N_T2_MRCC_14 Sch=sw[3]
set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 } [get_ports { THREE }];
#IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { FOUR }];
#IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 } [get_ports { FIVE }];
#IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { SW[7] }];
#IO_L5N_T0_D07_14 Sch=sw[7]
##7 segment display
set_property -dict { PACKAGE_PIN T10 IOSTANDARD LVCMOS33 } [get_ports { CA }];
#IO_L24N_T3_A00_D16_14 Sch=ca
set_property -dict { PACKAGE_PIN R10 IOSTANDARD LVCMOS33 } [get_ports { CB }]; #IO_25_14 Sch=cb
set_property -dict { PACKAGE_PIN K16 IOSTANDARD LVCMOS33 } [get_ports { CC }]; #IO_25_15 Sch=cc
set_property -dict { PACKAGE_PIN K13 IOSTANDARD LVCMOS33 } [get_ports { CD }];
#IO_L17P_T2_A26_15 Sch=cd
set_property -dict { PACKAGE_PIN P15 IOSTANDARD LVCMOS33 } [get_ports { CE }];
#IO_L13P_T2_MRCC_14 Sch=ce
set_property -dict { PACKAGE_PIN T11 IOSTANDARD LVCMOS33 } [get_ports { CF }];
#IO_L19P_T3_A10_D26_14 Sch=cf
set_property -dict { PACKAGE_PIN L18 IOSTANDARD LVCMOS33 } [get_ports { CG }];
#IO_L4P_T0_D04_14 Sch=cg
set_property -dict { PACKAGE_PIN H15 IOSTANDARD LVCMOS33 } [get_ports { DP }];
#IO_L19N_T3_A21_VREF_15 Sch=dp
FulladderBinary (06-09-2024)
module fa4(a,b,c,s,cout);
input a,b,c;
output s,cout;
assign s=a^b^c;
assign cout=(a&b)|(b&c)|(c&a);
endmodule
module fa1(a,b,s);
input [3:0]a,b;
output [4:0]s;
wire w1,w2,w3;
fa4 f1(a[0],b[0],1'b0,s[0],w1);
fa4 f2(a[1],b[1],w1,s[1],w2);
fa4 f3(a[2],b[2],w2,s[2],w3);
fa4 f4(a[3],b[3],w3,s[3],s[4]);
endmodule
TestBench:-
module fa4_tb();
reg [3:0]a,b;
wire [4:0]s;
fa1 f1(a,b,s);
initial
begin
a=4'b0100;
b=4'b0110;
#20
a=4'b0011;
b=4'b0001;
#20
a=4'b1011;
b=4'b1101;
#20
$finish;
end
endmodule
XDC FILE:-
##Switches
set_property -dict { PACKAGE_PIN M15 IOSTANDARD LVCMOS33 } [get_ports { a[0] }];
#IO_L24N_T3_RS0_15 Sch=sw[0]
set_property -dict { PACKAGE_PIN H17 IOSTANDARD LVCMOS33 } [get_ports { b[0] }];
#IO_L3N_T0_DQS_EMCCLK_14 Sch=sw[1]
set_property -dict { PACKAGE_PIN H18 IOSTANDARD LVCMOS33 } [get_ports { a[1] }];
#IO_L6N_T0_D08_VREF_14 Sch=sw[2]
set_property -dict { PACKAGE_PIN H19 IOSTANDARD LVCMOS33 } [get_ports { b[1] }];
#IO_L13N_T2_MRCC_14 Sch=sw[3]
set_property -dict { PACKAGE_PIN F21 IOSTANDARD LVCMOS33 } [get_ports { a[2] }];
#IO_L12N_T1_MRCC_14 Sch=sw[4]
set_property -dict { PACKAGE_PIN H22 IOSTANDARD LVCMOS33 } [get_ports { b[2] }];
#IO_L7N_T1_D10_14 Sch=sw[5]
set_property -dict { PACKAGE_PIN G22 IOSTANDARD LVCMOS33 } [get_ports { a[3] }];
#IO_L17N_T2_A13_D29_14 Sch=sw[6]
set_property -dict { PACKAGE_PIN F22 IOSTANDARD LVCMOS33 } [get_ports { b[3] }];
#IO_L5N_T0_D07_14 Sch=sw[7]
## LEDs
set_property -dict { PACKAGE_PIN V22 IOSTANDARD LVCMOS33 } [get_ports { s[0] }];
#IO_L18P_T2_A24_15 Sch=led[0]
set_property -dict { PACKAGE_PIN U21 IOSTANDARD LVCMOS33 } [get_ports { s[1] }];
#IO_L24P_T3_RS1_15 Sch=led[1]
set_property -dict { PACKAGE_PIN U22 IOSTANDARD LVCMOS33 } [get_ports { s[2] }];
#IO_L17N_T2_A25_15 Sch=led[2]
set_property -dict { PACKAGE_PIN T21 IOSTANDARD LVCMOS33 } [get_ports { s[3] }];
#IO_L8P_T1_D11_14 Sch=led[3]
set_property -dict { PACKAGE_PIN T22 IOSTANDARD LVCMOS33 } [get_ports { s[4] }];
#IO_L7P_T1_D09_14 Sch=led[4]
