IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO.

3, MARCH 2009 775

A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm

CMOS Technology
Lan-Chou Cho, Chihun Lee, Chao-Ching Hung, and Shen-Iuan Liu, Senior Member, IEEE

Abstract—A 33.6–33.8 Gb/s burst-mode clock/data recovery GVCO. To improve the above issues, a two-stage LC GVCO is
circuit (BMCDR) is presented in this paper. To reduce the data presented.
jitter and generate the high-frequency output clock, the LC gated
voltage-controlled oscillator is presented. To receive and transmit
To receive the broadband data, a wideband input matching
the broadband data, a wideband input matching circuit and circuit is indispensable. In [6], the conventional input matching
a wideband data buffer are presented, respectively. The phase circuit is designed as the microstrip lines of 50 to absorb the
selector is proposed to overcome the false phase lock due to the routing and pad capacitance. The inductive peaking technique
full-rate operation. This proposed BMCDR has been fabricated
in a 90 nm CMOS process. The measured peak-to-peak and rms extends the bandwidth and provides a better 50 matching
jitters for the recovered data are 7.56 ps and 1.15 ps, respectively, at high frequency. Although this configuration has the input
for a 33.72 Gb/s, 211 1 PRBS. The measured bit error rate is impedance of 50 up to 50 GHz, the simulated input return
less than 10 8 for a 33.72 Gb/s, 27 1 PRBS. It consumes 73 mW loss degrades quickly and it is larger than 10 dB when the fre-
without buffers from a 1.2 V supply.
quency is 20 GHz. The proposed input matching circuit is pre-
Index Terms—Burst-mode clock/data recovery, gated voltage- sented to improve the input loss and the symmetric inductors are
controlled oscillator, passive optical networks, phase-locked loop.
used to save the chip area. In addition, a PLL is used to stabilize
the frequency of a GVCO for a conventional burst-mode CDR
I. INTRODUCTION (BMCDR) circuit. In this work, a fully differential phase fre-
quency detector (PFD) and a voltage-to-current converter (V/I

H IGH-SPEED and long-distance communication systems

mostly adopt the optical networks in various applications.
For example, passive optical networks (PONs) are attractive in
converter) are presented to improve the jitter performance.
This paper is organized as follows. Section II describes the
circuits in the proposed BMCDR circuit. Section III gives the
the point-to-multipoint communication systems. In PONs, each
measurement results. The conclusions are given in Section IV.
asynchronous packet has to be correctly received within several
tens of bit times. Conventional phase-locked loops (PLLs) are
II. CIRCUIT DESCRIPTION
widely utilized in clock/data recovery (CDR) circuits; however
they suffer from a long settling time. The proposed BMCDR circuit [7] is shown in Fig. 1. It is
Several CDR circuits have been presented to achieve a short composed of an input matching circuit, differential microstrip
locked time. In [1], [2], the gated voltage-controlled oscillator lines, a phase selector, a retimed D flip flop (DFF), a wideband
(GVCO) is enabled and stopped by input data to align in phase. data buffer, two clock buffers, the first LC GVCO (GVCO1),
It results in the data dependent jitter, because this GVCO [1], [2] and a PLL. With an external reference clock of 4.215 GHz, this
has to oscillate and latch alternatively. Moreover, it takes a long PLL locks the frequency of the second LC GVCO (GVCO2) at
start-up time to re-oscillate a several tens-GHz GVCO. The ad- 33.72 GHz. The GVCO2 is a replica of the GVCO1 and this
ditional jitter-rejection block [2] is indispensable and it will in- PLL ensures the GVCO1 to operate at the same frequency as
crease circuit complexity and power consumption. In [3], [4], a GVCO2. The GVCO1 is gated by input data and generates the
short and accurate delay line is needed for the GVCO. However, recovered clock. Since the full-rate GVCO is adopted in this
it is difficult to realize an accurate delay line for a several-tens BMCDR circuit, this GVCO may lock with either the rising
GHz circuit. The delay line affects the duty cycle of the recov- or falling edge of the input date. To recover the correct data,
ered clock and limits the oscillation frequency of the GVCO. In a phase selector is proposed. The detail circuits are discussed in
[5], five multiplexers form two GVCOs. The limited bandwidth the following.
of the multiplexers in the GVCO induces a large inter-symbol
A. LC GVCO
interference (ISI). It also limits the oscillation frequency of the
The proposed LC GVCO is shown in Fig. 2. It is composed
Manuscript received April 24, 2008; revised September 22, 2008. Current of two LC delay stages and a data-triggering multiplexer. When
version published February 25, 2009. This work was supported by the National the input data, Din, is high, the upper LC delay stage and the
Science Council of Taiwan.
The authors are with the Graduate Institute of Electronics Engineering and
multiplexer realize a two-stage LC ring oscillator and the clocks
Department of Electrical Engineering, National Taiwan University, Taipei come from two LC delay stages are in phase. Once the input data
10617, Taiwan. goes to low, the lower LC delay stage and the multiplexer form
Color versions of one or more of the figures in this paper are available online
at http://ieeexplore.ieee.org. another oscillator and the output of the upper LC stage tracks
Digital Object Identifier 10.1109/JSSC.2008.2012326 with that of the lower LC stage. Note that the clocks A and B

0018-9200/$25.00 © 2009 IEEE

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776 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 3, MARCH 2009

Fig. 1. Proposed burst-mode CDR circuit.

Fig. 3. (a) Transient response as clock leads data. (b) Transient response as
clock lags data.

clocks, A and B. To understand the phase aligning mechanism,

the simplified model for the LC GVCO is shown in Fig. 4 [9],
[10]. The multiplexer is modeled as the mixer and an LC tank
load. The LC delay stage is modeled as a bandpass gain stage,
which is realized by a transconductance (i.e., ) multiplied by
Fig. 2. Proposed LC GVCO. an LC tank load. Since the LC delay stage and the multiplexer
utilized the equal inductors, assume the LC tank load is identical
for both circuits. In the LC GVCO, the input data mixes
are in-phase; thus, no oscillator is stopped during the normal op- with the output clock . To simplify the analysis, assume the
eration. It will significantly reduce the data-dependent jitter. In input data is random NRZ signal with the amplitude of
Fig. 2, this multiplexer is modeled as a mixer with two inputs, and the bit time of . The first spectrum null is at .
and . Since the clocks A and B are identical, they serve The output clock is a cosine wave with the frequency of
as one of the mixer’s inputs, . When the input data rate is . Compared with input data, the peak of the mixer output
identical with the oscillation frequency of the LC GVCO, the spectrum is shifted to and the first spectrum null is also
phase error is close to zero [8]. It is because that the injection shifted to . The mixer output is filtered by the LC tank load
locking mechanism will align the phases of input data and the and the resulting output is filtered by the bandpass gain stage
clock, when their frequency offset is zero [8]. The transient re- to generate the output clock . As the resonant frequency of
sponse helps us to understand the behavior of this LC GVCO. In LC GVCO is close to , the output will be locked at the
Fig. 3(a), the input data rate is equal to the resonant frequency frequency. The pattern density of will affect the clock
of the LC GVCO and the clock leads the data initially. When jitter performance and the bit error rate (BER). To simplify the
each rising-edge data comes, the clock will be triggered. The derivation, only the case of a periodic 0–1 pattern for the CDR
phase error between input data and the clock is decreasing. In is derived.
Fig. 3(b), the condition that the clock lags the data can be derived For this LC GVCO to work properly as shown in Fig. 4, the
similarly. The oscillation frequency of the dummy LC GVCO is loop gain at must be at least unity. Assume
adjusted by MOS varactors, which exist in both the multiplexer the transfer function of the LC tank load is modeled as
and LC delay stage, by using the PLL. The simulated gain of
this GVCO is around 1 GHz/V, while consuming 9.6 mA.
As mentioned before, the LC delay stage and the multiplexer (1)
realize a two-stage LC ring oscillator to generate two in-phase

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CHO et al.: A 33.6-TO-33.8 Gb/s BURST-MODE CDR IN 90 nm CMOS TECHNOLOGY 777

LC GVCO is locked, the frequency offset induces the static

phase error [8], and the relationship is derived by

(8)
Fig. 4. The equivalent model for the LC GVCO.
From (8), if input data rate is equal to the resonant fre-
quency of the LC GVCO, the clock of the GVCO will align
where and . The loop gain is with the input data. However, the frequency offset between
demanded to the data and the GVCO is inevitable. It may result in the static
phase error and it degrades the performance of the BMCDR
circuit, such as the BER and jitter. To consider the BER and
(2) jitter in practice, the actual operational frequency range of the
LC GVCO must be reconsidered. From [11], the BER is derived
where denotes the mixer conversion factor in units of . as follows:
That is,

(9)
(3)
where is the static phase error, is the rms jitter of the
clock, ,
The minimum input amplitude is given by and UI is the unity interval of the bit time, .
Based on (8) and (9), the relationship between the BER and
operational frequency range could be found. For example, let the
clock’s rms jitter be 0.1 UI. To achieve the ,
(4) the static phase error must be less than 0.05 UI. Therefore, the
actual operational frequency range is derived as

Assume and the frequency offset is .

The following approximation can be achieved as (10)

(5) B. The Phase Selector

When the input data triggers the GVCO, either the rising or
Hence, substituting (5) into (4), the following equation is ob- falling edge of the GVCO’s output clock may align
tained as with the input data as shown in Fig. 5. Once the input data
aligns with , the recovered clock should be comple-
mentary of and vice versa. In order to
(6) retime the data, it has to generate the recovered clock correctly.
To avoid this phase ambiguity, the proposed phase selector is
shown in Fig. 6(a). It is composed of a multiplexer, a DFF, and
The magnitude of the input data must be greater than a delay cell with the delay of , which is also realized by an
to maintain the oscillation for the LC GVCO. For example when LC delay stage. The timing diagrams of the phase selector are
the magnitude of the input data is , the maximum fre- shown in Fig. 6(b), where the input data aligns with GVCO’s
quency offset is given by output clock. For the left-hand figure in Fig. 6(b), the input data
aligns with . The input data will sample the low level
of the delayed clock, , which is delayed by from
(7) . The DFF outputs a logic low and is se-
lected to be the recovered clock, . On the contrary, for
For a fixed input power, the locking range of the LC GVCO the right-hand figure in Fig. 6(b), the input data aligns with the
is defined as . The high quality factor will result in the falling edge of ; i.e., aligning with the rising edge of
better phase noise but degrade the locking range. The locking . The DFF outputs a logic high and is se-
range of the LC GVCO is directly affected by the input ampli- lected to be the recovered clock, . Therefore, no matter
tude. Thus, a wideband input matching circuit is important to the input data aligns with either the rising or falling edge of
minimize the input loss, which will be discussed later. As the , the correct recovered clock is generated. Note that

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778 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 3, MARCH 2009

Fig. 5. The possible locking behavior for the LC GVCO with D .

Fig. 6. The proposed phase selector. (b) Timing diagram of the phase selector.

Fig. 7. The proposed input matching circuit.

the accuracy of is not stringent; it has to meet the setup and

hold time of the DFF. In this work, can be is designed within
, i.e., 7.4 ps 14.8 ps.

C. The Input Matching Circuit

The proposed input matching circuit realizes an input
impedance of 50 over a wideband bandwidth and it is shown
in Fig. 7. The input symmetric transformer is used to absorb Fig. 8. (a) The simulated input return loss (S ) for the matching circuit in [6]
and the proposed one in Fig. 7 with inductors and transformers. (b) The simu-
the pad capacitance. The shunt peaking circuit is realized lated input return loss (S ) with self-inductance variations. (c) The simulated
by two symmetric transformers and resistors to enhance the input return loss (S ) with pad capacitance variations.
bandwidth. The transformers are used to achieve the wideband
matching, compared with the resister and the narrow band LC
matching. All the transformers are implemented in a symmetric peaking in [6] and the proposed one using the inductors and
fashion so as to save the chip area. The differential microstrip the transformers with the coupling factor of 0.5 is shown in
lines of 50 are realized by the 9th metal layer over the first Fig. 8(a). For the required input return loss less than 10 dB,
metal layer. The length and width of each microstrip line is the simulated bandwidth of the conventional matching circuit
370 m and 2 m, respectively. The simulated input return in [6] is around 20 GHz. For the proposed matching circuit
loss for the conventional matching circuit with inductive with inductors in Fig. 7, the simulated bandwidth is around

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CHO et al.: A 33.6-TO-33.8 Gb/s BURST-MODE CDR IN 90 nm CMOS TECHNOLOGY 779

Fig. 9. The proposed wideband data buffer.

30 GHz. As the proposed matching circuit with transformers in

Fig. 7, the simulated bandwidth is up to 70 GHz under the same
required input return loss. The simulated bandwidth is further
improved by a factor of 3.5, compared with [6]. To ensure Fig. 10. (a) The equivalent model of a conventional Cherry–Hooper amplifier
with resistive loads. (b) The load impedances for the proposed wideband data
the models of inductors and parasitic capacitors, the whole buffer.
routing layout of the input matching circuit is simulated by EM
simulation tool. For our matching circuit, the non-ideal LC does
not seriously affect the bandwidth for the required input return and
loss. The simulated input return loss with the different
self inductances of the transformer is shown in Fig. 8(b).
Note that the coupling factor is 0.5. The simulated bandwidth (13)
is varied 2 GHz for 10% inductance variation. The simulated
input return loss with different pad capacitances is shown
where and . and
in Fig. 8(c). The simulated bandwidth is varied 0.5 GHz for
are the total capacitances connected to the drain of a MOS
10% capacitance variation.
device. is the gate capacitance of a MOS device. is the
load capacitance. Substituting (13) and (12) into (11), its 3 dB
D. The Proposed Wideband Data Buffer bandwidth is derived by

To realize a 40 Gb/s data buffer, the requirements for the

wide bandwidth and the flatness of the gain are important. Once
the bandwidth is not wide or the gain is not flat, it may in-
duce significant jitters. The conventional Cherry–Hooper am- (14)
plifier is widely utilized for these purposes. Fig. 9 shows the
proposed output data buffer. The Cherry–Hooper amplifier com-
Assume that , ,
bined with the inductive peaking technique [12] is used to lower
and . The 3 dB bandwidth is given as
the input capacitance load. In Fig. 9, the asymmetric 2:1 trans-
former is indicated by the coupled inductors, and , and
the symmetric 1:1 transformer is indicated by the coupled in-
ductors, and .
For a conventional Cherry–Hooper amplifier with resistive (15)
loads, the equivalent model and the load impedances and
are shown in Fig. 10(a). Its transfer function is given by This 3 dB bandwidth is much higher than the pole ,
if without the feedback resistor . For a typical design,
70 , 0.5, 30 fF and 200 fF, the 3 dB
(11) bandwidth is calculated as 15.75 GHz.
The 3 dB bandwidth of the proposed wideband data buffer
by using only inductors in Fig. 9 can be derived by the same
The load impedances and of a conventional
way. Assume its load impedances and is shown in
Cherry–Hooper amplifier are expressed as
Fig. 10(b) and they are expressed as shown in (16) and (17) at
the bottom of the next page. Assume that ,
in , and in
(12) with , ,

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780 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 3, MARCH 2009

for our design. The 3 dB bandwidth is derived by

(18), shown at the bottom of the page, where

(19)

and

(20)

To simplify the equation, we assume that and

. Its 3 dB frequency is given as

(21)
Fig. 11. The simulated frequency responses for the Cherry–Hooper amplifier
with or without inductor peaking and the proposed data buffer.
For the 400 pH, 0.5, 30 fF and
200 fF in our design, the 3 dB bandwidth with
and without the feedback resistor is about 54.6 GHz and 2 1 PRBS, the simulated peak-to-peak jitter of this data
43.6 GHz. The bandwidth of the proposed data buffer by using buffer is 0.032UI (i.e., 0.8 ps).
transformers is not derived here. To match the output load,
is designed as 50 and the simulated frequency responses for E. The Remaining Circuits
the Cherry–Hooper amplifier with or without inductor peaking To match the oscillation frequencies of a GVCO and the input
and the proposed data buffer by using the transformer with the data, a PLL circuit is needed. This PLL is composed of a PFD,
coupling factor of 0.5 is shown in Fig. 11. Note that the coupling the V/I converter, and a divide-by-8 divider, as shown in Fig. 1.
factor plays an important role in bandwidth enhancement [13]. The operation speed of the conventional PFD is limited in the
Compared with the conventional Cherry–Hooper amplifier D-flip-flop and feedback NOR gate. The differential D-flip-flop
with resistive loads, the inductor peaking technique enhances speeds up the PFD and generates the differential outputs ,
the bandwidth by a factor of 1.9; however, the passband gain , and . To use the conventional single-ended V/I
is not flat. The simulated 3 dB bandwidth of the proposed converter, two V/I converters and two loop filters are needed.
data buffer is 55.5 GHz. Compared with the conventional In addition, the current mismatch between the tail currents of
Cherry–Hooper amplifier with resistive loads, the simulated the V/I converters induces the static phase error. To solve above
3 dB bandwidth is enhanced by a factor of 3. For a 40 Gb/s problems, the differential PFD and differential-to-single-ended

(16)

(17)

(18)

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CHO et al.: A 33.6-TO-33.8 Gb/s BURST-MODE CDR IN 90 nm CMOS TECHNOLOGY 781

Fig. 12. The differential PFD and V/I converter.

Fig. 15. The measured frequency spectrum of the free-running GVCO with the
33.76 Gb/s input data and the PLL is off.

Fig. 16. The measured recovered data.

Fig. 13. Die photo.

and pads. It consumes 98 mW and 73 mW with and without

buffers, respectively, from a 1.2 V supply. This BMCDR circuit
recovers the input data within 33.6 33.8 Gb/s. Fig. 14 shows
the measured transfer curve of the GVCO. This VCO covers
from 33.5 GHz to 34.6 GHz within the controlling voltage of
0 1.2 V. It exhibits the tuning range of 1.2 GHz and the gain
is about 1.5 GHz/V. Fig. 15 shows the measured frequency
spectrum of the free-running GVCO output clock with input
data of 33.76 Gb/s and the PLL is off. The measured phase
noise at the offset frequency of 500-KHz is 89.67 dBc/Hz.
Fig. 16 shows the measured single-ended recovered data for a
Fig. 14. Measured GVCO’s transfer curve. 33.72 Gb/s, 2 1 PRBS. The measured peak-to-peak and rms
jitters for the recovered data are 7.56 ps and 1.15 ps, respec-
tively. The measured BER is less than 10 for a 33.72 Gb/s,
V/I converter is shown in Fig. 12 [14]. The differential PFD can 2 1 PRBS. Fig. 17 is the measured recovered clock and the
work up to 5 GHz. operation frequency is 33.72 GHz. The measured peak-to-peak
and rms jitters are 3.44 ps and 0.42 ps, respectively. The
III. EXPERIMENTAL RESULTS measured operational range for the output clock of the PLL is
This proposed BMCDR circuit has been fabricated in 90 nm 33.5–34.5 GHz. Fig. 18 is the measured frequency spectrum of
CMOS technology. All the inductors are implemented in a the GVCO with the 33.72 Gb/s input data and the PLL is on.
symmetric fashion in this work. Fig. 13 shows the die photo. To demonstrate the burst-mode transient behavior, the user-
Its area is 0.8 mm 0.8 mm with the on-chip loop filter defined bit sequence is used. The measured recovered data and

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782 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 44, NO. 3, MARCH 2009

TABLE I
PERFORMANCE SUMMARY AND COMPARISONS

is presented. The phase selector overcomes the false phase lock

is also presented. The input matching circuit and the wideband
Fig. 17. The measured recovered clock.
data buffer minimizes the input loss and amplifies the output
data. A fully-integrated PLL is also realized to lock the fre-
quency of the gated voltage-controlled oscillator. The experi-
mental and analysis results are presented to verify the proposed
circuits. The nominal supply voltage for the 90 nm CMOS tech-
nology is 1 V. A higher supply voltage of 1.2 V is used to en-
hance the circuit speed. But, it may degrade the reliability and
long-term functionality of the circuit.

ACKNOWLEDGMENT
The authors would like to thank TSMC and National Science
Council for chip fabrication and support for this work.

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Shen-Iuan Liu (S’88–M’93–SM’03) was born in

Keelung, Taiwan, in 1965. He received the B.S.
and Ph.D. degrees in electrical engineering from
National Taiwan University (NTU), Taipei, Taiwan,
Lan-Chou Cho (S’04) was born in Taipei, Taiwan, in in 1987 and 1991, respectively.
1978. He received the B.S., M.S., and Ph.D. degrees During 1991–1993, he served as a Second Lieu-
in electrical engineering from National Taiwan Uni- tenant in the Chinese Air Force. During 1991–1994,
versity, Taipei, in 2001, 2003, and 2008, respectively. he was an Associate Professor in the Department of
He is currently with Mediatek Inc., Hsinchu, Electronic Engineering, National Taiwan Institute of
Taiwan. His research interests include phase-locked Technology. He joined the Department of Electrical
loops, delay-locked loops, and high-speed CMOS Engineering, NTU, in 1994, where he has been a Pro-
data-communication circuits for multiple gigabit fessor since 1998. His research interests are in analog and digital integrated cir-
applications. cuits and systems.
Dr. Liu has served as chair of the IEEE SSCS Taipei Chapter in 2004–2008.
He has served as general chair of the 15th VLSI Design/CAD Symposium,
Taiwan, (2004) and as Program Co-chair of the Fourth IEEE Asia-Pacific
Conference on Advanced System Integrated Circuits, Fukuoka, Japan (2004).
He was the recipient of the Engineering Paper Award from the Chinese Institute
Chihun Lee (S’03) was born in Chiayi, Taiwan, of Engineers in 2003, the Young Professor Teaching Award from MXIC Inc.,
in 1978. He received the B.S. degree in electric the Research Achievement Award from NTU, and the Outstanding Research
engineering from National Cheng-Kung University, Award from National Science Council in 2004. He has served as a technical
Tainan, Taiwan, in 2000, the M.S. degree in electric program committee member for ISSCC in 2006–2008 and A-SSCC since
engineering from National Chiao-Tung University, 2005. He was an Associate Editor for IEEE TRANSACTIONS ON CIRCUITS AND
Hsinchu, Taiwan, in 2002, and the Ph.D. degree in SYSTEMS—II: EXPRESS BRIEFS in 2006–2007. Now, he is an Associate Editor
electric engineering from National Taiwan Univer- for IEEE JOURNAL OF SOLID-STATE CIRCUITS since 2006 and an Associate
sity, Taipei, Taiwan, in 2007. Editor for IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR
He is currently with Mediatek Inc., Hsinchu, PAPERS from 2008. He is also an Associate Editor for IEICE (The Institute of
Taiwan. His research interests are broadband ampli- Electronics, Information and Communication Engineers) TRANSACTIONS ON
fication, phase-locked loops, frequency synthesizers, ELECTRONICS since 2008. He joined the Editorial Board of Research Letters in
and clock data recovery. Electronics in 2008. He is a member of IEICE.

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