ELECTRICAL AND ELECTRONICS

CODE COURSE NAME CATEGORY L T P CREDIT

EET453 DIGITAL SIGNAL PROCESSING PEC 2 1 0 3

Preamble: This course introduces the discrete Fourier transform (DFT) and its computation
using direct method and fast Fourier transform (FFT). Techniques for designing infinite
impulse response (IIR) and finite impulse response (FIR) filters from given specifications are
also introduced. Various structures for realization of IIR and FIR filters are discussed.
Detailed analysis of finite word-length effects in fixed point DSP systems is included.
Architecture of a digital signal processor is also discussed.

Prerequisite : EET305 - Signals and Systems

Course Outcomes: After the completion of the course the student will be able to
CO 1 Compute Discrete Fourier transform and Fast Fourier transform .
CO 2 Discuss the various structures for realization of IIR and FIR discrete-time systems.
Design IIR (Butterworth and Chebyshev) digital filters using impulse invariant and
CO 3
bilinear transformation methods.
CO 4 Design FIR filters using frequency sampling method and window function method.
Compare fixed point and floating point arithmetic used in digital signal processors
CO 5
and discuss the finite word length effects.
CO 6 Explain the architecture of digital signal processors and the applications of DSP.

Mapping of course outcomes with program outcomes

PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO11 PO12
CO 1 3 2 - 2 2 - - - - - - 2
CO 2 3 2 - 2 2 - - - - - - 2
CO 3 3 2 - 2 2 - - - - - - 2
CO 4 3 2 - 2 2 - - - - - - 2
CO 5 3 2 - - 2 - - - - - - 2
CO 6 3 - 2 - 2 2 - - - - - 3

Assessment Pattern
Continuous Assessment Tests
Bloom’s Category End Semester Examination
1 2
Remember (K1) 10 10 10
Understand (K2) 10 10 30
Apply (K3) 30 30 60
Analyse (K4)
Evaluate (K5)
Create (K6)
Mark distribution ELECTRICAL AND ELECTRONICS
Total ESE
CIE ESE
Marks Duration
150 50 100 3 hours

Continuous Internal Evaluation Pattern:

Attendance : 10 marks
Continuous Assessment Test (2 numbers) : 25 marks
Assignment/Quiz/Course project : 15 marks

End Semester Examination Pattern: There will be two parts; Part A and Part B. Part A
contain 10 questions with 2 questions from each module, having 3 marks for each question.
Students should answer all questions. Part B contains 2 questions from each module of which
student should answer any one. Each question can have maximum 2 sub-divisions and carry
14 marks.

Course Level Assessment Questions

Course Outcome 1 (CO1)

1. State and prove various properties of DFT - (K1, PO1,PO2,PO12)
2. Determine the linear convolution using DFT – (K2,PO1,PO2,PO4,PO5,PO12)
3. Determine the linear convolution using overlap-add and overlap-save method –
(K3,PO1,PO2,PO4,PO5)
4. Compute DFT using DIT FFT and DIF FFT – (K2,PO1,PO2,PO4,PO5)

Course Outcome 2 (CO2)

1. Determine the structures for direct form, cascade, parallel, transposed and lattice-
ladder realisations of IIR systems –( K2,PO1,PO2,PO4,PO5,PO12)
2. Determine the structures for direct form, cascade, lattice ,and linear phase realizations
of FIR systems – (K2,PO1,PO2,PO4,PO5)

Course Outcome 3(CO3)

1. Design IIR digital LP/HP/BP/BS filter using Butterworth and Chebyshev methods –
(K3,PO1,PO2,PO4,PO5)
2. Transform H(s) to H(z) using impulse invariant technique and bilinear transformation
– (K2,PO1,PO2,PO4,PO5,PO12)

Course Outcome 4 (CO4)

1. Design FIR digital LP/HP/BP/BS filter using frequency sampling method –
(K3,PO1,PO2,PO4,PO5,PO12)
2. Design FIR digital LP/HP/BP/BS filter using window function –
(K3,PO1,PO2,PO4,PO5)
 Course Outcome 5 (CO5) ELECTRICAL AND ELECTRONICS
1. Differentiate between fixed-point arithmetic and floating point arithmetic -
(K2,PO1,PO2,PO12)
2. Explain various finite word length effects in fixed point DSP processors.-
(K2,PO1,PO2)
3. Problems to determine steady state output noise power and round-off noise power –
(K3,PO1,PO2)
4. Explain limit cycle oscillations and methods for its elimination - (K2,PO1,PO2)

Course Outcome 6 (CO6)

1. Explain Harvard architecture –( K1,PO1,PO5,PO12)
2. Describe the architecture of a fixed-point DSP processor – (K1,PO1,PO5)
3. List various applications of digital signal processor – (K3,PO1,PO3,PO6)

Model Question Paper PAGES: 3

QPCODE:
Reg. No:
Name:

APJ ABDUL KALAM TECHNOLOGICAL UNIVERSITY

SEVENTH SEMESTER B. TECH DEGREE EXAMINATION
MONTH & YEAR

Course Code: EET453

Course Name: DIGITAL SIGNAL PROCESSING

Max. Marks: 100 Duration: 3 Hours

PART A
Answer all Questions.
Each question carries 3 Marks
1 List any 3 properties of DFT.
The first 5 points of the 8-point DFT of a real valued sequence are
2 X (k ) ={0.25, 0.125 − j 0.3, 0, 0.125 − j 0.05, 0} . Determine the remaining 3
points.
Obtain direct form 1 realization for a digital IIR system described by the
3 z + 0.2
system function, H ( z ) = 2 .
z + 0.5 z + 1
Obtain realization with minimum number of multipliers for the system
4 1 1
function H ( z ) = + z −1 + z −2 .
2 2
5 ELECTRICAL AND ELECTRONICS
Explain warping effect in bilinear transformation.
Determine the order of a Chebyshev analog lowpass filter with a maximum
6 passband attenuation of 2.5dB at Ωp = 20 rad/sec and the stopband
attenuation of 30dB at Ωs = 50 rad/sec.
What are the desirable characteristics of a window function used for
7
truncating the infinite impulse response?
Represent the numbers i) +4.5 and ii) -4.5 in IEEE 754 single-precision
8
floating point format.
List any 3 finite-word length effects in a fixed point digital signal
9
processor.
Draw the block diagram of a basic Harvard architecture in digital signal
10
processor.

PART B
Answer any one full question from each module.
Each question carries 14 Marks
Module 1
11 a) Find the 4-point DFT of the sequence, x(n) ={1, −1,1, −1} . Also, using time (7)
shift property, find the DFT of the sequence, y=
(n) x((n − 2)) 4 .
b) Two finite duration sequences are h(n) = {1,0,1} (7)

and x(n) ={−1, 2, −1,0,1,3, −2,1, −3, −2, −1,0, −2} . Use overlap-save method, to
( n) x ( n) ∗ h( n) .
find y=
OR
12 Compute IDFT of the sequence (14)
{7, −0.707 − j 0.707, − j,0.707 − j 0.707,1,0.707 + j 0.707, j, −0.707 + j.707}
X (k ) =
using DIT FFT.
Module 2
13 a) 1 + 13 z −1 (6)
Realize the system function in cascade form H ( z ) = .
1 − 3 4 z −1 + 18 z −2
b) Determine the direct form 2 and transposed direct form structure for the (8)
1 1
given system y (=n) y (n − 1) − y (n − 2) + x(n) + x(n − 1) .
2 4
OR
14 a) Obtain the direct form realization of linear phase FIR system given by (7)
3 17 3
1 + z −1 + z −2 + z −3 + z −4
H ( z) =
4 8 4
b) Determine the coefficients km of the lattice filter corresponding to FIR filter (7)
−1 −2
described by the system function H ( z ) = 1 + 2 z + 1 3 z . Also, draw the
corresponding second order lattice structure
 ELECTRICAL AND ELECTRONICS
Module 3
15 a) Find H(z) using impulse invariant transformation. (7)
1
=H ( s) =
2
; T 1sec .
s + 2s + 1
b) A Butterworth lowpass filter has to meet the following specifications. (7)
i) Passband gain = -3dB at fp = 500Hz
ii) Stopband attenuation greater than or equal to 40dB at fs = 1000Hz
Determine the order of the Butterworth filter to meet the above
specifications. Also, find the cut off frequency.
OR
16 Design a Chebyshev digital lowpass filter with a maximum passband (14)
attenuation of 2dB at 100Hz and minimum stopband attenuation of 20dB
at 500Hz. Sampling rate is 4000 samples/sec. Use bilinear transformation.

Module 4
17 a) Design a linear phase lowpass FIR filter with N = 7 and a cut-off frequency (7)
0.3π radian using the frequency sampling method.
b) ω 1 3ω (7)
A linear phase FIR filter has frequency response H=(ω ) cos + cos
2 2 2
Determine the impulse response h(n).
OR
18 A band stop filter is to be designed with the following desired frequency (14)
e − jωα
jω − ωc1 ≤ ω ≤ ωc1 ωc 2 ≤ ω ≤ π
response H d (e ) = 
0 otherwise
Design with N = 7, ωc1 = π/4 rad/sec, ωc2 = 3π/4 rad/sec using rectangular
window.
Module 5
19 a) Compare between fixed point and floating point digital signal processors. (6)
b) The output of an ADC is applied to a digital filter with system function (8)
0.5 z
H ( z) = . Find the output noise power from digital filter when
( z − 0.5)
input signal is quantized to have 8 bits.

OR
20 a) Draw and explain the architecture of any fixed-point DSP processor. (8)
b) Explain the techniques used to prevent overflow in fixed-point DSP (6)
operations.
 SyllabusELECTRICAL AND ELECTRONICS

Module 1 - DISCRETE-FOURIER TRANSFORM

Review of signals and systems - Frequency domain sampling - Discrete Fourier transform
(DFT) – inverse DFT (IDFT) - properties of DFT – linearity, periodicity, symmetry, time
reversal, circular time shift, circular frequency shift, circular convolution, complex conjugate
property – Filtering of long data sequences – over-lap save method, over-lap add method –
Fast Fourier transform (FFT) – advantages over direct computation of DFT - radix -2
decimation-in-time FFT (DITFFT) algorithm, Radix-2 decimation-in-frequency FFT
(DIFFFT) algorithm.

Module 2 - REALIZATION OF IIR AND FIR SYSTEMS

Introduction to FIR and IIR systems - Realization of IIR systems – direct form 1, direct form
2, cascade form, parallel form, lattice structure for all-pole system, lattice-ladder structure –
conversion of lattice to direct form and vice-versa - signal flow graphs and transposed
structures – Realization of FIR systems – direct form, cascade form, lattice structure, linear
phase realization.

Module 3 - IIR FILTER DESIGN

Conversion of analog transfer function to digital transfer function – impulse invarient
transformation and bilinear transformation – warping effect
Design of IIR filters – low-pass, high-pass, band-pass, band-stop filters – Butterworth and
Chebyshev filter – frequency transformation in analog domain - design of LP, HP, BP, BS IIR
digital filters using impulse invariance and bilinear transformation.

Module 4 - FIR FILTER DESIGN AND REPRESENTATION OF NUMBERS

Impulse response of ideal low pass filter – linear phase FIR filter – frequency response of
linear phase FIR filter – Design of FIR filter using window functions (LP, HP, BP, BS
filters) – Rectangular, Bartlett, Hanning, Hamming and Blackmann only – FIR filter design
based on frequency sampling approach (LP, HP, BP, BS filters)
Representation of numbers – fixed point representation – sign-magnitude, one’s complement,
two’s complement – floating point representation – IEEE 754 32-bit single precision floating
point representation

Module 5 - FINITE WORD LENGTH EFFECTS AND DIGITAL SIGNAL

PROCESSORS
Finite word length effects in digital Filters – input quantization – quantisation noise power –
steady-state output noise power – coefficient quantisation – overflow – techniques to prevent
overflow - product quantization error – rounding and truncation – round-off noise power –
limit cycle oscillations – zero input limit cycle oscillations – overflow limit cycle oscillations
– signal scaling.
Digital signal processor architecture based on Harvard architecture (block diagram) –
Harvard architecture, pipelining, dedicated hardware multiplier/accumulator, special
instructions dedicated to DSP, replication, on-chip memory cache, extended parallelism
 ELECTRICAL processor
(Reference [2]) - comparison of fixed-point and floating-point AND ELECTRONICS
– applications of
DSP

Text Books
1. John G. Proakis & Dimitris G.Manolakis, “Digital Signal Processing Principles,
Algorithms & Applications”, Pearson

Reference Books
1. Emmanuel Ifeachor & Barrie W Jervis, “Digital Signal Processing”, Pearson, 13th
edition, 2013
2. P. Ramesh Babu, “Digital Signal Processing”, Scitech Publications (India) Pvt Ltd,
2nd edition, 2003
3. Li Tan, “Digital Signal Processing, Fundamentals & Applications”, Academic Press,
Ist edition, 2008
4. D. Ganesh Rao & Vineeta P Gejji, “Digital Signal Processing, A Simplified
Approach”, Sanguine Technical Publishers, 2nd edition, 2008

Course Contents and Lecture Schedule

Sl. No. of
Topic
No Lectures
1 DISCRETE-FOURIER TRANSFORM (7 hours)
1.1 Review of signals, systems and discrete-time Fourier transform (DTFT), 3 hours
Frequency domain sampling, discrete-Fourier transform (DFT), twiddle
factor, inverse DFT, properties of DFT - linearity, periodicity, symmetry,
time reversal, circular time shift, circular frequency shift, circular
convolution, complex conjugate property
1.2 Linear filtering using DFT, linear filtering of long data sequences, 1 hour
overlap-save method, overlap-add method
1.3 Fast Fourier transform (FFT) – comparison with direct computation of 3 hours
DFT - radix -2 decimation-in-time FFT (DITFFT) algorithm – bit reversal
- Radix-2 decimation-in-frequency FFT (DIFFFT) algorithm
2 REALIZATION OF IIR AND FIR SYSTEMS (7 hours)
2.1 Introduction to FIR and IIR systems - comparison - Realization of IIR 3 hours
systems – direct form 1, direct form 2, cascade form, parallel form
2.2 Lattice structure for all-pole system - lattice-ladder structure – conversion 2 hours
of lattice to direct form and vice-versa signal flow graphs and transposed
structures
2.3 Realization of FIR systems – direct form, cascade form, lattice structure, 2 hours
linear phase realization.
3 IIR FILTER DESIGN (7 hours)
3.1 Conversion of analog transfer function to digital transfer function – impulse 2 hours
invarient transformation and bilinear transformation – warping effect
3.2 Design of IIR filters – characteristics of ideal and practical low-pass, high- 3 hours
pass, band-pass, band-stop filters – design of Butterworth filter –
 ELECTRICAL
normalised analog filter - frequency transformation in analogAND ELECTRONICS
domain -
design of LP, HP, BP, BS IIR digital filters using impulse invariance and
bilinear transformation.
3.3 Design of Chebyshev filter – design of LP, HP, BP, BS IIR digital filters 2 hours
using impulse invariance and bilinear transformation
4 FIR FILTER DESIGN AND REPRESENTATION OF NUMBERS (7 hours)
4.1 Impulse response of ideal low pass filter – linear phase FIR filter – 3 hours
frequency response of linear phase FIR filter – Design of FIR filter using
window function (LP, HP, BP, BS filters) – Rectangular, Bartlett,
Hanning, Hamming and Blackmann only
4.2 FIR filter design based on frequency sampling approach (LP, HP, BP, BS 2 hours
filters)
4.3 Representation of numbers – fixed point representation – sign-magnitude, 2 hours
one’s complement, two’s complement – floating point representation –
IEEE 754 32-bit single precision floating point representation
5 FINITE WORD LENGTH EFFECTS AND DIGITAL SIGNAL PROCESSORS
(7 hours)
5.1 Finite word length effects in digital Filters – input quantization – 2 hours
quantisation noise power – steady-state output noise power
5.2 Coefficient quantisation – overflow – techniques to prevent overflow - 1 hour
product quantization error – rounding and truncation – round-off noise
power
5.3 Limit cycle oscillations – zero input limit cycle oscillations – overflow 1 hour
limit cycle oscillations – signal scaling.
5.4 Digital signal processor architecture based on Harvard architecture (block 2 hours
diagram) – Harvard architecture, pipelining, dedicated hardware
multiplier/accumulator, special instructions dedicated to DSP, replication,
on-chip memory cache, extended parallelism (Reference [1])
5.5 Comparison of fixed-point and floating-point processor – applications of 1 hour
digital signal processor

Note: Preferable list of computer based assignments

Assignments using signal processing tool of MATLAB/SCILAB etc
1 Determine 4-point/8-point DFT/IDFT of any sequence by direct computation
2 Compute 4-point/8-point DFT/IDFT using DIT FFT and DIF FFT algorithms.
3 Find the linear convolution and circular convolution of two sequences.
4 Find the linear convolution using overlap-add and overlap-save methods.
5 Determine 2 stage/3 stage lattice ladder coefficients if the system function of IIR
direct form is given.
6 Obtain coefficients of IIR direct form from lattice ladder form.
7 Transform an analog filter into digital filter using impulse invariant
technique/bilinear transformation.
8 Calculate the order and cut-off frequency of a low pass Butterworth filter
9 Obtain the frequency response and filter coefficients of a LP/HP/BP/BS IIR
 Butterworth filter ELECTRICAL AND ELECTRONICS
10 Obtain the frequency response and filter coefficients of a LP/HP/BP/BS IIR
Chebyshev filter
11 Compute LP/HP/BP/BS FIR filter coefficients using
rectangular/Bartlett/Hamming/Hanning/Blackmann window