Microelectronics Journal 108 (2021) 104970

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Microelectronics Journal
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High gain 0.18 𝜇 m-GaAs MMIC cascode-distributed low-noise amplifier for

UWB application
Moustapha El Bakkali ∗ , Naima Amar Touhami, Taj-eddin Elhamadi, Hanae Elftouh,
Mohammed Lamsalli
Information System and Telecommunication Laboratory, Faculty of Sciences, Abdelmalek Essaadi University, BP.2121 M’Hannech II, 93030, Tetuan, Morocco

A R T I C L E I N F O A B S T R A C T

Keywords: This paper describes a design of 3 GHz–12 GHz MMIC distributed Low Noise Amplifiers (LNAs) for Ultra Wide-
Distributed low noise amplifier band communications systems. The proposed circuit is a common source and cascode topology using a standard
Cascode configuration
0.18 𝜇m ED02AH process from OMMIC foundry. The ultra-wideband LNA achieves a power gain of 16.9 ± 1.7 dB
Miller effect
and an average noise figure of 2.9 ± 0.58 dB. The input and output reflection coefficients are less than −10 dB,
GaAs-pHEMT
UWB
the reverse gain S1 2 is less than −37dB and a high linearity IIP3 of [4–6.2] dBm. The chip area including testing
pads is only about 1.3 × 1.3 mm2 .

1. Introduction sipated and also low noise figure. UWB DA is being developed for inno-
vative of medical systems contributing to breast cancer detection [14].
Distributed amplifiers (DAs) are one of the most popular broad- It is also used in received system [15] and radar system to detect peo-
band amplifier architecture. Its principle was first proposed by W.S. ple buried underground [16] or for localization and tracking of human
Percival in 1937 [1]. They are structured with a well defined num- targets and objects in indoor environments [17].
ber of active devices in parallel from which the wave propagates along In this work we chose the distributed amplifier based on GaAs
its input and output artificial transmission lines (ATLs). DAs based Pseudomorphic High Electron Mobility Transistors (pHEMTs). They are
on complementary-metal-oxide-semiconductor (CMOS) are character- characterized by lower power consumption, low noise levels and large
ized by small size, low power consumption and low cost. However gain [18]. The gate-drain capacitance Cgd of these transistors can dete-
it’s characterized by losses in transmission lines which lead to a lower riorates the dynamic performance by Miller effect [19]. It induces a
gain, a higher noises figure NF and very poor linearity [2,3]. Gallium decrease in the input impedance, the gain and the bandwidth [9,20,21].
Arsenide (GaAs) technology provides several advantages for DA imple- In this paper, we present an approach to minimize Miller effect and
mentation. It offers low loss transmission lines; provide high gain, low to obtain a high quasi-invariant gain S21 with a low noise figure (NF)
NF and good linearity [4–6]. Indium phosphide (InP) based on Mono- in the frequency range between 3 GHz and 12 GHz using a cascode
lithic Microwave Integrated Circuits (MMIC) DA offer higher bandwidth configuration.
compared with Silicon (Si) and Silicon–Germanium (SiGe) technologies,
while their bandwidth gain is lower than that of DA GaAs and its power 2. The distributed amplifier design
consumption is relatively high [7,8]. DAs using Gallium Nitride (GaN)
technologies have been developed to provide high output power, high 2.1. MMIC process
linearity and lower self heating [9,10]. However, their bandwidth is
limited due to the lower transition frequencies and its dissipated power For this study, a pHEMT (pseudomorphic High Electron Mobility
is very high compared to CMOS, GaAs and InP technologies [11–13]. Transistor) transistor from OMMIC foundry is used. The technology
The Ultra-wideband (UWB) DA has attracted a lot of interest in the used is known as ED02AH process whose gate length is 0.18 𝜇 m in
last years, both in academia and in the industry, especially at the level enhanced and depletion mode. Different gate widths are available (15,
of the band-which is very wide with a flat gain, low cost, low power dis- 30 or 50 𝜇 m) and the number of gate fingers varies from 2 to 6. This

∗ Corresponding author.
E-mail addresses: [Link]@[Link], elbakkalimoustapha91@[Link] (M. El Bakkali).

[Link]
Received 29 May 2020; Received in revised form 3 November 2020; Accepted 14 December 2020
Available online 24 December 2020
0026-2692/© 2020 Elsevier Ltd. All rights reserved.
M. El Bakkali et al. Microelectronics Journal 108 (2021) 104970

Fig. 1. Chip size of ED02AH transistor.

Fig. 3. Evolution of minimum noise figure. (Vgs = −0.3V, W0 = 15 𝜇m and

Freq = 8 GHz).

Fig. 2. Evolution of the power dissipated (V ds = 3V, Ng = 6 and Freq = 8 GHz).

process has been developed specifically for microwave applications up Fig. 4. NFmin according to Vgs and Vds (size 6 × 15𝜇m).
to millimetric wavelengths, and for high speed digital circuits for opti-
cal links.

2.2. Sizing and bias of the transistor

The choice of the bias point and the size of the transistor are mainly
based on performance in terms of minimum noise figure NFmin , gain
S21 and the dissipated power Pdc .
The size of the transistor corresponding to the total width of the gate
is Ng x W0 , where Ng is the number of fingers and w0 is the width of
a gate finger. An example of the layout of a transistor which the size is
6 × 15 𝜇 m is given in Fig. 1.
Fig. 2 shows that the power dissipated Pdc depends mainly on the
gate finger width W0 . The minimum values of Pdc are obtained for Vgs
ranging from −0.2V and −0.5V. The optimal width of W0 is obtained
for W0opt = 15 𝜇 m.
We are now looking for optimal conditions in terms of noise and
gain. We present the evolution of minimum noise figure NFmin and max- Fig. 5. Max gain according to Frequency and Vds (size 6 × 15𝜇m and
imum gain as a function of the drain-source bias Vds and the number of Vgs = −0.3V).
fingers of the transistor. We choose from Fig. 3, Ngopt = 6 for its best
NFmin over the entire Vds polarization range.
The evolution of the minimum noise figure NFmin as a function of polarization Vds = 3V and Vgs = −0.3V.
the drain-source voltage for the values of Vgs situated between −0.2V
and −0.5V is illustrated in Fig. 4. The result indicates that the optimal 2.3. Distributed amplifier and Miller effect
value of Vgs minimizing the noise is Vgsopt = −0.3V. And from Fig. 5
the maximum gain remains almost invariant from Vds = 3V–7V. In this The structure of a distributed amplifier is most suitable for very
case the dissipated power Pdc increases more than the maximum gain, wideband, with a flatness gain and excellent adaptations. This structure
so the optimal voltage Vds is Vdsopt = 3V. is very suitable for the MMIC technology.
This study allowed us to determine the bias points and the size of The gates and drains of the transistors are connected by inductances.
the transistor that will be used as the basic brick of the low noise dis- Fig. 6 shows that two transmission lines were thus formed. The gate line
tributed amplifier. The transistor chosen is of size 6 × 15𝜇 m with the consists of the inductors Lg associated with the input capacitors Cgs . The

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M. El Bakkali et al. Microelectronics Journal 108 (2021) 104970

Table 1
Intrinsic parameters of the 6 × 15 𝜇m ED02AH transistor with Vds = 3V &
Vgs = − 0.3V and the values of the inductances Lg and Ld .
Cgd (fF) Cds (fF) Cgs (fF) Rgs (Ω) Rds (Ω) Lg (pH) Ld (pH)
20.8 18.18 91.245 5 344.88 288.1 45.45

Fig. 6. The MMIC distributed amplifier [22].

gate signal propagates along the transmission line by shifting from cell
to cell by an amount 𝜃 g . This line is characterized by its attenuation
coefficient 𝛼 g , phase constant 𝛽 g and its characteristic impedance Z0g
[23].
√
𝜔Rgs Cgs Lg Cgs 𝜔2
𝛼g = √ (1)
4 + (2Rgs Cgs 𝜔)2 − Lg Cgs 𝜔2

Lg Cgs 𝜔2
𝛽 g = Arccos(1 − ) (2)
2(1 + (Rgs Cgs 𝜔)2 )
√
Lg √ 𝜔 2 𝜔
Z0g = 1−( ) +j (3)
Cgs 𝜔cg 𝜔g
2 1
Where ∶ 𝜔cg = √ and 𝜔g =
Lg Cgs Rgs Cgs

The drain line consists of the inductances Ld associated with the out-
put capacities Cds and the current generators gm Vg . This line is distin-
guished by periodically distributed current generators. It is also char-
acterized by its attenuation coefficient 𝛼 d , phase constant 𝛽 d and its Fig. 7. Evolution of the: characteristic impedance of the (a) gate and (b) drain
lines.
characteristic impedance Z0d .
√
Ld 1
𝛼d = √ (4) 6 × 15𝜇 m transistor with a bias Vds = 3V and Vgs = −0.3V is used.
Cds Rds 4 − Ld Cds 𝜔2
Table 1 gives us, the values of small-signal pHEMT elements of simpli-
Ld Cds 𝜔2 fied equivalent diagram as well as the values of inductors Lg and Ld
𝛽 d = Arccos(1 − ) (5)
2 calculated at a characteristic impedances of 50Ω.
√ √ From Fig. 7, the real part of the gate line remains near 50Ω and the
Ld 𝜔 2 1 imaginary part is almost zero for frequencies lower than 20 GHz. For
Z0d = 1−( ) − (6)
Cds 𝜔cd 1 + j 𝜔𝜔 the drain line, the real part is less than 50Ω and the imaginary part
d
increases with the frequency. This phenomenon is due to losses on the
2 1
Where ∶ 𝜔cd = √ and 𝜔d = drain line. So for frequencies below 20 GHz the amplifier needs a more
Ld Cds Rds Cds
complicated impedance matching circuit on the drain line.
The phase velocities can be expressed as a function of intrinsic ele- According to Fig. 8, the attenuation in the gate line varies as a func-
ments of the transistor in the form: tion of 𝜔2 , and the attenuation in the drain line remains invariant. It
𝜔 is therefore important to minimize the 𝛼 d parameter which depends
v𝜙d = (7)
𝛽d on the output conductance value 1/Rds or to add a more complicated
impedance matching circuit to the drain line. The phase velocities of the
𝜔
v𝜙g = (8) two lines are different and the ratio v𝜙d ∕v𝜙g is equal to the ratio of the
𝛽g
capacitances Cgs /Cds . The equality of the input and output capacitance
We evaluate the characteristic impedances of the drain and gate is therefore necessary to realize v𝜙d = v𝜙g , and the currents supplied
lines as a function of frequency. This allows us to study the input and by each stage are in phase at the level of each cell and add up. We
output adaptation conditions of the amplifier over the entire band. usually have Cgs > Cds . In order to compensate for this difference, it
The characteristic impedances depend on the intrinsic elements is possible to add a capacitor, denoted C0 , in parallel with Cds where,
of the transistor. In order to extract the values of these elements, a Cgs = C0 +Cds .

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M. El Bakkali et al. Microelectronics Journal 108 (2021) 104970

Fig. 10. Evolution of gate-drain (Cgd ) capacities of Common source “CS” and
common source-common gate “CS-CG” structures as a function of frequency.

Fig. 8. (a) Attenuation on the drain and gate line, (b) Phase velocities on gate
and drain lines.

Fig. 9. (a) Common gate transistor; (b) Cascode configuration “Common source
- Common gate”.

2.4. The proposed UWB LNA

The use of a cascode structure as an elementary cell makes the

losses in the output line compensate and gives a lower output conduc-
tance value than a common source transistor. In addition, this struc-
ture presents on each of the elementary cells a weak Miller effect. This Fig. 11. (a) Variation of S21 and (b) NF as a function of number of cells “n”.
improves the isolation of the cell and decreases the values of the input
and output capacitors, which gives a flat gain operation over a larger imizes the gain and the other minimizes the noise figure.
frequency band. The expression of the gain is [24]:
From Figs. 9 and 10, the gate-drain capacitance Cgd of the cascode (gm Z0d Z0g )
configuration is decreased compared to a common source transistor. |S21 |2 = n2 (9)
4
This property allows having a better unilaterality and guaranteeing a
The noise figure of a distributed amplifier given by the simplified
flat gain over a wide frequency band.
Beyer model [25] is:
The optimal number of elementary cells of the amplifier is deter-
mined from two optimal numbers, optimum cell number for the gain nZg 𝜔2 C2gs R 4P
S21 and the optimal cell number for the noise figure NF. The first max- NF ≅ 10log(1 + + ) (10)
3gm nZg gm

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M. El Bakkali et al. Microelectronics Journal 108 (2021) 104970

Fig. 12. UWB Low noise amplifier with “n” cells.

Where, P and R are two numerical factors that vary with the drain Table 2
current. In order to evaluate the parameter S21 and the noise figure NF, Gate and drain cell parameters.
we realize an amplifier with n cells.
Cin (fF) Cout (fF) Co (fF) Ld (nH) Lg (nH)
Fig. 11 show that the gain S21 increases and noise figure decreases
260 181.3 78.3 0.65 0.65
with the number of cells. From 4 cells, the chip surface continues to
increase but the two parameters S21 and NF do not change any more
significantly. The optimal number of cells chosen is 4.
Our choice fell on the classical distributed amplifier using the cas-
code configuration as an elementary cell. This amplifier has one of the
best figures of merit (FOM>2) [26], gain (S21 ) >14 dB and noise figure
NF < 3 dB over wide frequency band with a reasonable consumption.

|S21 |.BW(GHz).IIP3(mW)
FOM = (11)
(NF − 1).Pdc (mW)

Where NF is the linear noise figure, Pdc is the dissipated power, BW

is the bandwidth at −10dB and IIP3 is the third order input intercept
point of the amplifier.

3. Results and discussions

The ultra wideband LNA in Fig. 12 uses the cascode configuration

with 4 cells. A capacitance C0 is added in parallel with the output
capacitance Cout of elementary cell. It compensates for the difference
between Cout and the input capacitance Cin of the elementary cell. The Fig. 13. The scattering parameters [S] of distributed low noise amplifier with
values of Cin and Cout are extracted from the imaginary part of the input initiation values of Lg , Ld and C0 .
impedance and the output admittance of the elementary cell. The value
of C0 equal Cin -Cout . The inductive line “L” is added to each cascode
cell to perform a “peaking”. This technique is used to extend bandwidth
and achieve maximum flat gain by resonating an attenuation pole. The The power gain remains almost invariant throughout the frequency
biases of the transistors are fed via the drain and gate lines. The induc- band studied (15.08 ± 0.4 dB). The input and output reflection coeffi-
tors, named respectively L1 and L2 , must be dimensioned in order to cients are less than −10 dB over a frequency range of 4 GHz–12 GHz
have high impedance with respect to the RF signals. The module of the with an average noise figure of 2.84 dB as shown in Fig. 14.
impedances ZLd and ZLg of these inductances is written: We improve the performance of the distributed amplifier with the
use of real elements provided by OMMIC foundry. Its values are opti-
|ZLd | = 2𝜋.f.L1 (12) mized to have the desired results.
We will add a reactive stability circuit constituting Ls and Cs in par-
allel with a resistor Rs which ensures the bias of the circuit. This circuit
|ZLg | = 2𝜋.f.L2 (13) is set in series on the gate access of the common gate transistor. This
method slightly affects the transconductance of the cell and has a better
In order to ensure a good transmission of RF signals, ZLd and ZLg stability for the amplifier.
must be greater than 4 times the values of characteristic impedance of From Fig. 15, the amplifier in its initial state is unstable in this band
the drain and gate lines to the minimum operating frequency (3 GHz). of frequency. After the addition of the Ls Cs circuit, the stability fac-
The gate and drain lines are made by ideal inductors respectively tor becomes greater than unity, which shows that our amplifiers are
Lg and Ld . They are closed by charges 50Ω. We show the values of the unconditionally stable.
elements of the rows in Table 2. From the optimized values of the real elements presented in Table 3,
Fig. 13 show the evolution of the scattering parameters [S] of the we find that the noise figure varies slightly in the frequency band from
UWB distributed LNA according to the initiation parameters Lg , Ld and 1 GHz up to 12 GHz, hence NF= (2.9 ± 0.58)dB. Outside this band the
C0 . noise figure becomes very high as shown in Fig. 16.

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M. El Bakkali et al. Microelectronics Journal 108 (2021) 104970

Table 3
The optimized real parameters of the ultra wideband distributed low noise amplifier.
Lg (nH) Ld (nH) Co (pF) Ls (nH) Cs (pF) Rs (Ω) C1 &C2 (pF) R1 &R2 (Ω)
1 1 0.142 0.7 1 10 1.35 50

Fig. 14. Noise figure of distributed low noise amplifier with initiation values of
Fig. 16. Evolution of noise figure NF of the distributed low noise amplifier.
Lg , Ld and C0 .

Fig. 17. The optimized scattering parameters [S] of the ultra wideband dis-
Fig. 15. Evolution of the stability factor as a function of frequency. tributed LNA.

From Fig. 17, the input S11 and output S22 reflection coefficients of
our distributed low noise amplifier are adapted such that its values are
less than −10dB on a frequency band of 3 GHz–14.5 GHz. On the other
hand, the 4 GHz–12 GHz band is characterized by better adaptation (S11
and S22 are less than −15dB) can be used in C-band (4 GHz–8 GHz) and
X-band (8 GHz–12 GHz) applications.
The small-signal gain S21 remains almost invariant with an average
value of 16.9 dB and low ripple of 1.7 dB over the 3.1 GHz–12 GHz.
Then, this gain begins to decrease.
The low noise amplifier is considered linear only if the compression
point P1dB and the third input intercept point IIP3 values are high. We
generated at the input of the distributed amplifier a two-Tone signal
(Pin1 and Pin2 ) of frequency F and spacing of 1 [Link]: Pin1 : with
a frequency of (F - 0.001) GHz.
Pin2 : with a frequency of (F + 0.001) GHz.
F 𝜖 {2–12} Fig. 18. The linearity of the distributed low noise amplifier.
IIP3 is determined from the intersection of the fundamental output
power and third order output power IM3.
UWB LNA designed has good linearity as shown in Fig. 18. The max- value decreases gradually with frequency, such that its minimum value
imum value of IIP3 is 6.4dBm measured at the frequency of 2 GHz. This found at 12 GHz is 4dBm.

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M. El Bakkali et al. Microelectronics Journal 108 (2021) 104970

Table 4
Performance summary of the proposed LNA and recent works. (∗ average value).
[12] [13] [27] [28] [29] [30] [31] This work
Data Measured Simulated Simulated Simulated Measured Simulated Measured Simulated
Techno (𝜇 m) 0.25-GaN 0.2-GaN 0.18-CMOS 0.18-NMOS 0.18-CMOS 0.18-CMOS 0.1-GaAs 0.18-GaAs
State Cascode Cascade Cascode Cascode Cascode Cascode Cascode Cascode
BW (GHz) 1–12 4.5–8 3.1–10.6 5–10.6 5–11 3.2–10.6 2–40 3–12
S11 (dB) <-10 NA <-9.5 <-8.5 <-3 <-7.5 <-5 <-10
S22 (dB) <-10 NA NA NA NA <-15 <-3 <-10
S21 (dB) 12 ± 1.5 11 Max 12.1 ± 0.7 16.15 ± 5.8 14.5 Max 17 Max 15.3∗ 16.9 ± 1.7
S12 (dB) NA NA NA NA NA <-45 NA <-35
NF (dB) 4.5 ± 1 1.4 Min 4.63 ± 0.07 3.8 ± 1.8 3.18 Min 4.1 ± 1.6 2.3∗ 2.9 ± 0.58
IIP3 (dBm) NA NA NA −14@5 GHz −16@8 GHz NA NA 5@5 GHz
FOM 1.35 NA 1.84 NA 4.76 29.03 NA 4.34
Pdc (mW) 735 450 13.6 5.3 6.6 16.5 110 127
Die area (mm2 ) 1 × 0.99 NA NA 0.66 × 0.74 0.83 × 0.95 0.78 × 0.84 1.57 × 1.19 1.3 × 1.3

tional stability of our distributed amplifier, we used reactive circuits.

We determined the number of cells as the best compromise between
performance (gain and noise figure) and chip size. We optimized line
characteristic impedances to have input/output adaptation, minimize
the NF and a flat gain in all the frequency range studied.
The results show that the proposed LNA achieves high and flat gain
of 16.9 ± 1.7 dB, low noise figure of 2.9 ± 0.58 dB and the input-output
reflection coefficients are less than −10 dB in 3–12 GHz frequency band.

Authors contributions

El Bakkali Moustapha: Conceptualization, Methodology, Software,

Investigation, Writing - Original Draft. Taj-eddin Elhamadi: Validation,
Writing - Review & Editing, Project administration. Amar Touhami
Naima; Resources, Visualization, Supervision. Elftouh Hanae: Method-
ology, Writing - Review & Editing. Lamsali Mohammed: Latex Source
File Writing, Writing - Review & Editing.

Declaration of competing interest

The authors declare that they have no known competing financial

interests or personal relationships that could have appeared to influence
the work reported in this paper.

Fig. 19. Ultra WideBand distributed low noise amplifier Layout

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