Pass Transistors and Transmission Gates

Some properties of pass transistors and transmission gates.

• Gate logic is based on the general arrangement typified by the inverter circuits (the inverter being the
stmplest gate).

• Both Nand and Nor and, with CMOS, And and Or gate arrangements are available.

• Inverters are also employed to complement and restore logic levels that have been degraded (e.g. because
they have passed through pass transistors).

N-MOS Zpu / Zpd the channel length to width ratio for each MOS transistor as shown

In achieving the desired pull-up to pull-down ratio, several possibilities emerge, two of which are illustrated
in Figures for an 8:1 nMOS inverter.
Figure - 8:1 n-MOS inverter (minimum size p.d.) Figure - An alternative 8:1 n-MOS inverter
The nMOS (and pseudo-nMOS) L: W ratios should be carefully noted since they must be chosen to achieve the
desired overall Zp.u/ Z p d ratio (where Zpd. is contributed in this case by both input transistors in series).

Figure n-MOS, CMOS 2-input Nand gates.

The nMOS (and pseudo-nMOS) L: W ratios should be carefully noted since they must be chosen to achieve the desired
overall Zp.u/ Z p d ratio (where Zpd. is contributed in this case by both input transistors in series).

In order to arrive at the required L: W ratios for an nMOS (or pseudo-nMOS) Nand gate with n inputs, it is only necessary to
consider the very simple circuit model of the gate in the condition when all n pull-down transistors are conducting as in
Figure 6.7. The critical factor here is that the output voltage V0 u1 must be near enough to ground to turn off any following
inverter-like stages, that is
that is, the ratio between Zp.u. and the sum of all the pull-down Zp.d.s. must be 4:1 (as for the nMOS inverter).
This ratio must be adjusted appropriately if input signals are derived through pass transistors.

Further consideration of the nMOS Nand gate geometry reveals two significant factors:
1. n-MOS Nand gate area requirements are considerably greater than those of a corresponding nMOS inverter,
since not only must pull-down transistors be added in series to provide the desired number of inputs, but, as
inputs are added, so must there be a corresponding adjustment of the length of the pull-up transistor channel to
maintain the required overall ratio .

2. n-MOS Nand gate delays are also increased in direct proportion to the number of inputs added. If each pull-down
transistor is kept to minimum size (2A. x 2A.), then each will present 10Cg at its iQput, but if there are n such inputs,
.tf\en the length and resistance of the pull-up transistor must be increased by a factor of n to keep the correct ratio.
Thus, delays associated · with the nMOS Nand are

In consequence of these properties, the nMOS Nand gate is used only where absolutely necessary and the number of
inputs is restricted
Two-Input nMOS, CMOS for Gates
nMOS (or pseudo nMOS) form of Nor gate can be expanded to
accommodate any reasonable number of inputs and, in those
technologies, is preferred to the Nand gate when there is a
choice (which is usually the case if logical expressions are
suitably manipulated).

Since both 'legs' of the two-input nMOS Nor gate· provide a

path to ground from the pull-up transistor, the ratios must be
such that any one conducting pull-down leg will give the
appropriate inverter-like transfer characteristic.

Thus, each leg has the same ratio as would be the case for an
nMOS inverter. This applies irrespective of the number of
inputs accommodated.

mmodated. The area occupied by the nMOS (or pseudo-nMOS)

Nor gate is reasonable since the pull-up transistor dimensions
are unaffected by the number of inputs accommodated.
Why NAND structures are preferred over NOR ones?
Both NAND and NOR are classified as universal gates, but we see that NAND is preferred over NOR in CMOS logic
structures. Let us discuss why it is so:

We know that when output is at logic 1, pull up structure for the output stage is on and it provides a path from VDD to
output. Similarly, pull down structure provides a path from GND to output when output is logic 0. Pull up and pull down
resistances are one of major factor in determining the speed of cell. The inverse of pull up and pull down resistances are
called output high drive and output low drive of the cell respectively. In general, cells are designed to have similar drive
strength of pull up and pull down structures to have comparable rise and fall time.

NMOS has half the resistance of an equal sized PMOS. let us say resistance of a given sized NMOS is R then resistance
of PMOS of same size will be 2R. In NAND gate, two NMOS are connected in series and two PMOS are connected in
parallel. So, pull up and pull down resistances will be:

Pull up resistance = 2R || 2R = R
Pull down resistance = R + R = 2R
 On the other hand, in a NOR gate, two NMOS are connected in parallel and two PMOS are connected in series. The
pull-up and pull-down resistances, now, will be:

Pull up resistance = 2R + 2R = 4R
Pull down resistance = R || R = R/2

NAND gate has better ratio of output high drive and output low drive as compared to NOR gate. Hence NAND gate is
preferred over NOR.

To use NOR gate as universal gate either pull up or pull down structure has to be resized(decrease the length of PMOS
cells or increase length of NMOS cells) to have similar resistance as resistance is directly proportional to length (length
of channel here).
Other Forms of CMOS Logic
The availability of both n- and p-transistors makes it possible for the CMOS designer to
explore and exploit various alternatives to inverter-based CMOS logic.

Pseudo-nMOS logic

Clearly, if we replace the depletion mode pull-up transistor of

the standard nMOS circuits with a p-transistor with gate
connected to VSS, we have a structure similar to the nMOS
equivalent.

This approach to logic design is illustrated by the three-input

Nand gate. The circuit arrangements look and behave much like
nMOS circuits and appropriate ratio rules must be applied.

Pseudo-nMOS Nand gate.

 Dynamic CMOS logic

Dynamic circuit class, which relies on temporary storage of signal values on the capacitance of high-
impedance circuit nodes. In this section, an alternate logic style called dynamic logic is presented
that obtains a similar result, while avoiding static power consumption. With the addition of a clock
input, it uses a sequence of precharge and conditional evaluation phases.

The basic construction of an (n-type) dynamic logic gate is shown in Figure. The PDN (pull-down
network) is constructed exactly as in complementary CMOS. The operation of this circuit is divided
into two major phases: precharge and evaluation, with the mode of operation determined by the
clock signal CLK.
Charge Sharing Problem