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IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS 1

A High-PSRR NMOS LDO Regulator With

Intrinsic Gain-Tracking Ripple
Cancellation Technique
Jung Sik Kim , Seunggyun Ha, Graduate Student Member, IEEE,
Hongyup Jeong, Graduate Student Member, IEEE,
and Jeongjin Roh , Senior Member, IEEE

Abstract— This paper presents an NMOS low dropout (LDO)

regulator with a high-power supply rejection ratio (PSRR) and
low quiescent current that uses an intrinsic gain-tracking ripple
cancellation (IGTRC) technique with an adaptive biasing scheme.
The proposed LDO is fabricated using a 180 nm CMOS process
and achieves a quiescent current of 3.7 µA with superior figure-
of-merits (FOMs) of 7.6E9 (FOM1) and 0.005 ps (FOM2).
Index Terms— Intrinsic gain-tracking ripple cancellation
(IGTRC), loop-gain stabilization, high power supply rejec-
tion ratio (PSRR), low quiescent current, low drop-out
regulator (LDO).

I. I NTRODUCTION

M ANY power management integrated circuits (PMICs)

use high-efficiency switch-mode power supplies
(SMPSs) to convert DC levels, resulting in noisy voltage
ripples (VIN ). To generate a clean supply voltage, a low-
dropout (LDO) regulator is subsequently positioned after the Fig. 1. Conceptual block diagram of a battery-powered PMIC with an NMOS
SMPS. Unlike the PMOS LDOs, the NMOS LDOs require LDO [1].
high gate voltage, so circuits other than the pass transistor
(MPT ) often receive direct power from the battery. This an LDO. However, multi-gain stages require a large quiescent
arrangement is depicted in Fig. 1 [1], [2], [3], [4], [5]. current (IQ ) to maintain the high frequency of their internal
Several state-of-the-art techniques have been proposed to
non-dominant poles [10].
improve the power supply rejection ratio (PSRR) performance
In [11], [12], [13], [14], and [15], a feedforward technique
of LDOs [7], [8], [9], [11], [12], [13], [14], [15]. In [7], was employed to enhance the PSRR performance. For
[8], and [9], multiple small-gain stages were implemented to PMOS LDOs, VIN ripples were incorporated into the main
increase the loop gain and enhance the PSRR performance of control loop to improve the PSRR [11], [12], [13], [14].
Manuscript received 1 April 2024; revised 31 May 2024 and 16 June However, this feedforward technique typically requires three
2024; accepted 23 June 2024. This work was supported in part by the or more amplifiers, resulting in significant increases in
Technology Innovation Program, Development of Half-Bridge Driving IC with IQ and design complexity. Additionally, achieving PSRR
Built-in Precision DT Control Circuit for 650V High-Speed Switching GaN
Driving through MOTIE Korea under Grant RS-2024-00402382; in part by improvement becomes challenging when the feedforward gain
Korea Evaluation Institute of Industrial Technology (KEIT), Development varies with changes in VIN , output voltage (VOUT ), and load
of Integrated Power System with Embedded GaN Device for Intelligent current (IL ).
Multi-LED Headlamp of Electric Vehicle through MOTIE Korea under Grant
00154973; and in part by the Technology Innovation Program, BMS IC For NMOS LDOs, the conventional approach shown in
Development for Electric Vehicles Featuring Active Cell Balancing and Fig. 2(a) incorporates a signal representing the intrinsic gain of
Wireless Control through MOTIE Korea under Grant RS-2024-00403397. the replica pass transistor (MRPT ) into the main control loop to
This article was recommended by Associate Editor J. Anders. (Corresponding
author: Jeongjin Roh.) improve the PSRR performance [15]. However, generating the
The authors are with the Department of Electronics Engineering, Hanyang appropriate intrinsic gain of the MPT through MRPT requires
University, Ansan 15588, South Korea (e-mail: [email protected]). an additional adaptive reference voltage (VREF2 ) that adjusts
Color versions of one or more figures in this article are available at
https://doi.org/10.1109/TCSI.2024.3422001. to according to variations in VOUT and VIN of the LDO.
Digital Object Identifier 10.1109/TCSI.2024.3422001 Moreover, the noise amplitude of the switching converter’s
1549-8328 © 2024 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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2 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 3. Block diagram of the intrinsic gain-tracking ripple cancellation

technique.
Fig. 2. Conceptual block diagram of intrinsic gain feed-forward ripple
cancellation: (a) conventional LDO and (b) proposed LDO.

output voltage should be minimized to ensure enhanced PSRR

performance when using this technique.
To overcome the disadvantages of the conventional intrinsic
gain feedforward technique, the proposed LDO generates an
intrinsic gain signal through MRPT , which is configured as a
source follower. MPT and MRPT share gate and drain voltages
and have similar current densities, meaning their the DC
operating points are the same. Consequently, it can generate
a robust intrinsic gain signal without requiring additional
auxiliary amplifiers (AUX OTA) or VREF2 . Moreover, the LDO
is independent of the noise amplitude from the switching
converter’s output voltage. Additionally, this approach enables Fig. 4. Small signal model of the proposed LDO for PSRR analysis.
a reduction in IQ and simplifies the circuit structure. The
LDO requires two power supplies: VBAT and VIN . VBAT
is the battery voltage and powers the EA, SA, and sub-
clocks, whereas VIN is the output voltage of the switching
regulator [15].
This paper is organized as follows: Section II presents the
proposed IGTRC technique, including the circuit implemen-
tation of the proposed LDO, PSRR analysis, and stability
analysis. Section III presents the measurement results and
Section IV concludes the paper.

II. P ROPOSED I NTRINSIC G AIN -T RACKING R IPPLE

C ANCELLATION LDO
Fig. 5. Mathematical model of the proposed LDO for PSRR analysis.
As shown in Fig. 3, the block diagram of the proposed
IGTRC LDO consists of the following stages: the error
amplifier (EA) and compensation, summing, intrinsic gain- MRPT is supplied with an adaptive bias current from the
tracking, and current sensing. Furthermore, Fig. 3 includes current sensing stage to achieve a similar current density as the
MPT , MRPT , a buffer (B), an output capacitor (CL ), MPT . Additionally, since MRPT shares the same gate and drain
an equivalent series resistor (RESR ) representing the parasitic voltages with MPT , their operating conditions are the same,
component of CL , and a load resistor (RL ) modeling IL . resulting in them having the same intrinsic gain. Consequently,
The EA forms the main control loop of the LDO and the intrinsic gain-tracking stage generates a signal that matches
senses the VOUT to generate an error signal. Simultaneously, the intrinsic gain of MPT .
the compensation stage consists of a series connection of a As a result, the signal generated by the intrinsic gain-
capacitor, resistor, and transistor. The transistor adjusts the tracking stage and the error signal from the EA are
series resistance in proportion to IL , generating the zero for simultaneously summed by the SA, resulting in improved
frequency compensation [3]. PSRR performance (> 50 dB up to 10 MHz) for a wide IL

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KIM et al.: HIGH-PSRR NMOS LDO REGULATOR WITH IGTRC TECHNIQUE 3

Fig. 7. Monte Carlo simulation results of PSRR for 1000 samples of

the proposed LDO when IL = 100 mA at (a) 100 kHz, (b) 1 MHz, and
(c) 10 MHz.

A. Intrinsic Gain-Tracking Ripple Cancellation Technique

For PSRR analysis of the proposed IGTRC LDO, a small-
signal model based on VIN is shown in Fig. 4, was employed
where CZ is the compensation capacitor, Cp(SA) is the parasitic
capacitance of the SA, and gm(EA) is the transconductance
of the EA. In addition, gm(PT) and gm(RPT) are the
transconductances of MPT and MRPT , respectively; ro(EA) ,
ro(SA) , ro(PT) , ro(RPT) , and ro(SEN) are the output resistances
of the EA, SA, MPT , MRPT , and the transistor supplying
current to MRPT , respectively; RZT is the compensation zero-
generation resistance; and RFB1 and RFB2 are the feedback
resistors of the SA.
As shown in Fig. 4, the proposed LDO achieves improved
PSRR by synthesizing the two signal paths from VIN to VOUT .
Fig. 6. PSRR post-layout simulation results of the LDO for (a) conventional, The first path involves the finite ro(PT) of MPT , which serves as
(b) proposed IGTRC, and (c) improvement of PSRR with IL variation.
the inherent main path for ripple noise affecting VOUT . Under
heavy load conditions, the PSRR is degraded due to the inverse
proportionality of ro(PT) to IL .
range (100 µA–100 mA). A detailed analysis is provided in The second path involves the IGTRC signal path generated
Sections II-A to II-C. by MRPT in response to VIN . Consequently, the IGTRC

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4 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

the current density between MPT and MRPT . Consequently,

they have the same current density, which results in the same
source voltages.
Under these conditions, MRPT has the same gate-source
voltage, gate-drain voltage, drain-source voltage, and current
density as MPT . Consequently, MRPT and MPT have the same
intrinsic gain. The aspect ratio of MPT and MRPT was set
to 1/466 to significantly reduce both IQ under heavy load
conditions and the design area. As a result, the operating
environment of MRPT becomes similar to MPT for all IL ,
resulting in similar intrinsic gains for both transistors.
Second, if the first condition is satisfied, the condition for
Fig. 8. Small signal model of the proposed LDO for stability analysis. setting the numerator to zero in (2) is that the ratio of RFB2
to RFB1 should be large, which can be expressed as

R F B2 /R F B1 R
F B2

≃ 1, ≫1 . (3)
1 + R F B2 /R F B1 R F B1

If the two conditions are satisfied, the numerator of (2)

approaches zero, enhancing the PSRR performance. However,
an excessive resistance ratio can increase the parasitic
capacitance, resulting in stability issues, as discussed in
Section II-B. Additionally, the EA and SA are not affected
by VIN because they are powered by VBAT .
Fig. 6(a) and (b) show the post-layout simulated PSRR
performance of the conventional and proposed IGTRC LDOs,
Fig. 9. Mathematical model of the proposed LDO for stability analysis. respectively, under 100 µA, 1 mA, 10 mA, 50 mA, and
100 mA IL conditions. Fig. 6(c) presents a comparison of
signal and the inherent signal are simultaneously input to the the post-layout simulated PSRR between the conventional and
summing stage. This means that the IGTRC signal is input IGTRC LDOs across varying IL conditions at frequencies of
to the inverting input of the operational amplifier, while the 10 kHz, 1 MHz, and 10 MHz, respectively. As shown in
inherent signal is input to the non-inverting input. Hence, these Fig. 6(c), the PSRR improvement ranges from 3 dB to 55 dB
two signals are synthesized at the SA output. as IL was varied at a low frequency (10 kHz).
The mathematical model is shown in Fig. 5, where However, under light load conditions, the PSRR improve-
Z(s), ASA (s), and AEA (s) represent the compensation zero, ment at frequencies beyond 10 kHz was further degraded
SA loop gain, and EA loop gain, respectively. Assuming due to the bandwidth limitation of the SA. The lowest
1 ≫ (1 + RFB2 /RFB1 )/ASUM (s), 1 ≫ 1/gm(MRPT) ro(MRPT) , improvement occurred under light load conditions due to the
and ro(ISEN) ≫ ro(RPT) [16], the transfer function from VIN to substantial IQ decrease in the SA, causing a larger SA offset
VOUT is defined by (2), as shown at the bottom of the page. current. This offset current flows through RFB1 and RFB2 ,
The PSRR can be significantly improved by minimizing (2) reducing linearity [21]. However, under light loads, the high
through setting its numerator to zero, as expressed in (1). inherent PSRR resulted from the increased ro(PT) .
Equation (1) summarizes the two optimal conditions to When comparing the conventional LDO with the proposed
enhance the PSRR IGTRC LDO, the comparison was conducted by removing the
intrinsic gain tracking stage and summing stages to maintain
(R F B2 /R F B1 )gm(P T )ro(P T )
= 1. (1) the same main control loop.
(1 + R F B2 /R F B1 )gm(R P T )ro(R P T ) If noise occurs in VBAT , the finite gains of EA and
First, MPT and MRPT should have similar intrinsic gains SA can affect VOUT . This can be analyzed as shown in
according to IL , meaning their DC operating points should be equation (4), where PSRR(s)EA is the PSRR of the EA,
matched. As demonstrated in Fig. 3, the proposed structure PSRR(s)SA is the PSRR of the SA, and T(s)gloabal is the loop
enables MRPT to share gate and drain nodes with MPT , gain of LDO [11]. Equation (4) shows that the finite PSRR
receiving current supply from the sensing stage, equalizing due to EA and SA is an amplified quantity of PSRR(s)EA

(R F B2 /R F B1 )gm(P T )ro(P T )
1−
VOU T (1 + R F B2 /R F B1 )gm(R P T )ro(R P T )
P S R R(s) = = ro(P T ) (2)
VI N 1 + gm(P T )ro(P T ) (1 + A E A (s)Z (s)) +
ZL

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KIM et al.: HIGH-PSRR NMOS LDO REGULATOR WITH IGTRC TECHNIQUE 5

Fig. 10. (a) Cross section of a poly resistor and subcircuit models,
and (b) simplified II-section model of the poly resistor and an expected
representation of Cp(SA) .

and PSRR(s)SA .
T (s)global
P S R R(s)| E A&S A = (P S R R E A + P S R R S A ).
1 + T (s)global
(4)
Fig. 7 presents the statistics from a 1,000-run Monte Carlo
simulation, displaying results at 100 kHz, 1 MHz, and 10 MHz
under maximum IL . The mean PSRR values (µ) were 84.8 dB
at 100 kHz, 83.2 dB at 1 MHz, and 61.1 dB at 10 MHz
Fig. 11. (a) AC post-layout simulation results of the proposed LDO. (b) Phase
with corresponding standard deviations (α) of 8.4 dB, 4.7 dB, margin with IL versus process corner, supply voltage, and temperature
and 0.9 dB, respectively. It should be noted that the parasitic variation.
capacitance components are not reflected in Fig. 7, and the
Monte Carlo simulation results of the LDO were conducted terminal of the EA by CZ and ro(EA) . The third non-dominant
under the following conditions: VIN = 1.4 V, VREF = 1.2 V, pole (ω p3 ) is generated from the signal synthesis of the main
VBAT = 3.8 V, and 27 ◦ C. control loops and the IGTRC loop in the SA.
In applications requiring very high load currents (>1A), As indicated in (3), a large value for RFB2 is required
there could be performance variations due to the mismatch to enhance the PSRR performance, resulting in significant
between MPT and MRPT and current sensing inaccuracies. parasitic capacitance due to the large area of RFB2 . For SA to
Thus, further research into techniques that can enhance have sufficient gain, ro(SA) should also have a sufficient value.
matching performance will be required in future studies. Under both conditions, ω p3 moves to a lower frequency
1
ω p1 = (5)
B. Stability Analysis C L (ro(P T ) ∥ Z L )
In the proposed design, the signal paths of each loop are 1
ω p2 = (6)
superimposed at the gates of MPT and MRPT , as depicted C Z (ro(E A) + R Z )
in Fig. 8. The two loops have distinct functions, where the 1
IGTRC loop containing MRPT , B, and SA functions as a ripple ω p3 =  (7)
 1 + R F B2 /R F B1
cancellation loop to improve the PSRR, and the main control C p(S A)ro(S A)
gm(S A)ro(S A) + 1 + R F B2 /R F B1
loop feeds VOUT back to the EA to regulate VOUT .
1
To analyze the global loop stability (T(s)global ), open- ωz1 = (8)
loop AC analysis was performed by opening the loop at CZ RZ
1
the summing stage output, as modeled in Fig. 9 and based ωz2 = (9)
on Fig. 8 [22]. Assuming 1 ≫ (1 + RFF2 /RFF1 )/ASUM (s) CL RE S R
[16], the overall loop gain transfer function of the LDO as Cp(SA) increases, indicating the deteriorating phase margin
is defined by (10), as shown at the bottom of the next and stability of the LDO under large values of Cp(SA) .
page, which contains three poles and two zeros that can be Therefore, to mitigate stability issues while improving
expressed as (5)-(9). PSRR performance, high sheet-resistance resistors with low
The dominant pole (ω p1 ) is generated by CL , while the parasitic capacitance should be used. High sheet resistance
second non-dominant pole (ω p2 ) is generated at the output poly-resistors have lower parasitic capacitance compared to

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6 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 12. Transistor-level circuit implementation of the IGTRC LDO.

other resistors because they can be placed on top of a thick In the presented design, RFB1 and RFB2 were constructed
oxide [18]. using unit resistors, each with a resistance of 20.1 k. RFB1
Fig. 10(a) shows the cross-sectional layout of a typical consisted of 9 units connected in parallel, and RFB2 consisted
poly-resistor. The resistor is surrounded by oxides on all of 16 units connected in series. Therefore, the resistance ratio
sides, which provides capacitive dielectric coupling of the between RFB1 and RFB2 was approximately 160. RFB2 had
resistor to neighboring components. This parasitic capacitance a poly area of 53.44 µm2 , resulting in parasitic capacitance
is uniformly distributed along the poly-resistor, where the Cp(SA) of approximately 29.3 fF.
deposited and field oxides have capacitances of 0.5 fF/µm2 The first zero (ωz1 ) is generated at the output terminal of the
and 0.05 µm2 , respectively [19]. EA through the series connection of CZ , RZ , and a transistor.
Therefore, as shown in Fig. 10(b), Cp(SA) can be defined This transistor adjusts the series resistance to be inversely
as the sum of the parasitic capacitance of the poly resistor. proportional to IL to compensate for the second non-dominant
Consequently, the total parasitic capacitance of both oxides is pole [3]. The second zero (ωz2 ) is induced by the equivalent
0.55 fF/µm2 . series resistance (ESR) of CL .

Vol,out
= T (s)global
Vol.in
 
R F B1
−gm(E A)ro(E A) 1 + (1 + sC Z R Z )(1 + sC L R E S R )
R F B2
≃ (10)
1 + R F B2 /R F B1
  
{1 + sC L (ro(P T ) ||Z L )}{1 + sC Z (ro(E A) + R Z )} 1 + sC p(S A)ro(S A)
gm(S A)ro(S A) + 1 + R F B2 /R F B1

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KIM et al.: HIGH-PSRR NMOS LDO REGULATOR WITH IGTRC TECHNIQUE 7

Fig. 13. Microchip photograph and test PCB.

Fig. 14. Block diagram of the PSRR measurement setup.

The post-layout AC simulation results in Fig. 11 demon-

strate the stability of the proposed LDO. The loop gain and
phase response of T(s)global under different IL values (ranging
from 100 µA to 100 mA) are shown in Fig. 11(a).
Fig. 11(b) shows the variations in phase margin with
changes in IL under process corner, supply voltage, and
temperature (PVT) variations. The phase margins for the cases
when IL = 100 mA, 50 mA, 10 mA, 1 mA, and 100 µA
were 58◦ , 86◦ , 96◦ , 110◦ , and 49◦ , respectively. The worst-
case phase margin was 35◦ , demonstrating the robust stability
of the proposed LDO.

C. Transistor-Level Circuit Implementation

Fig. 12 shows the transistor implementation of the proposed
IGTRC-LDO. The EA uses active current sources with a
high output impedance as the active loads [20]. An internal
feedback loop formed by transistors M10 -M13 increases the
ro(EA) and gm(EA) . The SA employs a conventional OTA to
synthesize signals for the main control and the IGTRC loops.
Both the EA and SA employ adaptive biasing to reduce IQ
consumption.
A series connection of RZ , M18 , and CZ generates a zero Fig. 15. Measured PSRR when (a) IL = 0.1 mA, (b) IL = 50 mA,
to compensate the non-dominant pole by adjusting drain-to- (c) IL = 100 mA.
source resistance of M18 via adaptive bias. A buffer between
the SA and MPT isolates the large MPT gate capacitance, during transients [21]. To mitigate large excursions, a
thereby improving the loop stability and transient response. 1 pF CLF and 1 M RLF form a low-pass filter (LPF).
This buffer utilizes an impedance attenuation technique [17]. Additionally, to minimize the effects of parasitic capacitances
In Fig. 12, the current sensor includes transistors M33 - and inductances, low-pass filters are placed on each of the
M38 and bias currents (IB(ISEN1) ) and (IB(ISEN2) ). The current current mirror branches close to the circuit blocks.
sense circuit forces the drain voltages of MRPT and M38 to be
equal so that the current sense error due to the drain-to-source III. M EASUREMENT R ESULTS
voltage difference between MRPT and M38 is minimized. The The LDO was fabricated using 0.18 µm CMOS technology,
sensing ratio is defined as M38 /MPT to enable the adaptive and chip micrograph is shown in Fig. 13. The total active area
biasing technique [3]. of the LDO was 0.022 mm2 . Fig. 14 shows the measurement
Furthermore, amplifiers can exhibit nonlinear large-signal setup for PSRR. A Rohde schwarz FPL1003 spectrum analyzer
step responses due to significant bias voltage and current was used to measure the PSRR of the proposed LDO.
excursions, causing pole and zero frequencies to vary In addition, the measurement setup included an Agilent U3401

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8 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

Fig. 16. Measured (a) load regulation, (b) line regulation (IL = 100 mA), (c) quiescent current, (d) load transient response for a IL step of 100 mA, (e) line
transient response for a VIN step of 1 V (IL = 100 mA).

TABLE I
P ERFORMANCE S UMMARY AND C OMPARISON W ITH S TATE - OF - THE -A RT LDO S

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KIM et al.: HIGH-PSRR NMOS LDO REGULATOR WITH IGTRC TECHNIQUE 9

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changes from 0 to 100 mA. Under heavy load conditions, the [12] Y.-S. Yuk, S. Jung, C. Kim, H.-D. Gwon, S. Choi, and G.-H. Cho, “PSR
current efficiency is 98.2 % [26]. enhancement through super gain boosting and differential feed-forward
Fig. 16(d) shows the change in the IL from 100 µA to noise cancellation in a 65-nm CMOS LDO regulator,” IEEE Trans.
Very Large Scale Integr. (VLSI) Syst., vol. 22, no. 10, pp. 2181–2191,
100 mA at an edge time of 100 ns. The measured undershoot Oct. 2014.
and overshoot voltages were 33 and 17 mV, respectively, and [13] S. J. Yun, J. S. Yun, and Y. S. Kim, “Capless LDO regulator achieving
the IGTRC LDO settled in 2.6 µs (TS ). The measured line −76 dB PSR and 96.3 fs FOM,” IEEE Trans. Circuits Syst. II, Exp.
Briefs, vol. 64, no. 10, pp. 1147–1151, Oct. 2017.
transient response with a change in the VIN from 1.4 to 2.4 V [14] K. Joshi, S. Manandhar, and B. Bakkaloglu, “A 5.6 µA wide bandwidth,
at an edge time of 200 ns under maximum load conditions is high power supply rejection linear low-dropout regulator with 68 dB
shown in Fig. 16(e). of PSR up to 2 MHz,” IEEE J. Solid-State Circuits, vol. 55, no. 8,
pp. 2151–2160, Aug. 2020.
IV. C ONCLUSION [15] J. Jiang, W. Shu, and J. S. Chang, “A 65-nm CMOS low dropout
regulator featuring >60-dB PSRR over 10-MHz frequency range and
In this paper, a high PSRR LDO and designed IGTRC 100-mA load current range,” IEEE J. Solid-State Circuits, vol. 53, no. 8,
technique were proposed. This technique used MRPT and SA pp. 2331–2342, Aug. 2018.
in the IGTRC loop for PSRR enhancement. The measured [16] A. S. Sedra and K. C. Smith, Microelectronic Circuits, 8th ed. Oxford,
results verified the operation of the proposed IGTRC technique U.K.: Oxford Univ. Press, 2020.
[17] M. Al-Shyoukh, H. Lee, and R. Perez, “A transient-enhanced
over wide ranges of IL and frequencies. The proposed LDO low-quiescent current low-dropout regulator with buffer impedance
achieved a PSRR of 50 dB up to 10 MHz with 3.7 µA of attenuation,” IEEE J. Solid-State Circuits, vol. 42, no. 8, pp. 1732–1742,
IQ , along with FoM1 and FoM2 values of 7.6E9 and 0.005 ps, Aug. 2007.
[18] Y. P. Tsividis, Mixed Analog-Digital VLSI Devices and Technology: An
respectively. The measurement results, along with the high Introduction. New York, NY, USA: McGraw-Hill, 1996, pp. 205–257.
PSRR and low IQ presented in Table I, verified the superior [19] A. Hastings, The Art of Analog Layout, 2nd ed., Upper Saddle River,
FoM of the proposed LDO. NJ, USA: Pearson, 2005.
[20] J. Roh, “High-gain class-AB OTA with low quiescent current,” Anal.
ACKNOWLEDGMENT Integr. Circuits Signal Process., vol. 47, no. 2, pp. 225–228, May 2006.
The EDA tool was supported by the IC Design Education [21] B. Razavi, Design of Analog CMOS Integrated Circuits, 2nd ed.,
New York, NY, USA: McGraw-Hill, 2015.
Center (IDEC), South Korea. [22] G. Li, H. Qian, J. Guo, B. Mo, Y. Lu, and D. Chen, “Dual active-
feedback frequency compensation for output-capacitorless LDO with
R EFERENCES transient and stability enhancement in 65-nm CMOS,” IEEE Trans.
[1] K. Li, C. Yang, T. Guo, and Y. Zheng, “A multi-loop slew-rate- Power Electron., vol. 35, no. 1, pp. 415–429, Jan. 2020.
enhanced NMOS LDO handling 1-a-load-current step with fast transient [23] A. P. Patel and G. A. Rincón-Mora, “High power-supply-rejection (PSR)
for 5G applications,” IEEE J. Solid-State Circuits, vol. 55, no. 11, current-mode low-dropout (LDO) regulator,” IEEE Trans. Circuits Syst.
pp. 3076–3086, Nov. 2020. II, Exp. Briefs, vol. 57, no. 11, pp. 868–873, Nov. 2010.

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10 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS

[24] F. Lavalle-Aviles, J. Torres, and E. Snchez-Sinencio, “A high power Hongyup Jeong (Graduate Student Member, IEEE)
supply rejection and fast settling time capacitor-less LDO,” IEEE Trans. received the B.S. degree in electrical and com-
Power Electron., vol. 34, no. 1, pp. 474–484, Jan. 2019. puter engineering from Anyang University, Anyang,
[25] T. Guo, W. Kang, and J. Roh, “A 0.9-µA quiescent current high PSRR South Korea, in 2024. He is currently pursuing the
low dropout regulator using a capacitive feed-forward ripple cancellation M.S. degree with the Department of Electrical and
technique,” IEEE J. Solid-State Circuits, vol. 57, no. 10, pp. 3139–3149, Electronic Engineering, Hanyang University, Ansan,
Oct. 2022. South Korea. His research interests include power
[26] K.-H. Chen, Power Management Techniques for Integrated Circuit management circuits and mixed-signal integrated
Design, 1st ed., Singapore: Wiley, 2016. circuits.

Jung Sik Kim received the B.S. degree in

semiconductor science and technology from Junbuk
University, Junju, South Korea, in 2017. He is
currently pursuing the Ph.D. degree with the
Department of Electrical and Electronic Engineer-
ing, Hanyang University, Ansan, South Korea.
His research interests include power management
circuits and mixed-signal integrated circuits.

Jeongjin Roh (Senior Member, IEEE) received the

B.S. degree in electrical engineering from Hanyang
University, Seoul, South Korea, in 1990, the M.S.
degree in electrical engineering from The Pennsylva-
nia State University in 1998, and the Ph.D. degree in
Seunggyun Ha (Graduate Student Member, IEEE) computer engineering from The University of Texas
received the B.S. degree in semiconductor engineer- at Austin in 2001. From 1990 to 1996, he was with
ing from Chungju University, Chungju, South Korea, Samsung Electronics, Giheung, South Korea, as a
in 2022. He is currently pursuing the M.S. Senior Circuit Designer, where he was involved in
degree with the Department of Electrical and several mixed-signal products. From 2000 to 2001,
Electronic Engineering, Hanyang University, Ansan, he was with Intel Corporation, Austin, TX, USA,
South Korea. His research interests include power as a Senior Analog Designer, where he was involved in delta-sigma data
management circuits and mixed-signal integrated converters. In 2001, he joined as a Faculty Member with Hanyang University,
circuits. Ansan, South Korea. His research interests include over sampled delta-sigma
converters and power management circuits.

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