Chapter 11: Digital Logic

1. The operand ________ yields true if and only if both of its operands are true.

A. XOR B. OR

C. AND D. NOT

2. The operation _________ yields true if either or both of its+ operands are
true.

A. NOT B. AND

C. NAND D. OR

3. The unary operation _________ inverts the value of its operand.

A. OR B. NOT

C. NAND D. XOR

4. A _______ is an electronic circuit that produces an output signal that is a

simple Boolean operation on its input signals.

A. gate B. decoder

C. counter D. flip-flop
5. Which of the following is a functionally complete set?

A. AND, NOT B. NOR

C. AND, OR, NOT D. all of the above

6. For more than four variables an alternative approach is a tabular technique

referred to as the _________ method.

A. DeMorgan B. Quine-McCluskey

C. Karnaugh map D. Boole-Shannon

7. ________ are used in digital circuits to control signal and data routing.

A. Multiplexers B. Program counters

C. Flip-flops D. Gates

8. ________ is implemented with combinational circuits.

A. Nano memory B. Random access memory

C. Read only memory D. No memory

9. The ________ exists in one of two states and, in the absence of input,
remains in that state.

A. assert B. complex PLD

C. decoder D. flip-flop

10. The ________ flip-flop has two inputs and all possible combinations of
input values are valid.

A. J-K B. D

C. S-R D. clocked S-R

11. A _________ accepts and/or transfers information serially.

A. S-R latch B. shift register

C. FPGA D. parallel register

12. Counters can be designated as _________.

A. asynchronous

B. synchronous

C. both asynchronous and synchronous

D. neither asynchronous or synchronous

13. CPUs make use of _________ counters, in which all of the flip-flops of the
counter change at the same time.

A. synchronous B. asynchronous

C. clocked S-R D. timed ripple

14. The _________ table provides the value of the next output when the inputs
and the present output are known, which is exactly the information needed to
design the counter or any sequential circuit.

A. excitation B. Kenough
C. J-K flip-flop D. FPGA

15. A _________ is a PLD featuring a general structure that allows very high
logic capacity and offers more narrow logic resources and a higher ration of flip-
flops to logic resources than do CPLDs.

A. SPLD B. FPGA
C. PAL D. PLA

Chapter 12:
1. The ________ specifies the operation to be performed.

A. source operand reference B. opcode

C. next instruction reference D. processor register

2. A(n) _________ expresses operations in a concise algebraic form using

variables.

A. opcode B. high-level language

C. machine language D. register

3. There must be ________ instructions for moving data between memory and
the registers.

A. branch B. logic
 C. memory D. I/O

4. ________ instructions operate on the bits of a word as bits rather than as

numbers, providing capabilities for processing any other type of data the
user may wish to employ.

A. Logic B. Arithmetic

C. Memory D. Test

5. _________ instructions provide computational capabilities for processing

number data.

A. Boolean B. Logic

C. Memory D. Arithmetic

6. _______ instructions are needed to transfer programs and data into memory
and the results of computations back out to the user.

A. I/O B. Transfer

C. Control D. Branch

7. The x86 data type that is a signed binary value contained in a byte, word, or
doubleword, using twos complement representation is _________.

A. general B. ordinal
 C. integer D. packed BCD

8. The most fundamental type of machine instruction is the _________

instruction.

A. conversion B. data transfer

C. arithmetic D. logical

9. The _________ instruction includes an implied address.

A. skip B. rotate

C. stack D. push

10.Which of the following is a true statement?

A. a procedure can be called from more than one location

B. a procedure call can appear in a procedure

C. each procedure call is matched by a return in the called program

D. all of the above

11.The entire set of parameters, including return address, which is stored for a
procedure invocation is referred to as a _________.
 A. branch B. stack frame

C. pop D. push

12.Which ARM operation category includes logical instructions (AND, OR,

XOR), add and subtract instructions, and test and compare instructions?

A. data-processing instructions B. branch instructions

C. load and store instructions D. extend instructions

13.In the ARM architecture only _________ instructions access memory

locations.

A. data processing B. status register access

C. load and store D. branch

14.Which data type is defined in MMX?

A. packed byte B. packed word

C. packed doubleword D. all of the above

15.A branch instruction in which the branch is always taken is _________.

A. conditional branch B. unconditional branch

C. jump D. bi-endian

Chapter 13
1. The advantage of __________ is that no memory reference other than the
instruction fetch is required to obtain the operand.

A. direct addressing B. immediate addressing

C. register addressing D. stack addressing

2. The principal advantage of ___________ addressing is that it is a very

simple form of addressing.

A. displacement B. register

C. stack D. direct

3. __________ has the advantage of large address space, however it has the
disadvantage of multiple memory references.

A. Indirect addressing B. Direct addressing

C. Immediate addressingD. Stack addressing

4. The advantages of _________ addressing are that only a small address

field is needed in the instruction and no time-consuming memory
references are required.

A. direct B. indirect
 C. register D. displacement

5. __________ has the advantage of flexibility, but the disadvantage of

complexity.

A. Stack addressing B. Displacement addressing

C. Direct addressing D. Register addressing

6. For _________, the address field references a main memory address and
the referenced register contains a positive displacement from that
address.

A. indexing B. base-register addressing

C. relative addressing D. all of the above

7. Indexing performed after the indirection is __________.

A. relative addressing B. autoindexing

C. postindexing D. preindexing

8. For the _________ mode, the operand is included in the instruction.

A. immediate B. base
 C. register D. displacement

9. The only form of addressing for branch instructions is _________

addressing.

A. register B. relative

C. base D. immediate

10.Which of the following interrelated factors go into determining the use of

the addressing bits?

A. number of operands B. number of register sets

C. address range D. all of the above

11._________ is a principle by which two variables are independent of each

other.

A. Opcode B. Orthogonality

C. Completeness D. Autoindexing
12.The _________ was designed to provide a powerful and flexible
instruction set within the constraints of a 16-bit minicomputer.

A. PDP-1 B. PDP-8
 C. PDP-11 D. PDP-10

13.The __________ byte consists of three fields: the Scale field, the Index
field and the Base field.

A. SIB B. VAX

C. PDP-11 D. ModR/M

14.All instructions in the ARM architecture are __________ bits long and
follow a regular format.

A. 8 B. 16

C. 32 D. 64

15.__________ is a design principle employed in designing the PDP-10

instruction set.

A. Orthogonality B. Completeness

C. Direct addressing D. All of the above

Chater 14
1. __________ are a set of storage locations.

A. Processors B. PSWs
 C. Registers D. Control units

2. The ________ controls the movement of data and instructions into and out
of the processor.

A. control unit B. ALU

C. shifter D. branch

3. ________ registers may be used only to hold data and cannot be employed
in the calculation of an operand address.

A. General purpose B. Data

C. Address D. Condition code

4. __________ are bits set by the processor hardware as the result of

operations.

A. MIPS B. Condition codes

C. Stacks D. PSWs

5. The _________ contains the address of an instruction to be fetched.

A. instruction register B. memory address register

C. memory buffer register D. program counter

6. The _________ contains a word of data to be written to memory or the
word most recently read.

A. MAR B. PC

C. MBR D. IR

7. The ________ determines the opcode and the operand specifiers.

A. decode instruction B. fetch operands

C. calculate operands D. execute instruction

8. _________ is a pipeline hazard.

A. Control B. Resource

C. Data D. All of the above

9. A ________ hazard occurs when there is a conflict in the access of an

operand location.

A. resource B. data

C. structural D. control
10.A _________ is a small, very-high-speed memory maintained by the
instruction fetch stage of the pipeline and containing the n most recently
fetched instructions in sequence.

A. loop buffer B. delayed branch

C. multiple stream D. branch prediction

11.The _________ is a small cache memory associated with the instruction

fetch stage of the pipeline.

A. dynamic branch B. loop table

C. branch history table D. flag

12.The _________ stage includes ALU operations, cache access, and

register update.

A. decode B. execute

C. fetch D. write back

13.________ is used for debugging.

A. Direction flag B. Alignment check

 C. Trap flag D. Identification flag

14.The ARM architecture supports _______ execution modes.

A. 2 B. 8

C. 11 D. 7

15.The OS usually runs in ________.

A. supervisor mode B. abort mode

C. undefined mode D. fast interrupt mode

Chapter 15
1. _________ determines the control and pipeline organization.

A. Calculation B. Execution sequencing

C. Operations performed D. Operands used

2. The Patterson study examined the dynamic behavior of _________

programs, independent of the underlying architecture.

A. HLL B. RISC
 C. CISC D. all of the above

3. _________ is the fastest available storage device.

A. Main memory B. Cache

C. Register storage D. HLL

4. The first commercial RISC product was _________.

A. SPARC B. CISC

C. VAX D. the Pyramid

5. _________ instructions are used to position quantities in registers

temporarily for computational operations.

A. Load-and-store B. Window

C. Complex D. Branch

6. Which stage is required for load and store operations?

A. I B. E

C. D D. all of the above

7. A ________ instruction can be used to account for data and branch
delays.

A. SUB B. NOOP

C. JUMP D. all of the above

8. The instruction location immediately following the delayed branch is
referred to as the ________.

A. delay load B. delay file

C. delay slot D. delay register

9. A tactic similar to the delayed branch is the _________, which can be

used on LOAD instructions.

A. delayed load B. delayed program

C. delayed slot D. delayed register

10.The MIPS R4000 uses ________ bits for all internal and external data
paths and for addresses, registers, and the ALU.

A. 16 B. 32

C. 64 D. 128
11.All MIPS R series processor instructions are encoded in a single
________ word format.

A. 4-bit B. 8-bit

C. 16-bit D. 32-bit

12.A _________ architecture is one that makes use of more, and more fine-
grained pipeline stages.

A. parallel B. superpipelined

C. superscalar D. hybrid

13.The R4000 can have as many as _______ instructions in the pipeline at

the same time.

A. 8 B. 10

C. 5 D. 3

14.SPARC refers to an architecture defined by ________.

A. Microsoft B. Apple
 C. Sun Microsystems D. IBM

15.The R4000 pipeline stage where the instruction result is written back to
the register file is the __________ stage.

A. write back B. tag check

C. data cache D. instruction execute

Chapter 16

1. The superscalar approach can be used on __________ architecture.

A. RISC B. CISC

C. neither RISC nor CISC D. both RISC and CISC

2. The essence of the ________ approach is the ability to execute

instructions independently and concurrently in different pipelines.

A. scalar B. branch

C. superscalar D. flow dependency

3. Which of the following is a fundamental limitation to parallelism with

which the system must cope?
 A. procedural dependency B. resource conflicts

C. antidependency D. all of the above

4. The situation where the second instruction needs data produced by the
first instruction to execute is referred to as __________.

A. true data dependency B. output dependency

C. procedural dependency D. antidependency

5. The instructions following a branch have a _________ on the branch and

cannot be executed until the branch is executed.

A. resource dependency B. procedural dependency

C. output dependency D. true data dependency

6. ________ refers to the process of initiating instruction execution in the

processor’s functional units.

A. Instruction issue B. In-order issue

C. Out-of-order issue D. Procedural issue

7. Instead of the first instruction producing a value that the second
instruction uses, with ___________ the second instruction destroys a
value that the first instruction uses.

A. in-order issue B. resource conflict

C. antidependency D. out-of-order completion

8. ________ indicates whether this micro-op is scheduled for execution, has

been dispatched for execution, or has completed execution and is ready
for retirement.

A. State B. Memory address

C. Micro-op D. Alias register

9. __________ exists when instructions in a sequence are independent and

thus can be executed in parallel by overlapping.

A. Flow dependency B. Instruction-level parallelism

C. Machine parallelism D. Instruction issue

10._________ is determined by the number of instructions that can be

fetched and executed at the same time and by the speed and
sophistication of the mechanisms that the processor uses to find
independent instructions.

A. Machine parallelism B. Instruction-level parallelism

C. Output dependency D. Procedural dependency

11.________ is a protocol used to issue instructions.

A. Micro-ops B. Scalar

C. SIMD D. Instruction issue policy

12.________ is used in scalar RISC processors to improve the performance

of instructions that require multiple cycles.

A. In-order completion B. In-order issue

C. Out-of-order completion D. Out-of-order issue

13.Which of the following is a hardware technique that can be used in a

superscalar processor to enhance performance?

A. duplication of resources B. out-of-order issue

C. renaming D. all of the above

14.The ________ introduced a full-blown superscalar design with out-of-

order execution.

A. Pentium B. Pentium Pro

C. 386 D. 486
 15.Utilizing a branch target buffer (BTB), the _________ uses a dynamic
branch prediction strategy based on the history of recent executions of
branch instructions.

A. 486 B. Pentium

C. Pentium 4 D. Pentium Pro

Chapter 17

1. A taxonomy first introduced by _______ is still the most common way of

categorizing systems with parallel processing capability.

A. Randolph B. Flynn

C. von Neuman D. Desai

2. Uniprocessors fall into the _______ category of computer systems.

A. MIMD B. SIMD

C. SISD D. MISD

3. Vector and array processors fall into the ________ category of computer
systems.

A. SIMD B. SISD
 C. MISD D. MIMD

4. SMPs, clusters, and NUMA systems fit into the ________ category of
computer systems.

A. SISD B. MIMD

C. SIMD D. MISD

5. A _________ problem arises when multiple copies of the same data can
exist in different caches simultaneously, and if processors are allowed to
update their own copies freely, an inconsistent view of memory can
result.

A. cache coherence B. cluster

C. failover D. failback

6. Hardware-based solutions are generally referred to as cache coherence

_______.

A. clusters B. streams

C. protocols D. vectors

7. A __________ is an instance of a program running on a computer.

A. process B. process switch

 C. thread D. thread switch

8. A ________ is a dispatchable unit of work within a process that includes

a processor context and its own data area for a stack.

A. process B. process switch

C. thread D. thread switch

9. Replicating the entire processor on a single chip with each processor

handling separate threads is _________.

A. interleaved multithreading B. blocked multithreading

C. simultaneous multithreading D. chip multiprocessing

10.With no multithreading, _________ is the simple pipeline found in

traditional RISC and CISC machines.

A. superscalar

B. single-threaded scalar

C. blocked multithreaded scalar

D. interleaved multithreaded scalar

11. _________ causes results issuing from one functional unit to be fed
immediately into another functional unit and so on.

A. Chaining B. Rollover

C. Passive standby D. Pipelining

12. The ________ contains control fields, such as the vector count, that
determine how many elements in the vector registers are to be processed.

A. vector-mask register B. vector-activity count

C. vector-status register D. vector-instruction register

13. Which of the following is an approach to vector computation?

A. pipelined ALU B. parallel ALU’s

C. parallel processors D. all of the above

14. An operation that switches the processor from one process to another by
saving all the process control data, register, and other information for the
first and replacing them with the process information for the second is:

A. resource ownership switch B. process switch

C. thread switch D. cluster switch

 15. With ________ instructions are simultaneously issued from multiple
threads to the execution units of a superscalar processor.

A. SMT B. single-threaded scalar

C. coarse-grained multithreading D. chip multiprocessing

Chapter 18
1. With _______, register banks are replicated so that multiple threads can
share the use of pipeline resources.

A. SMT B. pipelining

C. scalar D. superscalar

2. _________ is where individual instructions are executed through a pipeline

of stages so that while one instruction is executing in one stage of the
pipeline, another instruction is executing in another stage of the pipeline.

A. Superscalar B. Scalar

C. Pipelining D. Simultaneous multithreading

3. _________ is when multiple pipelines are constructed by replicating

execution resources, enabling parallel execution of instructions in parallel
pipelines so long as hazards are avoided.
 A. Vectoring B. Superscalar

C. Hybrid multithreading D. Pipelining

4. One way to control power density is to use more of the chip area for
________.

A. multicore B. cache memory

C. silicon D. resistors

5. Lotus Domino or Siebel CRM are examples of ___________ applications.

A. threaded B. multi-process

C. Java D. multi-instance

6. Oracle database, SAP, and PeopleSoft are examples of ________

applications.

A. Java B. multithreaded native

C. multi-instance D. multi-process

7. _______ applications that can benefit directly from multicore resources

include application servers such as Sun’s Java Application Server, BEA’s
Weblogic, IBM’s Websphere, and the open-source Tomcat application
server.
 A. Multi-instance B. Multi-process

C. Java D. Threaded

8. Putting rendering on one processor, AI on another, and physics on another is

an example of _________ threading.

A. coarse B. multi-instance

C. fine-grained D. hybrid

9. A loop that iterates over an array of data can be split up into a number of
smaller parallel loops in individual threads that can be scheduled in parallel
when using ________ threading.

A. multi-process B. fine-grained

C. hybrid D. coarse

10.The _________ is an example of splitting off a separate, shared L3 cache,

with dedicated L1 and L2 caches for each core processor.

A. IBM 370 B. ARM11 MPCore

 C. AMD Opteron D. Intel Core i7

11.The ________ connects to the external bus, known as the Front Side Bus,
which connects to main memory, I/O controllers, and other processor chips.

A. L2 B. APIC

C. bus interface D. all of the above

12.The Intel Core i7-990X, introduced in 2008, implements ______ x86 SMT
processors, each with a dedicated L2 cache, and with a shared L3 cache.

A. 2 B. 4

C. 6 D. 8

13.Processors are called ________.

A. dies B. cores

C. QPI D. interconnects

14.The ________ feature enables moving dirty data from one CPU to
another without writing to L2 and reading the data back in from external
memory.

A. migratory lines B. DDI

 C. VFP unit D. IPIs

15.The ________ is responsible for maintaining coherency among L1 data

caches.

A. VFP unit B. distributed interrupt controller

C. snoop control unit (SCU) D. watchdog