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CS2 - Chapter 2

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69 views98 pages

CS2 - Chapter 2

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Paper-II(Hardware)

TOPICS MARKS

1.Introduction to microprocessors and Organisation of 8085 21 Marks

2.Instruction Set and Programming of 8085 43 Marks

3.Introduction of Intel X-86 Family 4 Marks

4.Introduction to Microcontroller 8 Marks


5.Networking Technology 18 Marks
Instruction Set and Programming of 8085
43 Marks
Length of instructions
Addressing Modes
Instruction classification of 8085 or
Groups in detail
Length of instructions
 How instructions of 8085 are classified accordingly to its
length ? - 3M

The instructions of 8085 are classified into 3 types accordingly


to its length.
1.One Byte instructions
2.Two Byte instructions
3.Three Byte instructions
1.One Byte instructions
These instructions are having only opcode or
both opcode and operand in one byte. These require
one byte to store in memory.
OPCODE 1 Byte
OR
OPCODE  OPERAND 1 Byte

Ex. CMA , ADD B


2.Two Byte instructions
These instructions require 2 bytes to store in memory.
First byte gives opcode second byte gives
operand(1byte/8 bit).

First Byte Second Byte


OPCODE OPERAND(1byte/ 8 bit)

Ex. ANI 1byte , MVI M,1byte


3.Three Byte instructions
In this type of instruction the first byte specifies the
opcode but second and third byte together specify 16-bit
address of operand or 16-bit data. The second byte is
lower order byte and the third byte is higher order byte.
First Byte Second Byte Third Byte
OPCODE Data/Address Data/Address
Lower order byte Higher order byte

Ex. STA 16bit, LDA 16bit


Addressing Modes-3/4 M
 Addressing Mode of a microprocessor is the various
formats of specifying the operands. The operands can
be register, 8bit data or 16bit address. There are 5
addressing Modes which are given below.
1.Direct Addressing Mode
2.Immediate Addressing Mode
3.Register Addressing Mode
4.Register Indirect Addressing Mode
5.Implicit Addressing Mode
1.Direct Addressing Mode
In this addressing mode the address of the
operand is specified within the instruction
itself.
Here address appears after opcode of
instruction in program memory.
Here all the instructions are of 3 byte.
Ex. STA 16bit, LDA 16bit
2. Immediate Addressing Mode
 Inthis addressing mode the instructions are of 2 or 3
byte .
 For 2 byte instruction the data is specified within the
instruction.
 For 3 byte instruction the operand is specified within the
instruction itself. Also I appears at 3rd position of opcode
with 16 bit
Ex. CPI 8bit - 2byte
LXI H,16bit -3byte
3.Register Addressing Mode
 In this addressing mode the source operands are
general purpose register whose name is
specified within the instruction.
 This is register to register or accumulator to
register transfer.
 Usually these instructions are single byte
instruction.
Ex. ADD B, MOV B,C
4.Register Indirect Addressing Mode
 In this addressing mode the content of register
pair points to the address of the operand.
 A register pair [HL]=M is specified for addressing
16 bit address of memory location or X appear at
4th position of opcode.
 Usually these instructions are single byte
instruction.
Ex. ADD M, STAX B
5. Implicit / Implied Addressing Mode

 In this addressing mode only opcode is


present.
Usually these instructions are single byte
instructions.
Ex. CMA
Instruction classification of 8085 or Groups in detail-3M
There are 5 groups in 8085
1) Arithmetic Group Instructions-The instructions in this group
performs arithmetic operations like addition, Subtraction, increment
and Decrement on data in registers or memory.
Ex. ADD B, SUB C
2) Logical Group Instructions- This group performs logical
operations like AND,OR,XOR etc generally with the accumulator.
Ex. CMA
3)Data Transfer Group- This group of instruction copies data from a
location called source to another location called as destination
without modifying the contents of source. These
instructions move data between registers or between
memory locations and registers.
Ex. MOV A,B
4) Branching Group Instructions- This group of
instructions allow programmer to change the sequence of
execution of program either conditionally or
unconditionally.
Ex. JMP 16bit
5)Machine Control Group-This group of instructions
control machine operations such as halt, stack operations
etc.
1) Arithmetic Group Instructions-Total No. of instructions=20
1) ADD r
Format - A ← A + r
AM - Register
Byte - 1
Meaning-The contents of accumulator is added with the contents
of register and the result is stored in the accumulator. Here r is
General Purpose Register A,B,C,D,E,H,L.
Ex. Let A=25,B=35
Instruction ADD B
After Execution - A=25= 00100101
+ B=35= 00110101
01011010 =5A Therefore A=5A
2 ) ADD M
Format - A ← A + M where M=[HL]
AM - Register Indirect
Byte - 1
Meaning-The contents of accumulator is added with the
contents of memory location whose address is stored in
[HL]pair and the result is stored in the accumulator.
Ex. Let A=A5,M=[HL]=2008=56
Instruction ADD M
After Execution - A=A5= 10100101
+ M=56= 01010110
11111011 Therefore A=FB
3 ) ADI 1byte
Format - A ← A + data
AM - Immediate
Byte - 2
Meaning-The contents of accumulator is added with 8 bit
immediate data and the result is stored in the accumulator.
Ex. Let A=67
Instruction ADI 25
After Execution - A=67= 01100111
+ data=25= 00100101
10001100 Therefore A=8C
4) ADC r
Format - A ← A + r +Cy Where Cy is carry
AM - Register
Byte - 1
Meaning-The contents of accumulator is added with the contents of
register and carry and the result is stored in the accumulator. Here r is
General Purpose Register A,B,C,D,E,H,L.
Ex. Let A=25,B=35,Cy=1
Instruction ADC B
After Execution - A=25= 00100101
+ B=35= 00110101
+ Cy=01=00000001
01011011 =5B Therefore A=5B
5 ) ADC M
Format - A ← A + M + Cy where M=[HL] , Cy=carry
AM - Register Indirect
Byte - 1
Meaning-The contents of accumulator is added with the contents of
memory location whose address is stored in [HL]pair and carry and
the result is stored in the accumulator.
Ex. Let A=A5,M=[HL]=2008=56, Cy=01
Instruction ADC M
After Execution - A=A5= 10100101
+ M=56= 01010110
+ Cy=01=00000001
11111100 =FC Therefore A=FC
6 ) ACI 1byte
Format - A ← A + data +Cy where Cy is carry
AM - Immediate
Byte - 2
Meaning-The contents of accumulator is added with 8 bit
immediate data and carry and the result is stored in the
accumulator.
Ex. Let A=67, Cy=01
Instruction ACI 25
After Execution - A=67= 01100111
+ data=25= 00100101
+Cy =01= 00000001
10001101=8D Therefore A=8D
7) SUB r
Format - A ← A - r
AM - Register
Byte - 1
Meaning-The contents of register is subtracted from the contents of
accumulator and the result is stored in the accumulator. Here r is
General Purpose Register A,B,C,D,E,H,L.
Ex. Let A=05, D=03
Instruction SUB D
After execution A=05=00000101
- D=03=11111101 -2’s Complement of 00000011
1 00000010 11111100+1=11111101
Therefore Cy=0, A=02
8) SUB M
Format - A ← A – M where M=[HL]
AM - Register Indirect
Byte - 1
Meaning-The contents of memory location whose address is stored
in[HL]pair is subtracted from the contents of accumulator and the
result is stored in the accumulator.
Ex. Let A=08, M=[HL]=C004=03
Instruction SUB M
After execution A=08= 00001000
- M=03= 11111101 -2’s Complement of 00000011
1 00000101 11111100+1=11111101
Therefore Cy=0, A=05
9) SUI 1byte
Format - A ← A - data
AM - Immediate
Byte - 2
Meaning- 8 bit immediate data is subtracted from the contents of
accumulator and the result is stored in the accumulator.
Ex. Let A=09
Instruction SUI 03
After execution A=09=00001001
-data=03=11111101 -2’s Complement of 00000011
1 00000110 11111100+1=11111101
Therefore Cy=0, A=06
10) SBB r
Format - A ← A – r- Cy where Cy is borrow
AM - Register
Byte - 1
Meaning-The contents of register and the contents of borrow is
subtracted from the contents of accumulator and the result is
stored in the accumulator. Here r is General Purpose Register
A,B,C,D,E,H,L.
Ex. Let A=0A, E=02,Cy=01
Instruction SBB E
After execution A=0A=00001010
-(E+Cy)=03=11111101 -2’s Complement of 00000011
1 00000111 11111100+1=11111101
Therefore Cy=0, A=07
11) SBB M
Format - A ← A – M- Cy where M=[HL],Cy is borrow
AM - Register Indirect
Byte - 1
Meaning-The contents of memory location whose address is stored
in[HL]pair and the contents of borrow is subtracted from the
contents of accumulator and the result is stored in the accumulator.
Ex. Let A=0B, M=[HL]=D005=02,Cy=01
Instruction SBB M
After execution A=0B= 00001011
-(M+Cy)=03=11111101 -2’s Complement of 00000011
1 00001000 11111100+1=11111101
Therefore Cy=0, A=08
12) SBI 1byte
Format - A ← A – data- Cy where Cy is borrow
AM - Immediate
Byte - 2
Meaning- 8bit immediate data and the contents of borrow is
subtracted from the contents of accumulator and the result is
stored in the accumulator.
Ex. Let A=0C, Cy=01
Instruction SBI 02
After execution A=0C= 00001100
-(data+Cy) =03= 11111101 -2’s Complement of 00000011
1 00001001 11111100+1=11111101
Therefore Cy=0, A=09
13) INR r
Format - r ← r + 1
AM - Register
Byte - 1
Meaning- The contents of register is incremented by one and the
result is stored in the register. Here r is general purpose register
A,B,C,D,E,H,L.
Ex. Let E=09
Instruction INR E
After execution E=09= 00001001
+ 01= 00000001
00001010
Therefore E=0A
14) INR M
Format - [HL] ← [HL] + 1, where M=[HL]
AM - Register Indirect
Byte - 1
Meaning- The contents of memory location whose address is stored
in [HL]pair is incremented by one and the result is stored in the
memory location.
Ex. Let M=[HL]=2009=0A
Instruction INR M
After execution M=0A= 00001010
+ 01= 00000001
00001011
Therefore M=[HL]=2009=0B
15) INX rp
Format - rp ← rp + 1
AM - Register
Byte - 1
Meaning- The register pair(rp) is incremented by one and the
result is stored in the register pair(rp) . Here rp is register pair
B=[BC],D=[DE] , H=[HL]and SP.
Ex. Let B=[BC]=2009
Instruction INX B
After execution B=[BC]= 200A
16) DCR r
Format - r ← r - 1
AM - Register
Byte - 1
Meaning- The contents of register is decremented by one and the
result is stored in the register . Here r is general purpose register
A,B,C,D,E,H,L.
Ex. Let C=25
Instruction DCR C
After execution C= 24
17) DCR M
Format - [HL]← [HL] – 1 where M=[HL]
AM - Register Indirect
Byte - 1
Meaning- The contents of memory location whose address
is stored in [HL]pair is decremented by one and the result
is stored in the memory location.

Ex. Let M=[HL]=2001=06


Instruction DCR M
After execution M=[HL]=2001=05
18) DCX rp
Format - rp ← rp - 1
AM - Register
Byte - 1
Meaning- The register pair(rp) is decremented by one and
the result is stored in the register pair(rp) . Here rp is
register pair B=[BC],D=[DE], H=[HL]and SP.
Ex. Let B=[BC]=2005
Instruction DCX B
After execution B=[BC]= 2004
19) DAD rp
Format - [HL] ← [HL] +rp
AM - Register
Byte - 1
Meaning- The contents of register pair(rp) are added to the
contents[HL]pair and the result is stored in [HL]pair . Here rp is
register pair B=[BC],D=[DE] , H=[HL] and SP.
Ex. Let B=20,C=05,B=[BC]=2005=56,H=06,L=05,[HL]=0605=25
Instruction DAD B
After execution H=H+B=06+20 =26
L=L+C=05+05=0A
Therefore[HL]=[260A]
20) DAA(Decimal Adjust Accumulator)
AM - Implicit
Byte - 1
Meaning- The 8bit number in the accumulator is adjusted to form two
4bit Binary coded Decimal (BCD)digits by this instruction. It can be done
by following process.
1)Carry out BCD addition.
2)If the value of LSB(least significant 4 bits) of the Accumulator( A3-A0 )
is greater than 9 then 06 is added to lower order 4 bits of accumulator.
3) If the value of MSB(most significant 4 bits) of the Accumulator( A7-A4 )
is greater than 9 then 60 is added to higher order 4 bits of accumulator .
4) If both LSB and MSB of the accumulator are greater than 9
respectively then add 66 to the accumulator contents.
Example: ADD 12 to 39 BCD
39 = 00111001
+ 12 = 00010010
51 01001011=4B

The binary sum is 4B.


Since LSB is greater than 9 add 06 to 4B to get the result
01001011
+ 00000110
01010001 =51
Therefore A=51
2) Logical Group Instructions-Total No. of instructions=19
1) ANA r
Format - A ← A ^ r
AM - Register
Byte - 1
Meaning-The contents of accumulator is logical AND with the
contents of register and the result is stored in the accumulator.
Here r is General Purpose Register A,B,C,D,E,H,L.
Ex. Let A=25,B=35
Instruction ANA B
After Execution - A=25= 00100101
^ B=35= 00110101
00100101 =25
Therefore A=25
2 ) ANA M
Format - A ← A ^ M where M=[HL]
AM - Register Indirect
Byte - 1
Meaning-The contents of accumulator is logical AND with the
contents of memory location whose address is stored in
[HL]pair and the result is stored in the accumulator.
Ex. Let A=A5,M=[HL]=2008=56
Instruction ANA M
After Execution - A=A5= 10100101
^ M=56= 01010110
Therefore A=04 00000100 =04
3 ) ANI 1byte
Format - A ← A ^ data
AM - Immediate
Byte - 2
Meaning-The contents of accumulator is logical AND with 8 bit
immediate data and the result is stored in the accumulator.
Ex. Let A=67
Instruction ANI 25
After Execution - A=67= 01100111
^ data=25= 00100101
00100101=25
Therefore A=25
4) ORA r
Format - A ← A v r
AM - Register
Byte - 1
Meaning-The contents of accumulator is logical OR with the
contents of register and the result is stored in the accumulator.
Here r is General Purpose Register A,B,C,D,E,H,L.
Ex. Let A=25,B=35
Instruction ORA B
After Execution - A=25= 00100101
v B=35= 00110101
00110101 =35
Therefore A=35
5) ORA M
Format - A ← A v M where M=[HL]
AM - Register Indirect
Byte - 1
Meaning-The contents of accumulator is logical OR with the
contents of memory location whose address is stored in
[HL]pair and the result is stored in the accumulator.
Ex. Let A=A5,M=[HL]=2000=56
Instruction ORA M
After Execution - A=A5= 10100101
v M=56= 01010110
Therefore A=F7 11110111=F7
6) ORI 1byte
Format - A ← A v data
AM - Immediate
Byte - 2
Meaning-The contents of accumulator is logical OR with 8 bit
immediate data and the result is stored in the accumulator.
Ex. Let A=67
Instruction ORI 25
After Execution - A=67= 01100111
v data=25= 00100101
01100111=67
Therefore A=67
7) XRA r
Format - A ← A v r
AM - Register
Byte - 1
Meaning-The contents of accumulator is logical XOR with the
contents of register and the result is stored in the accumulator.
Here r is General Purpose Register A,B,C,D,E,H,L.
Ex. Let A=25,B=35
Instruction XRA B
After Execution - A=25= 00100101
v B=35= 00110101
00010000 =10
Therefore A=10
8) XRA M
Format - A ← A v M where M=[HL]
AM - Register Indirect
Byte - 1
Meaning-The contents of accumulator is logical XOR with the
contents of memory location whose address is stored in
[HL]pair and the result is stored in the accumulator.
Ex. Let A=A5,M=[HL]=2000=56
Instruction XRA M
After Execution - A=A5= 10100101
v M=56= 01010110
Therefore A=F3 11110011
9) XRI 1byte
Format - A ← A v data
AM - Immediate
Byte - 2
Meaning-The contents of accumulator is logical XOR with 8 bit
immediate data and the result is stored in the accumulator.
Ex. Let A=67
Instruction XRI 25
After Execution - A=67= 01100111
v data=25= 00100101
01000010=42
Therefore A=42
10) CMP r
AM - Register
Byte - 1
Meaning-The contents of accumulator is compared with the
contents of register and the result of comparison is shown by
setting the flags as:
a) If A=r then Zero flag is set(Z=1).
b) If A<r then carry flag is set(Cy=1).
c) If A>r then both zero and carry flag are reset(Z,Cy=0).
Ex. Let A=15H and D=57H
Instruction CMP D
After execution Carry flag is set (Cy=1)
11) CMP M
AM - Register Indirect
Byte - 1
Meaning-The contents of accumulator is compared with the
contents of memory location whose address is stored in [HL] pair
and the result of comparison is shown by setting the flags as:
a) If A=M then Zero flag is set(Z=1).
b) If A<M then carry flag is set(Cy=1).
c) If A>M then both zero and carry flag are reset(Z,Cy=0).
Ex. Let A=57H and M=[HL]=3005=57H
Instruction CMP M
After execution Zero flag is set (Z=1)
12) CPI 1byte
AM - Immediate
Byte - 2
Meaning-The contents of accumulator is compared with the
contents of 8 bit immediate data and the result of comparison is
shown by setting the flags as:
a) If A=data then Zero flag is set(Z=1).
b) If A< data then carry flag is set(Cy=1).
c) If A> data then both zero and carry flag are reset(Z,Cy=0).
Ex. Let A=57H
Instruction CPI 23
After execution Both Zero and carry flags are reset (Z,Cy=0)
4 Rotate Instructions -4M
13) RLC(Rotate Accumulator Left without carry)
Cy A 7 A 6 A5 A4 A3 A2 A1 A0

Format : An+1 An , CyA7 , A0A7


AM : Implicit
Byte : 1Byte
Meaning : The contents of accumulator are rotated left
by 1bit position without carry. The contents
of bit A7 are stored in bit A0 as well as carry.
Ex.Let A=93H Cy=0
Instruction RLC
Before Execution: 00 1 0 0 1 0 0 1 1

After Execution RLC


11 0 0 1 0 0 1 1 1

Therefore Cy=1, A=27H


14) RRC(Rotate Accumulator Right without carry)
Cy A7 A6 A5 A4 A3 A2 A1 A0

Format : An An+1 , CyA0 , A7A0


AM : Implicit
Byte : 1Byte
Meaning : The contents of accumulator are rotated right by 1
bit position without carry. The contents of bit A0 are
stored in bit A7 as well as carry.
Ex. Let A=83H Cy=0
Instruction RRC
Before Execution: 00 1 0 0 0 0 0 1 1

After Execution RRC


11 1 1 0 0 0 0 0 1

Therefore Cy=1, A=C1H


15) RAL(Rotate Accumulator Left with carry)
Cy A7 A6 A5 A4 A3 A2 A1 A0

Format : An+1 An , CyA7 , A0Cy


AM : Implicit
Byte : 1Byte
Meaning : The contents of accumulator are rotated left by 1
bit position with carry. The contents of bit A7 is stored
in bit Cy and the contents of Cy is stored in A0 .
Ex. Let A=29H Cy=1
Instruction RAL
Before Execution: 1 0 0 1 0 1 0 0 1

After Execution RAL


10 0 1 0 1 0 0 1 1

Therefore Cy=0, A=53H


16) RAR(Rotate Accumulator Right with carry)
Cy A7 A6 A5 A4 A3 A2 A1 A0

Format : An An+1 , A7 Cy , CyA0


AM : Implicit
Byte : 1Byte
Meaning : The contents of accumulator are rotated right by 1
bit position with carry. The contents of bit A0 is stored
in bit Cy and the contents of Cy is stored in bit A7 .
Ex.Let A=3BH Cy=1
Instruction RAR
Before Execution: 01 0 0 1 1 1 0 1 1

After Execution RAR


11 1 0 0 1 1 1 0 1

Therefore Cy=1, A=9DH


17) CMA(Complement the Accumulator)
Format : A
AM : Implicit
Byte : 1 byte
Meaning : This instruction complements the accumulator
contents and the result is stored in accumulator.

Ex. Let A=3B=00111011


Instruction : CMA
After Execution A=11000100=C4
18) CMC(Complement the Carry)
Format : Cy
AM : Implicit
Byte : 1 byte
Meaning : This instruction complements the carry contents and
the result is stored in carry.

Ex. Let Cy=1


Instruction : CMC
After Execution Cy=0
19) STC(Set the Carry)
Format : Cy 1
AM : Implicit
Byte : 1 byte
Meaning : Here the carry flag is set to 1.
3) Data Transfer Group Instructions-Total No. of instructions=13
1) MOV rd , rs
Format - rd  rs
AM - Register
Byte - 1
Meaning-This instruction will move the contents of source
register(rs ) to the content of destination register(rd ), where
the contents of source register remains unchanged. Here r is
General Purpose Register A,B,C,D,E,H,L.
Ex. Let A=25,B=35
Instruction MOV A,B
After Execution- A=35,B=35
2) MOV r , M
Format - r  [HL], where M=[HL]
AM - Register/ Register Indirect
Byte - 1
Meaning-This instruction will move with content of memory
location ,whose address is stored in[HL] pair to the register
where the contents of memory location remains unchanged.
Here r is General Purpose Register A,B,C,D,E,H,L.
Ex. Let D=25,M=[HL]=2008=35
Instruction MOV D,M
After Execution- D=35,M=35
3) MOV M,r
Format - [HL] r , where M=[HL]
AM - Register/ Register Indirect
Byte - 1
Meaning-This instruction will copy register content to
memory location ,whose address is stored in[HL] pair, where
the contents of register remains unchanged. Here r is
General Purpose Register A,B,C,D,E,H,L.
Ex. Let M=[HL]=2008=35,E=45
Instruction MOV M,E
After Execution- M=45,E=45
4) MVI r , 1byte
Format - r data
AM - Immediate
Byte - 2
Meaning-This instruction will copy 8bit immediate data to
register. Here r is General Purpose Register A,B,C,D,E,H,L.
Ex.
Instruction MVI C,56
After Execution- C=56
5) MVI M , 1byte
Format - [HL] data ,where M=[HL]
AM - Immediate
Byte - 2
Meaning-This instruction will copy 8bit immediate data to
memory location whose address is stored in [HL] pair.
Ex. Let M=[HL]=2005
Instruction MVI M,56
After Execution- M=[HL]=2005=56
6) XCHG
Format - H D
E  L
AM - Register
Byte - 1
Meaning-The contents of register H are exchanged with that of
register D and the contents of register L are exchanged with
that of register E.
Ex. Let H=23H,L=33H,D=53H,E=55H
Instruction XCHG
After Execution-H=53H, D=23H,L=55H,E=33H
7) LXI rp,16bit
Format - rp16bit or rp(byte3)(byte2)
AM - Immediate
Byte - 3
Meaning-The first byte gives the opcode. Second and third
byte specify 16 bit address. Here rp is register pair
B=[BC],D=[DE],H=[HL], SP.
Ex. LXI B,2005
After execution B=20,C=05
8) LDA 16bit
Format - A(byte3)(byte2)
AM - Direct
Byte - 3
Meaning-This instruction will load accumulator with the
contents of memory location whose address is given in the
instruction itself.
Ex. Let 4005=25
Instruction LDA 4005
After execution A=25
9) STA 16bit
Format - (byte3)(byte2)  A
AM - Direct
Byte - 3
Meaning-This instruction will copy the accumulator contents
to memory location whose address is given in the instruction
itself.
Ex. Let A=62
Instruction STA D005
After execution D005=62
10) LDAX rp
Format - A rp
AM - Register Indirect
Byte - 1
Meaning-The contents of memory location whose address is
stored in register pair(rp) are loaded to accumulator. Here rp
is register pair B=[BC],D=[DE].
Ex. Let D=45,E=56,D=[DE]=[4556]=22
Instruction LDAX D
After execution A=22
11) STAX rp
Format - rp  A
AM - Register Indirect
Byte - 1
Meaning-The contents of accumulator are transferred to
memory location whose address is stored in register pair(rp) .
Here rp is register pair B=[BC],D=[DE].
Ex. Let A=9E, B=45,C=22, B=[BC]=[4522]
Instruction STAX B
After execution B=[BC]=[4522]=9E.
12) LHLD 16bit
Format - L((byte3)(byte2))
H [((byte3)(byte2))+1]
AM - Direct
Byte - 3
Meaning- In this instruction first byte gives opcode, second and
third byte gives 16bit address. The contents of memory location
whose address is specified in the instruction is moved to register L
and the contents of next memory location is moved to register H.
Ex. Let 2001=45,2002=67
Instruction-LHLD 2001
After execution-H=67,L=45
13) SHLD 16bit
Format - ((byte3)(byte2))  L
[((byte3)(byte2))+1]  H
AM - Direct
Byte - 3
Meaning- In this instruction first byte gives opcode, second and
third byte gives 16bit address. The contents of register L is moved
to memory location whose address is specified by byte 3 and byte
2 of instruction and the contents of register H is moved to next
memory location .
Ex. Let H=72,L=58
Instruction-SHLD 2001
After execution-2001=58 ,2002=72
4) Branching Group Instructions
What are branching instructions? Explain the jumping
instructions with jump conditions? -4M
 The instructions which allow user to change the
control of flow of program execution are called
branching instructions.
 There are 2 types of branching instruction
1) Unconditional Jump
2) Conditional Jump
1) Unconditional Jump :
Instruction: JMP 16bit
Byte: 3
Meaning: In this jump no condition is tested. When this
instruction is executed the program control is
unconditionally transferred to the address given in
instruction. Such an instruction allows user to set up
unconditional loops.
Ex. Instruction JMP F009
After execution of the above instruction control is
transferred to F009.
2) Conditional Jump
Instruction: Jcondition 16bit
Byte: 3
Meaning: In this instruction the jump is taken only if the condition is
true.
There are 8 types of conditional jump
1)JP 16bit-Jump on plus(S=0)
2)JM 16bit-Jump on minus(S=1)
3)JZ 16bit-Jump on zero(Z=1)
4)JNZ 16bit-Jump on Non Zero(Z=0)
5)JPE 16bit-Jump on even parity(P=1)
6)JPO 16bit-Jump on odd parity(P=0)
7)JC 16bit-Jump on carry(Cy=1)
8)JNC 16bit-Jump on no carry(Cy=0)
 Note: There are 5 flags in 8085 .Only 4 flags are used in
conditional Jump(i.e Sign,Zero,Parity and carry Flag)
Here Auxilliary Carry(Ac) Flag is not used.
How a subroutine can be called conditionally and
unconditionally or Explain CALL Instruction. - 4M
A subroutine is a short set of program instructions written
separately from the main program to perform a function
that occurs repeatedly in the main program.
There are 2 types of CALL instruction:
1) Unconditional CALL
2) Conditional CALL
1) Unconditional CALL
Instruction : CALL 16bit
Format : SP-1PCH
SP-2 PCL
SP SP-2
Byte :3
Meaning : First byte is opcode and second and third byte gives
the subroutine address. On execution the address of the
instruction following CALL is stored in stack. It decrements SP by
two. It then jumps unconditionally to subroutine address.
2)conditional CALL
Instruction : Ccondition 16bit
Format : SP-1PCH SP-2 PCL
2000
SP-2 PCL SP-1 PCH
2001
SP SP-2 SP 2002
Byte :3
Meaning : Here the subroutine is called only when the
condition is true. There are 8 types of conditional call.
1)CP 16bit- Call on plus(S=0)
2)CM 16bit- Call on minus(S=1)
3)CZ 16bit- Call on zero(Z=1)
4)CNZ 16bit-Call on Non Zero(Z=0)
5)CPE 16bit-Call on even parity(P=1)
6)CPO 16bit-Call on odd parity(P=0)
7)CC 16bit- Call on carry(Cy=1)
8)CNC 16bit-Call on no carry(Cy=0)
Explain return procedure in RET instruction -4M
The RET instructions are used to return from subroutine to main program.
The return instruction is written at the end of the subroutine indicating end
of subroutine.
There are 2 types of RET instruction:
1) Unconditional RET
2) Conditional RET
1)Unconditional RET
Instruction : RET
Format: PCLSP
PCHSP+1
SPSP+2
Byte: 1
Meaning: The contents of memory location whose address is specified in
stack pointer are moved to the lower order byte of Program counter. The
content of the memory location whose address is one more than the
content of SP moved to the higher order byte of program counter. The
contents of stack pointer are increment by 2.
2)conditional RET
Instruction : Rcondition 2000 PCL SP
Format : PCLSP 2001 PCH SP+1
PCHSP+1 2002 SP+2
SPSP+2
Byte :1
Meaning : If the specified condition is true, the actions specified in RET are
performed. Otherwise the control continues sequentially.
1)RP - Return on plus(S=0)
2)RM - Return on minus(S=1)
3)RZ - Return on zero(Z=1)
4)RNZ - Return on Non Zero(Z=0)
5)RPE - Return on even parity(P=1)
6)RPO - Return on odd parity(P=0)
7)RC - Return on carry(Cy=1)
8)RNC - Return on no carry(Cy=0)
4) Restart Instruction-RST
 We have seen the use and functioning of interrupts. We know that on
giving the 8085 an interruption , the pin INTR microprocessor
fetches the Interrupt Service Routine(ISR) branch address from data
bus. For this we should externally provide the instruction. RST
instructions are one of the instructions, which can be used to
transfer the control to ISR. There are 8 different RST instructions
RST 0 to RST 7.These are all of 1 byte.
Instruction : RST n
Byte : 1 byte
Meaning : Here n=0 to 7 .These interrupts are called as
software interrupts.
5) Machine Control Group of Instructions
There are 3 types in the above group
1)Stack Operations
2)Interrupt Control Operations
3)Machine control operations
1)Stack Operations :
Explain PUSH Instruction-4M
1)Instruction : PUSH rp
Format: SP -1rh
SP-2rl
SPSP-2
Byte :1
Meaning: The contents of higher order register of register
pair rp are moved to memory location whose address is one
less than the contents of stack pointer.
The contents of lower order register of register pair rp are
moved to memory location whose address is two less than
the contents of stack pointer.
The stack pointer is decremented by 2. Here rp is register
pair B=[BC],D=[DE] and H=[HL]
Ex. Let SP=D015 ,B=25 C=55
Instruction PUSH B
After execution : SP=D013, D013=55,D014=25
2)Instruction : PUSH PSW
7 6 5 4 3 2 1 0

Format: SP -1A S Z - Ac - P - Cy

[SP-2]0Cy
[SP-2]2P
[SP-2]4Ac
[SP-2]6Z
[SP-2]7S
SPSP-2 , [SP-2]5X, [SP-2]3X, [SP-2]1X
Where X is not defined
Meaning:The contents of accumulator are moved to memory
location whose address is one less than the contents of stack
pointer. The contents of PSW(processor status word) (i.e)
flag register are moved to memory location whose address is
two less than the contents of stack pointer. The stack
pointer is decremented by 2.
Ex. Let A=33 Flag register=25 SP=D015
Instruction : PUSH PSW
After execution D014=33, D013=25 ,SP=D013
Explain POP Instruction-4M
1)Instruction : POP rp
Format: rlSP
rhSP+1
SPSP+2
Byte :1
Meaning: The contents of memory location whose address is specified
by the stack pointer are moved to lower order register of register pair
rp. The contents of memory location whose address is one more than
the contents of stack pointer are moved to higher order register of
register pair rp.
The stack pointer is incremented by 2. Here rp is register pair
B=[BC],D=[DE] and H=[HL]
Ex. Let SP=2001
Instruction POP H
Before execution
2001 10 SP
2002 20
2003

After execution SP=2003, H=20,L=10


2)Instruction : POP PSW
Format: Cy[SP]0
P[SP]2 7 6 5 4 3 2 1 0
Ac[SP]4 S Z - Ac - P - Cy

Z[SP]6
S[SP]7
ASP+1 , SPSP+2, X[SP]5, X[SP]3, X[SP]1
Byte: 1
Meaning : The contents of memory location whose address is
specified by the contents of stack pointer are moved to
processor status word(PSW) or flag register. The contents of
memory location whose address is one more than stack pointer
are moved to accumulator. The stack pointer is incremented by
2.
Eg: Let SP=D013=45,D014=90, D015=72
Instruction : POP PSW
After execution flag register=45,A=90,SP=D015

Instruction : XTHL(Exchange H and L with top of the stack)


Format : L SP
H SP+1
Byte: 1
Meaning: The contents of L register are exchanged with the contents
of the memory location, whose address is stored in stack pointer.The
contents of the H register are exchanged with the contents of the
memory location, whose address is one more than the contents of the
stack pointer.
Ex. Let H=20, L=FF
Stack
AB SP
CD

Instruction :XTHL
After execution:
H=CD, L=AB
SP=FF,SP+1=20
Instruction : SPHL
Format : SPL  L
SPH H
Byte : 1
Meaning : This instruction copies contents of L register into lower byte
of SP and contents of H register into higher byte of SP. The contents of
H and L registers are unaffected.
Ex. Let H=25H, L=59H
Instruction : SPHL
After execution :SP=2559
2)Interrupt Control Operations
1) Instruction : SIM(Set Interrupt Mask)
Byte : 1
D7 D6 D5 D4 D3 D2 D1 D0
SOD SDE XXX R7.5 MSE M7.5 M6.5 M5.5

Serial Serial Reset R7.5 Mask Mask interrupts if bit=1


Output Data if D4=1 Set
Data Enable Enable
1=Enable if D3=1
Meaning: This is a multipurpose instruction which allows setting of
masking of interrupts and serial output data.
2) Instruction : RIM(Read Interrupt Mask)
Byte : 1
D7 D6 D5 D4 D3 D2 D1 D0
SID I7 I6 I5 IE 7.5 6.5 5.5

Serial Interrupt Interrupt Mask interrupts


Input Pending Enable if bit=1
Data if bit=1 if bit=1

Meaning: This is a multipurpose instruction which is used for reading


interrupt masking information as well as serial input data.
3) Instruction : EI (Enable Interrupt)
Byte : 1
Meaning: On execution interrupt enable flip flop is set and all
interrupts are enabled.

3)Machine control operations :


1)Instruction :PCHL
Format : PCH  H
PCL  L
Byte : 1
Meaning : This instruction moves the content of register H to higher
order byte of PC and contents of register L into lower order byte of
PC.
2) Instruction : NOP
Byte :1
Meaning : On execution no operation is performed only
instruction is fetched and decoded.
3) Instruction :HLT
Byte : 1
Meaning : After completing its execution CPU goes to a halt
state halting further execution. During Halt CPU maintains
register contents.
Define the following terms with diagram
a)T state b)Machine cycle c) Instruction cycle -3M
Clock

T state

T1 T2 T3 T1 T2 T3 T4

Machine Cycle 1 Machine Cycle 2

Instruction Cycle 1
1)T state : The subdivision of an operation which is performed
in one clock period is called as T state.
2) Machine Cycle :It is defined as the time required to
complete any operation which is subpart of the instruction. It
may contain any number of T states.It consists of 3 to 6 T
states depending upon which machine cycle operation is being
carried out.
3) Instruction Cycle : It is defined as the time required to
complete the execution of an instruction. It consists of one to
five machine cycle.

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