Module 1

1. Determine the binary and hexadecimal equivalent of decimal number 3049.57

2. Determine the Decimal and Hex equivalent of binary number 10111101.11
3. Convert (i) Binary 10101011 to Gray Code (ii) Gray 10011011 to Binary
4. Mention the applications of different number systems
5. Convert the decimal numbers from 0 to 12 to binary, BCD, excess-3 and gray codes.
6. Mention the applications of ASCII codes.
7. List the identifiers used in Verilog.
8. List the operators and their functions used in Verilog

Module 2

2.1 Boolean postulates and laws – Logic Functions and Gates, De-Morgan’s Theorems, Principle of
Duality

Part A

1. State and prove De-Morgan’s Laws.

2. Mention the significance of universal gates. Illustrate with an example.
3. Realize NOT, OR, AND, EX-OR gates using NAND gates.
4. Realize NOT, OR, AND, EX-OR gates using NOR gates
5. Using Boolean Algebra simplify the expression AB̅ C + B +BD̅ + ABD̅ + A̅ C
6. Find the complement of f = ab + cd. Show that f + f̅ = 1
7. Realize the following functions using NAND gates and AND-OR-INVERT (AOI) logic.

i)A Ꚛ B ii) ABC +AD + CD̅ ii) F(A,B,C,D) = AC̅ + AB̅ C +ABCD + ABD̅

iii) F(X,Y,Z) = XY + X̅ Y̅+ X̅ Y̅ Z̅

8. Mention the significance of duality principle in Boolean algebra.

Write the duels of the following function: AB̅ + ABC + A( B + AB̅ ) = 0 ii) A + B . A̅ .(A + B ) = 1

9. Find the complement of the following expressions

i)( x̅ + y + z̅) (x + y̅ ) (x + z) ii) f (A, B, C) = AB . ( A + B). C

10. Minimize the Boolean expression A̅ B (D̅ +C̅ D) + B (A +A̅ CD) into a single literal function.

11. Express F = P (Q̅ + S) into standard POS form.

12. Express the following function into sum of minterms.
i) F( w,x,y,z) = Σm(3,5,9,11, 15) ii) F( A.B.C) = ПM (2,4,5,7)
13. Express F (A,B,C) = AB + AC̅ + BC into standard SOP form.
14. Reduce the following function and implement the same using NAND gates.
F (A,B,C,D) = ПM (2, 4, 10, 11, 14, 15)
15. Express the following function as a sum of minterms and product of

maxterms F (A,B,C,D) = B̅ D + A̅ D + BD

16. Expand A + BC̅ + ABD̅ + ABCD to minterms and maxterms

 17. Obtain the minimal SOP expression for Σm(2, 7, 3, 5, 9, 11, 12,13,14,15) and implement

using NAND gates.

18. Reduce F (A,B,C,D) = ПM (1,2,3,5,6,7,8,9,12,13) and implement it in universal logic.

19. Show that P = F (A,B,C,D) = Σm(0,2,5,7,8,10,13,15) is the complement of

Q = F (A,B,C,D) = ПM (1,3,4,6,9,11,12,14). Use K-map to illustrate the complement nature of the

two equations.

20. For the Boolean expression F = ab’c +a’b’c + abc + abc + abc

(a) Obtain the truth table of F

(b) Use Boolean algebra to simplify the function to a minimum number of literals.

(c ) Obtain the truth table of the simplified expression and show that it is the same as the

one in part(a).

(d) Draw the logic diagram from the simplified expression

21. Reduce the expressions using K-map.

a) (A + B)(A + B̅ + C)(A + C̅ )

b) F(A,B,C,D)= Σm (7,8,10,11,15) + d(0,2,3,4,5,9,14)

c) f = ПM (0,1,4,5,6,8,9,12,13,14)

22. Find all the prime implicants of the following Boolean function and the determine which are
essential and nonessential prime implicants.

F (A,B,C,D) = Σm (1,3,4,5,10,11,12,13,14,15)

23. Write a Verilog code for the following

a) Basic 2-input OR gate.
b) Basic 2-input AND gate.
c) Basic NOT gate
d) Basic NAND gate.
e) Basic 2-input XOR gate.
24. Write a Verilog code and testbench to implement AND, OR, NOT and EXOR gates.

Module 3
1. Design 2:1, 4:1, 8:1 multiplexers.
2. Design 1:2, 1:4, 1:8 demultiplexers.
3. Design a full adder using multiplexers.
4. Design a half adder using multiplexers.
5. Design a half adder using basic and NAND gates.
6. Design a full adder using basic and NAND gates.
7. Design a half subtractor using basic and NAND gates.
8. Design a full subtractor using basic and NAND gates.
 9. Design a BCD to binary Encoder.
10. Design a binary to BCD Decoder.
11. Realize the function Y = A’B’ + AC + AB using a multiplexer.
12. Design a 2 to 4 decoder.
13. Design a 4 to 2 line priority encoder.
14. Implement a full adder circuit using Verilog.
15. Implement a half adder circuit using Verilog.
16. Implement a full subtractor circuit using Verilog.
17. Implement a half subtractor circuit using Verilog

Module 4
1. Compare combinational and sequential circuits.
2. List the application of flip-flops.
3. Explain race-around problem in flip-flops. How it is eliminated?
4. Explain the working of an SR flip-flop.
5. Draw the circuit and truth table of an D flip-flop.
6. Draw the circuit and truth table of an T flip-flop.
7. Explain the working of a Master-Slave JK flip-flop with logic diagram and truth table.
8. Draw the circuit diagram of a positive edge triggered JK flip-flop and explain its operation
with the help of a truth table. What is the problem associated with this flip-flop? Explain how
this problem is eliminated?
9. Explain the working of a T flip-flop with logic diagram and truth table.
10. Realize SR flipflop using gates and write the Verilog code.
11. Write a Verilog code for implementing D flipflop.
12. Write a Verilog code for implementing T flipflop.
13. Write a Verilog code for implementing JK flipflop.
 Logic families and its characteristics:
5.1 TTL,ECL,CMOS- Electrical characteristics of logic gates – logic levels and noise
margins, fan-out, propagation delay, transition time, power consumption and
power-delay product.
5.2 TTL inverter - circuit description and operation
5.3 CMOS inverter - circuit description and operation
5.4 Structure and operations of TTL and CMOS gates; NAND in TTL, NAND and NOR
in CMOS

5.1 TTL,ECL,CMOS- Electrical characteristics of logic gates – logic levels and noise
margins, fan-out, propagation delay, transition time, power consumption and
power-delay product.

Part A
1. Distinguish between fan-in and fan-out.
2. Explain noise margin.
3. Define propagation delay and power dissipation
4. Define propagation delay, transition time
5. State any two advantages of CMOS circuits.

Past B

1. a. Explain the general characteristics of the logic families. (14)

2. a. Explain the terms noise margin, power dissipation and sped power product of
integrated circuits (9)

b. .Compare TTL & CMOS logic families in terms of fan-in, fan-out, supply voltage, power
supply and propagation delay (5)
 3. Explain Propagation delay, power dissipation, Noise margin, and Fan-out of logical
circuits. How these parameters affect the performance of a logical family? (14)
4. Compare TTL, ECL and CMOS logic families (14)

5.2 TTL inverter - circuit description and operation

Part A

1. Draw the circuit of a TTL inverter.

2. Draw the transfer characteristics of a TTL inverter and explain the different zones
3. Differentiate totem-pole and open collector output of a TTL inverter. Which one can be
preferred for high speed applications?
4. Explain the tri-state configuration of a TTL inverter. Mention its advantage.
5. Describe the characteristics of a buffer logical circuit.
Part B

1 a. Discuss the advantages and disadvantages of a totem-pole connection. (5)

b. Explain a tri-state TTL inverter with circuit diagram and truth table. (9)

2. a. Draw the circuit of an open-collector inverter and explain its working. (7)

b. Explain a tri-state TTL inverter with circuit diagram and truth table. (7)

3. Differentiate between conventional AND operation and wired AND operation.(5)

b. Draw the circuit of an open-collector inverter and explain its working. (9)

4. a. Explain circuit and transfer characteristics of a TTL gate used as an inverter (9

b. Describe the advantages and disadvantages of a totem pole connection (5)

5. a. Explain the terms current sinking, current sourcing and fan-out of regarding TTL gate (5)

b. Explain how a Tri-state TTL inverter is operated in enable and disable states. (9)

5.3 CMOS inverter - circuit description and operation

Part A
1. Draw the circuit diagram of a CMOS- NOT gate and explain the working with truth table.
2. Mention the advantages of CMOS logic families
3. Draw the circuit diagram of a CMOS inverter and explain the working.
4. State any three advantages of CMOS circuits.
5. Compare TTL and CMOS logic families.
Part B
a.
1. a. Draw the circuit diagram of a CMOS- NOT gate and explain the working with truth
table. (7)

b. Mention the advantages of CMOS families. Draw the circuit of a Tristate CMOS inverter
and explain its working. (7)

2. a. With circuit diagram and truth table explain the working of a CMOS inverter. (8)
 b. Explain how PMOS and NMOS transistors can be connected to form a tri-state

inverter. Also explain the working with the help of a truth table. (6)

Circuit – 4 marks, Truth table – 3 marks, Explanation – 5 marks

5.4 Structure and operations of TTL and CMOS gates; NAND in TTL, NAND and
NOR in CMOS

Part A

1. Calculate the fan out of a standard TTL gate

2. Explain the limitation of a TTL NAND gate.
3. Draw the circuit of a two input CMOS NAND gate.
4. Draw the circuit of a two input CMOS NOR gate.
5. Draw the circuit of a two input TTL NAND gate.

Part B

1. a. Draw the circuit and explain the working of a two input CMOS NAND gate.

b. Explain the working of a TTL NAND gate with the help of a truth table.

2. Give a detailed description on the working of a Two-input TTL NAND gate. Draw the I/O
characteristics and also mention the advantages and disadvantages of using Totem-pole
configuration. (14)

3 a. Draw the circuit and explain the working of a two input CMOS NOR gate. (7)

b. Explain the working of a TTL NAND gate with the help of a truth table. (7)

4. a. Explain the working of a TTL NAND gate with the help of a truth table. (7)

b. Draw the circuit and explain the working of a two input CMOS NOR gate. (7)

5. a. With a neat circuit diagram describe the working of a Two-input TTL NAND gate. Draw the I/O
characteristics and also mention the advantages and disadvantages of using Totem-pole
configuration. (14)