<XR_PAGE_TITLE

8 > 7 6 5 4 3 2 1

Veneno for Lenovo

LPC
LPC For Debug
CH0
PCIE G3 X1 for WIFI / CNVI SODIMM DDR4
D NGFF(KEY E) USB2.0 for Bluetooth 4GB/8GB/16GB DDR4 D
WIFI/BT MODULE

NGFF(KEY M) PCIE G3 X4/ OPTION SATA

SPI SPI NOR FLASH
SSD 128GB / 256GB / 512GB W25Q128JVZPIQ

CML
GPU AMD EDP signal X2 / DDI A
PCIE G3 X4
R19-m18-70 (CML-BASE) EDP_BKLT_EN
(Support MS) LCM Connector
EDP_BKLT_PWM

USB2.0
USB Charger Camera
C
TPS2546RTER DMIC C

Digital array, D-Mic ,x2

On IO Board
USB 3.1 Re-driver USB3.1 G1 /USB2.0
PS8713/Parade Speaker 2*2W
HDA AUDIO CODEC
TDP : 15W ALC3287
USB 3.1 Re-driver USB3.1 G1 /USB2.0 Audio JACK
PS8713/Parade

USB2.0
I2C FPR
Touchpad
B B

TPM BGA1528 USB3.1 G2

SPI RTS5457T-GR
Z32H320TC
(Opt i on) 46 x 24 mm DP DDI B +PS8812
USB2.0 Type C
UART3
Debug connector Switch VBUS
NX20P5090

HDMI1.4
HDMI
EN

Switch DC Jack
LPC
ADP+
A
SMBUS Charger ETA7015E8A With DC-in LED A

ISL9238/instersil
EC Controller BATTERY
Hall sensor*1 GPIO
APX8132Ha1 IT5576E/ ITE
SMBUS
THERMAL SENSOR Bitland Information Technology Co.,Ltd.
Page Name
COVER PAGE
Size
Project Name R ev
Custom
Veneno V1.0
Speed/Pwm Matrix Date: Wednesday, August 21, 2019 Sheet 1 of 87
FAN*2 keyboard PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

TABLE OF CONTENTS
D
01 -- COVER PAGE 31 -- NA 61--PWR-DDR VDDQ/VTT/VPP
02 -- TABLE OF CONTENTS 32 -- HDMI CONN 62--NA D

03--CMLL-U(1/12)DDI,MISC,XDP,EDP 33 -- NA 63--PWR-+1.0V_PRIM
04--CML-U(2/12)DDR4 34 -- NA 64--PWR-Load Switch
05--CML-U(3/12)SPI,ESPI,SMB,LPC 35 -- TPM2.0 65--PWR-+1.8V_PRIM
06--CML-U(4/12)HDA,EMMC,SD 36 -- DISPLAY 66--PWR-CPU VR RT3602AH
07--CML-U(5/12)CLK,GPIO 37 -- NA 67--PWR-VCC_CORE/GT/SA
08--CML-U(6/12)GPIO 38 -- SENSORS & LID 68--VDD1V2 FOR TYPEC
09--CML-U(7/12)PCIE,USB,SATA 39 -- NA 69--GPU-VRAM
C 10--CML-U(8/12)Power 40 -- NA 70--GPU-VCORE1 C

11--CML-U(9/12)Power 41 -- NA 71--GPU-VCORE2
12--CML-U(10/12)Power,SVID 42 -- NA 72--GPU-VCORE3
13--CML-U(11/12)GND 43 -- WLAN WIFI BT MODULE 73--POWER MAP
14--CML-U(12/12)RSVD 44 -- NA 74--GPU PCIE
15--SOC (DECOUPLING)-1 45 -- NA 75--GPU MEN
16--SOC (DECOUPLING)-2 46 -- AUDIO CODEC(ALC3287) 76--GPU GPIO MISC
17--CPU_STRAP_PIN 47 -- AUDIO-SPKRS 77--GPU DP INTERFACE
B
18--NA 48 -- AUDIO-HEADSET 78--NA B

19--SODIMM_CHB 49 -- IO CONN 79--GPU POWER&GND

20--Sequence&Power Map 50 -- EC&TP&KB 80--GPU_RAM(GDDR5)
21--NA 51 -- DP SWITCH 81--GPU MS
22--NA 52 -- TYPE-C SW_PD 82--NA
23--NA 53 -- TYPE-C CONTROLLER 83--IO Board_IO CONNECTOR
24--SYSTEM FLASH 54 -- NA 84--IO Board_USB3.0 Redriver
25--NA 55 -- NA 85--IO Board_USB3.0_AOU
26--PCIE SSD MODULE 56 -- NA 86--IO Board_USB3.0_PORT2
A
27--NA 57 -- UART CONN&HOLE&CLIP 87--IO Board_SWITCH & LED A

28--FP 58 -- PWR_DCIN/BATT CONN

29--CPU THERMAL SENSOR 59 -- PWR_CHARGER
30--FAN conn 60 -- PWR-+V5P0A / +V3P3A Bitland Information Technology Co.,Ltd.
Page Name
2
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 2 of 87
INTERNAL ONLY BPAGE DRAWING PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
sky_y_mrd._ documents or disclosed to others or used for any purpose other than that for which it
Wed Jun 03 11:22:42 2015 was obtained with the expressed written consent of Bitland

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 A B C D E

+1.0VS_VCCSTG

XDP_TDO
R328 1 ns 2 51.0_J R0201

XDP_TMS
R329 1 ns 2 51.0_J R0201

XDP_TDI
R327 1 ns 2 51.0_J R0201

XDP_TCK0
R331 1 ns 2 51.0_J R0201

+1.0VS_VCCSTG
XDP_TCK1_PCH
1 R334 1 ns 2 51.0_J R0201 1

XDP_TCK0
R332 1 ns 2 51.0_J R0201

1
XDP_TRST_N
R324 R333 1 ns 2 51.0_J R0201

1K_J
R0201
UC1D

2
20MIL TP319 1 CATERR_SOC_N AA4 T6 XDP_TCK0
R322 2 1 43.0_F R0402 PECI_SOC AR1
CATERR# PROC_TCK
U6 XDP_TDI
50 PECI_EC H_PROCHOT#_R PECI PROC_TDI XDP_TDO
50,59,66 PROCHOT_N R323 1 2 499.0_F R0402 Y4 Y5
THERMTRIP_SOC_N BJ1
PROCHOT# PROC_TDO
T5 XDP_TMS
THRMTRIP# PROC_TMS
AB6 XDP_TRST_N
PROC_TRST#
U1
U2
BPM#_0
W6 XDP_TCK1_PCH
CRB install 499R,ARMOUR install 0R U3
BPM#_1 PCH_TCK
U5 XDP_TDI
U4
BPM#_2 PCH_TDI
W5 XDP_TDO
BPM#_3 PCH_TDO
P5 XDP_TMS
PCH_TMS
Y6 XDP_TRST_N
PCH_TRST#
P6 XDP_TCK0
PCH_JTAGX
1 TP_GPP_E_3_CPU_GP_0CE9 W2
20MIL TP320 GPP_E3/CPU_GP0 PROC_PREQ#
1 CN3 W1
20MIL TP300 HW_ID3_NC GPP_E7/CPU_GP1 PROC_PRDY#
1 CB34
20MIL TP10132 GPP_B3/CPU_GP2
CC35
43 BT_RF_KILL_N GPP_B4/CPU_GP3

49.9_F R0201 2 1R325 CPU_POPIRCOMP BP27

49.9_F R0201 2 1R326 PCH_OPIRCOMP BW25
PROC_POPIRCOMP
+1.0V_VCCST PCH_OPIRCOMP

1K_J
THERMTRIP_SOC_N 4 of 20 WHL_U_IP_CCG
R321 2 1

R0201
2 2

+V3P3A +V3P3A 4,5,7,9,11,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81

+1.0VS_VCCIO +1.0VS_VCCIO 10,17,64
+1.0VS_VCCSTG +1.0VS_VCCSTG 10,12,64 UC1A
+1.0V_VCCST +1.0V_VCCST 7,10,12,17,64,66
AL5 AG4
32 DDI1_TX0_DN DDI1_TXN_0 EDP_TXN_0 EDP_TX0_SOC_DN 36
AL6 AG3
32 DDI1_TX0_DP DDI1_TXP_0 EDP_TXP_0 EDP_TX0_SOC_DP 36
32 DDI1_TX1_DN
AJ5
AJ6
DDI1_TXN_1 EDP_TXN_1
AG2
AG1
EDP_TX1_SOC_DN 36 <eDP>
32 DDI1_TX1_DP DDI1_TXP_1 EDP_TXP_1 EDP_TX1_SOC_DP 36
HDMI 32 DDI1_TX2_DN AF6
AF5
DDI1_TXN_2 EDP_TXN_2
AJ4
AJ3
32 DDI1_TX2_DP DDI1_TXP_2 EDP_TXP_2
AE5 AJ2
32 DDI1_TX3_DN DDI1_TXN_3 EDP_TXN_3
AE6 AJ1
32 DDI1_TX3_DP DDI1_TXP_3 EDP_TXP_3
AC4
3 51 DDI2_TX0_DN DDI2_TXN_0 3
AC3 AH4
51 DDI2_TX0_DP DDI2_TXP_0 EDP_AUX EDP_AUX_SOC_DN 36
AC1 AH3
51 DDI2_TX1_DN DDI2_TXN_1 EDP_AUX_P EDP_AUX_SOC_DP 36
AC2
51 DDI2_TX1_DP DDI2_TXP_1
<TYPEC > 51 DDI2_TX2_DN
AE4
AE3
DDI2_TXN_2 DISP_UTILS
AM7
51 DDI2_TX2_DP DDI2_TXP_2
AE1 AC7
51 DDI2_TX3_DN DDI2_TXN_3 DDI1_AUX
AE2 AC6
51 DDI2_TX3_DP DDI2_TXP_3 DDI1_AUX_P
AD4
DDI2_AUX DDI2_AUX_SOC_DN 51
DDI2_AUX_P
AD3
AG7
DDI2_AUX_SOC_DP 51 <TYPEC >
DDI3_AUX
AG6
DDI3_AUX_P

DDI1_HPD
CN6
GPP_E13/DDPB_HPD0/DISP_MISC0 DDI1_HPD 32
GPP_E14/DDPC_HPD1/DISP_MISC1
CM6
CP7 1
IN_HPD 51,52 <TYPEC >
GPP_E15/DPPD_HPD2/DISP_MISC2
CP6 SMC_RUNTIME_SCI_N TP349 20MIL
GPP_E16/DPPE_HPD3/DISP_MISC3
CM7 EDP_HPD SMC_RUNTIME_SCI_N 50
GPP_E17/EDP_HPD/DISP_MISC4 EDP_HPD 36
CK11
EDP_BKLTEN EDP_BKLT_EN 36
CG11
EDP_VDDEN
CH11
EDP_VDD_EN 36
+V3P3A +1.0VS_VCCIO EDP_BKLTCTL EDP_BKLT_PWM 36

<Type-c>--->Remove
1

R3091 2R0201 24.9_F EDP_COMP AM6

R392 DISP_RCOMP
2.2k_J CC8
R0201 32 DDI1_DDC_SCK GPP_E18/DPPB_CTRLCLK/CNV_BT_HOST_WAKE#
5/23 change to I HDMI 32 DDI1_DDC_SDA
CC9
GPP_E19/DPPB_CTRLDATA
TP_DDI2_DDC_SCL
20MIL TP363 1 CH4
2

DDI2_DDC_SDA GPP_E20/DPPC_CTRLCLK
CH3
GPP_E21/DPPC_CTRLDATA

DDI2_DDC_SDA
CP4
R11606 GPP_E22/DPPD_CTRLCLK
4 1 ns 2 0_J CN4 4
50 BOMACO_EN GPP_E23/DPPD_CTRLDATA
R0402 NI
CR26
20190423:Reserve GPIO for BOMACO_EN GPP_H16/DDPF_CTRLCLK

Vinafix.com
CP26
GPP_H17/DDPF_CTRLDATA
2

WHL_U_IP_CCG
1 of 20 Bitland Information Technology Co.,Ltd.
R11603
ns
100K_J Page Name
R0402 3
Size Project Name Re v
1

Custom
Veneno 1.3
Date: Thursday, August 22, 2019 Sheet 3 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

A B C D E

Vinafix.com
 5 4 3 2 1

Interleaved Interleaved
UC1B
UC1C
D V32 D
A26 DDR0_CKN_0/DDR0_CKN_0 J22 AF28
DDR0_DQ_0/DDR0_DQ_0 V31 19 M_B_DQ<0> DDR1_DQ_0/DDR0_DQ_16 DDR1_CKN_0/DDR1_CKN_0 M_B_DIM0_CK0_DDR1_DN 19
D26 DDR0_CKP_0/DDR0_CKP_0 H25 AF29
DDR0_DQ_1/DDR0_DQ_1 T32 19 M_B_DQ<1> DDR1_DQ_1/DDR0_DQ_17 DDR1_CKP_0/DDR1_CKP_0 M_B_DIM0_CK0_DDR1_DP 19
D28 DDR0_CKN_1/DDR0_CKN_1 G22 AE28
DDR0_DQ_2/DDR0_DQ_2 T31 19 M_B_DQ<2> DDR1_DQ_2/DDR0_DQ_18 DDR1_CKN_1/DDR1_CKN_1 M_B_DIM0_CK1_DDR1_DN 19
C28 DDR0_CKP_1/DDR0_CKP_1 H22 AE29
DDR0_DQ_3/DDR0_DQ_3 19 M_B_DQ<3> DDR1_DQ_3/DDR0_DQ_19 DDR1_CKP_1/DDR1_CKP_1 M_B_DIM0_CK1_DDR1_DP 19
B26 F25
DDR0_DQ_4/DDR0_DQ_4 U36 19 M_B_DQ<4> DDR1_DQ_4/DDR0_DQ_20
C26 DDR0_CKE_0/DDR0_CKE_0 J25 T28
DDR0_DQ_5/DDR0_DQ_5 U37 19 M_B_DQ<5> DDR1_DQ_5/DDR0_DQ_21 DDR1_CKE_0/DDR1_CKE_0 M_B_DIM0_CKE0 19
B28 DDR0_CKE_1/DDR0_CKE_1 G25 T29
DDR0_DQ_6/DDR0_DQ_6 U34 19 M_B_DQ<6> DDR1_DQ_6/DDR0_DQ_22 DDR1_CKE_1/DDR1_CKE_1 M_B_DIM0_CKE1 19
A28 DDR0_CKE_2/NC F22 V28
DDR0_DQ_7/DDR0_DQ_7 U35 19 M_B_DQ<7> DDR1_DQ_7/DDR0_DQ_23 DDR1_CKE_2/NC
B30 DDR0_CKE_3/NC D22 V29
DDR0_DQ_8/DDR0_DQ_8 19 M_B_DQ<8> DDR1_DQ_8/DDR0_DQ_24 DDR1_CKE_3/NC
D30 C22
DDR0_DQ_9/DDR0_DQ_9 AE32 19 M_B_DQ<9> DDR1_DQ_9/DDR0_DQ_25 AL37
B33 DDR0_CS#_0/DDR0_CS#_0
19 M_B_DQ<10>
C24 DDR1_CS#_0/DDR1_CS#_0 M_B_DIM0_CS0_N 19
DDR0_DQ_10/DDR0_DQ_10 AF32 DDR1_DQ_10/DDR0_DQ_26 AL35
D32 DDR0_CS#_1/DDR0_CS#_1
19 M_B_DQ<11> D24 DDR1_CS#_1/DDR1_CS#_1 M_B_DIM0_CS1_N 19
DDR0_DQ_11/DDR0_DQ_11 AE31 DDR1_DQ_11/DDR0_DQ_27 AL36
A30 DDR0_ODT_0/DDR0_ODT_0 A22 DDR1_ODT_0/DDR1_ODT_0 M_B_DIM0_ODT0 19
DDR0_DQ_12/DDR0_DQ_12 AF31 19 M_B_DQ<12> DDR1_DQ_12/DDR0_DQ_28 AL34
C30 NC/DDR0_ODT_1 B22 NC/DDR1_ODT_1 M_B_DIM0_ODT1 19
DDR0_DQ_13/DDR0_DQ_13 19 M_B_DQ<13> DDR1_DQ_13/DDR0_DQ_29
B32 A24 AG36
DDR0_DQ_14/DDR0_DQ_14 AC37 19 M_B_DQ<14> DDR1_DQ_14/DDR0_DQ_30 DDR1_CAB_9/DDR1_MA_0 M_B_A0 19
C32 DDR0_CAB_9/DDR0_MA_0 B24 AG35
DDR0_DQ_15/DDR0_DQ_15 AC36 19 M_B_DQ<15> DDR1_DQ_15/DDR0_DQ_31 DDR1_CAB_8/DDR1_MA_1 M_B_A1 19
H37 DDR0_CAB_8/DDR0_MA_1 G31 AF34
DDR0_DQ_16/DDR0_DQ_32 AC34 19 M_B_DQ<16> DDR1_DQ_16/DDR0_DQ_48 DDR1_CAB_5/DDR1_MA_2 M_B_A2 19
H34 DDR0_CAB_5/DDR0_MA_2 G32 AG37
DDR0_DQ_17/DDR0_DQ_33 AC35 19 M_B_DQ<17> DDR1_DQ_17/DDR0_DQ_49 NC/DDR1_MA_3 M_B_A3 19
K34 NC/DDR0_MA_3 H29 AE35
DDR0_DQ_18/DDR0_DQ_34 AA35 19 M_B_DQ<18> DDR1_DQ_18/DDR0_DQ_50 NC/DDR1_MA_4 M_B_A4 19
K35 NC/DDR0_MA_4 H28 AF35
DDR0_DQ_19/DDR0_DQ_35 AB35 19 M_B_DQ<19> DDR1_DQ_19/DDR0_DQ_51 DDR1_CAA_0/DDR1_MA_5 M_B_A5 19
H36 DDR0_CAA_0/DDR0_MA_5 G28 AE37
DDR0_DQ_20/DDR0_DQ_36 AA37 19 M_B_DQ<20> DDR1_DQ_20/DDR0_DQ_52 DDR1_CAA_2/DDR1_MA_6 M_B_A6 19
H35 DDR0_CAA_2/DDR0_MA_6 G29 AC29
DDR0_DQ_21/DDR0_DQ_37 AA36 19 M_B_DQ<21> DDR1_DQ_21/DDR0_DQ_53 DDR1_CAA_4/DDR1_MA_7 M_B_A7 19
K36 DDR0_CAA_4/DDR0_MA_7 H31 AE36
DDR0_DQ_22/DDR0_DQ_38 AB34 19 M_B_DQ<22> DDR1_DQ_22/DDR0_DQ_54 DDR1_CAA_3/DDR1_MA_8 M_B_A8 19
K37 DDR0_CAA_3/DDR0_MA_8 H32 AB29
DDR0_DQ_23/DDR0_DQ_39 W36 19 M_B_DQ<23> DDR1_DQ_23/DDR0_DQ_55 DDR1_CAA_1/DDR1_MA_9 M_B_A9 19
N36 DDR0_CAA_1/DDR0_MA_9 L31 AG34
DDR0_DQ_24/DDR0_DQ_40 Y31 19 M_B_DQ<24> DDR1_DQ_24/DDR0_DQ_56 DDR1_CAB_7/DDR1_MA_10 M_B_A10_AP 19
N34 DDR0_CAB_7/DDR0_MA_10 L32 AC28
DDR0_DQ_25/DDR0_DQ_41 W34 19 M_B_DQ<25> DDR1_DQ_25/DDR0_DQ_57 DDR1_CAA_7/DDR1_MA_11 M_B_A11 19
R37 DDR0_CAA_7/DDR0_MA_11 N29 AB28
DDR0_DQ_26/DDR0_DQ_42 AA34 19 M_B_DQ<26> DDR1_DQ_26/DDR0_DQ_58 DDR1_CAA_6/DDR1_MA_12 M_B_A12 19
R34 DDR0_CAA_6/DDR0_MA_12 N28 AK35
DDR0_DQ_27/DDR0_DQ_43 AC32 19 M_B_DQ<27> DDR1_DQ_27/DDR0_DQ_59 DDR1_CAB_0/DDR1_MA_13 M_B_A13 19
N37 DDR0_CAB_0/DDR0_MA_13 L28
DDR0_DQ_28/DDR0_DQ_44 19 M_B_DQ<28> DDR1_DQ_28/DDR0_DQ_60 AJ35
N35 L29 DDR1_CAB_2/DDR1_MA_14 M_B_A14_WE_N 19
DDR0_DQ_29/DDR0_DQ_45 AC31 19 M_B_DQ<29> DDR1_DQ_29/DDR0_DQ_61 AK34
R36 DDR0_CAB_2/DDR0_MA_14 N31 DDR1_CAB_1/DDR1_MA_15 M_B_A15_CAS_N 19
DDR0_DQ_30/DDR0_DQ_46 AB32 19 M_B_DQ<30> DDR1_DQ_30/DDR0_DQ_62 AJ34
R35 DDR0_CAB_1/DDR0_MA_15 N32 DDR1_CAB_3/DDR1_MA_16 M_B_A16_RAS_N 19
DDR0_DQ_31/DDR0_DQ_47 Y32 19 M_B_DQ<31> DDR1_DQ_31/DDR0_DQ_63
AN35 DDR0_CAB_3/DDR0_MA_16 AJ29
DDR0_DQ_32/DDR1_DQ_0 19 M_B_DQ<32> DDR1_DQ_32/DDR1_DQ_16 AJ37
AN34 AJ30 DDR1_CAB_4/DDR1_BA_0 M_B_BA0 19
DDR0_DQ_33/DDR1_DQ_1 W32 19 M_B_DQ<33> DDR1_DQ_33/DDR1_DQ_17 AJ36
AR35 DDR0_CAB_4/DDR0_BA_0 AM32 DDR1_CAB_6/DDR1_BA_1 M_B_BA1 19
C DDR0_DQ_34/DDR1_DQ_2 AB31 19 M_B_DQ<34> DDR1_DQ_34/DDR1_DQ_18 W29 C
AR34 DDR0_CAB_6/DDR0_BA_1 AM31 DDR1_CAA_5/DDR1_BG_0 M_B_BG0 19
DDR0_DQ_35/DDR1_DQ_3 V34 19 M_B_DQ<35> DDR1_DQ_35/DDR1_DQ_19
AN37
DDR0_DQ_36/DDR1_DQ_4
DDR0_CAA_5/DDR0_BG_0
19 M_B_DQ<36> AM30
DDR1_DQ_36/DDR1_DQ_20 Y28
M_B_BG1_C 1 RM98 2 SHORT_0201
AN36 AM29 DDR1_CAA_9/DDR1_BG_1 M_B_BG1 19
DDR0_DQ_37/DDR1_DQ_5 V35 19 M_B_DQ<37> DDR1_DQ_37/DDR1_DQ_21 W28
AR36 DDR0_CAA_8/DDR0_ACT# AJ31 DDR1_CAA_8/DDR1_ACT# M_B_ACT_N 19
DDR0_DQ_38/DDR1_DQ_6 W35 19 M_B_DQ<38> DDR1_DQ_38/DDR1_DQ_22
AR37 DDR0_CAA_9/DDR0_BG_1 AJ32
DDR0_DQ_39/DDR1_DQ_7 19 M_B_DQ<39> DDR1_DQ_39/DDR1_DQ_23 H24
AU35 AR31 DDR1_DQSN_0/DDR0_DQSN_2 M_B_DQS_DN<0> 19
DDR0_DQ_40/DDR1_DQ_8 C27 19 M_B_DQ<40> DDR1_DQ_40/DDR1_DQ_24 G24
AU34 DDR0_DQSN_0/DDR0_DQSN_0 AR32 DDR1_DQSP_0/DDR0_DQSP_2 M_B_DQS_DP<0> 19
DDR0_DQ_41/DDR1_DQ_9 D27 19 M_B_DQ<41> DDR1_DQ_41/DDR1_DQ_25 C23
AW35 DDR0_DQSP_0/DDR0_DQSP_0 AV30 DDR1_DQSN_1/DDR0_DQSN_3 M_B_DQS_DN<1> 19
DDR0_DQ_42/DDR1_DQ_10 D31 19 M_B_DQ<42> DDR1_DQ_42/DDR1_DQ_26 D23
AW34 DDR0_DQSN_1/DDR0_DQSN_1 AV29 DDR1_DQSP_1/DDR0_DQSP_3 M_B_DQS_DP<1> 19
DDR0_DQ_43/DDR1_DQ_11 C31 19 M_B_DQ<43> DDR1_DQ_43/DDR1_DQ_27 G30
AU37 DDR0_DQSP_1/DDR0_DQSP_1 AR30 DDR1_DQSN_2/DDR0_DQSN_6 M_B_DQS_DN<2> 19
DDR0_DQ_44/DDR1_DQ_12 J35 19 M_B_DQ<44> DDR1_DQ_44/DDR1_DQ_28 H30
AU36 DDR0_DQSN_2/DDR0_DQSN_4 AR29 DDR1_DQSP_2/DDR0_DQSP_6 M_B_DQS_DP<2> 19
DDR0_DQ_45/DDR1_DQ_13 J34 19 M_B_DQ<45> DDR1_DQ_45/DDR1_DQ_29 L30
AW36 DDR0_DQSP_2/DDR0_DQSP_4 AV32 DDR1_DQSN_3/DDR0_DQSN_7 M_B_DQS_DN<3> 19
DDR0_DQ_46/DDR1_DQ_14 P34 19 M_B_DQ<46> DDR1_DQ_46/DDR1_DQ_30 N30
AW37 DDR0_DQSN_3/DDR0_DQSN_5 AV31 DDR1_DQSP_3/DDR0_DQSP_7 M_B_DQS_DP<3> 19
DDR0_DQ_47/DDR1_DQ_15 P35 19 M_B_DQ<47> DDR1_DQ_47/DDR1_DQ_31 AL31
BA35 DDR0_DQSP_3/DDR0_DQSP_5 BA32 DDR1_DQSN_4/DDR1_DQSN_2 M_B_DQS_DN<4> 19
DDR0_DQ_48/DDR1_DQ_32 AP35 19 M_B_DQ<48> DDR1_DQ_48/DDR1_DQ_48 AL30
BA34 DDR0_DQSN_4/DDR1_DQSN_0 BA31 DDR1_DQSP_4/DDR1_DQSP_2 M_B_DQS_DP<4> 19
DDR0_DQ_49/DDR1_DQ_33 AP34 19 M_B_DQ<49> DDR1_DQ_49/DDR1_DQ_49 AU31
BC35 DDR0_DQSP_4/DDR1_DQSP_0 BD31 DDR1_DQSN_5/DDR1_DQSN_3 M_B_DQS_DN<5> 19
DDR0_DQ_50/DDR1_DQ_34 AV34 19 M_B_DQ<50> DDR1_DQ_50/DDR1_DQ_50 AU30
BC34 DDR0_DQSN_5/DDR1_DQSN_1 BD32 DDR1_DQSP_5/DDR1_DQSP_3 M_B_DQS_DP<5> 19
DDR0_DQ_51/DDR1_DQ_35 AV35 19 M_B_DQ<51> DDR1_DQ_51/DDR1_DQ_51 BC31
BA37 DDR0_DQSP_5/DDR1_DQSP_1 BA30 DDR1_DQSN_6/DDR1_DQSN_6 M_B_DQS_DN<6> 19
DDR0_DQ_52/DDR1_DQ_36 BB35 19 M_B_DQ<52> DDR1_DQ_52/DDR1_DQ_52 BC30
BA36 DDR0_DQSN_6/DDR1_DQSN_4 BA29 DDR1_DQSP_6/DDR1_DQSP_6 M_B_DQS_DP<6> 19
DDR0_DQ_53/DDR1_DQ_37 BB34 19 M_B_DQ<53> DDR1_DQ_53/DDR1_DQ_53 BH31
BC36 DDR0_DQSP_6/DDR1_DQSP_4 BD29 DDR1_DQSN_7/DDR1_DQSN_7 M_B_DQS_DN<7> 19
DDR0_DQ_54/DDR1_DQ_38 BF34 19 M_B_DQ<54> DDR1_DQ_54/DDR1_DQ_54 BH30
BC37 DDR0_DQSN_7/DDR1_DQSN_5 BD30 DDR1_DQSP_7/DDR1_DQSP_7 M_B_DQS_DP<7> 19
DDR0_DQ_55/DDR1_DQ_39 BF35 19 M_B_DQ<55> DDR1_DQ_55/DDR1_DQ_55
BE35 DDR0_DQSP_7/DDR1_DQSP_5 BG31
DDR0_DQ_56/DDR1_DQ_40 19 M_B_DQ<56> DDR1_DQ_56/DDR1_DQ_56 Y29
BE34 BG32 NC/DDR1_ALERT# DDR1_B_ALERT_N 19
DDR0_DQ_57/DDR1_DQ_41 W37 19 M_B_DQ<57> DDR1_DQ_57/DDR1_DQ_57 AE34
BG35 NC/DDR0_ALERT# BK32 NC/DDR1_PAR DDR4_DRAMRST_N DDR1_B_PARITY 19
DDR0_DQ_58/DDR1_DQ_42 W31 19 M_B_DQ<58> DDR1_DQ_58/DDR1_DQ_58 BU31
BG34 NC/DDR0_PAR BK31 DRAM_RESET# DDR4_DRAMRST_N 4,19
DDR0_DQ_59/DDR1_DQ_43 19 M_B_DQ<59> DDR1_DQ_59/DDR1_DQ_59
BE37 F36 BG29 SM_RCOMP0
DDR0_DQ_60/DDR1_DQ_44 DDR_VREF_CA +V_DDR_CA_VREF 19 19 M_B_DQ<60> DDR1_DQ_60/DDR1_DQ_60 BN28
BE36
DDR0_DQ_61/DDR1_DQ_45 DDR0_VREF_DQ_0
D35
19 M_B_DQ<61> BG30
DDR1_DQ_61/DDR1_DQ_61
DDR_RCOMP_0
BN27
SM_RCOMP1
BG36
DDR0_DQ_62/DDR1_DQ_46 DDR0_VREF_DQ_1
D37
19 M_B_DQ<62> BK30
DDR1_DQ_62/DDR1_DQ_62
DDR_RCOMP_1
BN29
SM_RCOMP2
BG37 E36 BK29 DDR_RCOMP_2
DDR0_DQ_63/DDR1_DQ_47 DDR1_VREF_DQ DDR_VTT_CTRL +V_DDR_VREFDQ02_CHB 19 19 M_B_DQ<63> DDR1_DQ_63/DDR1_DQ_63
C35
DDR_VTT_CTL

2
WHL_U_IP_CCG 3 of 20 R301 R49 R303
WHL_U_IP_CCG 2 of 20 100_F 80.6_F 121.0_F
R0201 R0201 R0402

B B

1
+V3P3SX
2

Default
R404
R0201
4.7K_F
Memory size 4Gb or 8Gb 16Gb
1

SM_PG_CTRL 4,61 +V3P3A RM95,RM96,RM97,RM98 RM95,RM96,RM97,RM98

need uninstall need install page4,19,20
DRAM M9 pin
RM99,RM100 RM99,RM100
3

2
Q328
need install need uninstall
1 2 1 LMBT3904LT1G R414
+V1P2U_VDDQ R486 10K_J R0201 SOT23-3
+V3P3A 10K_J RM79,RM81,RM83,RM85, RM79,RM81,RM83,RM85,
DDR_VTT_CTRL DRAM E9 pin RM87,RM89,RM91,RM93 RM87,RM89,RM91,RM93 page19,20
2

R0201
need install 0 ohm need install 240 ohm
1

C1170

1
0.01UF/10V,X7R
C0201 ns RM3 200 ohm RM3 121 ohm
page4
2

ns SOC RCOMP0 need install need install

R488
SM_PG_CTRL 4,61
10K_J
D2
R0201 2/2 Add (4Gb 8Gb) & (16Gb) BOM option table
Q3281B
1

ns NX3008NBKS 350mA 30V

A G2 A

D1
S2
Q3281A SOT363M
NI Bitland Information Technology Co.,Ltd.
DDR_VTT_CTRL G1 ns
Page Name
NX3008NBKS 350mA 30V
4
Size
SOT363M Project Name Re v
Custom
S1
NI Veneno 1.3
+V3P3A
ns Date: Wednesday, August 21, 2019 Sheet 4 of 87
+V3P3A 3,5,7,9,11,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81

Vinafix.com
+V1P2U_VDDQ +V1P2U_VDDQ 10,19,51,61,64 PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

+V3P3A +V3P3A

1
UC1E
R572 R573
CH37 CK14
24,35,50 SPI0_CLK SPI0_CLK GPP_C0/SMBCLK SODIMM0_1_SMB_CLK_R 19 ns 10K_Jns 10K_J
CF37 CH15
24,35,50 SPI0_MISO SPI0_MISO GPP_C1/SMBDATA SODIMM0_1_SMB_DATA_R 19 R0201 R0201
CF36 CJ15
24,35,50 SPI0_MOSI SPI0_MOSI GPP_C2/SMBALERT# STRAP_GPP_C2 17
CF34
SPI Flash 24 SPI0_IO2 SPI0_IO2 SML0_CLK
CG34 CH14 1 TP598 20MIL

2
24 SPI0_IO3 SPI0_IO3 GPP_C3/SML0CLK SML0_DATA
CG36 CF15 1 TP599 20MIL
D 24,50 FLASH_SPI_CS0_N CG35
SPI0_CS0# GPP_C4/SML0DATA
CG15 D
SPI0_CS1# GPP_C5/SML0ALERT# STRAP_GPP_C5 17
CH34
35 TPM_SPI_CS0_N SPI0_CS2#
CN15 SML1_CLK_R
GPP_C6/SML1CLK
CM15 SML1_DATA_R SOC_SML1_CLK
GPP_C7/SML1DATA THERMAL_ALERT#_R SOC_SML1_DATA 51
CC34 R563 2 1 0_J R0201
1 CF20
GPP_B23/SML1ALERT#/PCHHOT# THERMAL_ALERT# 29,50
20MIL TP10151 1 CG22
GPP_D1/SPI1_CLK/BK1/SBK1 ns
3/2 R9863 change to NI,THERMAL HW shutdown
20MIL TP10152 CF22
GPP_D2/SPI1_MISO_IO1/BK2/SBK2
GPP_D3/SPI1_MOSI_IO0/BK3/SBK3
1 CG23 CA29
20MIL TP10153 CH23
GPP_D21/SPI1_IO2 GPP_A1/LAD0/ESPI_IO0
BY29
LPC_AD0 43,50
+V3P3SX CG20
GPP_D22/SPI1_IO3 GPP_A2/LAD1/ESPI_IO1
BY27
LPC_AD1 43,50
GPP_D0/SPI1_CS0#/BK0/SBK0 GPP_A3/LAD2/ESPI_IO2
BV27
LPC_AD2 43,50 WLAN/EC
GPP_A4/LAD3/ESPI_IO3
CA28
LPC_AD3 43,50
1
GPP_A5/LFRAME#/ESPI_CS#
CA27 ESPI_RST LPC_FRAME_N 43,50
R566 CH7 GPP_A14/SUS_STAT#/ESPI_RESET# ESPI_RST 50
CL_CLK
10K_J CH8 LPC_CLK_EC_R 1 22.0_F
CL_DATA BV32 R564 2 r0201
R0201 CH9 GPP_A9/CLKOUT_LPC0/ESPI_CLK
BV30 LPC_CLK_PRT80_R R565 2 1 22.0_F
LPC_CLK_EC 50
CL_RST# r0201
GPP_A10/CLKOUT_LPC1 LPC_CLK_PRT80 43
5/9 EC_KBRST# Add PU R1066 10Kohm +V3P3SX BY30
GPP_A8/CLKRUN# PM_CLKRUN_N 50
2

BV29
50 EC_KBRST# GPP_A0/RCIN#/TIME_SYNC1
To EC 50 LPC_SERIRQ
BV28
GPP_A6/SERIRQ +V3P3A
LPC Mode WHL_U_IP_CCG 5 of 20

2
R501
+V3P3A 8.2k_J

C R559 1 210K_J R0201 LPC_SERIRQ C

1
PM_CLKRUN_N R0402
5/9 Page50 EC pin24 BAT_CHGOK_LED_N change to EC_KBRST#,connect to SOC pin AW13(RCIN)

2
R502
1K_J
+V3P3A +V3P3A 3,4,7,9,11,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81
ns

1
+V3P3SX +V3P3SX 4,6,7,17,19,26,30,32,36,43,46,50,64,81 R0201

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
5
Size Project Name Rev
Custom
Veneno 1.3

Vinafix.com
Date: Wednesday, August 21, 2019 Sheet 5 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

To Enable ME Override

R648 1 2 1K_J R0402 STRAP_HDA_SDO_SOC

ME_Flash_EN

D Difference with armour 5/23 R9848 install,BIOS request D

Add EC to enable ME override

R693 2 1 22.0_F r0201 HDA_SYNC_SOC

46 HDA_SYNC
R686 2 1 33.0_J R0201 HDA_BCLK
46 HDA_BCLK_R
R695 2 1 22.0_F r0201 STRAP_HDA_SDO_SOC
46 STRAP_HDA_SDO
HDA_RST_N_SOC

Rev_0.53

UC1G
HDA_SYNC_SOC BN34 CH36
HDA_BCLK BN37
HDA_SYNC/I2S0_SFRM GPP_G0/SD_CMD
CL35
STRAP_HDA_SDO_SOC BN36
HDA_BCLK/I2S0_SCLK GPP_G1/SD_DATA0
CL36
HDA_SDI0 HDA_SDO/I2S0_TXD GPP_G2/SD_DATA1
HDA for AUDIO 46 HDA_SDI0
BN35
BL36
HDA_SDI0/I2S0_RXD GPP_G3/SD_DATA2
CM35
CN35
20MIL TP10138 1 HDA_RST_N_SOC BL35
HDA_SDI1/I2S1_RXD/SNDW1_DATA GPP_G4/SD_DATA3
CH35
HDA_RST#/I2S1_SCLK/SNDW1_CLK GPP_G5/SD_CD#
CK23
GPP_D23/I2S_MCLK GPP_G6/SD_CLK
CK36 ns
CK34 TP_SD_WP R664 2 1 0_J R0201
GPP_G7/SD_WP
BL37
I2S1_SFRM/SNDW2_CLK
BL34
I2S1_TXD/SNDW2_DATA
C Difference with armour C
Add 0ohm NI
CJ32
43 CNVI_RF_RESET_N GPP_H1/I2S2_SFRM/CNV_BT_I2S_BCLK/CNV_RF_RESET#
20MIL TP10125 1 CH32
20180430 CH29
GPP_H0/I2S2_SCLK/CNV_BT_I2S_SCLK
43 XTAL_CLKREQ GPP_H2/I2S2_TXD/CNV_BT_I2S_SDI/MODEM_CLKREQ
20MIL TP10126 1 CH30
BW36
GPP_H3/I2S2_RXD/CNV_BT_I2S_SDO
GPP_A17/SD_VDD1_PWR_EN#/ISH_GP7
BY31
20MIL TP10161 1 CP24 GPP_A16/SD_1P8_SEL WLAN_DET_N 43,81
WIFI_DISABLE_N_R GPP_D19/DMIC_CLK0/SNDW4_CLK
43 WIFI_DISABLE_N R11614 2 1 SHORT_0201 CN24
GPP_D20/DMIC_DATA0/SNDW4_DATA CK33 R11478 2 ns 1 200_J R0201
SD_1P8_RCOMP
1 2 SHORT_0402 DMIC_CLK_CPU CK25
CM34 R615 2 1 200_J R0201
36,46 DMIC_CLK R11533 SD_3P3_RCOMP
R11534 1 2 SHORT_0402 DMIC_DATA_CPU CJ25
GPP_D17/DMIC_CLK1/SNDW3_CLK
36,46 DMIC_DATA GPP_D18/DMIC_DATA1/SNDW3_DATA

CF35
17,46,50 HDA_SPKR GPP_B14/SPKR
7 of 20
WHL_U_IP_CCG

1/4 Connect codec

+V3P3A +V3P3A 3,4,5,7,9,11,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81

+V3P3SX +V3P3SX 4,5,7,17,19,26,30,32,36,43,46,50,64,81

B UC1I 20180430 B
CR30
43 CNVI_WGR_DATA0_DN CNV_WR_D0N GPPC_H18_BOOTMPC
CP30 CN27
43 CNVI_WGR_DATA0_DP CNV_WR_D0P GPP_H18/CPU_C10_GATE# GPPC_H18_BOOTMPC 64

43 CNVI_WGR_DATA1_DN
CM30 CM27 R11549 2
ns
1 0_J R0201
CN30
CNV_WR_D1N GPP_H19/TIMESYNC_0 BOMACO_EN 50
43 CNVI_WGR_DATA1_DP CNV_WR_D1P GPP_H21 20190219: add 'BOMACO_EN' for dGPU MS design
CF25
GPP_H21 GPP_H21 17
CN32 CN26
43 CNVI_WT_DATA0_DN CNV_WT_D0N GPP_H22 GPP_H23
43 CNVI_WT_DATA0_DP CM32 CM26 1 TP662 20MIL
CNV_WT_D0P GPP_H23
CK17
3/27 Add TP662
GPP_F10
CP33
43 CNVI_WT_DATA1_DN CNV_WT_D1N
CN33
43 CNVI_WT_DATA1_DP CNV_WT_D1P GPD_7
BV35
GPD7 GPD_7 17
CN31 CN20
43 CNVI_WGR_CLK_DN CNV_WR_CLKN GPP_F3
CP31
43 CNVI_WGR_CLK_DP CNV_WR_CLKP CSI2_FLASH_STROBE
CG25 1
+V3P3SX GPP_D4/IMGCLKOUT0/BK4/SBK4 TP661 20MIL
CP34 CH25
43 CNVI_WT_CLK_DN CNV_WT_CLKN GPP_H20/IMGCLKOUT1
43 CNVI_WT_CLK_DP CN34 3/18 Add TP661
CNV_WT_CLKP
CNV_WT_RCOMP CR20
CP32 GPP_F12/EMMC_DATA0
2

CNV_WT_RCOMP_1 CM20
R697 1 r0201 2 150.0_F CR32 GPP_F13/EMMC_DATA1
R673 CNV_WT_RCOMP_2 CN19
GPP_F14/EMMC_DATA2
10K_J CP20 CM19
43 WLAN_COEX3_WWAN CK19
GPP_F0/CNV_PA_BLANKING GPP_F15/EMMC_DATA3
CN18
R0201
GPP_F1 GPP_F16/EMMC_DATA4
CG17 CR18
GPP_F2 GPP_F17/EMMC_DATA5
20180430 CP18
GPP_F18/EMMC_DATA6
1

CR14 CM18
69,81 PX_EN GPP_C8/UART0_RXD GPP_F19/EMMC_DATA7
CP14
74 DGPU_HOLD_RST# GPP_C9/UART0_TXD
2

CN14 CM16
GPU_EVENT#_SOC GPP_C10/UART0_RTS# GPP_F20/EMMC_RCLK
A R672 CM14
GPP_C11/UART0_CTS# GPP_F21/EMMC_CLK
CP16
A
10K_J CR16
GPP_F11/EMMC_CMD
R0201 43 WLAN_COEX1_WWAN
CJ17
GPP_F8/CNV_MFUART2_RXD GPP_F22/EMMC_RESET#
CN16 Bitland Information Technology Co.,Ltd.
ns 43 WLAN_COEX2_WWAN
CH17
GPP_F9/CNV_MFUART2_TXD EMMC_RCOMP R6142
CK15 1 200_J R0201 Page Name
6
1

EMMC_RCOMP
CF17
GPP_F23/A4WP_PRESENT
Size Project Name Rev
D6812 Custom
LBAT54XV2T1G WHL_U_IP_CCG 9 of 20
Veneno 1.3
sod523

Vinafix.com
Date: Thursday, August 22, 2019 Sheet 6 of 87
1 2 GPU_EVENT#_SOC
76 GPU_EVENT# PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
ns documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

XTAL_24M_SOC_OUT R0201 XTAL_24M_SOC_OUT_R

R11586 2 1 0_J

XTAL_24M_SOC_IN R0201 XTAL_24M_SOC_IN_R

R11587 2 1 0_J 1 2
R757 1M_J R0201
FOLLOW 720
Y701
2018-0930
24MHZ_10PPM
Y_4P_SMD3225
1 3
4 2
+3V_PRIM UC1J
PCIE_REFCLK_SSD_DN_R

1
AW2 AU1 C749 C750
26 PCIE_REFCLK_SSD_DN PCIE_REFCLK_SSD_DP_R CLKOUT_PCIE_N0 CLKOUT_ITPXDP
AY3 AU2 22PF/50V,NPO 22PF/50V,NPO
26 PCIE_REFCLK_SSD_DP CLKOUT_PCIE_P0 CLKOUT_ITPXDP_P C0402 C0402
CF32
26 SSD_CLK_REQ_N GPP_B5/SRCCLKREQ0#

2
1

BT32
D GPD8/SUSCLK SUS_CLK 43 D
R765 R766 SSD Close to SOC BC1
CLKOUT_PCIE_N1 XTAL_24M_SOC_IN
10K_J
R0201
10K_J
R0201
20180705 HW_ID0 HW_ID0
BC2
CE32
CLKOUT_PCIE_P1 XTAL_IN
CK3
CK2
XTAL_24M_SOC_OUT 3/10 Change C1249,C1250 from 22pF to 8.2pF
TPM_ID SIZE_ID R765 I, R721 NI, HW TPM GPP_B6/SRCCLKREQ1# XTAL_OUT
XCLK_BIASREF
HW_ID0 R765NI, R721 I, FW TPM BD3
CLKOUT_PCIE_N2 XCLK_BIASREF
CJ1 R795 2 1 60.4_F R0201
2

BC3 CM3
13OR14_ID 13OR14_ID CF30
CLKOUT_PCIE_P2 CLKIN_XTAL
36 13OR14_ID GPP_B7/SRCCLKREQ2# RTC_X1
BN31
20181219 13OR14_ID 74 CLK_PCIE_GPU#
BH3
CLKOUT_PCIE_N3
RTCX1
RTCX2
BN32
RTC_X2
CLKIN_XTAL_LCP
0, 13''
1

BH4 2 R11298 1 SHORT_0201

74 CLK_PCIE_GPU GPU_CLKREQ# CLKOUT_PCIE_P3 SRTC_RST_N CLKIN_XTAL_LCP 43
R721 R789 CE31 BR37
10K_J 10K_J 1, 14'' 76 GPU_CLKREQ# GPP_B8/SRCCLKREQ3# SRTCRST#
BR34
RTC_RST_N
RTCRST#

1
R0201 R0201 BA1
TPM_ID SIZE_ID SD BA2
CLKOUT_PCIE_N4
R11297
CLKOUT_PCIE_P_4

2
SRCCLKREQ4# CE30 10K_J C10971
GPP_B9/SRCCLKREQ4#
2

PCIE_REFCLK_WLAN_DN_R BE1
ns 8.2pF/50V,NPO
R0201 c0402
43 PCIE_REFCLK_WLAN_DN_R PCIE_REFCLK_WLAN_DP_R BE2 CLKOUT_PCIE_N5

1
WLAN 43 PCIE_REFCLK_WLAN_DP_R CLKOUT_PCIE_P5

2
CF31
43 WLAN_CLK_REQ_N GPP_B10/SRCCLKREQ5# RTC_X1

WHL_U_IP_CCG 10 of 20
RTC_X2 R756
+3V_PRIM R0201 ns r0201
R785 2 1 0_J SRTC_RST_N 2 10M_J 1
RTC_RST_N
1

1/13 Add RTC reset circuit. Y700

3
R739
D 2 1
10K_J Q709
R0201 L2N7002LT1G
50 SRTCRST_EC 1 SOT23-3
G 32.768KHZ
S

2
C751 Y_2P_SMD3215 C752
2

2
SRCCLKREQ4# R783 15pF/50V,NPO 15pF/50V,NPO
C c0402 c0402 C
10K_J

1
R0201 GND
GND GND

2
+V1P0A_VCCPRIM +V1P0A_VCCPRIM 14
+V3P3A +V3P3A 3,4,5,9,11,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81 +RTCVCC
+V3P3SX +V3P3SX 4,5,6,17,19,26,30,32,36,43,46,50,64,81
+V3P3A

+RTCVCC +RTCVCC 11
+3V_PRIM

1
+3V_PRIM 8,64
+1.0V_VCCST

2
+1.0V_VCCST 3,10,12,17,64,66 R772
10K_J R758 R760 R762
20K_F 20K_F 1M_J
R0201 R0201
R0201 R0201
PM_BATLOW_N

2
RTC_RST_N SRTC_RST_N SM_INTRUDER_N

1
C754 C753

2
1UF/6.3V,X5R 1UF/6.3V,X5R
C0201 C0201

1
Rev_0.53
+V3P3A +V3P3SX
UC1K
2

BJ35 BJ37
26,35,43,50,74 PLT_RST_N PM_SYSRST_N GPP_B13/PLTRST# GPP_B12/SLP_S0# SLP_S0_SOC 30,50,63,64
R793 R771 CN10 BU36
+V3P3SX SYS_RESET# GPD4/SLP_S3# SLP_S3_SOC 50,63
2.2k_J 2.2k_J BR36 BU27
50 RSMRST_N RSMRST# GPD5/SLP_S4# SLP_S4_SOC 50
BT29
R0201 R0201 TP_CPUPWRGD GPD10/SLP_S5# SLP_S5_SOC 50
20MIL TP721 1 AR2
H_VCCST_PWRGD BJ2 PROCPWRGD SLP_SUS_N
1

B ns VCCST_PWRGOOD SLP_SUS#
BU29
SLP_SUS_N 64
B
1

R750 BT31
PM_SYSRST_N CR10
SLP_LAN#
BT30
SLP_WLAN_N 1 TP730 20MIL
10K_J 50 SYS_PWROK SYS_PWROK GPD9/SPL_WLAN# SLP_A_N
50 IMVP_PCH_PWRGD
BP31 BU37 1 TP797 20MIL
RSMRST_N R0201 RSMRST_N BP30
PCH_PWROK GPD6/SLP_A#
DSW_PWROK
2

BU28
GPU_CLKREQ# TP_SUS_PWR_DN_ACKBV34 GPD3/PWRBTN# AC_PRESENT PM_PWRBTN_R_N 50
2

R779 20MIL TP781 1 BU35 +1.0V_VCCST

TP_SUSACK_N GPP_A13/SUSWARN#/SUSPWRDACK GPD1/ACPRESENT
1

100K_F 20MIL TP748 1 BY32 BV36

R0201 GPP_A15/SUSACK# GPD0/BATLOW# PM_BATLOW_N 50
C766

2
0.1UF/10V,X5R 26,43 PCIE_WAKE_PCH_N BU30
WAKE# SM_INTRUDER_N
2

C0201 +V3P3SX BU32 BR35

GPD2/LAN_WAKE# INTRUDER# +V3P3A
1

BU34 R744
+V3P3A GPD11/LANPHYPC
CC37
EXT_PWR_GATEB 1 TP725 20MIL
GPP_B11/EXT_PWR_GATE# R200_PWR_EN 1K_J
1

CC36 1 TP722 20MIL

2
GPP_B2/VRALERT# R0201
R11483 R741 1 210K_J R0201 H_VCCST_PWRGD

1
10K_J BT27 INPUT3VSEL
INPUT3VSEL INPUT3VSEL 17 R11560
3V SELECT STRAP

3
R0201 LOW-> 3.3V +/-5% 10K_J
D
HIGH->3.0V +/-5% 2018/03/27 r0201
SYS_PWROK WHL_U_IP_CCG
2

11 of 20

1
5 G
S Q703A
L2N7002DW1T1G

4
D SOT363

IMVP_PCH_PWRGD 2 G Q703B
+V3P3A S L2N7002DW1T1G
SOT363

1
2
SHORT_0201 2 R742 1
IMVP_PCH_PWRGD R786
66 VR_PWRGD

2
100K_F
R748 R0201
100K_F ns
2/24 Add R1042,VR_PWRGD connect to SOC and EC R0201

1
1
A A
AC_PRESENT
50 AC_PRESENT

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Custom
Veneno 1.3
Date: Thursday, August 22, 2019 Sheet 7 of 87

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PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

1
FP_SPI_CS0_N
+3V_PRIM 20MIL TP804 FP_SPI_CLK
1
+1.8V_PRIM +1.8V_PRIM 20MIL TP803 FP_SPI_MISO
1
20MIL TP802 1
FP_SPI_MOSI
20MIL TP805

1
1

1
R820
R870 R871 10K_J UC1F
20K_F 20K_F 20MIL TP10116 1 CC27
R0201 GPP_B15/GSPI0_CS0#
R0201 R0201 20MIL TP10110 1 CC32
Rev_0.53 +3V_PRIM
GPP_A7/PIRQA#/GSPI0_CS1#
20MIL TP10117 1 CE28 CN22 1 TP895 20MIL

2
ns ns 20MIL TP10142 1
GC6_FB_EN CE27
GPP_B16/GSPI0_CLK GPP_D9/ISH_SPI_CS#/GSPI2_CS0#
CR22 1 TP10111 20MIL

2
GPP_B17/GSPI0_MISO GPP_D10/ISH_SPI_CLK/GSPI2_CLK
CE29 CM22 1 TP10115 20MIL
17 TP_STRAP_GPP_B18 GPP_B18/GSPI0_MOSI GPP_D11/ISH_SPI_MISO/GSPI2_MISO
CP22 1
GPP_D12/ISH_SPI_MOSI/GSPI2_MOSI TP10114 20MIL
CA31 GPP_D12 17
PME_N FP_SPI_CS0_N GPP_B19/GSPI1_CS0#

1
D CA32 CK22 1 D
GPP_A11/PME#/GSPI1_CS1#/SD_VDD2_PWR_EN# GPP_D5/ISH_I2C0_SDA TP10112 20MIL
CC29 CH20 1
FP_SPI_CLK GPP_B20/GSPI1_CLK GPP_D6/ISH_I2C0_SCL TP10113 20MIL
FP_SPI_MISO
CC30 R11576 R11564
GPP_B21/GSPI1_MISO
CA30 CH22 1 TP10122 20MIL 10K_J 10K_J
FP_SPI_MOSI GPP_B22/GSPI1_MOSI GPP_D7/ISH_I2C1_SDA
CJ22 1 TP10118 20MIL R0201 R0201
GPP_D8/ISH_I2C1_SCL
43 CNVI_BRI_RSP CNVI_RGI_DT_R
CK20
GPP_F5/CNV_BRI_RSP
ns BOOK_ID

2
R0402 22.0_F 2 1R8C91 CG19 CJ27 1 TP10120 20MIL BOOK_ID0
17,43 CNVI_RGI_DT R0402 CNVI_BRI_DT_R GPP_F6/CNV_RGI_DT GPP_H10/I2C5_SDA/ISH_I2C2_SDA
17,43 CNVI_BRI_DT 22.0_F 2 1R8C92 CJ20 CJ29 1 TP10121 20MIL
CH19
GPP_F4/CNV_BRI_DT GPP_H11/I2C5_SCL/ISH_I2C2_SCL BOOK_ID1
43 CNVI_RGI_RSP GPP_F7/CNV_RGI_RSP MEM_DEC0
CM24
GPP_D13/ISH_UART0_RXD
CN23
MEM_DEC1 2019022:
UART for debug CR12
GPP_D14/ISH_UART0_TXD
CM23
MEM_DEC2 add book ID

1
UART for debug 57 UART2_RXD GPP_C20/UART2_RXD GPP_D15/ISH_UART0_RTS#/GSPI2_CS1# MEM_DEC3
CP12 CR24
57 UART2_TXD GPP_C21/UART2_TXD GPP_D16/ISH_UART0_CTS#/SML0BALERT# R11575 R11563
CN12
CM12
GPP_C22/UART2_RTS#
CG12
BOOK_ID0 10K_J 10K_J
GPP_C23/UART2_CTS# GPP_C12/UART1_RXD/ISH_UART1_RXD
CH12
BOOK_ID1 R0201 R0201
CM11
GPP_C13/UART1_TXD/ISH_UART1_TXD
CF12 ns BOOK_ID
50 TOUCH_PAD_DAT0 GPP_C16/I2C0_SDA GPP_C14/UART1_RTS#/ISH_UART1_RTS# ALS_INT_N
CN11 CG14 1 TP894 20MIL

2
50 TOUCH_PAD_CLK0 GPP_C17/I2C0_SCL GPP_C15/UART1_CTS#/ISH_UART1_CTS#

CK12 BW35
GYROSCOPE_INT 1 TP810 20MIL
GPP_C18/I2C1_SDA GPP_A18/ISH_GP0
CJ12 BW34 1 TP811 20MIL
GPP_C19/I2C1_SCL GPP_A19/ISH_GP1
CA37
GPP_A20/ISH_GP2 FP_SLEEP_N 1 TOUCH_PAD_INT 50
CF27 CA36 TP10130 20MIL
CF29
GPP_H4/I2C2_SDA GPP_A21/ISH_GP3
CA35
FP_DRDY 1 TP10131 20MIL
GPP_H5/I2C2_SCL GPP_A22/ISH_GP4
CA34
GPP_A23/ISH_GP5
CH27 BW37
GPP_H6/I2C3_SDA GPP_A12/ISH_GP6/BM_BUSY#/SX_EXIT_HOLDOFF#
CH28
GPP_H7/I2C3_SCL
CJ30
GPP_H8/I2C4_SDA
CJ31
GPP_H9/I2C4_SCL

WHL_U_IP_CCG 6 of 20

+3V_PRIM +3V_PRIM +3V_PRIM +3V_PRIM

C C
Memory Dectection

1
1

1
R803 R801 R806 R824
+3V_PRIM +3V_PRIM 7,64 10K_J 10K_J 10K_J 10K_J
+V3P3SX R0201 R0201 R0201 R0201
+V3P3SX 4,5,6,7,17,19,26,30,32,36,43,46,50,64,81
ns ns ns ns

2
+V3P3A +V3P3A 3,4,5,7,9,11,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81 MEM_DEC0 MEM_DEC1 MEM_DEC2 MEM_DEC3

2
1

1
R804 R802
R807 R825
10K_J 10K_J 10K_J 10K_J
R0201 R0201 R0201 R0201
ns ns ns ns

2
SIZE
2GB 4GB 8GB 16GB

MEM_DEC0 0 1 0 1

MEM_DEC1 0 0 1 1

Vender Samsung Hynix Micron

MEM_DEC2
0 1 0

MEM_DEC3 0 0 1
B B

A A

Bitland Information Technology Co.,Ltd.

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8
Size
Project Name Re v
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 8 of 87

Vinafix.com
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

Rev_0.53
UC1H
BW9 CB5
74 PCIE_CRX_GTX_N0 BW8
PCIE5_RXN/USB31_5_RXN PCIE1_RXN/USB31_1_RXN
CB6
USB3_P1_RX_DN 49
74 PCIE_CRX_GTX_P0
C978 2 1 0.22uF/6.3V,X5R C0201 PCIE_CTX_GRX_N0_C BW4 PCIE5_RXP/USB31_5_RXP PCIE1_RXP/USB31_1_RXP
CA4
USB3_P1_RX_DP 49
USB3_P1_TX_DN 49
USB3.0 CONN1 with AOU
74 PCIE_CTX_GRX_N0 PCIE_CTX_GRX_P0_C BW3 PCIE5_TXN/USB31_5_TXN PCIE1_TXN/USB31_1_TXN
C979 2 1 0.22uF/6.3V,X5R C0201 CA3
USB3_P1_TX_DP 49
74 PCIE_CTX_GRX_P0 PCIE5_TXP/USB31_5_TXP PCIE1_TXP/USB31_1_TXP

BU6 BY8
74 PCIE_CRX_GTX_N1 PCIE6_RXN/USB31_6_RXN PCIE2_RXN/USB31_2_RXN/SSIC_1_RXN USB3_P2_RX_DN 49 USB3.0 CONN2
BU5 BY9
74 PCIE_CRX_GTX_P1 PCIE_CTX_GRX_N1_C PCIE6_RXP/USB31_6_RXP PCIE2_RXP/USB31_2_RXP/SSIC_1_RXP USB3_P2_RX_DP 49
C988 2 1 0.22uF/6.3V,X5R C0201 BU4 CA2
74 PCIE_CTX_GRX_N1 PCIE_CTX_GRX_P1_C PCIE6_TXN/USB31_6_TXN PCIE2_TXN/USB31_2_TXN/SSIC_1_TXN USB3_P2_TX_DN 49
C989 2 1 0.22uF/6.3V,X5R C0201 BU3 CA1
D 74 PCIE_CTX_GRX_P1 PCIE6_TXP/USB31_6_TXP PCIE2_TXP/USB31_2_TXP/SSIC_1_TXP USB3_P2_TX_DP 49 D
GPU x4 BT7 BY7
USB3_P3_RX_DN 51
74 PCIE_CRX_GTX_N2 PCIE7_RXN PCIE3_RXN/USB31_3_RXN
74 PCIE_CRX_GTX_P2 PCIE_CTX_GRX_N2_C
BT6
PCIE7_RXP PCIE3_RXP/USB31_3_RXP
BY6
USB3_P3_RX_DP 51 Type-c
C990 2 1 0.22uF/6.3V,X5R C0201 BU2 BY4
USB3_P3_TX_DN 51
74 PCIE_CTX_GRX_N2 C991 2 1 0.22uF/6.3V,X5R C0201 PCIE_CTX_GRX_P2_C BU1
PCIE7_TXN PCIE3_TXN/USB31_3_TXN
BY3
74 PCIE_CTX_GRX_P2 PCIE7_TXP PCIE3_TXP/USB31_3_TXP USB3_P3_TX_DP 51
BU9 BW6
74 PCIE_CRX_GTX_N3 BU8
PCIE8_RXN PCIE4_RXN/USB31_4_RXN
BW5
74 PCIE_CRX_GTX_P3 PCIE_CTX_GRX_N3_C PCIE8_RXP PCIE4_RXP/USB31_4_RXP
C992 2 1 0.22uF/6.3V,X5R C0201 BT4 BW2
74 PCIE_CTX_GRX_N3 PCIE_CTX_GRX_P3_C PCIE8_TXN PCIE4_TXN/USB31_4_TXN
C980 2 1 0.22uF/6.3V,X5R C0201 BT3 BW1
74 PCIE_CTX_GRX_P3 PCIE8_TXP PCIE4_TXP/USB31_4_TXP

BP5 CE3
PCIE9_RXN USB2N_1 USB2_P1_DN 49
BP6
BR2
PCIE9_RXP USB2P_1
CE4
USB2_P1_DP 49 USB3.0 CONN1
PCIE9_TXN
BR1 CE1
PCIE9_TXP USB2N_2 USB2_P2_DN 49
BN6
USB2P_2
CE2
USB2_P2_DP 49 USB3.0 CONN2
43 PCIE_WLAN_LN0_RX_SOC_DN BN5
PCIE10_RXN
CG3
43 PCIE_WLAN_LN0_RX_SOC_DP PCIE10_RXP USB2N_3 USB2_P3_DN 53
NGFF WIFI Module 43 PCIE_WLAN_LN0_TX_SOC_DN
BR4
BR3
PCIE10_TXN USB2P_3
CG4
USB2_P3_DP 53 Type-C
43 PCIE_WLAN_LN0_TX_SOC_DP PCIE10_TXP
CD3
USB2N_4
BN10 CD4
PCIE11_RXN/SATA0_RXN USB2P_4
BN8
PCIE11_RXP/SATA0_RXP
BN4 CG5
PCIE11_TXN/SATA0_TXN USB2N_5 USB2_P5_BT_DN 43
BN3
PCIE11_TXP/SATA0_TXP USB2P_5
CG6
USB2_P5_BT_DP 43 BT
BL6 CC1
PCIE12_RXN/SATA1A_RXN USB2N_6
BL5 CC2
PCIE12_RXP/SATA1A_RXP USB2P_6
BN2
C PCIE12_TXN/SATA1A_TXN C
BN1 CG8
PCIE12_TXP/SATA1A_TXP USB2N_7 USB2_P7_CAM_DN 36
USB2P_7
CG9
USB2_P7_CAM_DP 36 Camera
BK6
26 PCIE9_SSD_RX_DN BK5
PCIE13_RXN
CB8
26 PCIE9_SSD_RX_DP PCIE9_SSD_TX_DN PCIE13_RXP USB2N_8 USB2_P8_FPR_DN 28
26 PCIE9_SSD_TX_DN_C C900 2 1 0.22uF/6.3V,X5R C0201 BM4 CB9
FPR
PCIE9_SSD_TX_DP PCIE13_TXN USB2P_8 USB2_P8_FPR_DP 28
26 PCIE9_SSD_TX_DP_C C901 2 1 0.22uF/6.3V,X5R C0201 BM3
PCIE13_TXP
CH5
USB2N_9
BJ6 CH6
26 PCIE10_SSD_RX_DN BJ5
PCIE14_RXN USB2P_9
26 PCIE10_SSD_RX_DP PCIE10_SSD_TX_DN BL2 PCIE14_RXP
26 PCIE10_SSD_TX_DN_C C902 2 1 0.22uF/6.3V,X5R C0201 CC3
C903 2 1 0.22uF/6.3V,X5R C0201 PCIE10_SSD_TX_DP BL1 PCIE14_TXN USB2N_10
CC4
NGFF SSD 26 PCIE10_SSD_TX_DP_C PCIE14_TXP USB2P_10

BG5 CC5 USB2_COMP R912 1 2 113.0_F R0201

26 PCIE11_SSD_RX_DN PCIE15_RXN/SATA1B_RXN USB2_COMP USB2_P1_WP1_OTG_ID R0201
BG6 CE8 R984 1 2 1K_J
26 PCIE11_SSD_RX_DP PCIE11_SSD_TX_DN BL4 PCIE15_RXP/SATA1B_RXP USB_ID USB2_VBUSSENSE
26 PCIE11_SSD_TX_DN_C C904 2 1 0.22uF/6.3V,X5R C0201 CC6 R985 1 2 1K_J R0201
C905 2 1 0.22uF/6.3V,X5R C0201 PCIE11_SSD_TX_DP BL3 PCIE15_TXN/SATA1B_TXN USB_VBUSSENSE
26 PCIE11_SSD_TX_DP_C PCIE15_TXP/SATA1B_TXP
CK6
BE5
GPP_E9/USB2_OC0#/GP_BSSB_CLK
CK5
USB_P1_WP_OC_N 49
26 PCIE12_SSD_RX_DN BE6
PCIE16_RXN/SATA2_RXN GPP_E10/USB2_OC1#/GP_BSSB_DI
CK8
USB_P2_WP_OC_N 49
26 PCIE12_SSD_RX_DP PCIE12_SSD_TX_DN BJ4 PCIE16_RXP/SATA2_RXP GPP_E11/USB2_OC2# USB2_TYPC_OC_N 52,53
26 PCIE12_SSD_TX_DN_C C906 2 1 0.22uF/6.3V,X5R C0201 CK9
+V3P3A +V3P3A
PCIE12_SSD_TX_DP BJ3 PCIE16_TXN/SATA2_TXN GPP_E12/USB2_OC3# USB2_P3_WP2_OC_N
26 PCIE12_SSD_TX_DP_C C907 2 1 0.22uF/6.3V,X5R C0201
PCIE16_TXP/SATA2_TXP
CP8 TP_SATA0_DEVSLP 1 20MIL
TP979
GPP_E4/DEVSLP0
CR8 SATA1_DEVSLP 1 TP901 20MIL
R963 100.0_F R0201
PCIE_RCOMP_N GPP_E5/DEVSLP1

2
1 2 CE6 CM8

2
PCIE_RCOMP_P PCIE_RCOMP GPP_E6/DEVSLP2 SATA2_DEVSLP 26
CE5 R982
PCIE_RCOMP_P TP_SSD_SATA0_PCIE_DET_N R901
CN8 1 TP980 20MIL 10K_J
GPP_E0/SATAXPCIE0/SATAGP0 10K_J
CR28 CM10 1 TP982 20MIL
CP28
GPP_H12/M2_SKT2_CFG0 GPP_E1/SATAXPCIE1/SATAGP1
CP10 SSD_SATA_PCIE_DET_N R0201
GPP_H13/M2_SKT2_CFG1 GPP_E2/SATAXPCIE2/SATAGP2 SSD_SATA_PCIE_DET_N 26 R0201
B CN28 B
TP_EDP2DSI_CORE_PWR_EN

1
GPP_H14/M2_SKT2_CFG2 TP913
CM28 CN7 1 20MIL USB2_P3_WP2_OC_N

1
GPP_H15/M2_SKT2_CFG3 GPP_E8/SATALED#/SPI1_CS1#

AR3
RSVD_1/FS_RESET#/RSVD_1 USB2_TYPC_OC_N
WHL_U_IP_CCG 8 of 20
1/7 Add PU +V3P3A for TYPE-C

GPIO DEVICE CONTROL

USB_OC0# Type C

USB_OC1# USB2 Port 2

USB_OC2# NA

USB_OC3# WWAN_PWR_ON
DEVSLP0 NA

DEVSLP1 NA

DEVSLP2 NGFF SSD KEY M

A SATA_GP0 NA A

Bitland Information Technology Co.,Ltd.

SATA_GP1 NA
Page Name
SATA_GP2 SSD_SATA_PCIE_DET_N 9
Size Project Name Rev
Custom
Veneno 1.3

Vinafix.com
Date: Wednesday, August 21, 2019 Sheet 9 of 87
PROPERTY NOTE: this document contains information confidential and property to
+V3P3A Bitland
+V3P3A 3,4,5,7,11,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81 Technology Co.,Ltd. and shall not be reproduced or transferred to other
+V3P3SX documents or disclosed to others or used for any purpose other than that for which it
+V3P3SX 4,5,6,7,17,19,26,30,32,36,43,46,50,64,81 was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

+1.0VS_VCCSTG +V1P2U_VDDQ
+1.0V_VCCST +1.0VS_VCCIO

+V1P2U_VDDQ +1.2V_VCCPLL_OC PSC Side UC1N

R1015
2 ns 1
0_J
AK24
0_J ns BSC Side R0402
AD36
VDDQ_1
VCCIO_OUT_1
AK26
R10032 1 AH32 VCCIO_OUT_2
VDDQ_2 AL24
AH36 VCCIO_OUT_3
VDDQ_3 AL25
R0402 AM36 VCCIO_OUT_4
D VDDQ_4 AL26 D

1
C1018 C1020 C1099 C10990 C10989 AN32 VCCIO_OUT_5
VDDQ_5 AL27

2
C1019 1UF/6.3V,X5R 1UF/6.3V,X5R 10uF/6.3V,X5R 22uF/6.3V,X5R 10uF/6.3V,X5R AW32 VCCIO_OUT_6
VDDQ_6 AM25
1UF/6.3V,X5R C0201 C0201 C0402 C0603 C0402 AY36 VCCIO_OUT_7
AM27

2
VDDQ_7
C0201 BE32 VCCIO_OUT_8
VDDQ_8 BH24

1
BH36 VCCIO_OUT_9
VDDQ_9 BH25
R32 VCCIO_OUT_10
VDDQ_10 BH26
Y36 VCCIO_OUT_11
VDDQ_11 BH27
20190621:Intel PDG requirement,Add C10990 and C10989 VCCIO_OUT_12
BJ24
VCCIO_OUT_13
BJ26
VCCIO_OUT_14
BP16
20MIL TP1026 1 BC28 VCCIO_OUT_15
RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev1.0 RSVD_60
VCCIO_OUT_16
BP18

BP11
+1.0V_VCCST VCCST_2 BG8
+1.0VS_VCCSTG BP2 VCCSA_1 +VCC_SA
VCCST_1 BG10
VCCSA_2
BH9
VCCSA_3
BSC Side BG1 VCCSA_4
BJ8
+1.0VS_VCCSTG +1.0V_VCCSFR VCCSTG_1 BJ9
+1.0V_VCCSFR +1.0VS_VCCSTG BG2 VCCSA_5
VCCSTG_2 BJ10
VCCSA_6
BK8
BL27 VCCSA_7
+1.2V_VCCPLL_OC VCCPLL_OC_1 BK25
2

C1030 BM26 VCCSA_8

VCCPLL_OC_2 BK27
1UF/6.3V,X5R VCCSA_9
BL8
C0201 2 R1016 1 ns
+1.0V_VCCST BR11 VCCSA_10
BL9
1

VCCPLL_1
BT11 VCCSA_11
SHORT_0402 C10972 VCCPLL_2 BL10

1
VCCSA_12
22uF/6.3V,X5R BL24

2
C1049 C0603 VCCSA_13
BL26
C 0.1UF/10V,X5R VCCSA_14 C
BM24

2
C0201 VCCSA_15
BN25

1
VCCSA_16
BP28 VCCIO_SENSE 1 TP1024 20MIL
VCCIO_SENSE
BP29 VSSIO_SENSE 1 TP1025 20MIL
VSSIO_SENSE
BE7 VSSSA_SENSE
VSSSA_SENSE VCCSA_SENSE VSSSA_SENSE 66
BG7
VCCSA_SENSE VCCSA_SENSE 66
RC208 Follow 544669_SKL_U__DDR3L_RVP7_Schematic_Rev0_53
14 of 20 WHL_U_IP_CCG

+1.0VS_VCCIO
BSC Side PSC Side

+1.0VS_VCCIO +1.0VS_VCCSTG
+VCC_SA
10uF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R
1

2
C1001 C1002 C1003 C1004 C1005 C1006 C1007 C1008 C1009

1
C0402 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
2

ns R1080 2
0_J
1 R0402
R1010
ns ns ns 100_F

1UF/6.3V,X5R
R0201

2
C1080
VCCSA_SENSE
C0201 VSSSA_SENSE

2
5/31 uninstall CAPs

1
B B
R1011
20180704
ADD R1080 AND C1080 100_F
+V1P2U_VDDQ R0201

2
12/2 Close to CPU
10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R

10uF/6.3V,X5R
1

C1010 C1011 C1012 C1013 C1014 C1015

1

C1016 C1017 C1038 C1039

22uF/6.3V,X5R ns ns ns ns
C0402 C0402 C0402 C0402 C0402 C0603
C0402 C0402 C0402 C0402
2

20180712 20180712
EE NOISE EE NOISE 20180712
EE NOISE

+V1P2U_VDDQ: 10UF/6.3V/0603 *4
22UF/6.3V/0402 *3

+VCC_SA +VCC_SA 16,66,67

A A
+V5CP +V5CP 49,53,60,64,65 Bitland Information Technology Co.,Ltd.
+1.8V_PRIM +1.8V_PRIM 8,11,17,46,50,57,65,68
Page Name
+V3P3A +V3P3A 3,4,5,7,9,11,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81 10
+V5P0S +V5P0S 30,32,46,64 Size
Project Name Rev
+V5P0A +V5P0A 43,46,61,63,64,66,67,68,69,70 Custom
+1.0V_PRIM +1.0V_PRIM 11,14,63,64 Veneno 1.3
+V3P3SX +V3P3SX 4,5,6,7,17,19,26,30,32,36,43,46,50,64,81 Date: Wednesday, August 21, 2019 Sheet 10 of 87
+V1P2U_VDDQ +V1P2U_VDDQ 4,19,51,61,64 PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
+1.0VS_VCCSTG +1.0VS_VCCSTG 3,12,64 documents or disclosed to others or used for any purpose other than that for which it
+1.0VS_VCCIO +1.0VS_VCCIO 3,17,64 was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com

Vinafix.com
 5 4 3 2 1

UC1P
+1.0V_PRIM BP20
+1.0V_PRIM +VCCA_XTAL_1P05_L +1.0V_PRIM +1.0V_PRIM +1.0V_PRIM VCCPRIM_1P05_5
BW16 CB16
+1.0V_PRIM +VCCAMPHYPLL_1P05_L VCCPRIM_1P05_6 VCCPRIM_3P3_3 +VCCPRIM_3P3
BW18
VCCPRIM_1P05_7
BW19
VCCPRIM_1P05_8
BY16
1 R1104 2 1 R1179 2 VCCPRIM_1P05_9
CA14 BR23
SHORT_0603 EMPTY SHORT_0603 EMPTY VCCPRIM_1P05_10 VCCRTC +RTCVCC
BY20
CC15 VCCPRIM_1P05_3 +1.0V_PRIM

2
C1197 C1196 C1195 +VCCPRIM_1P8 VCCPRIM_1P8_6

1
C1199 C1198 CD15 BP24

2
C1130 C1132 22uF/6.3V,X5R 22uF/6.3V,X5R 1UF/6.3V,X5R VCCPRIM_1P8_7 DCPRTC +VCCRTCEXT
1UF/6.3V,X5R 1UF/6.3V,X5R C0603 C0603
CD16
22uF/6.3V,X5R 1UF/6.3V,X5R C0201 VCCPRIM_1P8_8
C0201 C0201 ns CP17

1
C0603 C0201 VCCPRIM_1P8_9

2
D ns ns BR20 D

1
VCCPRIM_1P05_4 +1.0V_PRIM
CB22
+VCCPRIM_3P3 VCCPRIM_3P3_4
CB23 BT12
VCCPRIM_3P3_5 VCCAPLL_1P05_1 +1.0V_PRIM
CC22
VCCPRIM_3P3_6
CC23 BP14
VCCPRIM_3P3_7 VCCA_BCLK_1P05 +1.0V_PRIM
CD22
VCCPRIM_3P3_8
CD23 BR14
VCCPRIM_3P3_9 VCCAPLL_1P05_2 +1.0V_PRIM
CP29
VCCPRIM_3P3_10
BU12
+VCCPDSW_1P05 +VCCPRIM_1P8 +VCCPRIM_3P3 +VCCPDSW_3P3 BU15 VCCA_SRC_1P05 +1.0V_PRIM
+VCCPRIM_CORE BU22
VCCPRIM_CORE_1
VCCPRIM_CORE_2 CP5
BV15 VCCA_XTAL_1P05 +VCCA_XTAL_1P05_L
VCCPRIM_CORE_3
BV16
VCCPRIM_CORE_4 BY24
BV18 VCCDPHY_1P24_4 +VCCLDOSRAM_1P24
VCCPRIM_CORE_5 CA24
BV19 VCCDPHY_1P24_5
VCCPRIM_CORE_6
BV20
VCCPRIM_CORE_7 BY23
BV22 VCCDPHY_1P24_1

2
C1194 C1193 C1192 C1191 C1190 C1189 VCCPRIM_CORE_8 CA23
BW20 VCCDPHY_1P24_2
1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 0.1UF/10V,X5R 1UF/6.3V,X5R VCCPRIM_CORE_9 CP25
+VCCDPHY_1P24
C0201 BW22 VCCDPHY_1P24_3
C0201 C0201 C0201 C0201 C0201 VCCPRIM_CORE_10
ns ns ns ns CA12

1
VCCPRIM_CORE_11 BT23
CA16 VCCDSW_3P3_2 +VCCPDSW_3P3
VCCPRIM_CORE_12
CA18
VCCPRIM_CORE_13 BR12
CA19 VCCA_19P2_1P05 +1.0V_PRIM
VCCPRIM_CORE_14
CA20
VCCPRIM_CORE_15
CB12
VCCPRIM_CORE_16
+VCCPRIM_CORE CB14
VCCPRIM_CORE_17
CB15
VCCPRIM_CORE_18 CC18
VCCPRIM_1P8_1 +VCCPRIM_1P8
BT24 CC19
+VCCPDSW_1P05 VCCDSW_1P05 VCCPRIM_1P8_2
CD18
VCCPRIM_1P8_3
+RTCVCC +VCCRTCEXT +VCCDPHY_1P24 BU14 CD19
+1.0V_PRIM VCCAPLL_1P05_4 VCCPRIM_1P8_4
CP23
VCCPRIM_1P8_5
BV12
+1.0V_PRIM VCCPRIM_MPHY_1P05_2
BW12 BW23
VCCPRIM_MPHY_1P05_3 VCCPRIM_3P3_2 +VCCPRIM_3P3
BW14
VCCPRIM_MPHY_1P05_4
BY12
VCCPRIM_MPHY_1P05_5
C BY14 C
VCCPRIM_MPHY_1P05_6
2

1
C1154 C1188 C1187 C1186 C1185
BV2 BP23
1UF/6.3V,X5R 1UF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 4.7UF/6.3V,X5R +VCCAMPHYPLL_1P05_L VCCAMPHYPLL_1P05 VCCPRIM_3P3_1 +VCCPRIM_3P3
C0201 C0201 C0201 C0201 C0402 PRIMCORE_VID0 1
BR15 CB36 TP1130 20MIL
1

2
ns +1.0V_PRIM VCCAPLL_1P05_3 GPP_B0/CORE_VID0 PRIMCORE_VID1 1
CB35 TP1131 20MIL
GPP_B1/CORE_VID1
CC12
+1.0V_PRIM VCCDUSB_1P05
BR24
+VCCPDSW_3P3 VCCDSW_3P3_1
BT20
+VCCPAZIO_3P3_1P8_1P5 VCCHDA
BV23
+VCCPRIM_3P3 VCCSPI

BT18
+1.0V_PRIM VCCPRIM_1P05_11
BT19
VCCPRIM_1P05_12
BU18
VCCPRIM_1P05_13
BU19
VCCPRIM_1P05_14
BT22
+1.0V_PRIM VCCPRIM_1P05_1
BP22
+1.8V_PRIM +VCCPRIM_1P8 VCCPRIM_1P05_2
BV14
+1.0V_PRIM VCCPRIM_MPHY_1P05_1
1 R1196 2
16 of 20
WHL_U_IP_CCG
SHORT_0603 EMPTY

B B

+RTCVCC +RTCBATT
+RTCBATT_R
D1101 15mils 15mils
2 R1103 1K_F R0402

15mils 3
R1152

2
C1101 1 2 1
+V3.3AL
ns 1UF/6.3V,X5R
C0201
0.35V_0.2A_LBAT54CLT1G 1.5k_F

1
sot23-3 R0402

2
R1151
+1.8V_PRIM 45.3K_F
+V3P3A +VCCPAZIO_3P3_1P8_1P5 R0402
+V3P3A +VCCPRIM_3P3

1
R1194 R1192 1 2 0_J R0402
ns
r0805_short

R11588 1 2 0_J R0402

A A
+V3P3A +VCCPDSW_3P3

1 R1193 2 +RTCVCC +RTCVCC 7

+1.0V_PRIM +1.0V_PRIM 14,63,64 Bitland Information Technology Co.,Ltd.
SHORT_0603 EMPTY
+3V_PRIM +3V_PRIM 7,8,64
Page Name
+1.8V_PRIM
+V3P3A
+1.8V_PRIM 8,17,46,50,57,65,68
+V3P3A 3,4,5,7,9,17,19,24,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81
11
Size
+V5P0A +V5P0A 43,46,61,63,64,66,67,68,69,70 Project Name Re v
Custom
Veneno 1.3
Date: Friday, August 23, 2019 Sheet 11 of 87

Vinafix.com
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

+VCC_CORE
+VCC_CORE
UC1L
AN9 AW24 +VCC_GT +VCC_GT
VCCCORE_28 VCCCORE_67
AN10 AW25
VCCCORE_29 VCCCORE_68
AN24 AW26 UC1M
VCCCORE_30 VCCCORE_69
AN26 AW27
VCCCORE_31 VCCCORE_70 WHL QS/CFL/WHL_ES1_CNL U
AN27 AY24 A5 H12
VCCCORE_32 VCCCORE_71 VCCGT_1 VCCGT_60
AP2 AY26 A6 H14
VCCCORE_33 VCCCORE_72 VCCGT_2 VCCGT_61
AP9 BA5 A8 H15
VCCCORE_34 VCCCORE_73 VCCGT_3 VCCGT_62
AP24 BA7 A11 H17
VCCCORE_35 VCCCORE_74 VCCGT_4 VCCGT_63
AP26 BA8 A12 H18
VCCCORE_36 VCCCORE_75 VCCGT_5 VCCGT_64
D AR5 BA25 A14 H20 D
VCCCORE_37 VCCCORE_76 VCCGT_6 VCCGT_65
AR6 BA27 A15 J7
VCCCORE_38 VCCCORE_77 VCCGT_7 VCCGT_66
AR7 BB2 A17 J8
VCCCORE_39 VCCCORE_78 VCCGT_8 VCCGT_67
AR8 BB26 A18 J11
VCCCORE_40 VCCCORE_79 VCCGT_9 VCCGT_68
AR10 BC5 A20 J14
VCCCORE_41 VCCCORE_80 VCCGT_10 VCCGT_69
AR25 BC6 B3 J17
VCCCORE_42 VCCCORE_81 VCCGT_11 VCCGT_70
AR27 BC7 B4 J20
VCCCORE_43 VCCCORE_82 VCCGT_12 VCCGT_71
AT9 BC9 B6 K2
VCCCORE_44 VCCCORE_83 VCCGT_13 VCCGT_72
AT24 BC10 B8 K11
VCCCORE_45 VCCCORE_84 VCCGT_14 VCCGT_73
AT26 BC26 B11 L7
VCCCORE_46 VCCCORE_85 VCCGT_15 VCCGT_74
AU5 BC27 B14 L8
VCCCORE_47 VCCCORE_86 VCCGT_16 VCCGT_75
AU6 BD5 B17 L10
VCCCORE_48 VCCCORE_87 VCCGT_17 VCCGT_76
AU7 BD8 B20 M9
VCCCORE_49 VCCCORE_88 VCCGT_18 VCCGT_77
AU8 BD10 C2 N7
VCCCORE_50 VCCCORE_89 VCCGT_19 VCCGT_78
AU9 BD25 C3 N8
VCCCORE_51 VCCCORE_90 VCCGT_20 VCCGT_79
AU24 BD27 C6 N9
VCCCORE_52 VCCCORE_91 VCCGT_21 VCCGT_80
AU25 BE9 C7 N10
VCCCORE_53 VCCCORE_92 VCCGT_22 VCCGT_81
AU26 BE24 C8 P2
VCCCORE_54 VCCCORE_93 VCCGT_23 VCCGT_82
AU27 BE25 C11 P8
VCCCORE_55 VCCCORE_94 VCCGT_24 VCCGT_83
AV2 BE26 C12 R9
VCCCORE_56 VCCCORE_95 VCCGT_25 VCCGT_84
AV5 BE27 C14 T8
VCCCORE_57 VCCCORE_96 VCCGT_26 VCCGT_85
AV7 BF2 C15 T9
VCCCORE_58 VCCCORE_97 VCCGT_27 VCCGT_86
AV10 BF9 C17 T10
VCCCORE_59 VCCCORE_98 VCCGT_28 VCCGT_87
AV27 BF24 C18 U8
VCCCORE_60 VCCCORE_99 VCCGT_29 VCCGT_88
AW5 BF26 C20 U10
AW6
VCCCORE_61 VCCCORE_100
BG27 D4
VCCGT_30 VCCGT_89
V9
+VCC_CORE
VCCCORE_62 VCCCORE_101 VCCGT_31 VCCGT_90
AW7
VCCCORE_63
Trace Length < 25 mils D7
VCCGT_32 VCCGT_91
W8
AW8 AN6 D11 W9
VCCCORE_64 VCC_SENSE VCCSENSE 66 VCCGT_33 VCCGT_92
AW9 AN5 D12 AA9
VCCCORE_65 VSS_SENSE VSSSENSE 66 VCCGT_34
VCCCORE_1/VCCGT_93/VCCGT_93
C AW10 D14 AB2 C
VCCCORE_66 SOC_SVID_ALERT# VCCGT_35
VCCCORE_2/VCCGT_94/VCCGT_94
AA3 D15 AB8
VIDALERT# VCCGT_36
VCCCORE_3/VCCGT_95/VCCGT_95
BB9 D17 AB9
BC24
RSVD_61
AA1 SOC_SVID_CLK D18
VCCGT_37
VCCCORE_4/VCCGT_96/VCCGT_96
AB10
AY9
RSVD_62 VIDSCK SOC_SVID_CLK 66 D20
VCCGT_38
VCCCORE_5/VCCGT_97/VCCGT_97
AC8
BB24
RSVD_63
AA2 SOC_SVID_DAT E4
VCCGT_39
VCCCORE_6/VCCGT_98/VCCGT_98
AD9
RSVD_64 VIDSOUT VCCGT_40
VCCCORE_7/VCCGT_99/VCCGT_99
F5 AE8
VCCGT_41
VCCCORE_8/VCCGT_100/VCCGT_100
Y3 F6 AE9
RSVD_65 VCCGT_42
VCCCORE_9/VCCGT_101/VCCGT_101
F7 AE10
VCCGT_43
VCCCORE_10/VCCGT_102/VCCGT_102
BG3 +1.0VS_VCCSTG F8 AF2
VCCSTG_3 VCCGT_44
VCCCORE_11/VCCGT_103/VCCGT_103
F11 AF8
VCCGT_45
VCCCORE_12/VCCGT_104/VCCGT_104
F14 AF10
12 of 20
WHL_U_IP_CCG F17
VCCGT_46
VCCCORE_13/VCCGT_105/VCCGT_105
AG8
VCCGT_47
VCCCORE_14/VCCGT_106/VCCGT_106
F20 AG9
VCCGT_48
VCCCORE_15/VCCGT_107/VCCGT_107
G11 AH9
VCCGT_49
VCCCORE_16/VCCGT_108/VCCGT_108
G12 AJ8
VCCGT_50
VCCCORE_17/VCCGT_109/VCCGT_109
G14 AJ10
VCCGT_51
VCCCORE_18/VCCGT_110/VCCGT_110
G15 AK2
VCCGT_52
VCCCORE_19/VCCGT_111/VCCGT_111
G17 AK9
+1.0V_VCCST VCCGT_53
VCCCORE_20/VCCGT_112/VCCGT_112
Place the PU G18
VCCGT_54
VCCCORE_21/VCCGT_113/VCCGT_113
AL8

SVID ALERT resistors close to CPU G20

H5
VCCGT_55
VCCCORE_22/VCCGT_114/VCCGT_114
VCCGT_56
VCCCORE_23/VCCGT_115/VCCGT_115
AL9
AL10
1

H6 AM8
VCCGT_57
VCCCORE_24/VCCGT_116/VCCGT_116
R1279 H7 V2
VCCGT_58
VCCCORE_25/VCCGT_117/VCCGT_117
56.0_J H8 Y8
VCCGT_59
VCCCORE_26/VCCGT_118/VCCGT_118
H11 Y10
R0402 VCCGT_0
VCCCORE_27/VCCGT_119/VCCGT_119
R1280 E3
VCCGT_SENSE 66
VCCGT_SENSE
SOC_SVID_ALERT# D2
2

2 1 Trace Length < 25 mils VSSGT_SENSE VSSGT_SENSE 66

B SOC_SVID_ALERT#_R 66 B

(To VR) 13 of 20 WHL_U_IP_CCG

220_F
R0201

+1.0V_VCCST
Place the PU
resistors close to CPU
1

SVID DATA R1281 +VCC_CORE +VCC_GT

100.0_F
R0201

1
SOC_SVID_DAT
2

R1223 R1225
SOC_SVID_DAT 66
100.0_F 100.0_F
(To VR) R0201 R0201

VCCGT_SENSE

2
VCCSENSE
VSSSENSE VSSGT_SENSE

1
+VCC_CORE +VCC_CORE 15,66,67
+1.0VS_VCCSTG R1224 R1226
+1.0VS_VCCSTG 3,10,64
+VCC_GT +VCC_GT 15,66,67 100.0_F 100.0_F
+1.0V_VCCST +1.0V_VCCST 3,7,10,17,64,66 R0201 R0201

A A

2
12/2 Close to CPU Bitland Information Technology Co.,Ltd.

Page Name
12
Size Project Name Rev
Custom
Veneno 1.3

Vinafix.com
Date: Wednesday, August 21, 2019 Sheet 12 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

D D
UC1T

UC1S N6 CF23
VSS_66 VSS_99
UC1R BT35 BY25
B37 V4
VSS_73 VSS_106
VSS_277 VSS_180 CB3 BE30
D6 J18 VSS_79 VSS_115
CR34 BL7 VSS_290 VSS_183 P10 CF28
VSS_342 VSS_330 AL32 AU32 VSS_84 VSS_126
BT5 AE25 VSS_156 VSS_186 B5 W10
VSS_351 VSS_337 BT36 BY28 VSS_89 VSS_139
BY5 BM33 VSS_165 VSS_245 CB33 BE31
VSS_361 VSS_345 D8 J21 VSS_95 VSS_8
CP35 CM5 VSS_172 VSS_257 P3 CF3
VSS_371 VSS_354 AL7 AV25 VSS_102 VSS_19
CM37 AE27 VSS_208 VSS_270 B7 W27
VSS_381 VSS_364 D9 BY33 VSS_110 VSS_29
CK37 BM35 VSS_217 VSS_284 CB4 CF4
VSS_391 VSS_374 AM10 J24 VSS_120 VSS_83
AW1 CM9 VSS_227 VSS_151 P33 W30
VSS_401 VSS_384 BU11 AV28 VSS_132 VSS_87
CM1 AE30 VSS_238 VSS_161 B9 BF3
VSS_411 VSS_302 E23 BY35 VSS_145 VSS_92
BD6 BM36 VSS_250 VSS_169 CB7 CG33
VSS_421 VSS_308 AM28 J33 VSS_14 VSS_98
AY4 CN13 VSS_263 VSS_175 P36 W7
VSS_360 VSS_315 E27 AV3 VSS_25 VSS_105
B34 AE7 VSS_276 VSS_179 BA10 BF33
VSS_370 VSS_322 AM33 BY36 VSS_35 VSS_114
E35 BM9 VSS_289 VSS_182 CC11 CG7
VSS_380 VSS_329 BU23 J36 VSS_44 VSS_125
A4 CN17 VSS_155 VSS_233 P4 BF36
VSS_390 VSS_336 E29 AV33 VSS_52 VSS_138
AE24 AF27 VSS_164 VSS_244 BA28 Y26
VSS_400 VSS_344 AM35 J6 VSS_59 VSS_7
AE26 BN30 VSS_200 VSS_256 P7 BF4
VSS_410 VSS_353 BU24 AV36 VSS_65 VSS_18
AF25 CN21 VSS_207 VSS_269 BA3 CH31
VSS_420 VSS_363 E31 C1 VSS_72 VSS_77
AG24 AF3 VSS_216 VSS_283 CC20 Y27
VSS_428 VSS_373 BU25 K21 VSS_78 VSS_82
AG26 BN7 VSS_226 VSS_150 R27 BG25
VSS_434 VSS_295 E33 AV4 VSS_131 VSS_86
AH24 CN25 VSS_237 VSS_160 BB3 Y30
VSS_296 VSS_301 AN25 C21 VSS_144 VSS_91
AH25 AF30 VSS_249 VSS_168 CC25 BG28
VSS_350 VSS_307 BU7 K22 VSS_13 VSS_97
B2 CN29 VSS_262 VSS_174 R28 CJ11
VSS_359 VSS_314 E9 AV6 VSS_24 VSS_104
B36 AF33 VSS_275 VSS_178 BB33 Y33
VSS_369 VSS_321 AN28 C25 VSS_34 VSS_113
C36 BP15 VSS_288 VSS_222 CC28 CJ14
C VSS_379 VSS_328 BV11 K24 VSS_43 VSS_124 C
C37 AF36 VSS_154 VSS_232 R29 Y35
VSS_389 VSS_335 F12 AV8 VSS_51 VSS_137
CN1 AF4 VSS_194 VSS_243 BB36 BH28
VSS_399 VSS_343 AN29 C29 VSS_58 VSS_6
CN2 CN5 VSS_199 VSS_255 CC31 CJ19
VSS_409 VSS_352 F15 K25 VSS_64 VSS_70
CN37 AF7 VSS_206 VSS_268 R30 Y7
VSS_419 VSS_362 AN30 AW28 VSS_71 VSS_76
CP2 BP25 VSS_215 VSS_282 BB4 BH29
VSS_427 VSS_416 F18 C33 VSS_119 VSS_81
D1 CN9 VSS_225 VSS_149 CC7 CJ23
VSS_433 VSS_425 AN31 K27 VSS_130 VSS_85
A32 AG10 VSS_236 VSS_159 R31 BH32
VSS_341 VSS_432 BV3 AW29 VSS_143 VSS_90
F33 BP3 VSS_248 VSS_167 BC25 CJ28
VSS_349 VSS_294 F2 C4 VSS_12 VSS_96
A3 CP1 VSS_261 VSS_173 CD11 BH33
VSS_358 VSS_300 AN7 K28 VSS_23 VSS_103
BJ7 BP32 VSS_274 VSS_212 T27 CJ33
VSS_368 VSS_306 BV31 AW3 VSS_33 VSS_112
CJ36 CP11 VSS_287 VSS_221 CD12 BH35
VSS_378 VSS_313 F21 C9 VSS_42 VSS_123
A36 AH27 VSS_189 VSS_231 T30 CJ35
VSS_388 VSS_320 AN8 K29 VSS_50 VSS_136
BK10 BP33 VSS_193 VSS_242 BC29 BP19
VSS_398 VSS_327 BV33 AW30 VSS_57 VSS_5
CJ4 CP13 VSS_198 VSS_254 CD14 BR16
VSS_408 VSS_334 F24 CA11 VSS_63 VSS_17
AB27 AH28 VSS_205 VSS_267 T33 BY18
VSS_418 VSS_405 BV4 K3 VSS_109 VSS_28
BK2 BP4 VSS_214 VSS_281 T35 BY19
VSS_426 VSS_415 F3 AW31 VSS_118 VSS_38
CK1 CP15 VSS_224 VSS_148 BC32 CC16
VSS_333 VSS_424 AP3 CA15 VSS_129 VSS_47
AB3 AH29 VSS_235 VSS_158 CD24 BU16
VSS_340 VSS_431 BW11 K30 VSS_142 VSS_55
BK28 BP7 VSS_247 VSS_166 T36 CC14
VSS_348 VSS_293 F4 AY33 VSS_11 VSS_62
AB30 CP19 VSS_260 VSS_203 CD25 BR22
VSS_357 VSS_299 AP33 CA22 VSS_22 VSS_69
BK3 AH30 VSS_273 VSS_211 T7 BU20
VSS_367 VSS_305 BW15 K31 VSS_32 VSS_75
CK4 CP21 VSS_185 VSS_220 BC8 CD20
VSS_377 VSS_312 G21 AY35 VSS_41 VSS_80
AB33 AH31 VSS_188 VSS_230 CE33 BT14
VSS_387 VSS_319 AP36 K32 VSS_49 VSS_135
BK33 BR19 VSS_192 VSS_241 U26 BP12
VSS_397 VSS_326 G27 B12 VSS_56 VSS_4
CK7 CP27 VSS_197 VSS_253 BD28 CB24
VSS_407 VSS_394 AP4 K4 VSS_101 VSS_16
AB36 AH33 VSS_204 VSS_266 CE35 CC24
VSS_417 VSS_404 G33 B15 VSS_108 VSS_27
BK4 BR25 VSS_213 VSS_280 U7 J5
VSS_325 VSS_414 AR28 CA25 VSS_117 VSS_37
CL2 AH35 VSS_223 VSS_147 BD33 U24
VSS_332 VSS_423 G35 K9 VSS_128 VSS_46
B AB4 CP37 VSS_234 VSS_157 CE36 BD7 B
VSS_339 VSS_430 G36 B18 VSS_141 VSS_54
BK7 AJ25 VSS_246 VSS_196 V26 AR4
VSS_347 VSS_292 AT33 CB11 VSS_10 VSS_61
CM13 BT15 VSS_259 VSS_202 BD35 AU4
VSS_356 VSS_298 BW24 L27 VSS_21 VSS_68
AB7 AJ28 VSS_272 VSS_210 CE7 AW4
VSS_366 VSS_304 G9 B21 VSS_31 VSS_74
BL25 BT16 VSS_286 VSS_219 V27 BA6
VSS_376 VSS_311 AT35 L33 VSS_40 VSS_122
CM17 CP9 VSS_153 VSS_229 BD36 BC4
VSS_386 VSS_318 H21 B23 VSS_48 VSS_134
AC10 AJ7 VSS_163 VSS_240 CF11 BE4
VSS_396 VSS_383 AT36 L35 VSS_94 VSS_3
BL28 CR2 VSS_171 VSS_252 V3 BE8
VSS_406 VSS_393 BW7 B25 VSS_100 VSS_15
CM21 AK3 VSS_177 VSS_265 BE10 BA4
VSS_317 VSS_403 H27 CB18 VSS_107 VSS_26
AC27 CR36 VSS_181 VSS_279 CF14 BD4
VSS_324 VSS_413 AT4 L36 VSS_116 VSS_36
BL29 AK33 VSS_184 VSS_146 V30 BG4
VSS_331 VSS_422 BY11 B27 VSS_127 VSS_45
CM25 D21 VSS_187 VSS_190 BE28 CJ2
VSS_338 VSS_429 AU10 CB19 VSS_140 VSS_53
AC30 AK36 VSS_191 VSS_195 CF19 CJ3
VSS_346 VSS_291 BY15 L6 VSS_9 VSS_60
BL30 BT25 VSS_258 VSS_201 V33 AM5
VSS_355 VSS_297 H9 B29 VSS_20 VSS_67
CM29 D25 VSS_271 VSS_209 BE29 CM4
VSS_365 VSS_303 AU28 CB2 VSS_30 VSS_111
BL31 AK4 VSS_285 VSS_218 CF2 AC5
VSS_375 VSS_310 BY22 N25 VSS_39 VSS_121
CM31 BT28 VSS_152 VSS_228 V36 AG5
VSS_385 VSS_372 J12 B31 VSS_88 VSS_133
AD33 AL28 VSS_162 VSS_239 BE3 CR6
VSS_395 VSS_382 AU29 CB20 VSS_93 VSS_2
BL32 BT33 VSS_170 VSS_251
VSS_309 VSS_392 J15 N27
CM33 D5 VSS_176 VSS_264
VSS_316 VSS_402 CB25
AD35 AL29 VSS_278 19 of 20 WHL_U_IP_CCG
VSS_323 VSS_412
18 of 20 WHL_U_IP_CCG
17 of 20
WHL_U_IP_CCG

A A

Bitland Information Technology Co.,Ltd.

Page Name
13
Size Project Name Rev
Custom
Veneno 1.3

Vinafix.com
Date: Wednesday, August 21, 2019 Sheet 13 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

UC1Q
WHL QS/CFL/WHL_ES1_CNL U
CFG_0 T4 F37
17 CFG_0 CFG_0 RSVD_TP_5
F34
RSVD_TP_6
20MIL TP1401 1 R4
CP36
CFG_1
20MIL TP1402 1 T3 IST_TRIG
CN36
CFG_2
20MIL TP1403 1 R3 RSVD_TP_12
CFG_4 J4
CFG_3
D 17 CFG_4 CFG_4 D
20MIL TP1405 1 M4 BJ36
CFG_5 RSVD_TP_3/RSVD/RSVD_TP_3
20MIL TP1406 1 J3 BJ34
CFG_6 RSVD_TP_4/RSVD/RSVD_TP_4
20MIL TP1407 1 M3
CFG_7
20MIL TP1408 1 R2 BK34
UC1O CFG_9 N2
CFG_8 TP_3
BR18
17 CFG_9 CFG_9 TP_4
WHL QS/CFL U/WHL ES1_CNL U22WHL QS/CFL U/WHL ES1_CNL U22
20MIL TP1410 1 R1
CFG_10
K12 AA24 20MIL TP1411 1 N1
RSVD_25/VCC_OPC_1/RSVD_25
RSVD_39/VCCEOPIO_1/RSVD_39 CFG_11
K14 AA26 20MIL TP1412 1 J2
RSVD_26/VCC_OPC_2/RSVD_26
RSVD_40/VCCEOPIO_2/RSVD_40 CFG_12
K15 AB25 20MIL TP1413 1 L2 BT9
RSVD_27/VCC_OPC_3/RSVD_27
RSVD_41/VCCEOPIO_3/RSVD_41 CFG_13 RSVD_TP_8/RSVD/RSVD_TP_8
K17 AC24 20MIL TP1414 1 J1 BT8
RSVD_28/VCC_OPC_4/RSVD_28
RSVD_42/VCCEOPIO_4/RSVD_42 CFG_14 RSVD_TP_9/RSVD/RSVD_TP_9
K18 AC25 20MIL TP1415 1 L1
RSVD_29/VCC_OPC_5/RSVD_29
RSVD_43/VCCEOPIO_5/RSVD_43 CFG_15
K20 AC26 BP8
RSVD_30/VCC_OPC_6/RSVD_30
RSVD_44/VCCEOPIO_6/RSVD_44 RSVD_TP_10/RSVD/RSVD_TP_10
L25 AD24 L3 BP9
RSVD_31/VCC_OPC_7/RSVD_31
RSVD_45/VCCEOPIO_7/RSVD_45 CFG_16 RSVD_TP_11/RSVD/RSVD_TP_11
M24 AD26 N3
RSVD_32/VCC_OPC_8/RSVD_32
RSVD_46/VCCEOPIO_8/RSVD_46 CFG_18
M26 V25 CR4
RSVD_33/VCC_OPC_9/RSVD_23
RSVD_19/VCCEOPIO_SENSE/RSVD_19 L4 RSVD_14
P24 T25 CFG_17
RSVD_34/VCC_OPC_10/RSVD_34
RSVD_20/VSSEOPIO_SENSE/RSVD_20 N4
P26 A35 CFG_19
RSVD_35/VCC_OPC_11/RSVD_35 RSVD_56 CP3
R24 D34 R1499 R0201 49.9_F RSVD_15
CR3
R25
RSVD_36/VCC_OPC_12/RSVD_36 RSVD_57
N5 1 TP1418 20MIL 2 1 CFG_RCOMP AB5 RSVD_16
RSVD_37/VCC_OPC_13/RSVD_37
RSVD_58/OPC_RCOMP/RSVD_58 CFG_RCOMP
R26
V24
RSVD_38/VCC_OPC_14/RSVD_38 ITP_PMODE W4
RSVD_21/VCC_OPC_1P8_3/RSVD_21 ITP_PMODE
W25
RSVD_22/VCC_OPC_1P8_4/RSVD_22
Y24 CG2
RSVD_23/VCC_OPC_1P8_1/RSVD_23 +V1P0A_VCCPRIM RSVD_8
Y25 CG1
RSVD_24/VCC_OPC_1P8_2/RSVD_24 RSVD_9
G2 1K_J
RSVD_47
G1 R1467 2 1
AT3
RSVD_48
20MIL TP1416 1 C34 RSVD_TP_13/RSVD/RSVD_TP_13
AU3
RSVD_49/VSS_435/RSVD_49 R0201
G3 RSVD_TP_1/RSVD/RSVD_TP_1
RSVD_50/VSS_436/RSVD_50
G4 H4
C RSVD_51/VSS_437/RSVD_51 RSVD_10 C
A34 H3
RSVD_52/RSVD_TP/RSVD_52 RSVD_11
B35
RSVD_53/RSVD_TP/RSVD_53 AN1
AJ27 BV24 RSVD_2
RSVD_54/MSM#/RSVD_54 RSVD_12 AN2
AH26 BV25 RSVD_3
RSVD_55/ZVM#/RSVD_55 RSVD_13
20MIL TP1417 1 L5
AN4
RSVD_59/OPCE_RCOMP/RSVD_59
RSVD_6
AN3
15 of 20 +1.0V_PRIM +V1P0A_VCCPRIM RSVD_7

WHL_U_IP_CCG AL2
IST_TP_0/RSVD/IST_TP_0
AL1
2 R1427 1 IST_TP_1/RSVD/IST_TP_1
SHORT_0402
AL4 FOLLOW 575962 1.0
IST_TRIG_0/RSVD/IST_TRIG_0
AL3 2018/10/10
IST_TRIG_1/RSVD/IST_TRIG_1
BK36
RSVD_18 BP34
BK35 TP_2
RSVD_17 BP36 2 R11516 1
VSS_1/TP/VSS_1
BP35 SHORT_0402
W3 TP_1
RSVD_4
AM4
RSVD_5

AM3
RSVD_TP_7/RSVD/RSVD_TP_7

CR35 1 TP10133 20MIL

RSVD_TP_2/RSVD/RSVD_TP_2

B B
E1 SKL_CNL_N
SKTOCC# SKL_CNL_N 17

20 of 20 WHL_U_IP_CCG

+1.0VS_VCCIO +1.0VS_VCCIO 3,10,17,64

+V1P0A_VCCPRIM +V1P0A_VCCPRIM
+1.0V_PRIM +1.0V_PRIM 11,63,64
+1.0V_VCCST +1.0V_VCCST 3,7,10,12,17,64,66
A A
Display Port Presence Strap Bitland Information Technology Co.,Ltd.
Follow 544669_SKL_U_DDR3L_RVP7_schematic_rev1.0
Page Name
1 : Disabled; No Physical Display Port 14
CFG4 attached to Embedded Display Port For 2+3e Solution Size Project Name Rev
PM_ZVM# Custom
Veneno
PM_MSM# 1.3
0 : Enabled; An external Display Port device is

Vinafix.com
Date: Wednesday, August 21, 2019 Sheet 14 of 87
connected to the Embedded Display Port PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

+VCC_CORE

1
C1507 C1508

1
C1501 C1502 C1503 C1504 C1505 C1506 C1509 C1510 C1511 C1512 C1513 C1514 C1515 C1516 C1517 C1518 C1519 C1520 C1521 C1522 C1523 C1524
10uF/6.3V,X5R 22uF/6.3V,X5R
22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 10uF/6.3V,X5R 22uF/6.3V,X5R 10uF/6.3V,X5R C0402 C0603 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 10uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 10uF/6.3V,X5R
C0603 C0603 C0603 C0402 C0603 C0402 C0603 C0603 C0603 C0603 C0603 C0402 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0402

2
2

2
ns ns ns ns ns
20180712 20180712 20180712 20180712
EE NOISE EE NOISE EE NOISE EE NOISE
D D

1
C1536
1

1
C1525 C1526 C1527 C1528 C1529 C1530 C1531 C1532 C1533 C1534 C1535 C1537 C1538 C1539
10uF/6.3V,X5R
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R C0402 10uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R +VCC_CORE
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0603 C0603

2
2

2
20180712
EE NOISE

1
C15A68 C15A69
1

1
C1541 C1542 C1543 C1544 C1545 C15A64 C15A65 10uF/6.3V,X5R 10uF/6.3V,X5R
1

1
C1540 C1546 C1547 C1548 C15A66 C15A67

1
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R C15A63 10uF/6.3V,X5R 22uF/6.3V,X5R C0402 C0402
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R

2
C0402 C0402 C0402 C0402 C0402 22uF/6.3V,X5R C0402 C0603
C0402 C0402 C0402 C0402 C0402 C0402
2

2
C0603
2

2
2
ns 20180712 20180712
20180712 EE NOISE EE NOISE
EE NOISE
3/24 Power:add C15A68,C15A69 reserved

2
C1557
+VCC_CORE
2

2
C1549 C1550 C1551 C1552 C1553 C1554 C1555 C1556 C1558 C1559 C1560 C1561 C1562 C1563 C15A61 C15A62
1UF/6.3V,X5R
1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
C0201 C0201 C0201 C0201
C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201

1
47uF x0
1

1
C
22uF x25 change 22uF x40 C

10uF x23

2
C1570 C15A99 C15A50 C15A51 C15A52 C15A53 C15A54 C15A55 C15A56 C15A57
2

C1564 C1565 C1567 C1568

change 1uF x35
2

2
C1566 C1569 0.1UF/10V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 0.1UF/10V,X5R
1UF/6.3V,X5R
C0201
1UF/6.3V,X5R
C0201
1UF/6.3V,X5R
1UF/6.3V,X5R 1UF/6.3V,X5R
C0201 C0201
1UF/6.3V,X5R C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
1uF x33

1
C0201 C0201
1

change 100uF x0
1

+VCC_CORE
+VCC_CORE
100uF x10

2
C1587
1

1
C15A58 C1571 C1572 C1573 C1574 C1575 C1576 C15A60 C1578 C1579 C1580 C1581 C1582 C1585 C1586 C1588

1
C1583 1UF/6.3V,X5R
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 10uF/6.3V,X5R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0603 C0603 C0603 C0402 C0402 10uF/6.3V,X5R C0201 C0402
C0201 C0201

1
C0402
2

2
2
ns
20180712
+VCC_GT EE NOISE

+VCC_CORE
1

1
C1596 C1597 C1599 C15A01 C15A02
1

1
C10968 C10969 C1598
22uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
22uF/6.3V,X5R 22uF/6.3V,X5R C0603 C0402 10uF/6.3V,X5R C0402 C0402 C0402

2
C0603 C0603 C0402 C15A42 C15A43 C15A44 C15A45 C15A46 C15A47 C15A48 C15A49
2

2
2

2
ns 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
ns ns ns C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201

1
B 20180712 B
EE NOISE
1

C15A09
1

1
C15A03 C15A04 C15A05 C15A06 C15A07 C15A08 C15A10 C15A11 C15A12 C15A13 C15A14 C15A15
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603
10uF/6.3V,X5R
C0402
10uF/6.3V,X5R22uF/6.3V,X5R
C0402 C0603
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603 22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603 +VCCCORE_GT
2

10uF x7 change 10uF x8

2

2
ns ns
20180712
EE NOISE

1uF x7 change 1uF x8

+VCC_GT
1

C15A16 C15A17 C15A18 C15A19 C15A20 C15A21 C15A22 C15A23 C15A24

10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
2

ns ns

22uF x24 change 22uF x4

10uF x15
2

C15A25 C15A26 C15A27 C15A28 C15A29 C15A30 C15A31 C15A32 C15A33 C15A34 C15A35
1UF/6.3V,X5R
C0201
1UF/6.3V,X5R
C0201
1UF/6.3V,X5R
C0201
0.1UF/10V,X5R0.1UF/10V,X5R 1UF/6.3V,X5R
C0201 C0201 C0201
1UF/6.3V,X5R
C0201
0.1UF/10V,X5R 22uF/6.3V,X5R
C0201 C0603
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603 1uF x8
1

A 100uF x5 change 100uF x0 A

Bitland Information Technology Co.,Ltd.

Page Name
15
1

C15A37 C15A38 C15A39 C15A40 C15A41

1

C15A36 10uF/6.3V,X5R10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R Size Project Name Re v

10uF/6.3V,X5R C0402 C0402 C0402 C0402 C0402 Custom
Veneno
2

C0402 1.3
2

Date: Wednesday, August 21, 2019 Sheet 15 of 87

PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

D +VCC_SA
+VCC_SA 12/30 check PDG D

47uF x2

1
C1631 C1632 C1668 C1669
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603
22uF/6.3V,X5R
C0603 10uF x13
2

2
1uF x7
ns
1

1
C1618 C1619 C1620 C1621 C1622 C1623 C1624 C1625 C1626 C1627 C1628 C1629 C1630
10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R
C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
2

2
ns ns

+VCC_CORE +VCC_CORE 12,15,66,67

+VCC_GT +VCC_GT 12,15,66,67
+VCC_SA +VCC_SA 10,66,67
2

2
C1649 C10962 C10963 C10964 C10965 C10966 C10967
1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
C0201 C0201 C0201 C0201 C0201 C0201 C0201
1

1
C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
16
Size Project Name Re v
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 16 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

+1.0VS_VCCIO
+1.0VS_VCCIO +V3P3A +V3P3A

2
R1486 DDI1_DDC_SDA DDI2_DDC_SDA
2

1
2
10K_J 3,32 DDI1_DDC_SDA 3 DDI2_DDC_SDA
R1460 R553
R555
1K_J R0201
R0201 strap PIN 1K_J 100K_F Port B Detected Port C Detected
R0201
R0201
This signal has an integrated weak pull-down resistor (20 This signal has an integrated weak pull-down resistor (20
CFG_9 ns

1
ns GPP_C5 ESPI OR LPC KΩ no m i nal). KΩ no m i nal).
CFG_0 CFG_9 14 When this signal is sampled high, the Digital Display Port When this signal is sampled high, the Digital Display
1, ESPI
1

2
2
CFG_0 14

1
0, LPC B will be detected. Port C will be detected.
D R1485 D
CFG0 EAR-STALL/NOT STALL RESET
SEQUENCE AFTER PCU PLL IS 10K_J SVID OPTION PIN PAG3
STRAP_GPP_C5 5
LOCKED R0201 1, SUPPORT
1:(DEFAULT) NORMAL OPERATION; NO 0, NO SUPPORT

2
STALL ns R1715

1
0:STALL GPP_C2 TLS CONFIDENTIALITY
1, TLS EN 10K_J
CFG_4
CFG_4 14 0, TLS DIS R0201
2

STRAP_GPP_C2 5
R1449 ns

1
CFG4 DISPLAY PORT PRESENCE STRAP
1K_J
R0201 0: ENABLED-- AN EXTERNAL DISPLAY PORT
DEVICE IS CONNECTED TO THE EMBEDDED
DISPLAY PORT
1: DISABLED--NO PHYSICAL DISPLAY PORT
1

ATTACHED TO EMBEDDED DISPLAY PORT

PAG14 PAG5
+V3P3A
+V3P3A +V3P3A

ME_Flash_EN

2
2
ME_Flash_EN 2
R709
R676
Flash Descriptor Security Override RA107 4.7K_J
1, OVERRIDEN 100K_F
4.7K_J R0201
0, NOT OVERRIDEN R0201
R0201 20190322:Follow V540-WHL,Intel suggest install R676
C ns SoftStrap selectable with default SLP_WLAN#. No
C
+V3P3SX GPD_7

1
GPP_H21 pull-up/pull-down resistors needed. Signals driven

1
GPD_7 6 INPUT3VSEL 7
1

ns GPP_H21 6 by the PCH. If using WLAN, connect signal to

100K_F control WLAN subsystem power. If not using

2
R652 1 2
2

HDA_SPKR 6,46,50 WLAN, signal may be left as NC.

R0201 R708
GPP_H21Pin Strap for XTAL R677
RA117 frequency selection. An external 4.7K_J 3V SELECT STRAP
HDA_SPKR TOP SWAP OVERRIDE 20K_J LOW-> 3.3V +/-5%
1, TOP SWAP ENABLED 20K_J pull-up to VCC (1.8V or 3.3V) is R0201
required on this strap for 24 MHz
R0201 HIGH->3.0V +/-5%
0, DISABLED R0201 GPD_7 XTAL INPUT MODE
ns XTAL operation ns 0, XTAL INPUT IS SINGLE ENDED

1
1, 24MHz
1

1, XTAL IS ATTACHED
0, 38.4/19.2MHz (DEFAULT) PAG7
PAG6
+1.8V_PRIM

+V3P3SX +1.8V_PRIM

2
+V3P3A
JTAG ODT DISABLE
2018/06/26 R1701 LOW: JTAGE ODT DISABLED
2

20K_J HIGH: JTAG ODT ENABLED

Change R1701 from I to NI

2
R826 R0201 WAKE INTERNAL PU
R876 R11608
4.7K_J ns
20K_J

1
R0201 8,43 CNVI_BRI_DT 100K_F
R0201
ns GPP_F4 This signal has a weak internal pull-down. R0201 +1.0V_VCCST
CNVI_RGI_DT An external pull-up is required on this strap since 38.4 ns
1

B TP_STRAP_GPP_B18 8 CNVI_RGI_DT 8,43 B

MHz XTAL is not supported on the PCH.

1
2

0 = 38.4 XTAL frequency selected (Default)

2
GPP_D12 8
R877 M.2 CNVI MODES
R827 R1484
NO REBOOT 4.7K_J0, INTEGRATED CNVI ENABLE FP_SPI_MOSI
20K_J HIGH - NO REBOOT 1, INTEGRATED CNVI DISABLE 8 FP_SPI_MOSI 100K_F
R0201
R0201 LOW- REBOOT ENABLED R0201
ns ns This signal has an integrated weak
ns
pull-down resistor (20 KΩ no mi nal) t o
1

SKL_CNL_N

1
default boot from SPI. PAG8 14 SKL_CNL_N

2
USB_P1_WP_OC_N USB_P2_WP_OC_N USB2_P3_WP2_OC_N R1491
USB_P1_WP_OC_N 9,49 USB2_TYPC_OC_N USB_P2_WP_OC_N 9,49 USB2_P3_WP2_OC_N 9
USB2_TYPC_OC_N 9,52,53 0_J
R0201
RING OSCILLATOR BYPASS
LOW: RING OSCILLATOR XTAL INPUT MODE (HVM ONLY)
XTAL INPUT FREQUENCY [1:0] LOW: XTAL INPUT IS SINGLE ENDED
HIGH :BYPASS MODE ENABLED 00-24MHZ

1
HIGH: XTAL INPUT IS DIFFERENTIAL
01-25MHZ NO PU/PD
10-250MHZ HVM ONLY ( QUALIFIED BY DFXTESTMODE)
11-100MHZ
( QUALIFIED BY DFXTESTMODE)

PAG9

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J_DIMM1A
+V3P3SX
137 8
4 M_B_DIM0_CK0_DDR1_DP CK0_T DQ0 M_B_DQ<13> 4
D 139 7 D
4 M_B_DIM0_CK0_DDR1_DN CK0_C DQ1 M_B_DQ<9> 4
138 20
4 M_B_DIM0_CK1_DDR1_DP CK1_T DQ2 M_B_DQ<10> 4

1
140 21 +V2P5U_VPP

1
4 M_B_DIM0_CK1_DDR1_DN CK1_C DQ3 M_B_DQ<15> 4
RD11 RD6 4 +V1P2U_VDDQ +V0.6S_VTT +V2P5U_VPP +V3P3SX
RD17 DQ4 M_B_DQ<12> 4
109 3
0_J 0_J 4 M_B_DIM0_CKE0 CKE0 DQ5 M_B_DQ<8> 4
0_J 4 M_B_DIM0_CKE1
110 16
M_B_DQ<11> 4
CKE1 DQ6 J_DIMM1B

2
ns ns DQ7
17
M_B_DQ<14> 4 CD6 CD7 CD8 CD9
R0402 R0402 149 28 163 258 ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R
R0402 4 M_B_DIM0_CS0_N S0# DQ8 M_B_DQ<3> 4 VDD19 VTT
2

2
CHANNEL-1: 157 29 160 C0402 C0402 C0201 C0201

2
4 M_B_DIM0_CS1_N S1# DQ9 M_B_DQ<7> 4 VDD18

1
41 159 RD8
DQ10 M_B_DQ<6> 4 VDD17 ns
SA0:0 4 M_B_DIM0_ODT0
155
161
ODT0 DQ11
42
24
M_B_DQ<1> 4
154
153
VDD16 VPP2
259
257
SHORT_0603
1

1
4 M_B_DIM0_ODT1 ODT1 DQ12 M_B_DQ<0> 4 VDD15 VPP1

SA1:1
25 148
RD16 RD5 RD7 DQ13 M_B_DQ<2> 4 VDD14
115 38 147
4 M_B_BG0 BG0 DQ14 M_B_DQ<5> 4 VDD13
0_J 0_J 0_J 113 37 142
SA2:0 R0402
ns
4 M_B_BG1
4 M_B_BA0
150
145
BG1
BA0
DQ15
DQ16
50
49
M_B_DQ<4> 4
M_B_DQ<20> 4
141
136
VDD12
VDD11 VDDSPD
255
+V1P2U_VDDQ
R0402 R0402 4 M_B_BA1 BA1 DQ17 M_B_DQ<21> 4 VDD10
62 135
2

2
DQ18 M_B_DQ<23> 4 VDD9
144 63 130

1
4 M_B_A0 A0 DQ19 M_B_DQ<18> 4 VDD8 CD5
133 46 129

1
4 M_B_A1 A1 DQ20 M_B_DQ<17> 4 VDD7 2.2UF/6.3V,X5R CD10 CD11 CD12 CD13 CD14 CD15 CD16 CD17
132 45 124
4 M_B_A2 A2 DQ21 M_B_DQ<16> 4 VDD6 CD4 C0402 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R ns 10uF/6.3V,X5R
131 58 123

2
SA2_CHB_DIM1 4 M_B_A3 A3 DQ22 M_B_DQ<19> 4 VDD5 0.1uF/10V,X5R C0402 C0402 C0402 C0402 C0402 C0402 C0402 C0402
128 59 118 ns

2
4 M_B_A4 A4 DQ23 M_B_DQ<22> 4 VDD4 C0201
126 70 117 261
SA1_CHB_DIM1 4 M_B_A5 A5 DQ24 M_B_DQ<28> 4 VDD3 NPTH1
127 71 112 262
4 M_B_A6 A6 DQ25 M_B_DQ<24> 4 VDD2 NPTH2
122 83 111
SA0_CHB_DIM1 4 M_B_A7 A7 DQ26 M_B_DQ<30> 4 VDD1
125 84
4 M_B_A8 A8 DQ27 M_B_DQ<31> 4
121 66 +V1P2U_VDDQ
4 M_B_A9 A9 DQ28 M_B_DQ<25> 4
146 67
4 M_B_A10_AP A10_AP DQ29 M_B_DQ<29> 4
+V1P2U_VDDQ 120 79
4 M_B_A11 A11 DQ30 M_B_DQ<27> 4
119 80 251 252
4 M_B_A12 A12 DQ31 M_B_DQ<26> 4 VSS1 VSS48
158 174 247 248

2
4 M_B_A13 A13 DQ32 M_B_DQ<39> 4 VSS2 VSS49 CD18 CD19 CD20 CD21 CD22 CD23 CD24 CD25
151 173 243 244
4 M_B_A14_WE_N A14_WE# DQ33 M_B_DQ<32> 4 VSS3 VSS50 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R 1UF/6.3V,X5R ns 1UF/6.3V,X5R ns 1UF/6.3V,X5R ns 1UF/6.3V,X5R
RD9 4 M_B_A15_CAS_N
156 187
M_B_DQ<35> 4
239 238
A15_CAS# DQ34 VSS4 VSS51 C0201 C0201 C0201 C0201 C0201 C0201 C0201 C0201
240.0_F 152 186 235 234

1
1% 4 M_B_A16_RAS_N A16_RAS# DQ35 M_B_DQ<37> 4 VSS5 VSS52
170 231 230
r0201 DQ36 M_B_DQ<38> 4 VSS6 VSS53
169 227 226
I DQ37 M_B_DQ<33> 4 VSS7 VSS54
114 183 223 222
4 M_B_ACT_N ACT# DQ38 M_B_DQ<36> 4 VSS8 VSS55
182 217 218
DQ39 M_B_DQ<34> 4 VSS9 VSS56
143 195 213 214
4 DDR1_B_PARITY PARITY DQ40 M_B_DQ<40> 4 VSS10 VSS57
116 194 209 210
4 DDR1_B_ALERT_N ALERT# DQ41 M_B_DQ<41> 4 VSS11 VSS58
134 207 205 206
EVENT# DQ42 M_B_DQ<42> 4 VSS12 VSS59
108 208 201 202
19 DDR4_DRAMRST_RC0201 RESET# DQ43 M_B_DQ<43> 4 VSS13 VSS60
1 2 CD29 ns 191 197 196
+V_DDR_VREFCA_CHB_DIMM DQ44 M_B_DQ<44> 4 VSS14 VSS61
C +V_DDR_VREFCA_CHB_DIMM 0.1uF/10V,X5R 164 190
M_B_DQ<45> 4
193 192
C
VREFCA DQ45 VSS15 VSS62
203 189 188
DQ46 M_B_DQ<47> 4 VSS16 VSS63
254 204 185 184
5 SODIMM0_1_SMB_DATA_R SDA DQ47 M_B_DQ<46> 4 VSS17 VSS64
253 216 181 180
1

CD3 5 SODIMM0_1_SMB_CLK_R SCL DQ48 M_B_DQ<53> 4 VSS18 VSS65

215 175 176
CD2 2.2UF/6.3V,X5R SA2_CHB_DIM1 DQ49 M_B_DQ<49> 4 VSS19 VSS66
166 228 171 172
0.1uF/10V,X5R C0402 SA1_CHB_DIM1 SA2 DQ50 M_B_DQ<54> 4 VSS20 VSS67
260 229 167 168
2

C0201 SA0_CHB_DIM1 SA1 DQ51 M_B_DQ<51> 4 VSS21 VSS68

ns +V3P3A 256 211 107 106
SA0 DQ52 M_B_DQ<52> 4 VSS22 VSS69
212 103 102
DQ53 M_B_DQ<48> 4 VSS23 VSS70
224 99 98
DIMM_CB0 DQ54 M_B_DQ<55> 4 VSS24 VSS71
92 225 93 94
DIMM_CB1 CB0_NC DQ55 M_B_DQ<50> 4 VSS25 VSS72 +V0.6S_VTT
2

91 237 89 90
R10890 R10891 DIMM_CB2 CB1_NC DQ56 M_B_DQ<56> 4 VSS26 VSS73
101 236 85 86
DIMM_CB3 CB2_NC DQ57 M_B_DQ<60> 4 VSS27 VSS74
10K_J 10K_J DIMM_CB4 105 249
M_B_DQ<59> 4
81 82
CB3_NC DQ58 VSS28 VSS75
88 250 77 78
r0201 r0201 DIMM_CB5 CB4_NC DQ59 M_B_DQ<63> 4 VSS29 VSS76
87 232 73 72
DIMM_CB6

2
CB5_NC DQ60 M_B_DQ<61> 4 VSS30 VSS77 CD27 CD28 CD26
100 233 +V1P2U_VDDQ 69 68
SODIMM0_1_SMB_DATA_R DIMM_CB7 CB6_NC DQ61 M_B_DQ<57> 4 VSS31 VSS78 10uF/6.3V,X5R 10uF/6.3V,X5R 1UF/6.3V,X5R
1

104 245 65 64
CB7_NC DQ62 M_B_DQ<58> 4 VSS32 VSS79 C0402 C0402 C0201
SODIMM0_1_SMB_CLK_R 246 61 60

1
DQ63 M_B_DQ<62> 4 VSS33 VSS80
12 57 56
DM0#/DBI0# VSS34 VSS81
33 13 RD18 51 52
DM1#/DBI1# DQS0_T M_B_DQS_DP<1> 4 VSS35 VSS82
+V1P2U_VDDQ 54 34 240.0_F 47 48
DM2#/DBI2# DQS1_T M_B_DQS_DP<0> 4 1% VSS36 VSS83
75 55 43 44
DM3#/DBI3# DQS2_T M_B_DQS_DP<2> 4 r0201 VSS37 VSS84
178 76 39 40
DM4#/DBI4# DQS3_T M_B_DQS_DP<3> 4 I VSS38 VSS85
199 179 35 36
DM5#/DBI5# DQS4_T M_B_DQS_DP<4> 4 VSS39 VSS86
220 200 31 30
DM6#/DBI6# DQS5_T M_B_DQS_DP<5> 4 VSS40 VSS87
241 221 +V1P2U_VDDQ 27 26
DM7#/DBI7# DQS6_T M_B_DQS_DP<6> 4 VSS41 VSS88
96 242 23 22
DM8#/DBI8# DQS7_T M_B_DQS_DP<7> 4 VSS42 VSS89
97 19 18
DQS8_T VSS43 VSS90
15 14
VSS44 VSS91
11 RD19 9 10
DQS0_C M_B_DQS_DN<1> 4 VSS45 VSS92
32 240.0_F 5 6
DQS1_C M_B_DQS_DN<0> 4 1% VSS46 VSS93
53 1 2
DQS2_C M_B_DQS_DN<2> 4 VSS47 VSS94
+V1P2U_VDDQ 162 74 r0201
S2#/C0 DQS3_C M_B_DQS_DN<3> 4 I
165 177
S3#/C1 DQS4_C M_B_DQS_DN<4> 4
198 ASAA821-H4RB5-7H
DQS5_C M_B_DQS_DN<5> 4
219
DQS6_C M_B_DQS_DN<6> 4
2

240
DQS7_C M_B_DQS_DN<7> 4
CD31 RD12 95
0.1uF/10V,X5R DQS8_C
1K_F
1

+V1P2U_VDDQ
C0201 R0402

ASAA821-H4RB5-7H cn_dimm-ddr4_asaa821-h4rb5-7h
1

I DIMM_CB0
1 RD1 4 2 SHORT_0402 R10892 1%
240.0_F r0201 I
DIMM_CB1
2

R10893 1%
240.0_F r0201 I
B ns DIMM_CB2 B
CD30 R10894 1%
240.0_F r0201 I
2

DIMM_CB3
R10895 1%
240.0_F r0201 I
RD13 0.1uF/10V,X5R DIMM_CB4
1

R10896 1%
240.0_F r0201 I
1K_F
C0201 DIMM_CB5
R10897 1%
240.0_F r0201 I
DIMM_CB6
R0402 R10898 1%
240.0_F r0201 I
DIMM_CB7
R10899 1%
240.0_F r0201 I
1

+V_DDR_VREFCA_CHB_DIMM
RD10 1 2 2.2_F R0603
4 +V_DDR_VREFDQ02_CHB
+V1P2U_VDDQ +V1P2U_VDDQ 4,10,51,61,64
1

CD32 +V0.6S_VTT +V0.6S_VTT 61

0.022UF/25V,X7R
C0402
+V1P2U_VDDQ +V2P5U_VPP +V2P5U_VPP 61
2

+V3P3SX +V3P3SX 4,5,6,7,17,26,30,32,36,43,46,50,64,81

2

RD15
RM41
24.9_F
470.0_J
R0402
+V1P2U_VDDQ
1

DDR4_DRAMRST_R
1

R0402 1 RM 42 2 SHORT_0402
4 DDR4_DRAMRST_N DDR4_DRAMRST_R 19
2

ns
RD23

1
1K_F CM7
R0402 10PF/50V,NPO
C0402
2

20190222:
1

BOM add CM7 10pf 0402

2

RD22
1K_F
R0402
1

A A

RD20 1 2 2.2_F R0603

4 +V_DDR_CA_VREF
1

CD33
2

0.022UF/25V,X7R
CD38 C0402
0.1uF/10V,X5R
2

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2

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V540S Power Map

EC_SLP_S3_N EN +V3P3SX
DCIN +VSYS +V3.3AL VR +V3.3AL +V3P3SX SW
+3V_RTC U6003(MP2322)
EN
SRTC_RST#
Charger +VSYS U6402(EM5209)
U5901(IS9238)
RTC_RST# +VDD33
PX_EN +VDD33 SW
T1
BATT +BATT EN
D 9 ms
CN5801 +VSYS +V3P3A VR +V3P3A D

U6002(RT6258B)
+V3.3A_PWRGD
+VSYS EN PG +1.8V_PRIM
+1V8_AON LDO
EC_ALW_EN U6501(G9661)
+V3.3AL +V3.3A_PWRGD EN

EC-GPO CP_PWR_EN 1V8_AON

+1V8_AON LDO
UG6901(G9661)
+V5CP PX_EN EN

EC-GPO EC_ALW_EN

+V3P3A +VSYS +5VCP VR +5VCP +V5P0A SW +V5P0A

U6001(RT6258C)
+V5P0A EC_ALW_EN EN
EN PG
V5PCP_EN
From CPU CPU_C10_GATE#/SLP_S0# U6403(EM5209)
+V5P0S

EC_SLP_S3_N
+V5P0S SW
+V3.3A_PWRGD

+1.8V_PRIM

+1.8V_PWRGD
C C
+1.0V_PRIM

EC-GPI V1.0_PWROK +V1P2U_VDDQ

+VSYS +VDDQ VR
U6101(G5416)
EC-GPO RSMRST_N EC_SLP_S4_N +V2P5U_VPP
Tied together EN2
+1.2V_VCCPLL_OC SW +1.2V_VCCPLL_OC
EC-GPO DSWROK_EC(Ignored in non-DS) +V0.6S_VTT U6405(EM5201)
SM_PG_CTRL
EN1 DDR_PWRGD EN
PG
EC_SLP_S3_N
CPU_C10_GATE#

EC-GPI PWR_SWIN#
+VSYS +1.0V_PRIM VR +1.0V_PRIM +1.0VS_VCCIO SW +1.0VS_VCCIO
EC-GPI SLP_S4_SOC U6301(G5335QT1U) U6401(EM5201)
V1.0_PWROK
EN PG EN
EC-GPO EC_SLP_S4_N
+1.8V_PWRGD EC_SLP_S3_N
CPU_C10_GATE#
+V1P2U_VDDQ

+V2P5U_VPP
+1.0VS_VCCSTG SW +1.0VS_VCCSTG
EC-GPI DDR_PWRGD U6406(EM5201)
EN
EC-GPI SLP_S3_SOC EC_SLP_S3_N
CPU_C10_GATE#
B EC-GPO EC_SLP_S3_N B

+V5P0S/+1.0V_VCCST +1.0V_VCCST SW +1.0V_VCCST

U6404(EM5201)
+V3P3SX/+V1P8S/+1.2V_VCCPLL_OC/+1.0VS_VCCIO/+1.0VS_VCCSTG EN
EC_SLP_S3_N
From CPU DDR_VTT_CTRL
+VCC_CORE
+V0.6S_VTT
VCC CORE VR +VCC_GT
EC-GPO ALLSYSPWRGD +VSYS U6601(RT3602AH)

+VCC_SA
+VCCSA VR_PWRGD
EN PG
EC-GPI VR_PWRGD ALLSYSPWRGD

EC-GPO SYS_PWROK
VDDC
+VSYS
PLTRST# GPU CORE VR VDDCI
U9021(RT3662ACGQW)
+VCCCORE NVVDD_PGOOD
EN PG
PX_EN
+VCCGT

+MVDD VR +MVDD
A +VSYS A
UG6902(G5335Q)
VRAM_PWRGD
EN PG
PX_EN

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

+V3P3A +V3P3A_SPI_FLASH

CR3000
1 2 ns
D
D
0.45V_0.1A_RB500V-40_R1_10001
sod323
NI
40mA
1 SH9512 2
+V3P3A_SPI_FLASH
SHORT_0402

C3058

1
0.1uF/10V,X5R

2
2
C0201
R2401 R2402

2
R2461
10K_J
10K_J 10K_J SPI ROM
r0201 r0201
r0201
U3002
FLASH_SPI_CS0_N_R

1
R2471 1 2 0_J R0402 1 8

1
5,50 FLASH_SPI_CS0_N R0402 FLASH_SPI_MISO_R /CS VCC FLASH_SPI_IO3_R
5,35,50 SPI0_MISO R2442 1 2 33.0_J 2 7
R2421 1 2 33.0_J R0402 FLASH_SPI_IO2_R 3
DO(IO1) /HOLD(IO3)
6 FLASH_SPI_CLK_R
5 SPI0_IO2 4
/WP(IO2) CLK
5 FLASH_SPI_MOSI_R
GND DI(IO0)
C C
W25Q128JVSIQ
I
R2469 1 2 33.0_J R0402
5,35,50 SPI0_MOSI R0402
R2470 1 2 33.0_J
5,35,50 SPI0_CLK R0402
R2422 1 2 33.0_J
5 SPI0_IO3

4/5 Remove BIOS Socket

ROM Socket

B B

2/24 SIV:Delet ROM Socket @U3002

+V3P3A +V3P3A 3,4,5,7,9,11,17,19,29,32,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81

A A

Bitland Information Technology Co.,Ltd.

Page Name
24
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 24 of 87
BPAGE DRAWING PROPERTY NOTE: this document contains information confidential and property to
INTERNAL ONLY Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
sky_y_mrd.GND documents or disclosed to others or used for any purpose other than that for which it
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8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
25
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 25 of 87
PROPERTY NOTE: this document contains information confidential and property to
BPAGE DRAWING Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
INTERNAL ONLY documents or disclosed to others or used for any purpose other than that for which it
sky_y_mrd.GND
was obtained with the expressed written consent of Bitland
Wed Jun 03 11:22:52 2015

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M.2 SSD Module 1.4A @ADATA 128GB SSD

2.6A @ADATA 256GB SSD
+V3P3SX
+V3P3A_SSD

SH4200
D
r0805_short
D

Change SH4200 0805 shunt to resistor

+V3P3A_SSD

C4205 C4206 C4207 C4208

1

1
1

C4209 C4204
0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R
22uF/6.3V,X5R 22uF/6.3V,X5R C0201 C0201 C0201 C0201
C0603 C0603
2

2
CIS ok
2

ns
+V3P3A_SSD
2/16 change CONN
JSSD1
C C

1 2
GND_1 3.3V_2
3 4
GND_3 3.3V_4
5 6
9 PCIE9_SSD_RX_DN PERn3 Reserved_6
7 8
9 PCIE9_SSD_RX_DP PERp3 Reserved_8
9 10
GND_9 DAS/DSS# (O)(OD)
11 12
9 PCIE9_SSD_TX_DN_C 13
PETn3 3.3V_12
14
9 PCIE9_SSD_TX_DP_C PETp3 3.3V_14 +V3P3A_SSD
15 16
GND_15 3.3V_16
9 PCIE10_SSD_RX_DN
17 18 2019022:
PERn2 3.3V_18
19 20 'SSD_RST_R' rise/fall is not monotonous
9 PCIE10_SSD_RX_DP PERp2 Reserved_20 Add capacitance CS13 10PF/0402 at WIFI module side,
21 22

2
GND_21 Reserved_22 and add RS13 33ohm 0402
23 24
9 PCIE10_SSD_TX_DN_C 25
PETn2 Reserved_24
26
R2626
9 PCIE10_SSD_TX_DP_C 27
PETp2 Reserved_26
28 10K_J SSD_RST_R
GND_27 Reserved_28
29 30
9 PCIE11_SSD_RX_DN PERn1 Reserved_30 r0201 +V3P3A_SSD
PCIE12 RX 9 PCIE11_SSD_RX_DP
31
PERp1 Reserved_32
32

1
33 34 CS13

1
GND_33 Reserved_34
35 36 10PF/50V,NPO

2
follow intel 9 PCIE11_SSD_TX_DN_C
9 PCIE11_SSD_TX_DP_C
37
PETn1
PETp1
Reserved_36
DEVSLP (I)(0/3.3V)
38
SATA2_DEVSLP 9 R4207 C0402

2
39 40
PCIE12_SSD_RX_DP_R GND_39 Reserved_40 10K_J
B
CRB 9 PCIE12_SSD_RX_DP
9 PCIE12_SSD_RX_DN
R4200
R4201
1
1
2 SHORT_0402
2 SHORT_0402 PCIE12_SSD_RX_DN_R
41
43
PERn0/SATA-B+
PERp0/SATA-B-
Reserved_42
Reserved_44
42
44 r0201
B

45 46
GND_45 Reserved_46
Difference with armour 47 48

1
SSD interface SATA change to PCIE 9 PCIE12_SSD_TX_DN_C PETn0/SATA-A- Reserved_48 SSD_RST_R
49 50 RS13 1 2 33.0_J R0402
If install SATA CARD,R4200,R4201 need install 0.01uF 9 PCIE12_SSD_TX_DP_C 51
PETp0/SATA-A+ PERST# (I)(0/3.3V)
52 SSD_CLK_REQ_N_R R4206 1 2 SHORT_0402 PLT_RST_N 7,35,43,50,74
C0606,C0607 need install 0.01uF GND_51 CLKREQ# (IO)(0/3.3V) M.2_SSD_PE_WAKE_N R4205 2 SSD_CLK_REQ_N 7
53 54 1
7 PCIE_REFCLK_SSD_DN REFCLKN PEWake# (IO)(0/3.3V) ns R0402
PCIE_WAKE_PCH_N 7
55 56 0_J
7 PCIE_REFCLK_SSD_DP 57
REFCLKP Reserved_56
58
+V3P3SX GND_57 Reserved_58
Pin54
PICE module spec is N/C
2

SATA module spec is N/C

R10869 Key M
20K_F 67 68 PM_SUSCLK_SSD TP9980
NC32 SUSCLK(32kHz) (I)(0/3.3V)
69 70
R0402 PEDET (OC-PCIe) 3.3V_70
71 72 Pin68
GND_71 3.3V_72
73 74 PICE module spec is N/C
1

9 SSD_SATA_PCIE_DET_N GND_73 3.3V_74 SATA module spec is N/C

GND12

GND13
75
GND_75
2

Pin69
PICE module spec is 0 R10870
SATA module spec is 1 100K_F APCI0079-P002A

76

77
R0201 I

ns
1

A A

Bitland Information Technology Co.,Ltd.

Page Name
Co-lay PCIE12 RX,reserved R4202,R4203 +V3P3SX +V3P3SX 4,5,6,7,17,19,30,32,36,43,46,50,64,81 26
Size
please close to R4200,R4201 Custom
Project Name R ev
Veneno 1.3
Date: Thursday, August 22, 2019 Sheet 26 of 87
BPAGE DRAWING PROPERTY NOTE: this document contains information confidential and property to
INTERNAL ONLY Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
sky_y_mrd.+V3P3.26 documents or disclosed to others or used for any purpose other than that for which it
Wed Jun 03 11:22:52 2015 was obtained with the expressed written consent of Bitland

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D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
27
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 27 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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8 > 7 6 5 4 3 2 1

+V3.3AL R2828 1 2 0_J R0402

ns +V3.3S_FP
D
Q2826 D
DMP3160L-7
2 3

D
1
CF38

G
10uF/6.3V,X5R sot23-3
C0402

1
2

2
R11573
0_J
R0402

1
R2829 1 2 0_J R0402 FP_RST_R
50 FP_RST ns

2
C10987

1
R2886
0.1uF/10V,X5R 10K_J
C0201 R0201

1
C C

+V3.3S_FP

C2880

1
0.1uF/10V,X5R
C0201

2
J_FP1
B B
8 10
ns 1 R2812 2 SHORT_0402 USB2_P5_FP_CONN_DN USB2_P5_FP_CONN_DN 7
9 USB2_P8_FPR_DN USB2_P5_FP_CONN_DP 6
USB2_P5_FP_CONN_DP
9 USB2_P8_FPR_DP ns 1 R2811 2 SHORT_0402 5
4
50 DELINK 3

1
CR2826 CR2825 50 GPIO_AL0 FP_RST_R 2
1 9
50 GPIO_SCL_LED
ns ns cns8_0d5_r_51530
AZ5725-01F.R7GR 1uA 5V AZ5725-01F.R7GR 1uA 5V pitch=0.5mm_8pin
DFN1006p2x DFN1006p2x

2
A A

Bitland Information Technology Co.,Ltd.

Page Name
28
Size
Project Name R ev
Custom
Veneno 1.3
Date: Thursday, August 22, 2019 Sheet 28 of 87
BPAGE DRAWING PROPERTY NOTE: this document contains information confidential and property to
INTERNAL ONLY Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
sky_y_mrd.GND documents or disclosed to others or used for any purpose other than that for which it
Wed Jun 03 11:22:53 2015 was obtained with the expressed written consent of Bitland

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 1 2 3 4 5

Thermal Sensor EC_SMB1_CLK

+V3P3A
EC 50,52,76 EC_SMB1_CLK
50,52,76 EC_SMB1_DATA
EC_SMB1_DATA
+V3P3A_TH_SENSOR

SH2928 +V3P3A_TH_SENSOR
1 2
0_J R0402
+V3P3A_TH_SENSOR
A
+V3P3A_EC A
CHARGE SENSOR

2
C0201
SH9528 0.1UF/10V,X5R
1 2
C1126
CPU SENSOR
ns R0402 U2900
0_J

1
NCT7718W C1128

2
msop8_0d65_5d0
EC_SMB1_CLK 8 GND 1 2
R1502 1 C0201
SCLK VDD 2200PF/16V,X7R

3
7.5K_F
EC_SMB1_DATA 7 2 1 Q2900
R0201 SDATA D+
LMBT3904LT1G
R115991 2 0_J R0402 THERMAL_ALERT_U2900 6 3 SOT23-3

1
5,50 THERMAL_ALERT# ALERT D-

2
ns 5 4 R1503 2 1
GND THERM +V3P3A_TH_SENSOR
R2984 1 2 0_J R0402 R0402
50,60,64 EC_ALW_EN 10.5K_F
ns

ADDR: 1001_100xb
SHUTDOWN SYSTEM GND

+V3P3A_TH_SENSOR
B +V3P3A_TH_SENSOR B
EC_SMB1_DATA

GPU SENSOR
Environment SENSOR
5

Q8926

2
R2950
SMBDATA

ns 100K
R11514 5%
ns U8002
7.5K_F R0402_N
EC_SMB1_DATA 1 8
R0201 NI
EC_SMB1_CLK 1 3 R11515 2 I-DIS 1
SDA VCC
SMBCLK ALERT# +V3P3A_TH_SENSOR EC_SMB1_CLK 2 7

1
10.5K_F R0402 SCL A0

2
C0201
THERMAL_ALERT#_N 0.1UF/10V,X5R
GND

ns ns
+VS

3 6
+V3P3A_TH_SENSOR ALERT A1 C10028

1
G753T11U 4 5
GND A2
2

SOT23_5
I-DIS

TMP75AIDGKR
2

C0201 vssop8_3x3x1p1_0p65
0.1UF/10V,X5R NI
GND C10029

ADDR: 1001_000xb ADDR: 1001_010xb

1

I-DIS

C GND C

EC_ALW_EN

3
D
Q292
R2901 ns
2 1 1 L2N7002LT1G
20190507:Install all NTC for FVT debug 74 GPIO_19_CTF_R ns
r0201
2.2K_F I-DIS G S SOT23-3

2
I-DIS

2
+V3P3A_TH_SENSOR +V3P3A_TH_SENSOR +V3P3A_TH_SENSOR +V3P3A_TH_SENSOR R2900 C2907

1
ns
100K_F ns 0.1uF/10V,X5R
2

R0201 C0201

2
2

I-DIS I-DIS

1
R702 R11566

2
51.1K_F 51.1K_F R11518
R0402 R0402 51.1K_F GND GND
R0402 R11519
20190225:R703 Close to U2900 20190225:R11567 Close to Q2900
20190225:PRT8 Close to Q8926 51.1K_F 20190225:PRT9 Close to U8002
1

R0402
1

1
THERMAL_CHARGER 50 THERMAL_CPU 50 THERMAL_GPU
THERMAL_Environment Bitland Information Technology Co.,Ltd.
2

2
1

D CD36 CD37 D
1

2
R703 R11567 CD34

1
0.1uF/10V,X5R 0.1uF/10V,X5R PRT8 CD35 Page Name
NTC_47K
R0402
C0201 NTC_47K
R0402
C0201 NTC_47K
0.1uF/10V,X5R
C0201
PRT9
NTC_47K
0.1uF/10V,X5R 29
2

R0402 C0201 Size

2

R0402 Project Name Rev

2
B
Veneno
1

1 1.3
Date: Wednesday, August 21, 2019 Sheet 29 of 87
GND GND
GND GND PROPERTY NOTE: this document contains information confidential and property to
GND
GND Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 1 2 3 4 5

+V5P0S Q8928 +V5P0S_FAN

+V5P0S +V5P0S_FAN
WPM2301-3/TR
+V5P0S
2 3

D
40mil

2
1 R11524 2
R11522
ns

G
SHORT_0603
10K_J
C3001 3/7 R9847 connect to +V5P0S,change to +V3P3SX

21
1

1
A
C3000 +V3P3SX r0201 sot23-3 A
10uF/6.3V,X5R ns 0.1uF/10V,X5R +V3P3SX
C0603 C0201 10K_J
R11523
2

1
ns r0201

2
R3000
R3047 40mil
ns

1
10K_J 10K_J +V5P0S_FAN JFAN1

G2
TP3093
r0201 SLP_S0_SOC 7,50,63,64
r0201 TP3094

SH2
1
1

1
ns 2
50 FAN_SPEED1 2
3
3 5/10 change FAN CONN
C3002 EC_FAN_PWM1

1
4
50 EC_FAN_PWM1 4
0.01uF/10V,X5R

SH1
c0201

2
50208-00401-001
TP3095

G1
con_fpc4p_ph0p8_h1p7
I

1
C3062
1000pF/50V,X7R
C0402
FAN conn

2
ns

CIS ok
B B

+V5P0S +V5P0S 32,46,64

+V3P3SX +V3P3SX 4,5,6,7,17,19,26,32,36,43,46,50,64,81

+V5P0S

40mil 3/7 R9847 connect to +V5P0S,change to +V3P3SX

C3023
1

C3024 +V3P3SX
10uF/6.3V,X5R ns 0.1uF/10V,X5R +V3P3SX
C0603 C0201
2

+V5P0S_FAN
2

R3039
R3038 40mil
10K_J 10K_J TP3091 JFAN2

G2
r0201
r0201 TP3090

SH2
1
1
1

ns 2
50 FAN_SPEED2 2
3
3
C3025 EC_FAN_PWM2
1

C 4 C
50 EC_FAN_PWM2 4
0.01uF/10V,X5R
c0201 SH1
2

50208-00401-001
G1

con_fpc4p_ph0p8_h1p7
TP3092
I
1

C3063
1000pF/50V,X7R
C0402
2

ns

D D

Bitland Information Technology Co.,Ltd.

Page Name
30
Size Project Name Re v
Custom
Veneno 1.3
Date: Thursday, August 22, 2019 Sheet 30 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 Bitland Information Technology Co.,Ltd.
Page Name
31
Size
Project Name Rev
B
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 31 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

HDMI_TX2_CMC_DP
for EMI Co-lay
HDMI Connector HDMI_TX2_CMC_DN

HDMI_TX1_CMC_DP

C3201 1 2 0.1uF/10V,X5R C0201 HDMI_TX2_CMC_DP R3201 1 2 0_J R0402 HDMI_TX2_DP HDMI_TX1_CMC_DN

D 3 DDI1_TX0_DP
C3202 1 2 0.1uF/10V,X5R C0201 HDMI_TX2_CMC_DN R3202 1 2 0_J R0402 HDMI_TX2_DN HDMI_TX0_CMC_DP D
3 DDI1_TX0_DN
HDMI_TX0_CMC_DN
20180711:Follow V540S-WHL change list
Change HDMI from 15R to 0R HDMI_CLK_CMC_DP

HDMI_CLK_CMC_DN
C3203 1 2 0.1uF/10V,X5R C0201 HDMI_TX1_CMC_DP R3203 1 2 0_J R0402 HDMI_TX1_DP
3 DDI1_TX1_DP
C3204 1 2 0.1uF/10V,X5R C0201 HDMI_TX1_CMC_DN R3210 1 2 0_J R0402 HDMI_TX1_DN
3 DDI1_TX1_DN

2
R3208 R3209 R3204 R3205 R3211 R3212 R3206 R3207
470_J 470_J 470_J 470_J 470_J 470_J 470_J 470_J
+V3P3SX
R0201 R0201 R0201 R0201 R0201 R0201 R0201 R0201

HDMI_TX0_CMC_DP HDMI_TX0_DP HDMI_PLS_FET

1
C3205 1 2 0.1uF/10V,X5R C0201 R3213 1 2 0_J R0402
3 DDI1_TX2_DP
HDMI_TX0_CMC_DN HDMI_TX0_DN

2
C3206 1 2 0.1uF/10V,X5R C0201 R3214 1 2 0_J R0402
3 DDI1_TX2_DN R10043
10K_J

3
r0201
D Q3201
C C

1
L2N7002LT1G
HDMI_CLK_CMC_DP HDMI_CLK_DP 1
C3207 1 2 0.1uF/10V,X5R C0201 R3216 1 2 0_J R0402
3 DDI1_TX3_DP G S
C3208 1 2 0.1uF/10V,X5R C0201 HDMI_CLK_CMC_DN R3217 1 2 0_J R0402 HDMI_CLK_DN

2
3 DDI1_TX3_DN
SOT23-3

+V5P0S
+VHDMI
JHDMI1
G1
SHELL1
G2
HDMI_TX2_DP SHELL2

FUSE need to be 1.1A

1
D2+

2
2
HDMI_TX2_DN D2 Shield

2
3
R11520 HDMI_TX1_DP 4
D2-
F1 D1+
0_J 5
6V/1.1A HDMI_TX1_DN 6
D1 Shield
HDMI_TX1_DP
R0603 HDMI_TX0_DP D1-
HDMI_TX0_DN 7
D0+

1
HDMI_TX1_DN
HDMI_TX0_DP
HDMI_CLK_DN
ns HDMI_TX0_DN
8
D0 Shield
HDMI_TX2_DN 9
HDMI_CLK_DP
ESD3202 HDMI_CLK_DP 10
D0-
HDMI_TX2_DP fuse_1812
ESD3201 11
CK+

10
B HDMI_CLK_DN CK Shield B

9
7

6
10

12
9
7

HDMI_CEC_1 13
CK-

NC
NC

NC
NC
TP10144
NC
NC

NC
NC

CE Remote
14
HDMI_DDC_SCL 15
NC
+VHDMI HDMI_DDC_SDA 16
DDC CLK
1 I/O1 I/O3 4 DDC DATA
1 I/O1 I/O3 4 +VHDMI 17
2 I/O2 ns I/O4 5
2 I/O2 ns I/O4 5
18
GND
HDMI_HPD 19
+5V
HP DET
AZ1045-04F.R7G G3
SHELL3
1

1
lcc10_ns_2p5x1p0_p65h C3209 C3210 G4

GND

GND
0.45V_0.1A_RB500V-40_R1_10001 SHELL4
GND

GND

EMC_NI 1UF/10V,X5R 18PF/50V,NPO

C0402 C0402 30225-01902-001
sod323 AZ1045-04F.R7G

2
+V3P3A D3201 cn_hdmi-a_30225-00902-z01
8

lcc10_ns_2p5x1p0_p65h
I
EMC_NI
2

+V3P3A
RN_+VHDMI +V3P3SX yangzw change 20180502
Q3202B
2

L2N7002DW1T1G
2

R3219 C3211
R3218 R3221 R3222
1UF/10V,X5R

2
10K_J C0402
10K_J 1 6 10K_J 10K_J
S

R3220
2

r0201
r0201 r0201 r0201
1M_J
G
1

r0201
1

1
A A
DDI1_DDC_SCK SOT363 HDMI_DDC_SCL CR9053

G
1
3 DDI1_DDC_SCK 2 3 HDMI_HPD 1 2
1

CR3216 3 DDI1_HPD

D
S
AZ5825-01F 1uA 5V I

2
tvs_dfn1006p2x_0p5
Q3202A Q3203 R3223

1
L2N7002DW1T1G L2N7002LT1G C3212
AZ5825-01F 1uA 5V 1UF/10V,X5R 100K_F Bitland Information Technology Co.,Ltd.
SOT23-3
2

DDI1_DDC_SDA HDMI_DDC_SDA tvs_dfn1006p2x_0p5 C0402 R0201

4 3

2
S

3 DDI1_DDC_SDA Page Name

I
32
1

1
CR3217
G

Size
Project Name R ev
Custom
Veneno
5

SOT363 1.3
Date: Wednesday, August 21, 2019 Sheet 32 of 87
+V5P0S AZ5825-01F 1uA 5V PROPERTY NOTE: this document contains information confidential and property to
+V5P0S 30,46,64
2

tvs_dfn1006p2x_0p5 Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
+V3P3SX +V3P3SX 4,5,6,7,17,19,26,30,36,43,46,50,64,81 I documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
+V3P3A +V3P3A 3,4,5,7,9,11,17,19,24,29,35,36,43,49,50,51,57,60,61,63,64,65,66,68,69,74,81

8 7 6 5 4 3 2 1

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
33
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 33 of 87
PROPERTY NOTE: this document contains information confidential and property to
BPAGE DRAWING Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
INTERNAL ONLY documents or disclosed to others or used for any purpose other than that for which it
sky_y_mrd.+V1P0.33
was obtained with the expressed written consent of Bitland
Wed Jun 03 11:22:55 2015

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
34
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 34 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
Wed Jun 03 11:22:56 2015 was obtained with the expressed written consent of Bitland

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TPM 2.0

+V3P3A
+V3P3A_TPM

SH3528 1 2
SHORT_0402
+V3P3A_TPM

C3565 C3566 C3567

1
0.1uF/10V,X5R 0.1uF/10V,X5R ns 0.1uF/10V,X5R
+V3P3A_TPM C0201 C0201 C0201
2018/06/26 Reference 574047_ICL_U42_LP4_4X_SDS_HW_SCH_RN_0P8

2
I-TPM I-TPM NI
Change TPM power from +V3P3S to +V3P3A

U3506

2
R3500 R3501 1 3
NCI/VDD_1 NCI1
4
10K_J 10K_J NCI2
r0201 r0201 8 13
VDD_8 NCI3
ns 22
VDD_22 NCI4
10
NI I-TPM 14 31

1
NCI/VDD_14 NCI5

20 5
5 TPM_SPI_CS0_N CS# NCI6
11
R3502 1 I-TPM 2 33.0_J R0402 SPI0_MOSI_IO_0_TPM_R 21
NCI7
12
5,24,50 SPI0_MOSI MOSI NCI8
15
I-TPM R0402 SPI0_MISO_IO_1_TPM_R NCI9
R3503 1 2 33.0_J 24 25
5,24,50 SPI0_MISO MISO NCI10
26
PLT_RST_N_R NCI11
17 27
RST# NCI12
28
NCI13
18
SPI_TPM_INT_N PIRQ#
16
R3504 1 I-TPM 2 33.0_J R0402 SPI0_CLK_TPM_R 19
NCI_GND
5,24,50 SPI0_CLK SCLK
2
TP_SPI_GPIO 6
GND1
9
TP3500 GPIO GND2
1

C3568 23
GND3
1UF/6.3V,X5R NOBOM 29 32
C0402 NC1 GND4
30
NC2
2

ns TP_SPI_PP 7 33
+V3P3A_TPM TP3501 PP EPAD
NOBOM SPI VQFN32 ST33HTPH2E32AHC0 ST
vqfn32_5x5x0p9_0p5_ths3p6
2

I-TPM
+V3P3A_TPM R3594
2018/06/26
10K_J
ADD TPM_RST Circuit r0201

I-TPM
2

PLT_RST_N_R
1

R3595
10K_J
r0201 Q3526B
6

L2N7002DW1T1G
I-TPM D
1

2 G
S
Q3526A
1
3

L2N7002DW1T1G SOT363
D I-TPM

7,26,43,50,74 PLT_RST_N
5 G Bitland Information Technology Co.,Ltd.
S
Page Name
35
4

SOT363
I-TPM Size
Project Name Rev
B
Veneno 1.3
Date: Thursday, August 22, 2019 Sheet 35 of 87
PLT_RST_N R3596 1 2 0_J R0402 PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
ns documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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EDP DISPLAY 1920X1200 (12.2INCH) +V3P3SX 13" GND 7 13OR14_ID
37

14" NC
+V3P3_DISPLAY_CONN
+V3P3_DISPLAY

1 SH8201 2
SHORT_0603 EMPTY
+VBATA_BKLT_CONN 36

1
C3609 C3607 35
4.7uF/6.3V,X5R 4.7uF/6.3V,X5R TP10104 U3601 TP10105 34
C0402 C0402 TPS22929 C3641 1 R0402 2 33

1
C3601 C3600

2
SOT23-6 R11561 33.0_J 32
10uF/6.3V,X5R 1UF/6.3V,X5R 0.1uF/10V,X5R +V3P3_DISPLAY_CONN
6 1 31
VIN1 VOUT C0402 C0402 C0201
5 2 30

2
3/22 FB8200 0603 Bead change to JP8200 JUMP_43X79 4
GND2 GND1
3 29
VIN2 ON EDP_HPD
28
27
3 EDP_VDD_EN TP10106 26
R3611

2
25
100K_F 24
R0201 EDP_HPD 23
TP10103 +VBATA_BKLT_CONN 3 EDP_HPD
22
EDP_AUX_CONN_DP 21
EDP_AUX_CONN_DN
Difference with armour 20

1
U8201 WS4601E-5/TR 19
change to APL3512ABI-TRG EDP_TX0_CONN_DN 18
EDP_TX0_CONN_DP 17
C3602 C3640 16
ns ns EDP_TX1_CONN_DN
10uF/25V 10uF/25V 15
TP10107 TP10108 EDP_TX1_CONN_DP
C0603 C0603 14
13
12
3 EDP_BKLT_PWM EDP_BKLT_EN_R
R3609 1 2 11
+V3P3A +V3P3SX 3 EDP_BKLT_EN
1K_J R0201
10
20170927 Add R10109 for BL Control 9
R9917 1 2 0_J R0603 +V3P3SX_CAM 8
R11574 1 2 0_J R0603 7
ns 6
6,46 DMIC_DATA 5
EDP_BKLT_EN 6,46 DMIC_CLK 4
USB2_P7_CAM_DN_R 3
USB2_P7_CAM_DP_R

2
EDP_TX1_SOC_DP EDP_TX1_CONN_DP 2
2 1 0.1uF/10V,X5R Difference with armour
3 EDP_TX1_SOC_DP C0201 R8221 1 38
C8213 Add R8221 change to install USB 2.0 Camera
EDP_TX1_CONN_DN
100K_F

1
EDP_TX1_SOC_DN
2 1 0.1uF/10V,X5R C3692 C3662 C3663
3 EDP_TX1_SOC_DN R0201
C0201 C8214 1000pF/50V,X7R 33pF/50V,COG 33pF/50V,COG pitch=0.5mm_36pin
C0402 c0201 c0201 cns36_0d5_r_51540

2
EMC RESERVE JEDP1

EDP_TX0_SOC_DP EDP_TX0_CONN_DP
2 1 0.1uF/10V,X5R
3 EDP_TX0_SOC_DP C0201 C8215
EDP_TX0_SOC_DN EDP_TX0_CONN_DN 6.5V x [80.6/(220+80.6)] = 1.743V VGS= -4.5V
2 10.1uF/10V,X5R 1.743V - 6.5V = -4.757V
3 EDP_TX0_SOC_DN C0201 C8216
3/23 Add

+VSYS +VBATA_BKLT_CONN

1 RC458 2
330S
SHORT_0603 EMPTY
EDP_AUX_SOC_DP EDP_AUX_CONN_DP
2 1 0.1uF/10V,X5R

1
3 EDP_AUX_SOC_DP C8222 C8223

1
C0201 C8217 C8219 C8220 ns 33pF/50V,COG 0.1uF/25V,X5R
EDP_AUX_SOC_DN EDP_AUX_CONN_DN 1uF/25V,X5R 0.1uF/25V,X5R c0201 C0402
2 1 0.1uF/10V,X5R
3 EDP_AUX_SOC_DN C0603 C0402

2
C0201 C8218

2
ns

2 1 EDP_BKLT_EN_R
USB2_P7_CAM_DN_R 50 EC_LCDBLK_OFF
9 USB2_P7_CAM_DN
USB2_P7_CAM_DP_R D3611
9 USB2_P7_CAM_DP LBAT54XV2T1G
sod523

+VSYS +VSYS 59,60,61,63,67,69,71 Bitland Information Technology Co.,Ltd.

+V3P3SX +V3P3SX 4,5,6,7,17,19,26,30,32,43,46,50,64,81
Page Name
36
Size
Project Name R ev
Custom
Veneno 1.3
Date: Friday, August 23, 2019 Sheet 36 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

USB2.0

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
37
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 37 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

Sensors

D LID Sensor D

Working voltage 2.4/ 2.7/ 5.5

max current 2.5mA typ:3uA

+V3.3AL
C C

2
2
R8000
C8003
0.1uF/10V,X5R 100K_F
R0201

1
C0201 U8001

1
1
VDD
3
GND
LID_INT_N 2
50 LID_INT_N VOUT

APX8132Ha1
SOT23_3L_M
I

1
C10027
100pF/50V,NPO
C0201

2
B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
38
Size
Project Name R ev
Custom
Veneno 1.3
+V3.3AL +V3.3AL 11,28,49,50,58,60 Date: Thursday, August 22, 2019 Sheet 38 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 Bitland Information Technology Co.,Ltd.
Page Name
39
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 39 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
40
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 40 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland
Wed Jun 03 11:22:59 2015

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
41
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 41 of 87
BPAGE DRAWING
INTERNAL ONLY PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
sky_y_mrd.+V3P3.41
documents or disclosed to others or used for any purpose other than that for which it
Wed Jun 03 11:22:59 2015
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
42
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 42 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

WIFI & BT Module

+V3P3SX_CWS

D CNVI_RF_RESET_N
D

2
2/16 change CONN XTAL_CLKREQ
R11300

2
THIS DESIGN SUPPORTS STONE PEAK ONLY
R11299 75K_J
71.5K_F
CIS ok
R0402

2
1

1
C4320 C4321 C4323 ns

1
C4322 +V3P3SX_CWS
10uF/6.3V,X5R 4.7uF/6.3V,X5R 0.01uF/10V,X5R R0402
0.1uF/10V,X5R

1
C0402 C0402 c0201

1
JWLAN1
2

2
C0201 2018/06/26
1
GND_1 SLOT A KEY E
C6001 & C6003 FOR PIN 72 &73 3 2
9 USB2_P5_BT_DP USB_D+ 3.3V_2 TP10135 Change R11300 from NI to I
C6002 & C6000 FOR PIN 4 & 5 5 4
9 USB2_P5_BT_DN 7
USB_D- 3.3V_4
6
TP10136
9
GND_7 LED1_N
8
TP9992
6 CNVI_WGR_DATA1_DN SDIO_CLK PCM_CLK/I2S_SCK TP10124
11 10
6 CNVI_WGR_DATA1_DP SDIO_CMD PCM_SYNC/I2S_WS CNVI_RF_RESET_N 6
13 12
15
SDIO_DATA0 PCM_IN/I2S_SD_IN
14
TP10123
6 CNVI_WGR_DATA0_DN SDIO_DATA1 PCM_OUT/I2S_SD_OUT XTAL_CLKREQ 6
6 CNVI_WGR_DATA0_DP 17 16
19
SDIO_DATA2 LED2_N
18
TP9993
21
SDIO_DATA3 GND_18
20 WIFI/BT_SLOT_TX TP9976
6 CNVI_WGR_CLK_DN SDIO_WAKE_N UART_WAKE_N WIFI/BT_SLOT_RX
6 CNVI_WGR_CLK_DP 23 22 TP9977
SDIO_RESET_N UART_RX
C KEY E C
PLATFORM PIN OUT R4391 1 2 22.0_F r0201
CNVI_BRI_RSP 8
33 32
PCIE_WLAN_LN0_TX_SOC_DP C0201C4318 PCIE_WLAN_LN0_TX_DP GND_33 UART_TX CNVI_RGI_RSP_R CNVI_RGI_DT 8,17
1 2 0.1uF/10V,X5R 35 34 R4392 1 2 22.0_F CNVI_RGI_RSP 8
9 PCIE_WLAN_LN0_TX_SOC_DP PCIE_WLAN_LN0_TX_SOC_DN C0201C4319 PCIE_WLAN_LN0_TX_DN PETP0 UART_CTS r0201
1 2 0.1uF/10V,X5R 37 36
CNVI_BRI_DT 8,17
9 PCIE_WLAN_LN0_TX_SOC_DN 39
PETN0 UART_RTS
38
GND_39 RESERVED_38
41 40
9 PCIE_WLAN_LN0_RX_SOC_DP PERP0 RESERVED_40
43 42
9 PCIE_WLAN_LN0_RX_SOC_DN PERN0 RESERVED_42 NGFF1_CO_3
45 44 R3124 1 ns R0402 2 33.0_J
PCIE_REFCLK_WLAN_DP GND_45 COEX3 NGFF1_CO_2 WLAN_COEX3_WWAN 6
47 46 R3125 1 ns R0402 2 33.0_J WLAN_COEX2_WWAN 6
7 PCIE_REFCLK_WLAN_DP_R PCIE_REFCLK_WLAN_DN REFCLKP0 COEX2 NGFF1_CO_1
49 48 R3126 1 ns R0402 2 33.0_J WLAN_COEX1_WWAN 6
7 PCIE_REFCLK_WLAN_DN_R 51
REFCLKN0 COEX1
50 SUS_CLK_R
WLAN_CLK_REQ_N GND_51 SSCLK WLAN_RST_R R0402 SUS_CLK 7
7 WLAN_CLK_REQ_N
53 52 R4323 1 2 33.0_J
55
CLKREQ0_N PERST0_N
54
PLT_RST_N 7,26,35,43,50,74
7 PCIE_WAKE_PCH_N PEWAKE0_N RESERVED_W_DISABLE2_N BT_RF_KILL_N 3
57 56
59
GND_57 W_DISABLE1_N
58 SM_BAT_DATA_DEBUG WIFI_DISABLE_N 6
6 CNVI_WT_DATA1_DN RESERVED_2ND_PETP1 I2C_DATA SM_BAT_CLK_DEBUG TP10009
61 60
6 CNVI_WT_DATA1_DP RESERVED_2ND_PETN1 I2C_CLK TP10010
63 62

Debug Connector 6 CNVI_WT_DATA0_DN

6 CNVI_WT_DATA0_DP
65
67
GND_63
RESERVED_2ND_PERP1
RESERVED_2ND_PERN1
ALERT
RESERVED_64
UIM_SWP/PERST1_N
64
66
2018/06/26
CLKIN_XTAL_LCP 7
69 68
GND_69 UIM_PWR_SNK/CLREQ1_N
71 70
6 CNVI_WT_CLK_DN RESERVED/REFCLKN1 UIM_PWR_SRC/GPIO1/PEWAKE1_N Remove FB4305/C4310
+V3P3SX 73 72
B 6 CNVI_WT_CLK_DP RESERVED/REFCLKP1 3.3V_72 B
75 74
GND_75 3.3V_74

GND76

GND77

2
JDUG1

1
R11493 CW2
100K_F 10PF/50V,NPO
10
51750-0750P-005 C0402

76

77
TBD I R0201

2
7,26,35,43,50,74 PLT_RST_N 9 12
8
2019022:
G2 'WIFI_RST' rise/fall is not monotonous
5 LPC_CLK_PRT80

1
7
5,50 LPC_FRAME_N Add capacitance CW12 10PF/0402 at WIFI module side,
5,50 LPC_AD3 6 and add R4323 33ohm 0402
5,50 LPC_AD2 5
+V3P3SX_CWS
4 ns
5,50 LPC_AD1
5,50 LPC_AD0 3 WLAN PCIE AC CAPS +V3P3SX_CWS
2 +V3P3A
1
11 +V5P0A SH3101 1 2 0_J
+V3P3A

2
G1 R0603 +V3P3A R4321 R11620 R11621
DEBUG
cns10_0d5_r_51614 10K_J 10K_J ns 10K_J ns
40536W90-10PN-SHLOATCR SH9527 r0201 r0201 r0201
1 2 0_J
R0603

1
ns WLAN_CLK_REQ_N
2

NI
2

BT_RF_KILL_N
A R4315 WIFI_DISABLE_N A
R4319
100K_F
R0201 100K_F 20190625:
R0201 UC9
CNVI_DETEC_N ns Intel requiremnet，add 10K PU pl acehol der cl ose t o M
. 2 f or pi n54 and pi n56
6,81 WLAN_DET_N
CNVI EM5201BJ-45 For DS3
1

SOT23-6
1
2

ns 6 1 +V3P3SX +V3P3SX 4,5,6,7,17,19,26,30,32,36,46,50,64,81

ON GND
R4397
75K_J 5 2
3

VBIAS VIN Bitland Information Technology Co.,Ltd.

D Q4312
R0402 4 3
2N7002 VOUT NC Page Name
CNVI GND 3p3A CNVI_DETEC_N 1 SOT23-3 43
1

CNVI
PCIE HIGH 3P3S G S CNVI Size
ns Project Name R ev

1
ns C4360 Custom
Veneno
2

1UF/6.3V,X5R 1.3
C0201 Date: Wednesday, August 21, 2019 Sheet 43 of 87

2
50,61,64 EC_SLP_S3_N CNVI ns PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
44
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 44 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
45
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 45 of 87
BPAGE DRAWING PROPERTY NOTE: this document contains information confidential and property to
INTERNAL ONLY Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
sky_y_mrd.GND documents or disclosed to others or used for any purpose other than that for which it
Wed Jun 03 11:23:01 2015 was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

+V5P0S +V5P0A_AUDIO

1 R4691 2
SHORT_0603 EMPTY
+V3P3SX +V3P3SX_AUDIO +V5P0A_AUDIO +V5P0A

1 R4690 2
RA134

2
D SHORT_0402 2 1
10K_J R0402 I CA127 +1.8V_PRIM D
2.2UF/6.3V,X5R

1
20190427：Realt ek suggest ed change RA97 fr o m 0oh m t o 10 K C0402

2
RA97 1 SLEEVE
RING2 +V5P0S Q8935
10K_J R0402 NI

3
MIC2-VREFO-R 48 QM3010K
MIC2-VREFO-L 48 SOT23-3 D
+V3P3SX_AUDIO
RA98 HPOUT-L 48 RA16
2 1 HPOUT-R 48 2 1 1
RA121 r0201 R0201 G
6,17 HDA_SPKR
2 1 1K_J S
10K_J ns +1.8VS_AUDIO

2
1K_J R0201ns

2
RA15
RA118 PCBEEP_R
2 1 2 1 0.1uF/10V,X5R 100K_F

2
PCBEEP C0201 CA128 R0201
R0201 CA110
1K_J 1UF/6.3V,X5R
C0201

1
C10988

1
1
1UF/6.3V,X5R
RA120 UA1 C0201

31

30
36

35

27

26
29

28
34

32
33

25

2
10K_J ALC3287-CG

MIC2-R(PORT-F-R)/SLEEVE
LINE2-L(PORT-E-L)

LINE2-R(PORT-E-R)

MIC2-L(PORT-F-L)/RING2

HPOUT-L(PORT-I-L)

HPOUT-R(PORT-I-R)
PCBEEP

5VSTB

MIC2-CAP

MIC2-VREFO-L

CPVEE
MIC2-VREFO-R
r0201
C C
2
+V5P0S 20190427：Realt ek suggest ed add BA1

2 1 BA1
fb0603 120ohm/100MHz,2.5A 37 24 ns 1 RA119 2 SHORT_0402
AVSS1 CBN +1.8VS_AUDIO
2

CA138
CA111 1 2 2.2UF/6.3V,X5R 38 23 CA120 1 2 1UF/10V,X5R

1
2.2UF/6.3V,X5R C0402 VREF CBP
C0402 C0402 CA121 CA122
1

CA112 1 2 2.2UF/6.3V,X5R 39 22
C0402 LDO1-CAP AVSS2 2.2UF/6.3V,X5R 0.1uF/10V,X5R

2
C0201
2 1 0.1uF/10V,X5R 40 21 CA119 1 2 2.2UF/6.3V,X5R C0402
+V5P0A_AUDIO Analog AVDD1 LDO2-CAP +V3P3SX_AUDIO
C0201 CA113 C0402
Digital 41 20
PVDD1 CPVDD/AVDD2 Analog +1.8V_PRIM
47 SPK_LP
42
SPK-OUT-L+ LDO3-CAP
19 CA118 1 2 2.2UF/6.3V,X5R Digital
C0402
1

47 SPK_LN
43 18 RA129 1 2 0_J
CA114 SPK-OUT-L- DVDD-IO R0402
0.1uF/10V,X5R
44 17 RA132 1 2 0_J
2

C0201
47 SPK_RN SPK-OUT-R- AUDIOLINK:SDATA-OUT STRAP_HDA_SDO 6 ns R0402

2
B HAD_SDI0_R 1 RA101 B
47 SPK_RP
45 16 2 22.0_F HDA_SDI0 6
SPK-OUT-R+ AUDIOLINK:SDATA-IN r0201 CA116 CA117
46 15
0.1uF/10V,X5R 2.2UF/6.3V,X5R

1
PVDD2 AUDIOLINK:SYNC HDA_SYNC 6 C0201 C0402

47 14
MIC2/FROUT-JD(JD2) AUDIOLINK:BCLK HDA_BCLK_R 6
48 13
HPOUT-JD HP/LINE2-JD(JD1) DC-DET/EAPD EAPD

1
49
PVSS
GPIO2/DMIC-DATA34

GPIO0/DMIC-DATA12
TP10145

GPIO1/DMIC-CLK
20MIL

I2C-DATA

I2C-CLK
DVDD
PDB

NC1

NC2

NC3

NC4

NC5
qfn48_6x6x1_0p4_ths4p35
1

10

11

12
+V3P3SX_AUDIO +1.8VS_AUDIO I

I2C master interface

A RA131 1 2 0_J A
ns R0402
DMIC_DATA_CODEC

DMIC_CLK_CODEC

RA130 1 2 0_J
1

R0402
EMC request
CA115
0.1uF/10V,X5R CA137
2

C0201
2 1
Bitland Information Technology Co.,Ltd.
50 EC_MUTE# 2.2UF/6.3V,X5R
Page Name
C0402 46
2

R11467
Size
R1 R0402
1 2 0_J R0603 Project Name R ev
R3695 1 33.0_J Custom
10K_J 6,36 DMIC_DATA ns
2
Veneno 1.3
R3696 1 R0402 2 33.0_J Date: Wednesday, August 21, 2019 Sheet 46 of 87
r0201 6,36 DMIC_CLK ns
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
1

Analog_Ground Digital_Ground
ns documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

Speaker

D
D

SPK_LP SPK_LP_CONN
46 SPK_LP
CIS ok

1
C7033

1
CA4
2200pF/25V,X7R
C0402 JSPK
AZ5725-01F.R7GR 1uA 5V

2
DFN1006p2x 1
1

2
2
2
ns
G1
PAD1
G2
PAD2
C C

Internal Speaker connector

SPK_LN SPK_LN_CONN 11255W90-2P-S-5A-HF-R
46 SPK_LN wtb_2p_1p25_90_BAT

Placement near Audio Codec

1
I
C7035

1
CA6
2200pF/25V,X7R
C0402

SPK L+ L- R+ R- t race wi dth

AZ5725-01F.R7GR 1uA 5V

2
DFN1006p2x

2
ns Speaker 4 ohm ==> 40 mils
Speaker 8 ohm ==> 20 mils
SPK_RP SPK_RP_CONN
46 SPK_RP JSPK1

1
C7032
1
1
1

C4707 2
2
2200pF/25V,X7R
C0402 AZ5725-01F.R7GR 1uA 5V G1
B PAD1 B
2

DFN1006p2x G2
PAD2

2
ns
11255W90-2P-S-5A-HF-R
wtb_2p_1p25_90_BAT
I
SPK_RN SPK_RN_CONN
46 SPK_RN

1 C7034
1

C4709 6/21 JSPK1 footprint CON_FPC4P_PH0P8_H1P7

2200pF/25V,X7R change to con_wtb_4p_ph0p8_h1p7_50208
C0402
AZ5725-01F.R7GR 1uA 5V
2

DFN1006p2x
2

ns
20190927 Install CA3,CA4,CA5,CA6 2200PF

A A

Bitland Information Technology Co.,Ltd.

Page Name
47
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 47 of 87
PROPERTY NOTE: this document contains information confidential and property to
BPAGE DRAWING Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
INTERNAL ONLY documents or disclosed to others or used for any purpose other than that for which it
sky_y_mrd.GND
was obtained with the expressed written consent of Bitland
Wed Jun 03 11:23:02 2015

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Vinafix.com
 HEADSET JACK (Supports CTIA and OMTP headsets)
Important:
To ensure reliable headset detection for all
fast/slow plug-in scenarios use a jack with
the detect switch all the way at the end so
that the switch is tripped only when the jack
is plugged all the way in.

46 MIC2-VREFO-L

46 MIC2-VREFO-R

2
RA100
RA102
2.2K_F
2.2K_F
r0201
r0201

1
CA26
J_PHONEJACK_14
100pF/50V,NPO
C0201
ns

2
1
SLEEVE MIC~GND

RA103 1 2 68.0_J R0402 HPOUT_R_CONN 3

46 HPOUT-R R

RA104 1 2 68.0_J R0402 HPOUT_L_CONN 4

46 HPOUT-L L

1
CA24 CA25
100pF/50V,NPO 100pF/50V,NPO
C0201 C0201

2
HPOUT-JD_CONN 5
L_1
6
DET
2
RING2 GND~MIC

+1.8VS_AUDIO +V3P3SX_AUDIO

1
91PJ3-0396-30000H
RA108 jack_phone_6p_91pj3-0401-30000h
I
0_J
R4811 1 2
2

ns
SHORT_0402
R11590 R7055

2
ns R0402
100K_F 100K_F
R0201 R0201
1

RA106
R0402 200K_F
2 1
HPOUT-JD_CONN
HPOUT-JD

HPOUT-JD_CONN

HPOUT_R_CONN

HPOUT_L_CONN

SLEEVE

RING2
1

1
TVS5 TVS6 TVS7 TVS8 TVS9

AZ5725-01F.R7GR AZ5725-01F.R7GR AZ5725-01F.R7GR AZ5725-01F.R7GR AZ5725-01F.R7GR

DFN1006p2x DFN1006p2x DFN1006p2x DFN1006p2x DFN1006p2x
2

2
I I I I I

Bitland Information Technology Co.,Ltd.

Page Name
48

Vinafix.com
Size Project Name Re v
C
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 48 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

Vinafix.com
 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

+V5CP
+V3P3A

2
R3904

2
C3900

2
CC452 100K_F
R3903 R0201
22uF/6.3V,X5R 0.1uF/10V,X5R R3902
C0603 C0201 178K_F
D 20K_F

2
R0402

1
D
R0402

1
USB_P1_WP_OC_N 9

1
17
16
15
14
13
U3900 +V5P0A_USB_WP2

ILIM_HI

FAULT
PwPd

ILIM_LO
GND
1 12
IN OUT USB2_P1_DN_CONN +V3.3AL
2 11
9 USB2_P1_DN 3
DM_OUT DM_IN
10 USB2_P1_DP_CONN +V5CP
9 USB2_P1_DP DP_OUT DP_IN +V5P0A_USB_WP2
4 9
+V3.3AL ILIM_SEL STATE#

2
R3958

CTL1
CTL2
CTL3
2

2
EN
100K_F
+V3P3A R3900 R0201 C4963 C4962
TPS2546RTER
0.1uF/10V,X5R 0.1uF/10V,X5R

5
6
7
8
100K_F I

1
R0201 TPS2546_STATUS_N 50

1
C0201 C0201
2

TPS2546_CTL3 50

1
50 EC_AOU_LIMITED
R4963 TPS2546_CTL2 50

2
C C
100K_F R3901 TPS2546_CTL1 50
R0201
USB_P2_WP_OC_N 0_J
EC_USB1_PWR_EN 50
1

R0402 JCONN1_IO
+V5CP PCB Footprint
ns pitch=0.5mm_36pin

1
36 38
+V5P0A_USB_WP2
35
34
R11540 1 2 0_J R0402 I 33
32
L6303 31
2 1 USB3_P1_RX_DN_R 30
9 USB3_P1_RX_DN USB3_P1_RX_DP_R
9 USB3_P1_RX_DP
3 ns 4 l_4p_1012_choke 29
28
90ohm,160mA 27
26
25
R0402 I
USB3_P1_RX_DN_R 24
R11541 1 2 0_J USB3_P1_RX_DP_R 23
22
B USB3_P1_TX_DN_R 21
B
USB3_P1_TX_DP_R 20
USB2_P1_DN_CONN 19
R11542 1 2 0_J R0402 I USB2_P1_DP_CONN 18
17
L6304 16
2 1 USB3_P1_TX_DN_R
9 USB3_P1_TX_DN USB3_P1_TX_DP_R USB3_P2_RX_DN_R 15
9 USB3_P1_TX_DP
3 ns 4 l_4p_1012_choke
USB3_P2_RX_DP_R 14
13
90ohm,160mA
USB3_P2_TX_DN_R 12
USB3_P2_TX_DP_R 11
10
R0402 I 9 USB2_P2_DN
R11543 1 2 0_J 9
9 USB2_P2_DP 8
50 EC_BTN_GREEN_LED_N
7
50 EC_BTN_WHITE_LED_N 6
R0402 I
50 PWR_SWIN#
R11544 1 2 0_J +V3P3A 5
9 USB_P2_WP_OC_N 4
50,53 EC_LIMITED_CTL
L6305 3
2 1 USB3_P2_RX_DN_R 50 EC_USB2_PWR_EN 2
9 USB3_P2_RX_DN USB3_P2_RX_DP_R
9 USB3_P2_RX_DP
3 ns 4 l_4p_1012_choke 1 37

90ohm,160mA

A A
R11545 1 2 0_J R0402 I

R11546 1 2 0_J R0402 I

L6306
2 1 USB3_P2_TX_DN_R
9 USB3_P2_TX_DN USB3_P2_TX_DP_R +V3P3A_EC Bitland Information Technology Co.,Ltd.
9 USB3_P2_TX_DP
3 ns 4 l_4p_1012_choke

Page Name
90ohm,160mA 49

2
R0109 Size
Project Name R ev
Custom
R11547 1 2 0_J R0402 I ns
10K_J Veneno 1.3
r0201 Date: Wednesday, August 21, 2019 Sheet 49 of 87
20190218:RF requirement,reserve COMMON CHOCK for IO board USB3.0 signals PROPERTY NOTE: this document contains information confidential and property to

1
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
PWR_SWIN# documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

CAPS_LED# +V3P3A_EC
+V3P3A_EC AVCC +V3P3A_EC_VSTBY +V3P3A_EC +V3P3A_EC
+V3.3AL +V3P3A_EC R5024 1 2 SHORT_0402
AC_PRESENT 7
+V3P3A SPI_3.3V ns
Adapter ID DIS ID

2
SYS_PWROK 7

1
1 SH5002 2 FB5000 1 2
V1.0_PWROK 63

2
fb0402 R5055 R5013
SHORT_0603 EMPTY SRTCRST_EC 7 2019/04/11 change to 10K ohm
120ohm/100MHz,-400MA C5012 ALLSYSPWRGD 66 820.0_J 10K_J
R5082 1 2 To Vcore VR R0402
0.1uF/10V,X5R

2
C5000 EC_LCDBLK_OFF 36 R0402 DGPU_ID

1
SHORT_0402 DIS_ID
1000pF/50V,X7R C5001 C0201 EC_SLP_S4_N 61

1
2

2
C0402 0.1uF/10V,X5R EC_AOU_LIMITED 49

2
ADAPTER_ID0 50,58 VERSION_ID0 50

2
C0201
EC_USB1_PWR_EN 49 C5005 C5004 C5007 ns C5008 ns C5070
FB5001 1 2 C5003 PM_CLKRUN_N 5 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R 20180716

1
fb0402 0.1uF/10V,X5R 20180716 Adapter detect ID

1
C0201 C0201 C0201 C0201 C0201

1
120ohm/100MHz,-400MA C0201 DEL GC6_FB_EN_3.3 SINGAL
SPI_3.3V R5056 R5020
EC_AGND
ns 10K_J 10K_J
+V3P3A_EC AVCC R0402
R0402
DIS_ID DGPU_ID
VCC_LPC

2
VCC_LPC
D D
U5500

114
121

106

127

19
20

93
11

26
50
92

84
83
82
74

99
98
97
96
R5054 1 2

3
+V3P3A ns IT5576E-128
SHORT_0402 10 87
EC_SMB0_CLK 58,59
Battery/Charger

VSTBY

SMCLK4/L80HLAT/BAO/GPE0
VCC

EGCLK/GPE3
EGCS#/GPE2

SMDAT4/L80LLAT/GPE7

CLKRUN#/ID0/GPH0
EGAD/GPE1
VSTBY1
VSTBY2
VSTBY3
VSTBY4
VSTBY5

AVCC

ID6/GPH6
ID5/GPH5
ID4/GPH4
ID3/GPH3
GPH7
VSTBY_FSPI
5,43 LPC_AD0 9
EIO0/LAD0/GPM0(3) SMCLK0/GPF2
88

2
+1.8V_PRIM R11495 1 2 0_J 5,43 LPC_AD1 EIO1/LAD1/GPM1(3) SMDAT0/GPF3 EC_SMB0_DATA 58,59 +V3P3A_EC +V3P3A
R0402 ns C5002 5,43 LPC_AD2
8
7
EIO2/LAD2/GPM2(3) SM BUS SMCLK1/GPC1
115
116
EC_SMB1_CLK 29,52,76
GPU/Thermal/TYPE C
0.1uF/10V,X5R 5,43 LPC_AD3 PLT_ESPI_RST_N EIO3/LAD3/GPM3(3) SMDAT1/GPC2 EC_SMB1_DATA 29,52,76
1 R5071 1 2 22 117
C0201 7,26,35,43,74 PLT_RST_N 13
ERST#/LPCRST#/GPD2 PECI/SMCLK2/GPF6(3)
118
PECI_EC 3
SHORT_0402 5 LPC_CLK_EC ESCK/LPCCLK/GPM4(3) SMDAT2/PECIRQT#/GPF7(3) FP_RST 28 FPR

2
R5072 1 2 0_J 6
5 ESPI_RST 5,43 LPC_FRAME_N ECS#/LFRAME#/GPM5(3)
R0402 ns R11623 R11622
ns
0_J 0_J
ME_Flash_EN_R ME_FLASH R0402 R0402
+V3P3A R11510 1 2 126
+V3P3A_EC SHORT_0402 GA20/GPB5(3)
5 LPC_SERIRQ
5
ALERT#/SERIRQ/GPM6(3) GPIO PS2CLK0/CEC/TMB0/GPF0
85
DDR_PWRGD 61

1
To GPU 76 GPIO5_AC_DETECT
15
23
PLTRST#/ECSMI#/GPD4(3) LPC PS2DAT0/TMB1/GPF1
86
89
EC_PROCHOT VRAM_PWRGD 69
2

3 SMC_RUNTIME_SCI_N EC_WRST_N ECSCI#/GPD3 PS2CLK2/GPF4

R11509 EC_WRST_N
14
WRST# PS/2 PS2DAT2/GPF5
90
PM_PWRBTN_R_N 7

2
4
100K_F 5 EC_KBRST# KBRST#/GPB6(3)
R0201 R5028 R5027 R5081 R5080
2
2

IT5576
24
EC_BTN_GREEN_LED_N 49 4.7K_J 4.7K_J 4.7K_J 4.7K_J
CR5001 PWM0/GPA0
25
PWR BUTTON LED
1

R5010 LBAT54XV2T1G PWM1/GPA1 EC_BTN_WHITE_LED_N 49 PWR BUTTON LED R0402 R0402 R0402 R0402
ns 28 EC_SMB0_CLK
PWM2/GPA2 EC_FAN_PWM2 30

1
100K_F 1 R5088 2 SHORT_0402 GPC0 113 29 EC_SMB0_DATA

LQFP
R0201 sod523 THERMAL_SENSOR FPR 28 GPIO_SCL_LED ns CRX0/GPC0 PWM3/GPA3 EC_CHAR_WHITE_LED_N EC_FAN_PWM1 30
123
CIR 30
1

49 TPS2546_STATUS_N CTX0/TMA0/GPB2(3) SMCLK5/PWM4/GPA4 EC_CHAR_AMBER_LED_N PWR CHARGER LED EC_SMB1_CLK

ns SMDAT5/PWM5/GPA5
31
PWR CHARGER LED EC_SMB1_DATA
1

EC_WRST_N

PWM
2

80
R11508 60,65 +V3.3A_PWRGD DAC4/DCD0#/GPJ4(3)
2

C5010 119 47 EC_SLP_S3_N

100K_F 60 CP_PWR_EN DSR0#/GPG6 TACH0A/GPD6(3) FAN_SPEED1 30
1UF/6.3V,X5R 33 48 EC_SLP_S4_N
7 PM_BATLOW_N GINT/CTS0#/GPD5 TACH1A/TMA1/GPD7(3) FAN_SPEED2 30
C0201 R0201 SYS_PWROK
1

81 120 EC_USB2_PWR_EN
ns 49 TPS2546_CTL2 DAC5/RIG0#/GPJ5(3) TMRI0/GPC4(3) TPS2546_CTL3 49
124 R11553 1 2 0_J R0201 EC_LIMITED_CTL
1

EC_UART_DEBUG TMRI1/GPC6(3) SLP_S5_SOC 7 HDA_SPKR

TP5028
17 R11554 1 2 0_J R0201
BOMACO_EN 3,6,81
16
TXD/SOUT0/LPCPD#/GPE6
R11579 1 ns 2 0_J R0402
FPR 28 DELINK RXD/SIN0/PWUREQ#/BBO/SMCLK2ALT/GPC7(3) ns AD+_EN 59
ADAPTER_ID0_R

2
+V3P3A_EC R5049 1 2 R0402 1K_F 71 107
50,58 ADAPTER_ID0 ADC5/DCD1#/GPI5(3) GPE4 ALW_EN EC_SLP_S3_N 43,61,64
2 SHORT_0402
THERMAL_GPU
72
73
ADC6/DSR1#/GPI6(3) UART port WAKE UP RI1#/GPD0(3)
18
21
1 R5048
EC_ALW_EN 29,60,64 5VA&3VA enable R11601 R5051 R5050 R5083 R5094 R5079
+V3P3A THERMAL_Environment ADC7/CTS1#/GPI7(3) RI2#/GPD1 EC_USB2_PWR_EN 49 100K_F
RG6921 1 ns 2 0_J R0402 NI 35 100K_F 100K_F 100K_F 100K_F 100K_F
76 GPU_ALERT# RTS1#/GPE5 R11600 1 2 0_J R0402 R0201 R0201 R0201 R0201 R0201 R0201
C DIS ID 50 VERSION_ID0 34 HDA_SPKR 6,17 BIOS_SELF_HEALING ns ns C
PCBEEP PWM7/RIG1#/GPA7
122 112
49,53 EC_LIMITED_CTL DTR1#/SBUSY/GPG1/ID7 RING#/PWRFAIL#/CK32KOUT/LPCRST#/GPB7 THERMAL_ALERT# 5,29

1
2

95 110
R11487 R11632 49 TPS2546_CTL1 CTX1/SOUT1/GPH2/SMDAT3/ID2 PWRSW/GPB3 LID_INT_N_TP PWR_SWIN# 49 Power on
2

94 111
need confirm requirement 52 GPIO4_EC_INT CRX1/SIN1/SMCLK3/GPH1/ID1 GPB4 LID_INT_N_TP 50
10K_J 10K_Jns 109
R5097 2 SHORT_0402
FLASH_SPI_CLK_EC GPB1 LID_INT_N 38 MB:LID
r0201 r0201 5,24,35 SPI0_CLK R5003 1 105 108
100K_F 2 SHORT_0402
FLASH_SPI_CS0_N_EC FSCK GPB0 CHG_AC_PRES 59
R5004 1 101
R0201 PD_PWR_EN 5,24 FLASH_SPI_CS0_N FLASH_SPI_MOSI_EC FSCE#
2 SHORT_0402
SMC_RUNTIME_SCI_N 5,24,35 SPI0_MOSI R5002 1 102
FMOSI EXTERNAL SERIAL FLASH THERMAL_CPU_R
1

FLASH_SPI_MISO_EC
EC_GPG2 R5099 1 2 SHORT_0402 103 66 R11568 2 1 SHORT_0201 Amber
5,24,35 SPI0_MISO FMISO ADC0/GPI0(3) THERMAL_CPU 29 EC_CHAR_AMBER_LED_N
1

KSO16 R11626 1 2 0_J R0201

PD_PWR_EN_R
67 LED3A 2 1 1 2 120_F
R11627 1 ns 2 0_J R0201 56
ADC1/GPI1(3)
68
GPIO_AL0 28 FPR
R5053 r0402
52,60 PD_PWR_EN BKL_KB_DETECT KSO16/SMOSI/GPC3(3) ADC2/GPI2(3) BATT_ID# 58,59 GPIO_AL0 LED_0603
KSO17 R11617 1 2 0_J R0201
EC_BKLTEN
57 69
CHARGER_SENSOR Amber
+1.8V_PRIM +V3P3A +V3P3A_EC ns KSO17/SMISO/GPC5(3) ADC3/GPI3(3) ADP_I 59
32
PWM6/SSCK/GPA6 ADC4/GPI4(3)
70 R11565 1 2 SHORT_0201
THERMAL_CHARGER 29 Charger LED
EC_GPG2

2
NUM_LED#
100
SPI ENABLE A/D D/A 20190223:changed GPI4 net name from 'BAT_I' to 'THERMAL_CHARGER' C5020 EC_CHAR_WHITE_LED_N
SSCE0#/GPG2
2

125 1 1UF/6.3V,X5R LED1W 2 1 1 2 1.24K_F

2

R5032 SSCE1#/GPG0 TP10158 20MIL R0402

R11589 R5091 76
EC_MUTE# 46 C0201 R5078
TACH2A/GPJ0(3)

1
10K_J KSO0 36 77 White LED_0603
10K_J 10K_Jns KSO0/PD0 TACH2B/GPJ1(3) SLP_S3_SOC 7,63
KSO1 37 78
r0201 KSO1/PD1 DAC2/TACH0B/GPJ2(3) RSMRST_N 7 ns
r0201 r0201 KSO2 38 79
KSO2/PD2 DAC3/TACH1B/GPJ3(3) IMVP_PCH_PWRGD 7
KSO3 39
+V3P3A_EC
KSO3/PD3
1

KSO4 40
1

ME_Flash_EN_R KSO4/PD4
1 2 KSO5 41
ME_Flash_EN KSO5/PD5 R5011 PLT_RST_N
KSO6 42
KBMX 10K_J 2 1
CR5045 KSO7 43
KSO6/PD6 ns
2

KSO7/PD7 R5012 r0201 LPC_FRAME_N

LBAT54XV2T1G R5031 KSO8 44 10K_J 2 1
sod523 KSO9 45
KSO8/ACK# ns
10K_J KSO9/BUSY r0201
KSO10 46 1
KSO10/PE TP10156 20MIL
r0201 KSO11 51 2
KSO11/ERR# GPJ7 SLP_S4_SOC 7
ns KSO12 +V3P3A +V3P3A +V3P3A_EC +V3P3A_EC +V3P3A_EC
52
KSO12/SLCT CLOCK GPJ6
128
SLP_S0_SOC 7,30,63,64

KSI3/SLIN#
KSO13

KSI1/AFD#
KSI2/INIT#
KSI0/STB#
53 1
1

3,59,66 PROCHOT_N KSO13 TP10157 20MIL

KSO14

VCORE
54

AVSS
KSO14

VSS1

VSS2
VSS3
VSS4
VSS5
KSO15

KSI4
KSI5
KSI6
KSI7
55
3

2
KSO15
D R5000 R5087
I R5034 R5086 R5093
Q5500 10K_J 10K_J

58
59
60
61
62
63
64
65

27
49
91
104

75

12
EC_PROCHOT
L2N7002LT1G 1 100K_F 100K_F 100K_F
R0201 r0201 R0201 R0201 r0201
Sot23-3 G
S
ns
GPU_ALERT# PM_PWRBTN_R_N CHG_AC_PRES PWR_SWIN# EC_ALW_EN

1
2

2
KSI0
KSI1
KSI2
KSI3
KSI4
KSI5

KSI7
KSI6
R5017
2

C5011
10K_J 0.1uF/10V,X5R

1
B r0201 C0201 B
1

EC_AGND
TP5030
TP5031

GND

CNS32_0D8_R_51510_1 +V3P3SX_PAD
51612-TRP
KSI7 +V3P3SX +V3P3SX_PAD
Touch Pad
1
KSO1
2
NUM_LED# 3

2
4
KSO17
5 33 SH5003 1 2 SHORT_0402
KSO16 R5030 R5029 R5044
6 34
KSI1 PIN 27,28,29 for 15" KB JKBBL1 +V3P3A +V3P3SX_PAD
KSI7 7 4.7K_J 4.7K_J 4.7K_J
51653
8

2
KSI6 cns4_1d0_r_51653 R0402 R0402 R0402
9 +V3P3SX_PAD

1
KSO9 TOUCH_PAD_CLK0 C5094 C5006

2
10
KSI4 6 4 1 R11517 2 R11618 R5009 0.1uF/10V,X5R 4.7uF/6.3V,X5R
11 ns BKL_KB_DETECT TOUCH_PAD_DAT0

1
KSI5 3 SHORT_0603 1 2
I C0201
C0402
12 10K_J J_TP

2
KSO0 2 R0402 1K_F TOUCH_PAD_INT
13 51530-00801-001
KSI2 5 1 r0201
cn_fpc_51530-00801_0p5_1-8
KB connector
14
KSI3
15
KSO5 10

1
16
KSO1 TOUCH_PAD_CLK0 ns 8 G2
17
KSI0 7
18 8 TOUCH_PAD_CLK0 TOUCH_PAD_DAT0
KSO2 6
19 8 TOUCH_PAD_DAT0
3

KSO4 5
KSO7 20 D R11619
Q8924 4
21
KSO8 EC_BKLTEN KBBLK_EN BSS138 10K_J TOUCH_PAD_INT
3
22
KSO6 2 R599 1 1 SOT23-3 2
23 r0201 8 TOUCH_PAD_INT LID_INT_N_TP
KSO3 SHORT_0402 G S 1
24 50 LID_INT_N_TP
KSO12 9
25
2

1
2

KSO13 G1
26
KSO14 R723
27
KSO11 100K_J

AZ5725-01F.R7GR 1uA 5V
28

AZ5725-01F.R7GR 1uA 5V
KSO10

100pF/50V,NPO
R0402

100pF/50V,NPO
+V3P3A 29
A KSO15 A

1
CAPS_LED# 30 CR5028 CR5027 CR5029

1
C5062

1
31 C5063
1

1 2 330.0_J
32
GND ns ns
R5007 R0402 ns ns C0402 ns
C0402

2
J_KB

2
AZ5725-01F.R7GR 1uA 5V
GND GND DFN1006p2x DFN1006p2x DFN1006p2x
5/19 reserve V3P3A

2
Bitland Information Technology Co.,Ltd.

Page Name
50
Size
Project Name Re v
+V3.3AL +V3.3AL 11,28,38,49,58,60 Custom
+V3P3A
Veneno 1.3
+V3P3A 3,4,5,7,9,11,17,19,24,29,32,35,36,43,49,51,57,60,61,63,64,65,66,68,69,74,81
Date: Friday, August 23, 2019 Sheet 50 of 87
+V5P0A +V5P0A 43,46,61,63,64,66,67,68,69,70 PROPERTY NOTE: this document contains information confidential and property to
+V3P3SX +V3P3SX 4,5,6,7,17,19,26,30,32,36,43,46,64,81 Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
1V8_AON 1V8_AON 69,70,74,76,79 was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com

Vinafix.com
 5 4 3 2 1

SOC_SML1_DATA
5 SOC_SML1_DATA
SOC_SML1_CLK
SOC_SML1_CLK
D D
1.8V TO 3.3V OPEN DRAIN NO USED
3 DDI2_TX0_DP CA73 1 2 0_J R0201 ML0P VDD_DM_D
VDD_DM_D
3 DDI2_TX0_DN CA74 1 2 0_J R0201 ML0n

VDD_DM_D

VDD_DM_D
CA75 1 2 0_J R0201 ML1p

VDD_R2
VDD_R1
3 DDI2_TX1_DP

RX2p
RX2n

RX1n
RX1p
3 DDI2_TX1_DN CA76 1 2 0_J R0201 ML1n

3 DDI2_TX2_DP CA77 1 2 0_J R0201 ML2p

U1DP

10
9
8

5
4
3
2
7
6

1
3 DDI2_TX2_DN CA78 1 2 0_J R0201 ML2n TX1p_C
TX1p CA88 1 20.22uF/6.3V,X5R C0201

VDD_DM2
RX2p
RX2n

RX1n
RX1p
VDD_R2
VDD_R1
RSV
TEST

VDD_DM1
C1_TX1_P 53

CA79 1 2 0_J ML3P TX1n CA89 1 20.22uF/6.3V,X5R C0201

TX1n_C
R0201 VDD33 VDD33
3 DDI2_TX3_DP C1_TX1_N 53
53
3 DDI2_TX3_DN CA80 1 2 0_J R0201 ML3n EPAD TX2p_C
SSRXn 11 52 TX2p CA90 1 20.22uF/6.3V,X5R C0201
SSRXn VDD33_1 SOC_SML1_DATA C1_TX2_P 53
SSRXp 12 51 VDD_DCI
VDD_A1 SSRXp DCI_DATA SOC_SML1_CLK
13 50 TX2n_C

2
2 1 0.1uF/10V,X5R AUXp VDD_A1 DCI_CLK TX2n CA91 1 20.22uF/6.3V,X5R C0201
3 DDI2_AUX_SOC_DP C0201 SSTXn 14 49 RA62 C1_TX2_N 53
CA81 SSTXn VDD_DCI
SSTXp 15 48 CEQ
2 1 0.1uF/10V,X5R AUXn VDD_DM_D SSTXp CEQ VDD_A2 10K_J
3 DDI2_AUX_SOC_DN 16 47
C0201 CA82 VDD_DM_D
ML0p 17
VDD_DM3 PS8812 VDD_A2
46 SSEQ r0201 CA129
20.33UF/10V,X5R C0402
C1_RX1_P
ML0p SSEQ RX1p 1
ML0n 18 45 TX2p C1_RX1_P 53
ML0n TX2p
ADDR 19 44 TX2n CA130 C1_RX1_N

1
USB HOST ADDR TX2n RX1n 1 20.33UF/10V,X5R C0402
ML1p 20 43 C1_RX1_N 53
ML1p RESET#
ML1n 21 42 TX1n CA131 C1_RX2_P
CA83 1 20.22uF/6.3V,X5R C0201 SSTXp ML1n TX1n RX2p 1 20.33UF/10V,X5R C0402
9 USB3_P3_TX_DP DPEQ 22 41 TX1p C1_RX2_P 53
DPEQ TX1p IN_HPD

1
ML2p 23 40 CA92 CA132 C1_RX2_N
CA84 1 20.22uF/6.3V,X5R C0201 SSTXn ML2p IN_HPD RX2n 1 20.33UF/10V,X5R C0402
9 USB3_P3_TX_DN ML2n 24 39 1UF/10V,X5R C1_RX2_N 53
ML2n REXT C0402
ML3p 25 38

2
ML3p VDD_DM4 VDD_DM_D

2
ML3n 26 37
CA85 1 20.22uF/6.3V,X5R C0201 SSRXp ML3n FLIP
9 USB3_P3_RX_DP CA133 CA1 CA134 CA135

2
220K_J 220K_J 220K_J 220K_J
CA86 20.22uF/6.3V,X5R C0201 SSRXn

VDD33_0
C 1 C

CE_USB
VDD_D1
9 USB3_P3_RX_DN RA61

CE_DP
CSDA
CSCL

AUXp
AUXn
SBU1
SBU2
R0402 R0402 R0402 R0402
4.99K_F

1
VDD33
R0201 ns ns ns ns
PS8812

27
28
29
30
31
32
33
34
35
36

1
VDD33

2
52 PS8802_SCL CSCL
52 PS8802_SDA CSDA
RA60

SBU1
SBU2
SBU1

2
SBU1 53
4.7K_J
RA58
R0402
100K_F

2
IN_HPD VDD_DM_D

1
3,52 IN_HPD R0201 RA63
ns
AUXp 2M_F
2

3.3V PULLDOWN defoult

1
R0201
RA109
AUXn
100K_F

1
VDD33
R0201 RA59
100K_F
1

R0201 SBU2
SBU2 53
VDD33
+V1P2U_VDDQ 1

2
VDD1V2 RA64
VDD_DM_D 2M_F
2
2

R5194 1 2 0_J R0603 FB1 1 2 0_J

2

R0201

1
RA51 ns fb0402 CP65 CP66 CP67 CP80 CP81
RA48 RA50 ns
RA49 4.7uF/6.3V,X5R 0.1uF/10V,X5R 0.01uF/10V,X5R 0.1uF/10V,X5R 0.01uF/10V,X5R

1
4.7K_J C0402 C0201 c0201 C0201 c0201
4.7K_J 4.7K_J
4.7K_J

2
R0402
R0402 R0402
R0402
1

VDD_A1
1

ns FB2 1 2 0_J
1

ns ns ADDR

1
ns Default fb0402 CP68 CP69 CP70
DPEQ 4.7uF/6.3V,X5R ns 0.1uF/10V,X5R 0.01uF/10V,X5R
Default C0402 C0201 c0201
CEQ

2
B B
Default
SSEQ
Default
FB3 1 2 0_J VDD_A2
1

1
CP71 CP72 CP73
2

fb0402
2

ns 4.7uF/6.3V,X5R 0.1uF/10V,X5R 0.01uF/10V,X5R

RA52 RA53 RA55 C0402 C0201 c0201
RA54
2

2
4.7K_J 4.7K_J 4.7K_J
4.7K_J
R0402 R0402 R0402
R0402
VDD_R1
1

FB4 1 2 0_J
1

ns ns ns ns
1

1
fb0402 CP74 CP75 CP76
4.7uF/6.3V,X5R ns 0.1uF/10V,X5R 0.01uF/10V,X5R
C0402 C0201 c0201
2

2
FB5 1 2 0_J VDD_R2
1

1
fb0402 CP77 CP78 CP79
ns 4.7uF/6.3V,X5R 0.1uF/10V,X5R 0.01uF/10V,X5R
C0402 C0201 c0201
2

20190429：Foll o w V540-I WL sol uti on

， chang e al l F B t o r esisto r fo r VDD1V
2

VDD33
+V3P3A

FB6 1 2 0_J
fb0402
1

CP82 CP83 CP84

4.7uF/6.3V,X5R ns 0.1uF/10V,X5R 0.01uF/10V,X5R
C0402 C0201 c0201
2

VDD_DCI VDD33

A Connect to VDD33 when DCI NO USE A

FB7 1 2 0_J
fb0402

Bitland Information Technology Co.,Ltd.

Page Name

Vinafix.com
51
Size Project Name Re v
C
Veneno 1.3
Date: Friday, August 23, 2019 Sheet 51 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 +VBUS_TYPEC
AD+ +VBUS_TYPEC

2
2
2
RA116
RA94
R10931 200K_F
addr0&(LOC_PWR>6V): 590K 1% 200K_F
addr0&(LOC_PWR<=6V) :115K 1% 590K_F
R0402
ns

1
R0402

1
LOC_PWR_MON C_VMON C_IMON

1
R0402

2
2
RA115
RA92
10K_J

2
ns
4.99K_F
RA95 r0201
r0201
10K_J

1
VDD33

1
r0201
Remove these pull ups if
the I2C master is used as

1
GPIOs.
Part B
GND GND
GND
Note :

2
1.Choose only one of the two parts above.
2.The left CKT above is used for SMBUS slave addr0/1/2/3 setting during power on initialization.
RA73 RA74 RA75 The PDC has no ability to monitor local power when choosing this CKT.
4.7K_J 4.7K_J 4.7K_J 3.Choose the right CKT above when there are requirements for PDC to monitor local power to decide
if C port can source power. But the slave addr can only be set at addr0 when implement this CKT
R0402 R0402 R0402

1
51 PS8802_SCL 2 RA133 1 ns SHORT_0402
USB2_TYPC_OC_N 9,53

LOC_PWR_MON
51 PS8802_SDA
20190423:Realtek suggestion,NC RA115,and change 'USB2_TYPC_OC_N' to pin 18,Pin7 floating.

C_VMON
53 FAST_ON

C_IMON
GPIO10
U7
RTS5452_QFN24

22

23

19

17

18
5
4
I2C_INT/GPIO9

VMON/MGPIO9
I2C_EN/GPIO10

I2C_SCL/GPIO7
I2C_SDA/GPIO8

IMON/MGPIO8
LOC_PWR_MON
short to disable
dead battery function
16 RA126 1 ns
2 0_J R0402
GND
DB_CFG

12
CC1 C1_CC1 53
6 14
59 SINK_EN AUX_P/MGPIO4 CC2 C1_CC2 53
7

2
AUX_N/MGPIO5 C0402 C0402
220pF/50V,X7R 220pF/50V,X7R
CA93 CA94
Realtek

1
1
SBU1_RTS5457T 8
RTS5457T-GR 10
20MIL TP10154 SBU2_RTS5457T SBU1/MGPIO6 BB_DP/MGPIO0 VBUS_EN 53,59 GND
1 9 11
20MIL TP10155 SBU2/MGPIO7 BB_DM/MGPIO1 VBUS_DIS 53

Connected to 3:2 MUX and 3,51 IN_HPD 2

DP source HPD input HPD/GPIO3

1 +V5CP 5V_LDO_RT6258C_PD
50 GPIO4_EC_INT SM_SDA_RTS5457T 24 SM_INT /GPIO4
R11571 1 2 SHORT_0201
29,50,76 EC_SMB1_DATA SM_SCL_RTS5457T 3 SM_SDA/GPIO6
29,50,76 EC_SMB1_CLK R11572 1 2 SHORT_0201 I2C ADDR:0xBC
SM_SCL/GPIO5
RA135
2
1 2
ns
0_J R0402
20190225:Follow V540S-WHL,Changed RTS5457T SMBUS to EC port1 RA76 20

VCON_IN
LDO_3V3
REXT

E-PAD
4.7K_J

5V_IN
R0402 RA81
1 2 20190821：RA81 change t o no i nst all

2
0_J R0402
1

RA79

25

15

21

13
6.2K_F VCON_IN_1
R0402 RA83
LDO_3V3 1 2
0_J R0402
LDO_3V3
1

20190821：Add RA135 connect t o +V5 CP

1
CA96 CA97

1
1
CA95 10uF/6.3V,X5R
Note: 0.1uF/10V,X5R C0402
1.If the 5V_IN power supply voltage is fixed 5V or variable 4.7uF/6.3V,X5R C0201

2
from 3.3V to 5V. Remove the 0ohm resistor. GND C0402

2
2
2.If the 5V_IN power supply voltage is fixed 3.3V, stuff
the 0ohm resistor.
Close to IC 5V_LDO_RT6258C 5V_LDO_RT6258C_PD
GND

RA125 2 1 0_J R0402

Q8936
DMP3160L-7
2 3

D
ns

G
2

1
CF39
10uF/6.3V,X5R

1
1
C10992 sot23-3 C0402
R11629 ns 0.1uF/25V,X5R

2
ns
10K_J C0402

2
R0402

1
2
2
C10993
ns R11633
1UF/6.3V,X5R ns 1K_J
C0201 R0201

1
3
D
Q8937
1 ns L2N7002LT1G
50,60 PD_PWR_EN G S SOT23-3

2
2

R11631 C10991
1

100K_F ns 0.1uF/10V,X5R
R0201 C0201
2
1

Bitland Information Technology Co.,Ltd.

Page Name
52

Vinafix.com
Size Project Name Re v
C
Veneno 1.3
Date: Thursday, August 22, 2019 Sheet 52 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

Vinafix.com
 +V5CP

PROVIDES ESD PROTECTION, PLACE CLOSE TO CONNECTOR

USB_C_5V_OUT_D 2
D34
1
3A
ns

1
C5367

1
T + 100uF/6.3V C5371
+V5CP ns 4.7uF/6.3V,X5R ESD5401N-2/TR
TC3528 DFN1006p2x
C0402 +VBUS_TYPEC

2
2

C1
B1
B2
U5314

2
A1 C2

VCP_1
VCP_2
VCP_3
VIN_1 VBUS_1
R11584 A2 D1

1
R4701 VIN_2 VBUS_2
4.7K_J D2
4.7K_J VBUS_3

1
R0402 C5368 C5369
R0402 C5320
ns 9,52 USB2_TYPC_OC_N
A4 0.1uF/25V,X5R 10uF/25V,X5R ns ESD5401N-2/TR
ns FAULT_L C0402 C0603
VBUS_EN +VBUS_TYPEC_ILIM DFN1006p2x

2
B4 A3

1
52,59 VBUS_EN FAST_ON_R EN ILIM
1 2 C4

2
R11583
52 FAST_ON FAST_ON
SHORT_0402

GND_1
GND_2
GND_3
CAP
R11585 R11469
4.7K_J 4.7K_J

D4

B3
C3
D3
R0402 R0402 NX5P3290UK
wlcsp16_0d5_2d05x2d05
C430
1

2
1000pF/50V/X7R
C0402 R5302 R5303
10%
22K_F 53.6K_F
R0402
R0402

1
GND Q5326A
L2N7002DW1T1G

3
SOT363
D
I
+VBUS_TYPEC
R5301 1 1K_J 2 5 G
49,50 EC_LIMITED_CTL S

2
R0201
R11484

4
EN: 1K_J

enable input (active HIGH with internal 1 Mohm pull down resister)
R0201

Q5326B

6 1
L2N7002DW1T1G
FAST_ON: D SOT363
I
Fast turn on. Pull this pin HIGH to enable fast turn-on feature. 52 VBUS_DIS
2 G

1 Mohm pull down resister integrated.

S

1
Normal : OCP SET TO 3A

2
Sys power limit: OCP SET TO 0.9A R11485
100K_F
R0201

1
R5304 1 2 4.7_J R0402
51 C1_TX2_N
ns SSTX1-_CONN DM_CON
90ohm,160mA SSTX2-_CONN SSTX1+_CONN DP_CON
2 1
SSRX1+_CONN C1_CC1
3 4 l_4p_1012_choke SSTX2+_CONN
SSRX1-_CONN C1_CC2
L5302
C5321

10
9
7

6
C5318

10
9
7

6
R5305 1 2 4.7_J R0402
51 C1_TX2_P

NC
NC

NC
NC
NC
NC

NC
NC
R5306 1 2 4.7_J R0402
51 C1_TX1_N 1 I/O1 I/O3 4
1 I/O1 I/O3 4
2 I/O2 I/O4 5
2 I/O2 I/O4 5
L5305 SSTX1-_CONN
3 4
2 1 l_4p_1012_choke SSTX1+_CONN

GND

GND
GND

GND
90ohm,160mA AZ1045-04F.R7G

3
AZ1045-04F.R7G

3
ns R0402 DFN10_0D5_2D5X1D0
DFN10_0D5_2D5X1D0
R5307 1 2 4.7_J
51 C1_TX1_P I
I

R5308 1 2 4.7_J R0402

51 C1_RX2_N
ns
90ohm,160mA SSRX2-_CONN JTYPE_C
2 1
3 4 l_4p_1012_choke SSRX2+_CONN SSTX2+_CONN USB11249-0500B-1H I
+VBUS_TYPEC +VBUS_TYPEC
L5306 SSTX2-_CONN
SSRX2-_CONN 16 17
R5309 1 2 4.7_J R0402 GND_8
51 C1_RX2_P SSRX2+_CONN 15 GND_9 18 YZW 20180507
GND_7
14 GND_10
GND_6
13
C5319
10

GND_5
9
7

R5310 1 2 4.7_J R0402

51 C1_RX1_N
NC
NC

NC
NC

A12 B1
L5307 SSRX2+_CONN GND_2 GND_3 SSTX2+_CONN
SSRX1-_CONN A11 B2
3 4
SSRX2-_CONN A10
SSRXp2 SSTXp2 B3
SSTX2-_CONN
1 I/O1 I/O3 4 SSRXn2 SSTXn2
2 1 l_4p_1012_choke SSRX1+_CONN A9 B4
2 I/O2 I/O4 5 VBUS_2 VBUS_3
SBU1 A8 B5
DM_CON RFU1 CC2 DP_CON C1_CC2 52
90ohm,160mA A7 B6
DP_CON A6
Dn1 Dp2 B7
DM_CON
ns R0402 Dp1 Dn2
R5311 1 2 4.7_J A5 B8 SBU2
GND

GND

51 C1_RX1_P 52 C1_CC1 CC1 RFU2

A4 B9
SSTX1-_CONN A3
VBUS_1 VBUS_4 B10
SSRX1-_CONN
AZ1045-04F.R7G SSTX1+_CONN SSTXn1 SSRX1+_CONN
8

A2 SSRXn1 B11
R5312 1 2 4.7_J R0402 DFN10_0D5_2D5X1D0 SSTXp1
A1 SSRXp1 B12
I GND_1 GND_4

L5308 DM_CON cn_usb-c_ub11249-0500b-1h

9 USB2_P3_DN 3 4 SBU1 SBU2
51 SBU1 SBU2 51
2 1 l_4p_1012_choke DP_CON
9 USB2_P3_DP
1

90ohm,160mA D5315 D5316

ns
R5313 1 2 4.7_J R0402 Bitland Information Technology Co.,Ltd.
AZ5825-01F 1uA 5V Page Name
tvs_dfn1006p2x_0p5 AZ5825-01F 1uA 5V 53

Vinafix.com
2

I tvs_dfn1006p2x_0p5 Size Project Name Re v

C
I
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 53 of 87
+VBUS_TYPEC +VBUS_TYPEC 52,59 PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

Vinafix.com
 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
54
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 54 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

8 7 6 5 4 3 2 1

Vinafix.com

Vinafix.com
 <XR_PAGE_TITLE>
8 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
55
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 55 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

8 7 6 5 4 3 2 1

Vinafix.com

Vinafix.com
 <XR_PAGE_TITLE
8 > 7 6 5 4 3 2 1

D
D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
56
Size
Project Name R ev
Custom
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 56 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

8 7 6 5 4 3 2 1

Vinafix.com

Vinafix.com
 +V3P3A

2
R9720 R9721
49.9K_J 49.9K_J

r0402
r0402

1
DEBUG
DEBUG UART2_TXD_R
8 UART2_TXD TP10162
UART2_RXD_R
8 UART2_RXD TP10163

DEBUG
+V3P3A
+1.8V_PRIM
+V3P3A 3,4,5,7,9,11,17,19,24,29,32,35,36,43,49,50,51,60,61,63,64,65,66,68,69,74,81
+1.8V_PRIM 8,11,17,46,50,65,68 CONN

Shielding Holes
CLIP8
SODIMM GPU NUT WIFI NUT
CPU NUT
CLIP1
Z000-4G7U1-12000
Z000-4G7U1-12000
2

4
EMI_CLIP_6X1P2X1P36I
2

EMI_CLIP_6X1P2X1P36I
2

13

54
2

13

54

5
1

HOLE6732 HOLE6726 HOLE6720 HOLE1 HOLE6723 HOLE6736 HOLE6722

mht5p5b5p5d2p8h1p5_smd mht5p5b5p5d2p8h1p5_smd mht5p5b5p5d2p8h1p5_smd mht5p5b5p5d2p8h1p5_smd mht5p5b5p5d2p8h1p5_smd mht5p5b5p5d2p8h1p5_smd mht5p5b5p5d2p8h1p5_smd
I I I I I I I
CLIP2 CLIP3
Z000-4G7U1-12000 Z000-4G7U1-12000
2

EMI_CLIP_6X1P2X1P36I EMI_CLIP_6X1P2X1P36I
PTH PTH PTH PTH PTH PTH PTH
2

13

54

13

54
1

CLIP5

1
CLIP4
Z000-4G7U1-12000 GPU NUT GPU NUT GPU NUT CPU NUT CPU NUT CPU NUT WIFI NUT
Z000-4G7U1-12000
2

EMI_CLIP_6X1P2X1P36I
2

EMI_CLIP_6X1P2X1P36I
2

13

54
2

13

54

5
1

mht5p5b5p5d2p8h1p5_smd

CLIP11 CLIP12
Z000-4G7U1-12000 Z000-4G7U1-12000
GPU HOLE6719 HOLE6724
2

EMI_CLIP_6X1P2X1P36I EMI_CLIP_6X1P2X1P36I
MHOB6X7P8DOB3P8X5P6 MHOB6X7P8DOB3P8X5P6
NI NI
2

13

54

13

54
1

ns ns
PTH PTH
CLIP7 CLIP6
Z000-4G7U1-12000 Z000-4G7U1-12000
2

EMI_CLIP_6X1P2X1P36I EMI_CLIP_6X1P2X1P36I

1
2

13

54

13

54

ns ns
1

ns ns
CLIP10
CLIP9
Z000-4G7U1-12000
Z000-4G7U1-12000
2

EMI_CLIP_6X1P2X1P36I
2

EMI_CLIP_6X1P2X1P36I
2

13

54
2

13

54

5
1

ns ns

20190304:RF suggest NI CLIP9 and CLIP 12

HOLE6727 HOLE6734 HOLE6725 HOLE6735 HOLE6733 HOLE6728
MHT5B5D2P5 MHT5B5D2P5 MHT5B5D2P5 MHT5B5D2P5 MHT5B5D2P5 MHT5B5D2P5
NI NI NI NI NI NI

PTH PTH PTH PTH PTH PTH

1

1
ns ns ns ns ns ns
MK1 MK2 MK3

1 1 1
1 1 1
FMARKS FMARKS FMARKS
fmarks fmarks fmarks
ns ns ns

MK6 Bitland Information Technology Co.,Ltd.

MK4 MK5
1 Page Name
1
1
1
1
1
57

Vinafix.com
FMARKS Size Project Name Re v
FMARKS FMARKS fmarks C
fmarks fmarks ns Veneno 1.3
ns ns Date: Thursday, August 22, 2019 Sheet 57 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

Vinafix.com
 5 4 3 2 1

58: BATTERY CONNECTOR

BATT+ BATT+ 59

+V3.3AL +V3.3AL 11,28,38,49,50,60

DCIN DCIN 59

1 1

BATT+
TP10077 TP10075 TP10076

2
1

1
C5865 C5864 D5801 CN5801
0.1uF/50V,X5R 0.1uF/50V,X5R 1.0V_0.2A_LMDL914T1G
C0402 C0402
SOD323
wtb_8p_1d25_h2d0_dip
ns

2
WWAA1208-1D00
5A

1
I

10
9
8

SH1
SH2
TP10078 8
7
+V3.3AL 7

R5801 1 2 100_F R0201 BATT_CLK 6

50,59 EC_SMB0_CLK 6

R5803 1 2 100_F R0201 BATT_DAT 5

50,59 EC_SMB0_DATA 5

2
20190703; change to 120K R5804 BATT_TS 4
4
120K_F
R0201 TP10079 3
3

R5802 1 2 100_F R0201 2

50,59 BATT_ID#

1
2
1 BATT_CLK BATT_DAT BATT_TS

SH3
SH4
1

1
+RTCBATT TP10080 TVS1 TVS2 TVS3

11
12
2 2
AZ5725-01F.R7GR AZ5725-01F.R7GR AZ5725-01F.R7GR
DFN1006p2x DFN1006p2x DFN1006p2x
TP10083

2
I I I

TP10129
TP10082 TP10081
BATT_DAT BATT_CLK

1
C5803 C5804
100pF/50V,NPO 100pF/50V,NPO
C0402 C0402
Option = ns ns

J_DC
50278-00501-001 AD+
cn_wtb_5P_50278-00201_1p25
I
3A
3 3
G1

PFB1 2 1 30ohm/100MHz,3A fb0603

PAD2

5 PFB2 2 1 30ohm/100MHz,3A fb0603

5
1

C5866
4
4 0.1uF/50V,X5R

1
ADAPTER_ID0 C0402 C5801
3
2

3 ADAPTER_ID0 50 0.1uF/50V,X5R
C0402
2

2
2
1
1
PAD1

YZW 20180507 V530SPEK TP10140

TP10084
G2

LC 20180713 add adapter ID

1

C5862
0.1uF/50V,X5R
C0402
2

4 4

Bitland Information Technology Co.,Ltd.

Page Name

Vinafix.com
58
Size Project Name Re v
C
Veneno 1.3
Date: Friday, August 23, 2019 Sheet 58 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

59: BATTERY CHARGER

TP10149 TP10150

DCIN RECOMMENDED VALUE

FROME DATASHEET PPVAR_PWR_IN_BB
+VSYS Q6
EMB09P03V EMC
R522 0.02_F R1206 dfn8_0d65_3x3 BATT+
1
PPVAR_SYS PPVAR_BAT_G
R542 R1206 2
D5803 C538 C539 C542 C543 C545 0.01_F 3
2

C10994 C552 C554 C555 C3563 C560

AZ4020-01G 10uF/50V/X5R 10uF/50V/X5R 10uF/50V/X5R 10uF/50V/X5R 0.1uF/50V/X5R C550 S 5
SMA C0603 C0603 C0603 C0603 C0402 22uF/35V/X5R 0.1uF/50V/X5R 22uF/35V/X5R 22uF/35V/X5R 22uF/35V/X5R 22uF/35V/X5R 22uF/35V/X5R D
I C0402 G
1

C0805 C0805 C0805 C0805 C0805 C0805

5
10% 10% 10% 10% 10% 10%

4
D 2.2uH D R541 R543
D D
R505 R526 dfn8_0d65_3x3 L16 l_2p_6d6x7d3 1_J 1_J
1_J 1_J 1 ns 2 R0201 R0201
R0201 R0201 HDRIVE_1 4
EMB12N03 4
HDRIVE_2
G G
S Q12H S
Q23H
L13
BB_SWITCH_1 BB_SWITCH_2 EMB12N03

1
2
3

3
2
1
C536 1 2
dfn8_0d65_3x3
2 1 HPPC10020-2R2M-Q8L C557

5
l_2p_10d1x11 C0402
4.7uF/10V/X5R D D
C0402 1UF/10V,X5R

BATTERY_GATE_L
LDRIVE_1 4 4
LDRIVE_2
G G
S Q12L C548 C549 S C141
Q23L
C534 C537 EMB12N03 0.22uF/25V/X5R 0.22uF/25V/X5R 4700pF/25V/X5R
EMB12N03

1
2
3

3
2
1
1UF/35V,X5R 1UF/35V,X5R dfn8_0d65_3x3 C0402 C0402 C0402
dfn8_0d65_3x3
C556 C558

BB_BOOT1_R

BB_BOOT2_R
C0402 C0402
1UF/35V,X5R 1UF/35V,X5R
R479 R475 BOOST LEG C0402 C0402
0_J 0_J ns ns
+VSYS
R0201 R0201 BUCK LEG
DCIN R480 R481

2
0_J 0_J
R533 R534 R0201 R0201
0_J 0_J
R0201 R0201
2

D11
BB_LDRIVE_1 BB_LDRIVE_2

1
0.35V_0.2A_LBAT54CLT1G

BB_BOOT1

BB_BOOT2
sot23-3 BB_HDRIVE_1 BB_HDRIVE_2
3

C535 1UF/35V,X5R C0402

11

10

12

5
R506 1 2 1_F R0805 PPVAR_BB_IN

LAGTE1

LGATE2
UGATE1

PHASE1

BOOT1

BOOT2

PHASE2

UGATE2
C C

C540 2 1 4.7uF/10V/X5R 17
DCIN
C0402
VDD_BB_GATE_DRIVE 8
VDDP
DCIN
3
BB_PPVAR_SYS R539
1 0_J
2
PP5000_BB_LDO_OUT VSYS R0201
+VSYS
R528 4.7_F R0402 18
VDD
C551
C544 2 1 4.7uF/10V/X5R 1UF/35V,X5R
C0402 C0402
R503 BB_CSN 14
CSIN
ns
392K_F
R0402 BB_CSP 15
CSIP
ADAPTER VOLTAGE
VALID IF > 3.4V
BB_ACIN 19 2
BATTERY_SRP_BB
ACIN CSOP
PULL-UP FROM EC OR H1? BB_ASGATE 13
R504 TP109ns ASGATE BATTERY_SRN_BB
C533 1
120K_F CSON
0.1uF/50V/X5R DCIN
16 U5901
R0201 ADP
C0402 ISL9238
ISL9238BHRTZ-T BB_PPVAR_BAT
21 31 1 R540 2 SHORT_0201
50,58 EC_SMB0_DATA SDA QFN32_0D4_4X4 VBAT BATT+
22
50,58 EC_SMB0_CLK SCL I2C ADDR: 0X12 C553
1UF/35V,X5R
24 C0402
50 CHG_AC_PRES ACOK
BB_CHARGER_PROCHOT_ODL ns
R527 100_F R0201 23
3,50,66 PROCHOT_N PROCHOT#

PSYS R11557 0_J R0201 PSYS_R 30 32

BATTERY_GATE_L
66 PSYS ns PSYS BGATE

1 R530 2 SHORT_0201 29
50 ADP_I AMON/BMON
B B
R521 0_J R0201 BB_CMIN 20 25 R11610
1 0_J
2
+V3P3A_EC OTGEN/CMIN BATGONE R0201 BATT_ID# 50,58
ns BB_CMOUT 26
TP110 OTGPG/CMOUT
2

2
ns BB_COMP
1

R525 C541 28
COMP
R537 BATGONE LOW
PSYS_R 100K_F 0.01UF/16V/X7R 100K_J
C0402 INDICATES
R0201 R0201
BATTERY PRESENT
2

PROG
GND

R174 R532
1

C594
1

1
0.01UF/25V/X7R 6.04K_F 698_F
2

C0402 R0201 C541 GND PIN SHOULD GOES TO C546 R0402

33

27
2

PIN E1 AVSS OF U45 470pF/25V,X5R

C0402 FOR 0.476A ADAPTER CURRENT LIMIT
1

SETS GAIN R535

ns C547 215K_F
AND 733KHZ SWITCHING FREQUENCY:
0.022uF/25V/X5R R0402 2 CELL: 93.1K
C0402 3 CELL: 105K
4 CELL: 215K DCIN
D6817 AD+

AD+
1 +VCC_SELECT Q5901 Q5902
+VCC_SELECT EMB09P03V EMC EMB09P03V EMC
0.35V_0.2A_LBAT54CLT1G 3 dfn8_0d65_3x3 dfn8_0d65_3x3
ns 20190821：Add R11642 pull up SI NK_ EN_ R t o +VCC_ SEL ECT

1
sot23-3 1 1
PC7
2

2 2 2
52,53 VBUS_EN 1UF/25V,X5R
R11594 R11642
Type C Power IN Switch 3 3
C0402

2
1
100K_F 100K_F S 5 5 S
20190821：R11594 change t o no i nst all R0402 R0402 R11592 D D
ns 20K_J G G
+VBUS_TYPEC TypeC sink Intput

1
R0402 C5968
1

4
U11 DCIN 0.1uF/25V,X5R
NX20P5090UK_5A C0402
2

2
BGA15_0d5_2d56X1d54
R11598 B2 A1
0_J Q8933A VBUS1 VINT1
1

ns C2 B1
VBUS2 VINT2 AD+
3

R0201 L2N7002DW1T1G D2 C1 R5976

A VBUS3 VINT3 A
SOT363 D E1 D1
VBUS4 VINT4 20K_J
I E2
1

R0402
2

R11596 VBUS5
1 2 5.1K_F R0402 5 G TP167
52 SINK_EN S Active low A2
SINK_EN_R ACK R11580
3 2

A3 +VCC_SELECT
EN_L 110K_F
4

C3
ns D D6814
Q8933B GND1
D3
R0402 Q5936 Bitland Information Technology Co.,Ltd.
6

L2N7002DW1T1G B3
GND2
E3
L2N7002LT1G AD+
1
1

SOT363 D R11595 OVLO GND3 1 2 1K_J 1 SOT23-3 Page Name

Vinafix.com
R11597
I
1M_J
50,59 AD+_EN
R11593 R0402 G S 0.35V_0.2A_LBAT54CLT1G 3 59
1

0_J R0201 2 G sot23-3 Size

50,59 AD+_EN R0402 Project Name Re v
2
1

S C
R11577
PC10 +VBUS_TYPEC
2
Veneno V1.0
GND GND GND 1UF/25V,X5R
1

22K_F C0402 Date: Friday, August 23, 2019 Sheet 59 of 87

2

R0402
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
2

GND GND documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

+VSYS

V5P0A_VIN GND
C6003
2 1 1 2
GND

1
T + R6020

1
CT19 C6005 C6006 C6007 C6014 1000pF/50V,X7R
ns 33uF/25V 10uF/25V 10uF/25V ns 0.1UF/50V,X7R 0.1uF/10V/X5R 2.2_J C0402
tc7343 C0603 C0603 C0402 QFN12_0D45_3X3-3 C0201 R0805

2
5 10 V5P0A_OUT
VIN VOUT
GND GND GND
D D
C10985
2 1 11 9 R6004 1 2 1K_J C6034 10pF/50V/COG +V5P0A_DSW +V5CP
V5A_AGND VCC FF R0402 C0201
1UF/10V/X5R C0201
1
29,50,60,64 EC_ALW _EN L6001
R6023 V5PCP_EN V5P0A_PHASE 1.0uH ±20% 6.7mΩ 12A 15A
3 2 1 6 2 1 2
R0402 EN SW1
0_J l_2p_6d6x7d3

2
R6068 U6001 C6008

2
1 2 2 3
50 CP_PWR_EN

1
R6022 C6013 SW2 0.1uF/25V,X5R

1
SHORT_0402 RT6258CGQUF C6009 C6010 C6011 C6012 C6031 C6029
100K_F 0.1uF/10V/X5R C0402
C0201 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R ns 22uF/6.3V/X5R 22uF/6.3V/X5R
V5P0A_BST 2 R6001
1 V5P0A_BST_R

1
D6001 R0402 12 1 C0603 C0603 C0603 C0603 C0603 C0603

2
LDO BOOT
0.35V_0.2A_LBAT54CLT1G ns R0603 10.0_F
sot23-3

1
GND
GND GND GND GND GND GND
4 7
PGND PG
0_J
GND
5V_LDO_RT6258C R11634 1
ns
2 R0603 8
AGND

2
C6015
4.7uF/6.3V,X5R
C0402

1
1 R6005 2
V5A_AGND SHORT_0603

GND

V5A_AGND GND
+VSYS

C C

V3P0A_VIN C6002
V3P3A_DSW_BST
2 1 V3P3A_DSW_BST_R 2 1 1 2
GND
R6006 10.0_F
R6019
1

1
C6017 C6018 C6019 R0603 C6020 1000pF/50V,X7R
10uF/25V 10uF/25V ns 0.1UF/50V,X7R 2.2_J C0402
0.1uF/25V,X5R +V3P3A_DSW_R +V3P3A
C0603 C0603 C0402 R0805
C0402
2

2
1
L6002

BOOT
1.0uH ±20% 6.7mΩ 12A 15A
GND GND GND 5 2 1 2
VIN SW1 l_2p_6d6x7d3

V3P3A_DSW_EN

1
29,50,60,64 EC_ALW _EN
1 2 6 3 C6021 C6022 C6023 C6024 C6032 C6030
EN SW2
22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R ns 22uF/6.3V/X5R 22uF/6.3V/X5R 22uF/6.3V/X5R
1

R6021 C0603 C0603 C0603 C0603 C0603 C0603

100K_J

2
1

R0402 R6008
C6025 ns
ns 10K_F
1uF/6.3V/X5R
V3P3A_DSW_FF V3P3A_DSW_FF_RC GND
R0402
C0201 12 2 1 GND GND GND GND GND
FF
2

+V3.3AL U6002 R6009 1K_F R0402

1
RT6258B C6026
2

GND 10PF/50V,NPO
1 R6018 2 GND 11 C0402
V3P3A_DSW_OUT

2
ns LDO3 R6010
10 1 2
SHORT_0603 VOUT ns
SHORT_0603
2

C6027 8 4
AGND PGND
4.7uF/6.3V,X5R
VCC

1
PG

C0402
C6033
0.1uF/10V/X5R
1

C0201
7

2
B B
GND GND ns
V3A_AGND
GND
1

C6028
+VBUS_TYPEC +VSYS 1UF/10V/X5R 1 R6011 2
C0201
SHORT_0603
2

20190821：Add D6820 conect t o +V5 CP

， ad d D682
1 ， R60 16 chan ge t o no insta
l
V3A_AGND
1

V3A_AGND GND
D6821 D6820 R6017
RA136 +V3P3A
1 2
LMBR4010BST5G LMBR4010BST5G +V3.3A_PWRGD 50,65
ns 0_J 100K_F
SOD882 SOD882
R0201
2

R0402

20190821：R6024 change t o i nst all

+V3.3AL_VIN R6015
1 2
U6003 R0603 0_J
1

C6035 C6036 5V_LDO_RT6258C

10uF/25V 0.1UF/50V,X7R R6024
1

C6037
C0603 C0402 100K_F 0.1UF/50V,X7R
2

2 7
R0402 VIN BST C0402
2

20190821：Add D6821 and D6820 L6003 0_J

+V3.3AL_EN +V3.3AL_OUT
1

3 8 1 2 1 2
EN SW
4.7uH 1.3A 20% R6016 R0603
SML2520_1P2H I
1 2 R6025 +V3.3AL_PG 6 +V3.3AL_FB
1

A ns 2 1 5 R6026 C6001 C6038 C6039 A

PG FB
3

R11635 750K 22PF/50V,NPO 22uF/6.3V/X5R 0.1uF/10V/X5R

D 100K_F
0_J R11643 1% C0402 C0603 C0201 Bitland Information Technology Co.,Ltd.
+V3.3AL_VCC4
2

R0402 R0402 1 R0402_N

ns 1M_J VCC GND
1 I Page Name
60
1

50,52 PD_PWR_EN R0402 C6004

Q8939 G S 1UF/6.3V,X5R Size
L2N7002LT1G C0402 Project Name Rev
2

20190821：Add Q8939 SOT23-3 MP2322GQH Custom

V540
2

I
R6027
V1.0
100K
1% Date: Friday, August 23, 2019 Sheet 60 of 87
R0402_N PROPERTY NOTE: this document contains information confidential and property to
20190821：Add R11643 I Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

Vinafix.com
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

+VSYS

1
C6103 C6104 C6105 C6106
0.1uF/25V,X5R 10uF/25V 10uF/25V 10uF/25V
C0402 C0603 C0603 C0603

2
D +VDDQ_R +V1P2U_VDDQ D

19

20

21

22

31
GND GND GND GND

VIN1

VIN2

VIN3

VIN4

VIN5
VDDQ_LX R6101 VDDQ_TON VDDQ_BST 1
2 1 8 23 0_J 2 VDDQ_BST_R
TON BOOT
R6102 R0603
340K_F R0402

1
C6107
1 R6103 2 VDDQ_VCC 7 0.1uF/25V,X5R
+V5P0A VCC
9 C0402
SHORT_0402

2
LX1 +VDDQ_R

1
C6108
1UF/6.3V,X5R 10
+V3P3A C0201 LX2 L6101
VDDQ_LX 1.0uH ±20% 6.7mΩ 12A 15A

2
28 11 1 2
GND LX3 l_2p_6d6x7d3
1

1
12 C6109 C6110 C6111 C6112 C6113 C6114
LX4 ns 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R ns 0.1uF/10V,X5R
R6105 32 C0603 C0603 C0603 C0603 C0603 C0201

2
LX5
10K_J VDDQGND
R0201
30 GND GND GND GND GND GND
2

VDDQSENSE
6 U6101
50 DDR_PWRGD PG
G5416 1 1 2
VDDQSET
R6113
24
VLDOIN +VDDQ_R 6.04K_F
+V0.6S_VTT R0201
R6104

1
C6117
SLP_S4_L R6106 2 1 VDDQ_S4 5 25 10UF/6.3V,X5R 10K_F
50 EC_SLP_S4_N S5 VTT
R0201 10K_J C0402 R0201 1 2

2
1
27 C6116
C
SLP_S3_L R6107 2 1 VDDQ_S3 4
VTTSNS
10uF/6.3V,X5R GND C6102 C
43,50,64 EC_SLP_S3_N ns 10K_J S3
R0201 C0402 100pF/50V,NPO

2
26 C0201
VTTGND
1 VDDQGND
C6120
SM_PG_CTRL
2

4 SM_PG_CTRL R6108 2 1 C6115 29 GND 1 2

GND
R0201 VTTREF +V2P5U_VPP
0_J 1000pF/25V,X5R R6110
c0201 100K_F 0.1uF/10V,X5R
VDDQ_R=0.75*(R1850/PR61+1)
1

R0201 2 C0201
V2P5
ns
2

1
C6118

PGND1

PGND2

PGND3

PGND4

PGND5

PGND6
3
V3V +V3P3A
GND GND 10uF/6.3V,X5R

1
C6101 C0402

2
1UF/6.3V,X5R

13

14

15

16

17

18
C0201

2
GND
GND

GND

1 2
12

2017/3/8
JS6304
SHORT PAD
60X30Mil VDDQGND
B NOBOM B

A A

Bitland Information Technology Co.,Ltd.

Page Name
61
Size
Project Name Rev
Custom
Veneno VA
Date: Friday, August 23, 2019 Sheet 61 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

Vinafix.com
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

D D

C C

B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
NA
Size
Project Name Rev
Custom
Veneno VA
Date: Wednesday, August 21, 2019 Sheet 62 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

Vinafix.com
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

63: +1.0V_PRIM POWER SUPPLY R6305

R6304 1 2 10.0_J R0603 1 2
+V5P0A R0603 2.2_J

1
C6314 C6315
4.7uF/6.3V,X5R 0.1uF/25V,X7R
C0402 C6316 C0603

2
1 2

V1.0_BOOT
V1.0_VCC
V1.0_VIN
0.01UF/25V,X7R

V1.0_SS
V1.0_LX
C0402
V1.0_AGND

D D

23

22

21

20

18

25
19
1 R6303 2
65 +1.8V_PWRGD
SHORT_0402

VIN2

LX4

LX5
PGND4
VCC
SS

BST
1 17
50 V1.0_PWROK PGOOD LX3

V1.0_EN 2 16
EN LX2

1
C6317 V1.0_PFM
1UF/6.3V,X5R +V5P0A
1 2 3
PFM# U6301 PGND3
15
C0402 R6302 G5335QT1U

2
TQFN23_PH0P5_4X4_H0P8

2
0_J
12/29 power request pull high with EE ns R0402
R6306 V1.0_AGND
4
AGND I PGND2
14

ns 100K_J
R0402 V1.0_FB
+V3P3A 5 13
FB PGND1
V1.0_OUT

1
+1.0V_PRIM
2

6 12
TON PGND0
R6307
100K_J

VIN0

VIN1

VIN3
V1.0_AGND

LX0

LX1
NC
R0402

V1.0_TON
V1.0_PWROK

24

10

11
1

1 2
12
2017/3/8
C JS6303 C

V1.0_LX
R6310
SHORT PAD 80.6K_F L6301
60X30Mil V1.0_AGND R0402 1.0uH ±20% 6.7mΩ 12A 15A
NOBOM 1 2 1
l_2p_6d6x7d3
2

ns

1
C6306 C6307 C6308 C6309

1
C6330 C6333
R6308 R6301 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
V1.0_VIN C0603 C0603 C0603 C0603
0.1uF/25V,X5R 22uF/6.3V,X5R
2.2_J 6.19K_F
+VSYS C0402 C0603

2
R0805 R0402

1
C6301 C6302 C6329 C6303 C6304
V1.0_FB

1
10uF/25V 10uF/25V 10uF/25V 0.1uF/25V,X5R 1UF/25V,X5R

1
C0603 C0603 C0603 C0402 C0603 C6305

2
470PF/50V,X7R

2
ns C0402
R6309

1
C6310 C6311 C6312 C6313 C6331 C6332
20K_F 22uF/6.3V,X5R ns 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
R0402 C0603 C0603 C0603 C0603 C0603 C0603

2
I

1
V1.0_AGND

Remove LPM
+V3P3A

B B
2

R6330
+1.0V_PRIM +VCCPRIM_CORE
ns 10K_F
R0402
NI TP10143 R6320 1 ns 2 2.2_J R0402
NI
1

R11521 C10970
3

2 1 1 2
DQ8927 ns ns
1

C6323 2.2_J R0805

ns ns 0.22uF/50V,X7R 470PF/50V,X7R C0402

1 C0603
NI
2

7,50 SLP_S3_SOC G S L2N7002LT1G

6

9
7

SOT23-3 U6302
2

7,30,50,64 SLP_S0_SOC NI
LP#

MODE

BST

L6302
+VSYS
2
JP8208 ns
1
0.005_F
1
VIN SW
8 1
l2520 ns 0.47uH_
2 2
JP6301 ns
1
0.005_F
+VCCPRIM_CORE
R1206 V1.0_EN 5 12 R1206
NI +V3P3A +V3P3A EN VOUT NI
NB692GD
qfn13_3x2x1_0p5
1

C6320 C6321 C6322 R6329 100K C6328

3 2 1

1
ns 10uF/25V ns 10uF/25V ns 0.1uF/25V,X5R R0402_N ns 1% NI C1
ns
PGND ns 0.1uF/25V,X5R C6325 C6326 C6327
C0603 C0603 C0402 R6328 100K
4 11
C0402 ns 22uF/6.3V,X5R ns ns
22uF/6.3V,X5R 22uF/6.3V,X5R
2

NI NI NI ns 1% C0 AGND NI C0603 C0603 C0603

2

2
3V3
PG

R0402_N NI NI NI NI
+V3P3A
NI
2 13

10

A A
2

R6322
R6321 Bitland Information Technology Co.,Ltd.
ns100K_F ns 0_J
Page Name
R0402
NI
R0402 PWR-+1.0V_PRIM
NI Size
Project Name Rev
1

Custom
Veneno
1

VA
1

C6324 Date: Friday, August 23, 2019 Sheet 63 of 87

ns 1UF/10V,X5R PROPERTY NOTE: this document contains information confidential and property to
C0402 Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
2

NI documents or disclosed to others or used for any purpose other than that for which it

Vinafix.com
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

+3V_PRIM

+V3P3A +V3P3A +V3P3A to +3V_PRIM

2
+3V_PRIM
+V3P3A R6417
R6410 100K_J
C6416 2 1

1
R0402
C6415 0.1uF/10V,X5R SHORT_0603 I

1
C6413

1
+VDD33 0.1uF/10V,X5R C0201
0.1uF/10V,X5R

2
C0201 C0402 EC_SLP_S3_N GPPC_H18_BOOTMPC_R
2 0_J 1

2
D VDD33_VOUT
GND GND R6414 ns R0402 NI
D
+V3P3SX

7
2 R6401 1

VIN1

VIN2

VIN3

VIN4
SHORT_0603

1
C6417 C6418
10UF/6.3V,X5R 0.1uF/10V,X5R 13 8 D6401
VOUT1 VOUT3
C0402 C0201
2
2

1
I-DIS C6420
I-DIS
14 9 C6419 10UF/6.3V,X5R
VOUT2 VOUT4 3
GND GND 0.1uF/10V,X5R C0402
U6402

2
+V5P0A C0201 0.52V_200mA_LBAT54ALT1G
EM5209 6 GPPC_H18_BOOTMPC R6415 2 1 1
sot23-3 I-MS
1 2 4 11 GND GND SHORT_0402
GND VBIAS GND1
C6421 0.1uF/10V,X5R 15
GND2
C0201 0_J
7,30,50,63 SLP_S0_SOC 2 1 R11562 1 2
R6416 R0402 2.2k_J R0402 I-MS
69,81 +VDD33_EN 2 R6403 1 3 5 GND SHORT_0201 2 R6404 1 EC_SLP_S3_N 43,50,61,64
ON1 ON2
ns

CT1

CT2
SHORT_0402

1
C6423

12

10
0.1uF/10V,X5R

2
C0201

C6424
1000PF/25V,X5R ns
C6425
1000PF/25V,X5R
GND
IMAX=4.066A
+1.0V_PRIM C0402

2
C0201 C0201 0.1uF/10V,X5R
U6401
EM5201BJ-45 C6414

1
SOT23-6
GND GND
1 6 ns 2 R6409 1
GND GND ON GPPC_H18_BOOTMPC_R 64
+V5CP +V5CP SHORT_0402
C 2 5 C
VIN VBIAS +V3P3SX
3 4
NC VOUT +1.0VS_VCCIO

1
C6401

1
C6436 1UF/6.3V,X5R C6403 C6402
1

1
0.1uF/10V,X5R C0402 0.1uF/10V,X5R 0.1uF/10V,X5R
C6431

2
C0201 C0402 C0402

2
+V5P0S 0.1uF/10V,X5R
2

2
C0201
GND GND GND
GND GND
+V5P0A
1

7
VIN1

VIN2

VIN3

VIN4
1

C6428 C6433
10UF/6.3V,X5R 0.1uF/10V,X5R 13 8
VOUT1 VOUT3
C0402 C0201
2

1
C6427
14 9 C6430 10UF/6.3V,X5R +1.0V_PRIM
VOUT2 VOUT4
GND GND 0.1uF/10V,X5R C0402
C0402

2
U6403
2

2
+V5CP C0201
EM5209 U6406 0.1uF/10V,X5R
EM5201BJ-45 C6439
1 2 4 11 GND GND

1
GND VBIAS GND1 SOT23-6
C6429 0.1uF/10V,X5R
GND2
15
1 6 ns 2 R6413 1
C0201 GND GND ON GPPC_H18_BOOTMPC_R 64
SHORT_0402
2 5 2 0_J 1
+V3P3A
43,50,61,64 EC_SLP_S3_N 2 R6407 1 3 5 GND SHORT_0201 2 R6408 1 EC_ALW _EN 29,50,60 VIN VBIAS
ON1 ON2 R11591 R0402
CT1

CT2

SHORT_0402 3 4
1

NC VOUT +1.0VS_VCCSTG

1
C6435 C6411
C6426

1
0.1uF/10V,X5R 1UF/6.3V,X5R C6412 C6410
12

10

C0201 0.1uF/10V,X5R C0402 0.1uF/10V,X5R 0.1uF/10V,X5R

2

2
B C0201 B
C0402 C0402

2
GND GND
C6434 C6432
1000PF/25V,X5R 1000PF/25V,X5R GND GND GND
C0201 C0201

GND GND

+1.0V_PRIM C0402 +V1P2U_VDDQ C0402

2

2
U6404 0.1uF/10V,X5R U6405 0.1uF/10V,X5R
EM5201BJ-45 C6437 EM5201BJ-45 C6438
1

1
SOT23-6 SOT23-6
1 6 ns 2 R6411 1 1 6 ns GPPC_H18_BOOTMPC_R 2 0_J 1
GND GND ON EC_SLP_S3_N 43,50,61,64 GND GND ON SLP_SUS_N 7
SHORT_0402 R6412 ns R0402
2 5 2 5
VIN VBIAS +V3P3SX VIN VBIAS +V3P3SX
3 4 3 4
NC VOUT +1.0V_VCCST NC VOUT +1.2V_VCCPLL_OC
1

C6405 C6408
1

1
1UF/6.3V,X5R C6406 C6404 1UF/6.3V,X5R C6409 C6407
C0402 0.1uF/10V,X5R 0.1uF/10V,X5R C0402 0.1uF/10V,X5R 0.1uF/10V,X5R
2

A C0402 C0402 C0402 C0402 A

2

2
Bitland Information Technology Co.,Ltd.
GND GND GND GND GND GND
Page Name
PWR-load switch
Size
Project Name Rev
Custom
Veneno VA
Date: Wednesday, August 21, 2019 Sheet 64 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

Vinafix.com
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

D D

+V3P3A

2
R6506
+V3P3A
U6501 10K_J

1
C6501 G9661-25ADJF11U R0402
10uF/6.3V,X5R SOP8_PH1P27_4X5_H1P6_G1
C0603
I

1
2
3 1
VIN POK +1.8V_PWRGD 63
50,60 +V3.3A_PWRGD 2
VEN VO
6
+1.8V_PRIM
1.8V_ADJ

1
5 7 C6505
NC ADJ

2
10uF/6.3V,X5R

1
C6504 +V5CP 4 8 R6504 C0603

2
C VPP GND C
1UF/6.3V,X5R 13K_F

TP
C0402 20180703 R0402

2
Change to +V5CP

9
1
Option = ns C6503

1
1UF/6.3V,X5R
C0402

2
R6505
Option = ns 10.5K_F
R0402

1
B B

A A

Bitland Information Technology Co.,Ltd.

Page Name
PWR-+1.8V_PRIM
Size
Project Name Rev
Custom
Veneno VA
Date: Wednesday, August 21, 2019 Sheet 65 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it

Vinafix.com
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

+1.0V_VCCST

D D

1
R6646 R6642 R6647
73.2_F 100.0_F 45.3_F
R0402 R0402 r0402
ns

2
VREF SVID_ALERT#_R
1 R66 39 2 SHORT_0402
12 SOC_SVID_ALERT#_R
SVID_DIO_R
RT6701 R6667 2 1 10.0_F R0402
12 SOC_SVID_DAT
NTCCORE1P 1 2 NTCCORE1N SVID_CLK_R
R6656 2 1 49.9_F R0402
12 SOC_SVID_CLK
NTC_100K R6602
R0402
24.3K_F

1
1 R0402 2 2 R66 03 1
R6605 R6664 R6601 VREF
R6675 SHORT_0402 VREF
1.87K_F 36K_F 3.9_J
19.1K_F R0402
R0402 NTCCORE1N 2 R66 04 1
R0402
R0402
SHORT_0402

2 1
R6608
R6607

1
C6612 51K_F
1K_F R0402
0.47UF/6.3V,X5R NTCCORE1P 1 R0402 2 1 2

2
2

2
C0402

2
R6609 R6661 5.1M_F
R66 06 R6660
2k_F SHORT_0402 2K_F R6610
1 2 R6617
R6611 28.7K_F
R0402 R0402 R6612 R0402 34K_F PROCHOT_N 3,50,59
24.3K_F R6614 R0402 R0402 SVID_CLK_R
300.0_F

2
R0402 13.7K_F 2R0402
1 R0402 2 1 2 2 R66 13 1 1
AU1_SET1 VREF 1 2 R6615

1
SVID_DIO_R

1
AU1_SET2 SHORT_0402 RT6601 NTC_100K R0402
715.0_F
AU1_SET3 1 2
SVID_ALERT#_R

2
R0402

2
R0402

2
RT6602 NTC_100K
2

2
R0402 R6619 SHORT_0402
SHORT_0402
1 2 1 2 1 2 1 R0402 2 R66 71

1
R6618 R6625 R6645 VREF 1 2 40.2K_F R66 16
R6620 R6621 R6622 16K_F R6623 R0402
1.24K_F 2.2K_F 15K_F

1
1
R0402 PSYS R6624 5.1M_F R0402

IMON_CORE
R0402 R0402 20.0_J 18.2K_F 1K_F 1 R66 72 2
R0402 R0402 ALLSYSPWRGD 50

1
SHORT_0402
1 2 R0805
1

1
+VSYS_CPU C6607

2
R6658 2.2_J
1UF/6.3V,X5R

2
R6627
2

2
C0402
C6606

2
10K_F
1

R6651 R6641
3k_F R0402 0.22uF/25V,X7R

1
R66 26 2k_F

12

41
38

36
35
27

43

34

37
11

46
C0603

1
SHORT_0402
R0402 R0402

VDIO
VCLK
IMON_SA
VIN

ALERT#
TSEN_CORE

IMON_CORE

EN
VRHOT
TSEN_GT

IMON_GT

VREF06/PSET
2

PSYS
1

59 PSYS
C C
UGATE_CORE UGATE_CORE_R
50 21 1 R6628 2
PSYS UGATE_CORE ns UGATE_CORE_R 67
100.0_F R6630 AU1_SET1 PHASE_CORE SHORT_0603 EMPTY C0402
2 1 2 20
SET1 PHASE_CORE PHASE_CORE 67 C6608 1pF 50V NPO R6674 1M_J R0402
R0402 2.2_F 0.1UF/50V,X7R IMON_CORE
AU1_SET2 BOOT_CORE 1 2 1 2
5 22 1 2C6604
1 2
12 VSSSENSE SET2 BOOT_CORE R0603 C0603
AU1_SET3 LGATE_CORE R6629 LGATE_CORE_R ns ns Close to IC
6 19 1 R6631 2
SET3 LGATE_CORE ns LGATE_CORE_R 67
SHORT_0603
Difference pair 52
UGATE_SA
EMPTY
UGATE_SA_R
R6655 RGND_CORE
2 R66 32
GND
1 1 2 1 2 1 2 15 1 R6652 2
12 VCCSENSE VSEN_VCORE UGATE_SA ns UGATE_SA_R 67
SHORT_0402 R6653 10K_F R0402 51
PHASE_SA SHORT_0603 EMPTY
R0402 18k_F R0402 VSEN_CORE
100.0_F R6654 49.9k_F COMP_CORE 16
PHASE_SA 67
R0402 PHASE_SA
+VCC_CORE R6634
1 2 C6616 1 2 2 1 4
BOOT_SA R6633 2.2_F R0603 C6614 0.1UF/50V,X7R C0603
C0402 COMP_CORE
C6602 FB_CORE 14 1 2 1 2
C0402 BOOT_SA
2 1 330pF/50V,NPO 56PF/50V,X7R 3
FB_CORE LGATE_SA LGATE_SA_R
R6649 17 1 R6638 2
R0402 LGATE_SA ns LGATE_SA_R 67
12 VSSGT_SENSE 100.0_F 29
PWM_VCC SHORT_0603 EMPTY
RGND_GT

RT3602AH
Difference pair VSEN_GT
31
PWM_CORE
40
PWM_VCC 67
VSEN_GT
R6636 COMP_GT UGATE_GT UGATE_GT_R
1 R66 68 2 1 2 2 1 33K_F 30 25 1 R6635 2
12 VCCGT_SENSE R0402 R0402 COMP_GT UGATE_GT ns UGATE_GT_R 67
SHORT_0402 R6659 10K_F FB_GT PHASE_GT SHORT_0603 EMPTY
28 24
PHASE_GT 67
1R6637 2 100.0_F R0402 1 2 1 2
FB_GT U6601 PHASE_GT
BOOT_GT C6611 0.1uF/25V,X5R C0402
+VCC_GT
C6615 C0402 RT3602AH 26 1 2 2 1
BOOT_GT
C6610 330pF/50V,NPOC0402 120pF/50V,NPO 47
LGATE_GT R6663 2.2_F R0603 LGATE_GT_R
COMP_SA COMP_SA
23 1 R6657 2
LGATE_GT_R 67

ISEN2N_CORE

ISEN1N_CORE
ISEN2P_CORE

ISEN1P_CORE
LGATE_GT ns
100.0_F R6644 R0402 10K_F 49 SHORT_0603 EMPTY

ISEN1N_GT
FB_SA

ISEN1N_SA
ISEN1P_GT
VR_READY

ISEN1P_SA
R0402 R0402 FB_SA
+VCC_SA R6648 1 2 1 2 R6665 1 2 39K_F

DRVEN
48 53

PVCC
RGND_SA GND

VCC
1 R66 50 2 1 2 2 1
10 VCCSA_SENSE
SHORT_0402 C6609
Difference pair C6613 270pF/50V,X7RC0402

42

13

18

39

32

33

45

44

10
68PF/50V,NPO ISEN1P_CORE
C0402
10 VSSSA_SENSE ISEN1N_CORE ISEN1P_CORE 67

ISEN1P_GT

ISEN1N_SA

ISEN1P_SA
R6670 ISEN2P_CORE ISEN1N_CORE 67

DRVEN
7 VR_PWRGD ISEN2P_CORE 67
2 1 R6643 10K_F R0402
1 2
+V3P3A

1
100.0_F +V5P0A
1 2 C6619
R0402 1 2 C0402
R6666 +V5P0A 0.1UF/10V,X5R

DRVEN

67
4.7_J

2
R0603 R6669
5.1_F

1
C6605 R0603
10uF/6.3V,X5R

1
C0603 C6603
1UF/6.3V,X5R

2
C0402

2
B B

67
67

67

67

67
ISEN1P_GT

ISEN1P_SA
ISEN1N_GT

ISEN1N_SA

ISEN2N_CORE
1

1
C6601 C6617 C6618
C0402 C0402 C0402
0.1UF/10V,X5R 0.1UF/10V,X5R 0.1UF/10V,X5R

2
A A

Bitland Information Technology Co.,Ltd.

Page Name
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Si ze
Project Name Rev
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Veneno 1.3
Dat e: Friday, August 23, 2019 Sheet 66 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

+VSYS

+VSYS_CPU

1
1
C6702 C6707 C6708 T + CE6701
1UF/25V,X5R 10uF/25V 10uF/25V 33uF/25V
C0603 C0603 C0603 tc7343

2
ns
D GND GND GND GND D
3
D1[0]
4
D1[1]
9
D1[2]

+VCC_CORE
UGATE_CORE_R
1
66 UGATE_CORE_R G1
5
D2/S1[0]
PHASE_CORE
2 6
66 PHASE_CORE S1/D2 D2/S1[1]
7
1
PL6701
2 RDC=1.8m ohm TDC=48A (U42) ICCMAX=80A
D2/S1[2] 0.22uH_25A
LGATE_CORE_R l_2p_6d6x7d3
8

1
66 LGATE_CORE_R G2 C6714 0.47uF/25V,X7R CE6702
1 2 1 2 C0603 T + 330uF/2V
TC7343

2
R6701
453.0_F

2
R6716 R0402

S2
1.0_J
R0603 GND
Q6703

10
AOE6932 1 2
SN1_CORE

1
<PACKAGE>
I R6702

1
C6715
715.0_F
1000pF/50V,X7R R0402
C0402

2
GND

66 ISEN1P_CORE

R67 22 1 2 SHORT_0201
66 ISEN1N_CORE

+V5P0A
+VSYS_CPU
2

C C
R6715
10_J
R0603

1
C6705 C6722 C6723
3 1UF/25V,X5R 10uF/25V 10uF/25V
1

D1[0] C0603
R6714 0_J R0603 4 C0603 C0603
1 2 D1[1]

2
9
D1[2]
C6764
1
1

C6701 0.1uF/25V,X5R GND GND GND

C0402 +VCC_CORE
1UF/10V,X5R
C0402 U6701
2
2

1
G1
4 3 5
BOOT UG D2/S1[0]
8
VCC PH
2 2
S1/D2 D2/S1[1]
6 1
PL6702
2 RDC=1.8m ohm
0.22uH_25A
2 R67 21 1 SHORT_0402 5 7 7 l_2p_6d6x7d3
66 PWM_VCC PWM LG D2/S1[2]
2

1
CE6703

2
2 R67 17 1 SHORT_0402 1 6 8 R6703 T + 330uF/2V
66 DRVEN EN GND G2 TC7343
9 1.0_J R6704
EPAD
R0603 453.0_F

2
RT9610C R0402
1

C10986
1

GND
10PF/50V,NPO
S2

1
1

C0402 C6730
2

Q6704 1000pF/50V,X7R
10

20190107:Add C10986 AOE6932 C0402

<PACKAGE> 0.47uF/25V,X7R
2

I 1 2
C6729 C0603

1 2
+VSYS_CPU
R6705
ISEN2P_CORE 715.0_F
66 ISEN2P_CORE R0402

5
D Q6701

1
R67 18 1 2 SHORT_0201 C6703 C6752 C6753
66 ISEN2N_CORE EMB12N03V
1UF/25V,X5R 10uF/25V 10uF/25V
UGATE_SA_R C0603 C0603 C0603
4 dfn8_0d65_3x3

2
66 UGATE_SA_R G
S +VCC_SA

GND GND GND

TDC=4A (U42) ICCMAX=6A

1
2
3
PHASE_SA PL6705
1 2
66 PHASE_SA
0.47uh

5
l_2p_6d6x7d3

2
D Q6702

1
B EMB12N03V B

LGATE_SA_R R6710
4 G dfn8_0d65_3x3 1.0_J R6711
66 LGATE_SA_R R0603
S 562.0_F
R0402
SN_VCCSA

1
2
3

2
0.47uF/25V,X7R

1
C6759 1 2
1000pF/50V,X7R C6758 C0603
+VSYS_CPU C0402 R6712
R6713
20.0_J

2
R0402 715.0_F
1 2 1 R0402 2
GND
1

ISEN1P_SA NTC_10K
1

C6704 C6737 C6738 T + CE6704 1 2

1UF/25V,X5R 10uF/25V 10uF/25V 33uF/25V 66 ISEN1P_SA R0402
C0603 tc7343 RT6703
C0603 C0603
2

ns
R67 20 1 2 SHORT_0201
GND GND GND GND 66 ISEN1N_SA

3
D1[0]
D1[1]
4 LL/IMONA Compesation
9
D1[2] +VCC_GT

UGATE_GT_R
66 UGATE_GT_R
1
G1
5 1
PL6703
2
RDC=1.8m ohm TDC=21A (U42) ICCMAX=31A
D2/S1[0]
PHASE_GT 0.22uH_25A
2 6 l_2p_6d6x7d3
66 PHASE_GT S1/D2 D2/S1[1]
2

CE6705
2

7 T + 330uF/2V
D2/S1[2] TC7343
LGATE_GT_R R6707
8 R6706
66 LGATE_GT_R 1.0_J
G2
2

R0603 562.0_F
R0402
SN_VCCGT
1

GND
1
1

C6745 0.47uF/25V,X7R
1000pF/50V,X7R 1 2
S2

C0402 C6744 C0603

2

Q6705 392.0_F
10

AOE6932 200.0_F R0402

<PACKAGE> GND 1 2 1 2
I R6708 R0402 R6709

ISEN1P_GT NTC_10K
1 2
A 66 ISEN1P_GT R0402 A
RT6702

ISEN1N_GT
R67 19 1 2 SHORT_0201
66 ISEN1N_GT

Bitland Information Technology Co.,Ltd.

Page Name
PWR-VCC_CORE/GT/SA
Si ze
Project Name Rev
D
Veneno 1.3
Dat e: Friday, August 23, 2019 Sheet 67 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

D D

R6808
1 2
+1.8V_PRIM R0603 ns 0.01_F

C C

1 R6809 2
VDD1V2_VIN
+V3P3A
SHORT_0603
+V5P0A

1
C6801

2
10uF/6.3V,X5R
C0603 R6801

2
10K_J

1
R0402 C6802
1UF/6.3V,X5R

8
C0402 U6801

VIN1

VIN2
10 2 VO 1 R6810 2
VDD1V2
VPP VO1

2
SHORT_0603
VDD1V2_EN 6
VEN
3
R6802 MAX CURRENT=0.6A
VO2 4.99K_F
5

1
POK C6805

1
R0402 C6804
10uF/6.3V,X5R
11 4 10uF/6.3V,X5R

1
C6803 PAD ADJ C0603
ADJ C0603

NC2

NC1

2
0.1UF/10V,X5R

2
2
C0402
G9661-25ADJRE1U

2
Option = ns R6803

1
I
10K_F
R0402

1
B B

A A

Bitland Information Technology Co.,Ltd.

Page Name

Vinafix.com
PWR-CPU VR RT3602AH
Size Project Name Re v
C
Veneno 1.3
Date: Friday, August 23, 2019 Sheet 68 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

RG6910
10.0_J
R0603 RG6911
1 2 1 2
+V5P0A R0603 2.2_J
I-DIS
I-DIS

1
CG6908 CG6909
4.7uF/6.3V,X5R 0.1uF/25V,X7R
C0402 C0603

+MVDD_BOOT 2
D
CG6910 1 2 0.01UF/25V,X7R I-DIS D

+MVDD_VCC
C0402
I-DIS

+MVDD_VIN
+MVDD_SS
+MVDD_LX
+MVDD_AGND

23

22

21

20

18

25
19
1 RG6909 2
81 VRAM_EN
SHORT_0402

VIN2

LX4

LX5
SS

VCC

BST

PGND4
2
RG6944
100K_J 1 17
50 VRAM_PWRGD PGOOD LX3
R0402

I-DIS +MVDD_EN 2 16

1
EN LX2

+MVDD_PFM
+MVDD_AGND +V5P0A
1 2 3
PFM# UG6902 PGND3
15

RG6918 G5335QT1U

2
12/29 power request pull high with EE
0_J
RG6912
TQFN23_PH0P5_4X4_H0P8
R0402 +MVDD_AGND
4
AGND I-DIS PGND2
14

ns 100K_J
R0402 +MVDD_FB
+V3P3A NI 5
FB PGND1
13

+MVDD_OUT

1
I-DIS +MVDD
2

6 12
TON PGND0
RG6913
100K_J

VIN0

VIN1

VIN3
+MVDD_AGND

LX0

LX1
+MVDD_TON
R0402

NC
RG6919
I-DIS 0_J
VRAM_PWRGD

24

10

11
1

1 2 R0402
12 1 2
FB_VMEMIO 79
2017/3/8

+MVDD_LX
C JS6302 RG6917
LG6901 NI C
SHORT PAD 80.6K_F
1.0uH ±20% 6.7mΩ 12A 15A
ns
60X30Mil +MVDD_AGND R0402 l_2p_6d6x7d3
NOBOM 1 2 1 2

ns I-DIS

1
CG6917 CG6918 CG6919 CG6920 CG6926
I-DIS RG6914 RG6915 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 0.1uF/25V,X5R
C0603 C0603 C0603 C0603 C0402
2.2_J 6.98K_F
I-DIS I-DIS I-DIS I-DIS I-DIS

2
R0805 R0402

I-DIS
+MVDD_VIN +MVDD_FB

1
+VSYS I-DIS

1
CG6916
470PF/50V,X7R

2
1

1
CG6912 CG6913 CG6925 CG6914 CG6915 C0402
RG6916

1
10uF/25V 10uF/25V 10uF/25V ns 0.1uF/25V,X5R 1UF/25V,X5R CG6921 CG6922 CG6923 CG6924
C0603 C0603 C0603 C0402 C0603 I-DIS 10K_F 22uF/6.3V,X5R 22uF/6.3V,X5R ns 22uF/6.3V,X5R ns 22uF/6.3V,X5R

2
ns R0402 C0603 C0603 C0603 C0603
ns
I-DIS I-DIS NI NI I-DIS I-DIS NI NI

2
I-DIS
NI

1
+MVDD_AGND

1 2
+VDD33_EN 1 RG6901 2
B 6,81 PX_EN +VDD33_EN 64,81 +V3P3A B
SHORT_0603 UG6901
1

1
RG6903 CG6901 CG6905 G9661-25ADJF11U
1K_F 0.1UF/10V,X5R 10uF/6.3V,X5R SOP8_PH1P27_4X5_H1P6_G1
R0402 C0402 C0603
I-DIS I-DIS
2

2
I-DIS I-DIS
1V8_AON_VIN 3 1
GND VIN POK
1V8_AON_EN 1V8_AON_OUT RG6902
2 1 2
VEN VO
6 1 2
1V8_AON
RG6904 1V8_AON_ADJ SHORT_0603
1

2
CG6902 5 7
10K_F NC ADJ

1
0.1UF/10V,X5R RG6907 CG6907
R0402 C0402 4 8 10uF/6.3V,X5R
+V5P0A 13K_F
I-DIS VPP GND
2

I-DIS delay 20mS R0402

C0603
I-DIS

TP

2
I-DIS

1
CG6906

1
GND 1UF/6.3V,X5R
C0402

2
I-DIS

2
RG6908
10.5K_F
R0402

I-DIS

1
VDDC_EN
2 1
VDDC_EN 70
RG6905
1

10K_F CG6903
R0402 0.1UF/10V,X5R
C0402
I-DIS
2

I-DIS
A A

GND
VRAM_EN_R
1 2
VRAM_EN_R 81
RG6906
Bitland Information Technology Co.,Ltd.
1

60.4K_F CG6904
R0402 0.1UF/10V,X5R
Page Name

Vinafix.com
I-DIS C0402
GPU-VRAM
2

2018/06/26 I-DIS Size Project Name Re v

Change RG563 from NI to I C
20180716 Veneno 1.3
Change RG563 from 10K to 60.4K GND Date: Friday, August 23, 2019 Sheet 69 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

70: GPU POWER

+V5P0A

2
D D
U9021
RG15
nsRG14 4.7_J
SHORT_0603 R0603
SHORT PAD

RT3662AC

1
I-DIS 17 28 VIN_1
VCC VIN VIN_1 71
RNTC2P
71 RNTC2P
VREF_PINSET
TSEN
71 TSEN
RNTC2P_NB
72 RNTC2P_NB CG11 CG12

1
TSEN_NB 2.2UF/6.3V,X5R 2.2UF/6.3V,X5R

2
72 TSEN_NB C0402 C0402 38 BOOT1 BOOT1 71
RG21 RG16 RG22

2
BOOT1
34
750K_F 68K_F 267K_F PVCC
R0402 r0201 R0402 I-DIS I-DIS

37 UG1

1
UGATE1 UG1 71
I-DIS I-DIS I-DIS

RNTC2P TSEN
36 PH1 PH1 71
PHASE1
+VDD33 SET1 13
SET1
2

1 2 12
TSEN
RG24 RG23 187K_F R0402
18.2K_F I-DIS TSEN_NB 23 35 LG1 LG1 71
RNTC2P_NB TSEN_NB LGATE1
1

CG13 R0402
2

2
0.1uF/10V,X5R RG29 1 2
C0201 10K_J RG25 RG26 RG27 187K_F R0402
2

I-DIS r0201 I-DIS 34K_F 24.3K_F I-DIS

29
R0402 R0402 69 VDDC_EN EN
1

1
I-DIS
CG14
1

1
2

1000pF/25V,X5R 9 ISEN1P
NVVDD_PGOOD

C I-DIS I-DIS ISEN1P ISEN1P 71 C

RG6945 c0201

2
390_F I-DIS
10 ISEN1N ISEN1N 71
ISEN1N
R0402
1

I-DIS

2 BOOT2 BOOT2 71
BOOT2

1V8_AON 1V8_AON
RG34 1 2 2.2_J R0402 22 1 UG2 UG2 71
VDDIO UGATE2

1
CG16
I-DIS
1UF/6.3V,X5R
C0402
40 PH2
2

PHASE2 PH2 71
1

CG15 I-DIS
0.1uF/10V,X5R
2

C0201
RG35
2

4.7K_F I-DIS
39 LG2 71
R0201 LGATE2
1

I-DIS

18
74 GPU_PWROK PWROK

76 SVC R11613 2 1 SHORT_0201 19 7 ISEN2P ISEN2P 71

SVC ISEN2P

76 SVD R11612 2 1 SHORT_0201 20 8 VSEN

SVD VSEN

76 SVT 21
B SVT CG17 CG18 330pF/16V,X7R C0201 B

74 NVVDD_PGOOD 3 5 COMP 1 2 82pF/50V,NPO 1 2

PGOOD COMP
GPUVR_HOT 11
SVC 76 GPUVR_HOT VRHOT_L RG46 1 2 28.7K_F r0201 RG49 1 2 10K_F r0201
SVD C0402
SVT I-DIS I-DIS I-DIS
6 FB
IMON_NB IMON 14
FB
IMON
1

CG19 CG20 CG21 4 RGND

RGND VSEN
2

0.1uF/10V,X5R 0.1uF/10V,X5R 0.1uF/10V,X5R

C0201 C0201 C0201 RG57 FB_VDDC
RG51 16
2

ns FB_VDDC 79
2

IMON_NB
ns ns ns RG54 180_F SHORT_0402
NI NI NI RG58 SHORT
1 PAD 2 100_F R0201
6.34K_F RNTC1N 71 R0201 VDDC
I-DIS
1

1
R0201 RG53 1K_F CG23 CG24 I-DIS

1
RNTC1N 1 2 CG25
1

I-DIS 0.47uF/10V,Y5V 0.1uF/10V,X5R

0.1uF/10V,X5R
RNTC1N_NB RG55 10K_F R0402 C0402 C0201
1

1 2 ns C0201
2 2

2
2

72 RNTC1N_NB I-DIS

2
r0201
I-DIS NI ns
2

I-DIS
RG60 NI
RG64 1 2 100_F R0201
RG59 RNTC1P 71 8.45K_F RG45
12K_F r0201 4.7_J 15 RG63 I-DIS FB_VSSC
VREF_PINSET
R0201
RG62 15K_F
I-DIS R0603
BOOT_NB
ns SHORT_0402 FB_VSSC 79
1

Vinafix.com
I-DIS RNTC1P 1 2 30
1

BOOT_NB BOOT_NB 72 SHORT PAD

I-DIS
1

RG65 2K_F R0201

RNTC1P_NB 1 2 I-DIS
72 RNTC1P_NB
R0201
I-DIS 31 UG_NB
UGATE_NB UG_NB 72
VREF_PINSET

32 PH_NB
PHASE_NB PH_NB 72

A LG_NB A
CG27 27 33 LG_NB 72
CG26 330pF/16V,X7R C0201 COMP_NB COMP_NB LGATE_NB
FB_VDDCI RG73 VSEN_NB 1 2 1 2
79 FB_VDDCI ns C0402 33PF/50V,NPO
SHORT_0402
SHORT PAD RG68 RG71 80.6K_F R0201
2 1 1 2
VDDCI RG72 100_F R0201 Bitland Information Technology Co.,Ltd.
1 2 10K_J FB_NB 26
I-DIS I-DIS FB_NB
Page Name
r0201
GPU Vcore1
1

C10270 CG29 ISENP_NB

I-DIS I-DIS 25 ISENP_NB 72
0.1uF/10V,X5R 0.1uF/10V,X5R ISENP_NB
Size
C0201 C0201 ISENN_NB Project Name Rev
ns RG74 100_F R0201 ns Custom
41 24
Veneno
2

RG76 GND ISENN_NB ISENN_NB 72

NI 1 2 NI RGNDA RGND VA
ns SHORT_0402 Date: Wednesday, August 21, 2019 Sheet 70 of 87
I-DIS
SHORT PAD PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
I-DIS documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

+VSYS +VSYS_GPU

D D

RT_5, RT_6 close

to LG2.
RT_5 NTC_100K R0402

70 RNTC2P RNTC2P 1 2 TSEN TSEN 70

RT_6
I-DIS
NTC_100K R0402
+VSYS_GPU
VIN_1 RG78 1 2 4.7_J R0603 RNTC1P 1 2 RNTC1N
70 VIN_1 70 RNTC1P RNTC1N 70
1

CG6927
I-DIS
0.1uF/25V,X5R
I-DIS

1
C0402 CG31 CG32 CG33
0.1uF/25V,X5R 10uF/25V 10uF/25V
2

5
I-DIS QG3 C0402 C0603 C0603
ns

2
EMB09N03HR
UG1 4
dfn8_1d27_5x6 NI I-DIS I-DIS
70 UG1

G
VDDC

S
RG80 2.2_J
70 BOOT1 BOOT1 1 2

3
2
1
I-DIS
1

R0603 CG34
I-DIS 0.1UF/10V,X5R
C0402
20190107:LG2 change from 0630 to 0640,DCR=0.98mOHM
LG2
2

70 PH1 PH1 I-DIS 1 2

0.22uh

2
l_2p_6d6x7d3
QG4
RG82
EMB04N03HR I-DIS
5

2.2_J
5

dfn8_1d27_5x6
D

R0805
D

QG11
LG1 4 ns I
70 LG1 LG1 4 EMB04N03HR 1
CG42
G

RG84 1.1K_F
G

dfn8_1d27_5x6
1

C CG41 C
S

1 2 1 2
S

1000pF/50V,X7R
3
2
1

1
C0402 R0402 CG35 CG36 CG38
3
2
1

NI 0.47uF/10V,Y5V
2

T + 330uF/2V T + 330uF/2V T + 330uF/2V

I-DIS I I-DIS C0402 TC7343 TC7343 TC7343
I-DIS

2
RG86 1.47K_F I-DIS I-DIS I-DIS
70 ISEN1P ISEN1P 1 2

R0402
70,71 ISEN1N ISEN1N RG87 1 2 1_F R0402
I-DIS

1
20190108:RG86 from 422R to 1.47K CG48 CG49 CG50 CG51 CG52 CG53 CG54 CG55 CG56
I-DIS C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
1

CG47 +VSYS_GPU 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R

2
0.1UF/10V,X5R ns
C0402 I-DIS I-DIS NI I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS
2

I-DIS
1

CG57 CG58 CG59

0.1uF/25V,X5R 10uF/25V 10uF/25V
5

QG6 C0402 C0603 C0603

1
ns CG60 CG61 CG62 CG63 CG64 CG65 CG66 CG67 CG68
D

EMB09N03HR C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
UG2 4
dfn8_1d27_5x6 NI I-DIS I-DIS 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
70 UG2

2
G

I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS

S

RG89 2.2_J
70 BOOT2 BOOT2 1 2
3
2
1

CG69 I-DIS
1

R0603
I-DIS 0.1UF/10V,X5R
C0402
20190107:LG4 change from 0630 to 0640,DCR=0.98mOHM
LG4
2

70 PH2 PH2 I-DIS 1 2

0.22uh

1
l_2p_6d6x7d3 CG70 CG71 CG72 CG73 CG74 CG75 CG76 CG77 CG78
2

C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603

RG93 I-DIS 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
5

B B

2
2.2_J
5

ns ns ns
I-DIS I-DIS I-DIS I-DIS I-DIS
D

QG7 R0805
NI NI I-DIS NI
D

QG12
LG2 EMB04N03HR ns CG80
70 LG2 4
LG2 4 EMB04N03HR I RG94 1.1K_F
1
G

dfn8_1d27_5x6
G

dfn8_1d27_5x6 1 2 1 2
1

CG79
S

1000pF/50V,X7R R0402
3
2
1

C0402 0.47uF/10V,Y5V
3
2
1

I-DIS I-DIS
2

NI I C0402

I-DIS
1

1
CG306 CG302 CG305 CG304 CG303 CG301
RG97 1.47K_F C0603 C0603 C0603 C0603 C0603 C0603

70 ISEN2P ISEN2P 1 2 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R

2

2
R0402
NI NI NI NI NI NI
70,71 ISEN1N ISEN1N RG95 1 2 1_F R0402
Option = ns Option = ns Option = ns Option = ns Option = ns Option = ns
I-DIS
I-DIS 20190108:RG97 from 422R to 1.47K
1

CG82
0.1UF/10V,X5R
C0402
1

1
CG315 CG311 CG314 CG313
2

Option = ns C0603 C0603 C0603 C0603

NI 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R

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2

2
NI NI NI I-DIS
Option = ns Option = ns Option = ns

A A

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Page Name
GPU Vcore2
Size
Project Name Rev
Custom
V540 V1.0
Date: Thursday, August 22, 2019 Sheet 71 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

D D

RT_7, RT_8 close

to LG3.
RT_7 NTC_100K R0402
RNTC2P_NB 1 2 TSEN_NB
70 RNTC2P_NB TSEN_NB 70
I-DIS
RT_8 NTC_100K R0402
RNTC1P_NB 1 2 RNTC1N_NB
70 RNTC1P_NB RNTC1N_NB 70
I-DIS

+VSYS_GPU

1
CG83 CG84 CG85
0.1uF/25V,X5R 10uF/25V 10uF/25V
5

QG9 C0402 C0603 C0603

ns
D

2
EMB09N03HR NI I-DIS I-DIS
UG_NB dfn8_1d27_5x6
C 4 C
70 UG_NB
G

BOOT_NB RG102 2.2_J

70 BOOT_NB 1 2
3
2
1

I-DIS
1

R0603 CG86 VDDCI

I-DIS 0.1UF/10V,X5R 20190107:LG3 change from 0630 to 0640,DCR=0.98mOHM
C0402
LG3
2

PH_NB I-DIS 1 2
70 PH_NB
0.22uh
l_2p_6d6x7d3
2

RG104 I-DIS
2.2_J
5

R0805
D

QG10 I
RG106
LG_NB EMB04N03HR 665_F CG93
4
1

70 LG_NB R0402

1
G

dfn8_1d27_5x6 1 2 1 2 CG87 CG88

T + 330uF/2V T + 330uF/2V
1

CG92
S

1000pF/50V,X7R TC7343 TC7343

0.47uF/10V,Y5V
3
2
1

C0402
I-DIS
2

2
I C0402
I-DIS I-DIS
I-DIS
20190108:RG106 from 622R to 665R

RG109 2.7K_F
ISENP_NB 1 2
70 ISENP_NB

1
CG95 CG96 CG97 CG98 CG99 CG100 CG101 CG102
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
R0402 I-DIS
22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R
ISENN_NB

2
70 ISENN_NB RG324 1 2
I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS
SHORT_0402
1

CG94 20190108:RG109 from 422R to 2.7K

0.1UF/10V,X5R
C0402
2

I-DIS
B B

1
CG103 CG104 CG105 CG106 CG107 CG108 CG109 CG110
C0603 C0603 C0603 C0603 C0603 C0603 C0603 C0603
22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R 22uF/6.3V,X5R

2
I-DIS I-DIS I-DIS I-DIS

Option = ns Option = ns Option = ns Option = ns

NI NI NI NI

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A A

Bitland Information Technology Co.,Ltd.

Page Name
GPU Vcore3
Size
Project Name Rev
Custom
V540 V1.0
Date: Wednesday, August 21, 2019 Sheet 72 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

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 5 4 3 2 1

Power Map +VSYS_3V3 U6002

V3.3A_EN
+V3P3A
IMAX 5A
Jumper
RICHTEK Jumper 1V8_AON_EN
RT6258B GMT UG301 1V8_A O N
Jumper G9661 IMAX 1.5A For GPU

+V3.3A_PW RGD
D GMT U6501 +1. 8 V _ P R I M D
Jumper G9661 IMAX 0.72A
SOURCE
+V5CP
V5CP_EN
Type-c
+VBUS_TYPEC
U5314 SOURCE_EN
G518 +VSYS_5V
U6001
+V5 C P
IMAX 8A
Jumper RICHTEK Jumper

RT6258C
+VSYS_V3p3_VIN
MPS U6003 +V3 . 3 A L
PU2 Adapter MP2322 Jumper
100mA
ETA7015E8A
Jumper
SINK_EN

SM_PG_CTRL
EC_SLP_S4_N
+VSYS_VDDQ
U6101 +V1P2U_VDDQ
Jumper GMT IMAX 8A
SINK G5416 +V2P5U_VPP
C
U11
DCIN IMAX 1A Converter C

+V0.6S_VTT
NX20P5090 IMAX 0.6A
U5901 +VSYS
AC_DET
Charger
IS9238 V1.0_VIN
GMT U6301
+1.8V_PW RGD Controller
+1.0V_PRIM
Jumper G5335Q IMAX 10A
BATT+
MOS
DualMOS +VCC_CORE
AOE6932
Battery IMAX 70A
4S1P RICHTEK U6701 DualMOS Driver
BatteryCharge RT9610C AOE6932
+VSYS_CPU U6601
RICHTEK +VCC_GT
Jumper
RT3602AH
DualMOS
AOE6932 IMAX 31A LDO
B NMOS B
EMB12N03V +VCC_SA
IMAX 6A
NMOS
EMB06N03V
SWITCH

NMOS
AON6380*2 VDDC
IMAX 55A For GPU

U9021 NMOS
AON6324 *2
+VSYS_GPU RICHTEK Phase*2
Jumper
RT3662AC
NMOS
AON6380 VDDCI
IMAX 12A For GPU

NMOS
AON6324

VRAM_VIN
U6902 +MVDD

A Jumper GMT IMAX 8A For GPU Bitland Information Technology Co.,Ltd.

A

G5335Q For GPU Page Name

73
Size
Project Name Rev
B
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 73 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com

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 1 2 3 4 5

D6608
0.37V_30mA_LRB751V-40T1G
A PEX_GPU_RST# 2 1
A
ns GPIO_19_CTF_R 29
sod323
I-DIS

RG011 1 2 47K_J r0201

76 GPIO_19_CTF ns
UG1B

I-DIS symbol2

AT41 AV35
PCIE_TXP0 CG111 1 2 0.22uF/6.3V,X5R C0201
PCIE_RX0P PCIE_TX0P
9 PCIE_CTX_GRX_P0 PCIE_TXN0 PCIE_CRX_GTX_P0 9
AT40 PCIE_RX0N PCIE_TX0N AU35 CG112 1 2 0.22uF/6.3V,X5R C0201
9 PCIE_CTX_GRX_N0 PCIE_CRX_GTX_N0 9
PCIE_TXP1
AR41 PCIE_RX1P PCIE_TX1P AU38 CG113 1 2 0.22uF/6.3V,X5R C0201
9 PCIE_CTX_GRX_P1 PCIE_TXN1 PCIE_CRX_GTX_P1 9
AR40 PCIE_RX1N PCIE_TX1N AU39 CG114 1 2 0.22uF/6.3V,X5R C0201
9 PCIE_CTX_GRX_N1 I-DIS PCIE_CRX_GTX_N1 9
AP41 AR37
PCIE_TXP2 CG115 1 I-DIS 2 0.22uF/6.3V,X5R C0201
PCIE_RX2P PCIE_TX2P
9 PCIE_CTX_GRX_P2 PCIE_TXN2 PCIE_CRX_GTX_P2 9
AP40 PCIE_RX2N PCIE_TX2N AR38 CG116 1 2 0.22uF/6.3V,X5R C0201
9 PCIE_CTX_GRX_N2 I-DIS PCIE_CRX_GTX_N2 9
AM41 AN37
PCIE_TXP3 CG117 1 I-DIS 2 0.22uF/6.3V,X5R C0201
PCIE_RX3P PCIE_TX3P
9 PCIE_CTX_GRX_P3 PCIE_TXN3 PCIE_CRX_GTX_P3 9
AM40 PCIE_RX3N PCIE_TX3N AN38 CG118 1 2 0.22uF/6.3V,X5R C0201
9 PCIE_CTX_GRX_N3 I-DIS PCIE_CRX_GTX_N3 9
AL41 AL37 I-DIS
PCIE_RX4P PCIE_TX4P
AL40 PCIE_RX4N PCIE_TX4N AL38
I-DIS
AK41 AJ37 I-DIS
PCIE_RX5P PCIE_TX5P
AK40 PCIE_RX5N PCIE_TX5N AJ38

AJ41 PCIE_RX6P PCIE_TX6P AG37

AJ40 PCIE_RX6N PCIE_TX6N AG38

AH41 PCIE_RX7P PCIE_TX7P AE37

AH40 PCIE_RX7N PCIE_TX7N AE38

R0201 PEX_GPU_RST#
B AV33 PCIE_REFCLKP PERSTB AV41 RG110 1 2 33_J B
7 CLK_PCIE_GPU AU33 PCIE_REFCLKN
7 CLK_PCIE_GPU# AC41
GPU_PX_EN I-DIS
PX_EN

2
RG111
+VDD33 20190228:AMD suggest Reserve +V3P3A for UG8 PIN5
20190423:Adjust DGPU MS power sequence,change R11581 to install, 1K_J
and change R11582 to NI
+V3P3A +VDD33 R0201
PCIE_ZVSS
AU41 ns

1
PCIE_ZVSS
2

REV 0.91 NI

2
RG463

2
I-DIS
10K_J R11581 R11582
SHORT_0402 0_J

2
r0201 ns
ns R0402 RG112

1
NI
1

200_F
DGPU_HOLD_RST# UG8A

1
1 CG237 R0201
6 DGPU_HOLD_RST# PEX_GPU_RST#
4 1V8_AON
1 2
2

1
7,26,35,43,50 PLT_RST_N I-DIS

5
JTAG
2

SN74LVC1G08DBV 0.1uF/10V,X5R
RG016 I-DIS
C0201
<option>
10K_J I-DIS
2

2
r0201 RG017 UG8B
I-DIS RG113
100K_J SN74LVC1G08DBV RG115

3
10K_J
1

I-DIS 10K_J +VDD33

R0402
<option>
I-DIS
r0201
1

r0201 UG1A

2
symbol1
I-DIS I-DIS BP_0 JTAG_TDO
AA38 BP_0 JTAG_TDO AF41 RG117
BP_1
AA37 AD40
JTAG_TDI TP10049
BP_1 JTAG_TDI
JTAG_TMS TP10050 1K_J
JTAG_TMS AD41
C
AE41
JTAG_TCK TP10051 C
JTAG_TCK R0201
RG6920 TP10052
JTAG_TESTEN ns

1
2 1 DIECRACKMON B2 TEST6 TESTEN AE40 NI
JTAG_TRSTB AF40
+VDD33
10K_J
r0201 REV 0.91
RG119 1 2 1K_J R0201
I-DIS

2
I-DIS
I-DIS RG120
RG121 1 2 1K_J R0201
1V8_AON 1K_J

ns R0201
NI

1
I-DIS

2
D6816
CG243
NVVDD_PGOOD 1 0.1uF/10V,X5R

1
GPU_PWROK C0201
3
I-DIS
PEX_GPU_RST# 2 UG1J
symbol10

AM13 TSVDD DPLUS N35

0.52V_200mA_LBAT54ALT1G
sot23-3

+VDD33 J8 TEMPIN0
DMINUS N34
CG256
J7 TEMPINRETURN
1
UG11A 1 2
70 NVVDD_PGOOD R0201
4 U38 RG307 1 2 1K_J
5

ns GPIO_28_FDO
PEX_GPU_RST# GPU_PWROK 70
2 UG11B 0.1uF/10V,X5R N38 TS_A

C0201 ns
SN74LVC1G08DBV ns
I-DIS REV 0.91 NI
D NI I-DIS D
2

SN74LVC1G08DBV
RG015
3

RG018 NI
100K_J
100K_J
R0402 R0402 Bitland Information Technology Co.,Ltd.
ns I-DIS
1

Page Name
NI
74
Size
Project Name Re v
Custom
Veneno 1.3
Date: Friday, August 23, 2019 Sheet 74 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

Vinafix.com
1 2 3 4 5

Vinafix.com
 1 2 3 4 5

UG1D
symbol 4

C2 DQB0_0 DQB1_0 AH1

80 DQA0_[31..0] UG1C
DQA1_[31..0] 80 C1 DQB0_1 DQB1_1 AH2
D2 DQB0_2 DQB1_2 AJ2
symbol 3
D1 DQB0_3 DQB1_3 AK1
0 L34 DQA0_0 DQA1_0 B27 0
F1 DQB0_4 DQB1_4 AL2
1 L37 DQA0_1 DQA1_1 A27 1
G2 DQB0_5 DQB1_5 AM1
2 L38 DQA0_2 DQA1_2 B26 2
G1 DQB0_6 DQB1_6 AM2
3 J35 DQA0_3 DQA1_3 A26 3
H2 DQB0_7 DQB1_7 AN2
4 G37 DQA0_4 DQA1_4 A24 4
K2 DQB0_8 DQB1_8 AR1
5 E38 DQA0_5 DQA1_5 B23 5
K1 DQB0_9 DQB1_9 AR2
6 E35 DQA0_6 DQA1_6 A23 6
L2 DQB0_10 DQB1_10 AT1
7 D35 DQA0_7 DQA1_7 B22 7
L1 DQB0_11 DQB1_11 AT2
8 H41 DQA0_8 DQA1_8 B20 8
N2 DQB0_12 DQB1_12 AV2
9 H40 DQA0_9 DQA1_9 A20 9
P2 DQB0_13 DQB1_13 AW1
10 G41 DQA0_10 DQA1_10 B19 10
A P1 DQB0_14 DQB1_14 AW2 A
11 G40 DQA0_11 DQA1_11 A19 11
R2 DQB0_15 DQB1_15 AY3
12 E40 DQA0_12 DQA1_12 B17 12
R1 DQB0_16 DQB1_16 BA3
13 D41 DQA0_13 DQA1_13 A16 13
T2 DQB0_17 DQB1_17 AY4
14 D40 DQA0_14 DQA1_14 B16 14
T1 DQB0_18 DQB1_18 BA4
15 C41 DQA0_15 DQA1_15 A15 15
U2 DQB0_19 DQB1_19 AY5
16 C40 DQA0_16 DQA1_16 B15 16
W1 DQB0_20 DQB1_20 BA7
17 B39 DQA0_17 DQA1_17 A14 17
W2 DQB0_21 DQB1_21 AY7
18 A39 DQA0_18 DQA1_18 B14 18
Y1 DQB0_22 DQB1_22 AY8
19 B38 DQA0_19 DQA1_19 B13 19
Y2 DQB0_23 DQB1_23 BA8
20 B36 DQA0_20 DQA1_20 A11 20
AB2 DQB0_24 DQB1_24 AR4
21 A36 DQA0_21 DQA1_21 B11 21
AC1 DQB0_25 DQB1_25 AR5
22 B35 DQA0_22 DQA1_22 A10 22
AC2 DQB0_26 DQB1_26 AU4
23 A35 DQA0_23 DQA1_23 B10 23
AD1 DQB0_27 DQB1_27 AU7
24 B33 DQA0_24 DQA1_24 B8 24
AF1 DQB0_28 DQB1_28 AN8
25 B32 DQA0_25 DQA1_25 A7 25
AF2 DQB0_29 DQB1_29 AV11
26 A32 DQA0_26 DQA1_26 B7 26
AG1 DQB0_30 DQB1_30 AU11
27 B31 DQA0_27 DQA1_27 A6 27
AG2 DQB0_31 DQB1_31 AP11
28 A30 DQA0_28 DQA1_28 A4 28
29 B29 DQA0_29 DQA1_29 B4 29
30 B28 DQA0_30 DQA1_30 A3 30
R5 MAB0_0 MAB1_0 AE7
31 A28 DQA0_31 DQA1_31 B3 31
R8 MAB0_1 MAB1_1 AE8
N7 MAB0_2 MAB1_2 AG5
80 MAA0_[8..0] MAA1_[8..0] 80 N4 MAB0_3 MAB1_3 AG4
0 G25 MAA0_0 MAA1_0 E15 0
L8 MAB0_4 MAB1_4 AJ4
1 H25 MAA0_1 MAA1_1 H15 1
N8 MAB0_5 MAB1_5 AG8
2 E27 MAA0_2 MAA1_2 G13 2
U8 MAB0_6 MAB1_6 AC8
3 D27 MAA0_3 MAA1_3 D13 3
U7 MAB0_7 MAB1_7 AC5
4 D29 MAA0_4 MAA1_4 H11 4
R4 MAB0_8 MAB1_8 AE4
5 H27 MAA0_5 MAA1_5 H13 5
L5 MAB0_9 MAB1_9 AJ8
6 H23 MAA0_6 MAA1_6 H17 6
7 E23 MAA0_7 MAA1_7 G17 7
8 D25 MAA0_8 MAA1_8 D15 8
H1 WCKB0_0 WCKB1_0 AP1
H29 MAA0_9 MAA1_9 E11
J2 WCKB0B_0 WCKB1B_0 AP2

D33 WCKA0_0 WCKA1_0 A22

80 WCKA0_0 E33 WCKA0B_0 WCKA1B_0 B21 WCKA1_0 80 AB1 WCKB0_1 WCKB1_1 AN4
80 WCKA0B_0 WCKA1B_0 80 AA2 WCKB0B_1 WCKB1B_1 AN5

A34 WCKA0_1 WCKA1_1 A8

80 WCKA0_1 B34 WCKA0B_1 WCKA1B_1 B9 WCKA1_1 80 F2 EDCB0_0 EDCB1_0 AL1
80 WCKA0B_1 WCKA1B_1 80 M2 EDCB0_1 EDCB1_1 AU2
V1 EDCB0_2 EDCB1_2 BA6
AD2 EDCB0_3 EDCB1_3 AV7
G38 EDCA0_0 EDCA1_0 B24
80 EDCA0_0 F41 EDCA0_1 EDCA1_1 A18 EDCA1_0 80
80 EDCA0_1 B37 EDCA0_2 EDCA1_2 B12 EDCA1_1 80
80 EDCA0_2 A31 EDCA0_3 EDCA1_3 B6 EDCA1_2 80 E2 DDBIB0_0 DDBIB1_0 AK2
80 EDCA0_3 EDCA1_3 80 M1 DDBIB0_1 DDBIB1_1 AV1
V2 DDBIB0_2 DDBIB1_2 AY6
AE2 DDBIB0_3 DDBIB1_3 AV9
80 DDBIA0_0 J38 DDBIA0_0 DDBIA1_0 B25
B F40 DDBIA0_1 DDBIA1_1 B18 DDBIA1_0 80 B
80 DDBIA0_1 DDBIA1_1 80
A38 DDBIA0_2 DDBIA1_2 A12
80 DDBIA0_2 B30 DDBIA0_3 DDBIA1_3 B5 DDBIA1_2 80 W8 ADBIB0 ADBIB1 AA8
80 DDBIA0_3 DDBIA1_3 80

G5 CSB0B_0 CSB1B_0 AL8

H21 ADBIA0 ADBIA1 H19
80 ADBIA0 ADBIA1 80

H31 CSA0B_0 CSA1B_0 E7

80 CSA0B_0 CSA1B_0 80

U4 CASB0B CASB1B AC4 +VMEMIO

W4 RASB0B RASB1B AA4
L4 WEB0B WEB1B AJ7
20190218:Follow AMD design guide,
D23 CASA0B CASA1B D17 +VMEMIO changed 'MVREFDB' PU from '+MVDD' to '+VMEMIO'
80 CASA0B CASA1B 80
D21 RASA0B RASA1B D19

2
80 RASA0B RASA1B 80 W5 CKEB0 CKEB1 AA7
G29 WEA0B WEA1B D11 RG123
80 WEA0B WEA1B 80 20190218:Follow AMD design guide,
changed 'MVREFDA' PU from '+MVDD' to '+VMEMIO' G4 CLKB0 CLKB1 AL5 40.2_F
J4 AL4

2
CLKB0B CLKB1B
G21 CKEA0 CKEA1 E19
81 CKEA0_GPU CKEA1_GPU 81 RG122 R0402
E31 D7 MEM_CALRB

1
80 CLKA0 CLKA0 CLKA1
40.2_F R0402
D31 CLKA0B CLKA1B D9 CLKA1 80 RG125 1 2 120.0_F R10 MEM_CALRB MVREFDB U10 MVREFDB ns
80 CLKA0B CLKA1B 80 NI
R0402 NI

1
CG255
MEM_CALRA
ns

1
RG124 1 2 120.0_F R0402 K15 MEM_CALRA MVREFDA K17 MVREFDA I-DIS DRAM_RST_B_R 1UF/6.3V,X5R
AM11 DRAM_RST B
C0402

2
REV 0.91

2
I-DIS ns

1
CG254 I-DIS
NI RG127
DRAM_RST_A_R 1UF/6.3V,X5R
RG128 1 2 49.9_F R0402 RG129 1 2 10.0_F R0402 L32
81 DRAM_RST_A_GPU
DRAM_RST A
C0402 100_F

2
REV 0.91

2
I-DIS I-DIS I-DIS I-DIS RG133 GND R0201
RG130
5.1K_J

1
100_F
1

CG127 ns
2

120pF/50V,NPO R0402
C0402 RG132 GND R0201 NI
ns
2

1
4.99K_F NI

1
I-DIS
I-DIS
1

R0201

C C

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Dat e: Wednesday, August 21, 2019 Sheet 75 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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R0402 SMB_GPUCLK
1 2 0_J ns +VDD33
29,50,52,76 EC_SMB1_CLK
RG6926 NI

2
R0402 SMB_GPUDATA
1 2 0_J ns
29,50,52,76 EC_SMB1_DATA RG6923 RG6924
RG6925 NI
4.7K_F 4.7K_F
Q8929A
L2N7002DW1T1G

1
SMB_GPUCLK R0201 R0201
29,50,52,76 EC_SMB1_CLK 3 4

S
5 G
SOT363 Del bypass circuit for UG200
Q8929B
L2N7002DW1T1G

SMB_GPUDATA
6 1
29,50,52,76 EC_SMB1_DATA COMPONENTS SHOWN ARE EXAMPLES ONLY

S
AND ARE NOT NECESSARILY QUALIFIED

2 G
A +VDD33 A

SOT363

2
RG335 +VDD33
+VDD33 10K_J
r0201

2
+VDD33 RG571
GPIO_6
UG1E
10K_J
GPIO_0
AM31 VDD_33 symbol5 GPIO_0 W40 r0201
GPIO_1 AA40 GPIO_5
GPIO_2 D6619
AA35

1
GPIO_2
0.37V_30mA_LRB751V-40T1G

1
CG129
1 2
1UF/6.3V,X5R R0402
GPIO5_AC_DETECT 50
GPIO_5
C0402 GPIO_5_REG_HOT_AC_BATT AA34 1 2 0_J ns NI
GPIO_6 GPUVR_HOT 70 sod323

2
GPIO_6_TACH U35 RG306 1 2 0_J ns NI I-DIS
RG570 R0402
GPIO_8_ROMSO
GPIO_8_ROMSO AP25
GPIO_9_ROMSI TP10045 <BOM>
GPIO_9_ROMSI AM25
GPIO_10_ROMSCK TP10046 <BOM>
+VDD33 GPIO_10_ROMSCK AM27
GPIO_11 TP10047 <BOM>
GPIO_11 W41
GPIO_12
GPIO_12 Y40
(15) ASIC GPIO Straps CLK GPIO_13 Y41
GPIO_13

2
GPIO_14_HPD2 AU21 HPD2
RG140 RG141 AA41
GPIO_15
PIN STRAPS
Pre-PWROK Output Voltage GPIO_15
TP10134 Use either pull-up or pull-down depending on design specifics, but not both
4.7K_F 4.7K_F GPIO_16_8P_DETECT U34
GPU_GPIO_16 81
R37
GPIO_17_THERMAL_INT
GPU_ALERT# 50
GPIO_18_HPD3 AV25 HPD3
R38 +VDD33
GPIO_19_CTF
GPIO_20 GPIO_19_CTF 74

1
1V8_AON GPIO_20 AB40
3-PAD S / 2 R0201 R0201 GPU_SCL 5.1K_F GPIO_0
AC35 SCL GPIO_21 AB41 RG142 1 2 NI
PINSTRA P_BIF_TX_HA LF_SW ING half swing usage.
GPU_SDA GPIO_22_ROMCSB
AC34 SDA GPIO_22_ROMCSB AP27 5.1K_F ns
RG147 1 2 10K_F r0201 SVC 15 GPIO_29 TP10048 RG143 1 2 I-DIS R0402
GPIO_29 W37
8 SMB_GPUCLK R0402
AW40 SMBCLK GPIO_30 W38
RG148 1 NI 2 10K_F r0201 SMB_GPUDATA

2
ns AW41 SMBDAT GENERICA BA38
PS_1_NI
GENERICB AV29 RG330
RG153 1 NI 2 10K_F r0201 SVD 8 PS_2_NI 5.1K_F GPIO_2
ns 15
GENERICC AU31 10K_J RG144 1 2 I-DIS PINSTRA P_BIF_GEN3_EN_ A PCIe Gen3 is supported
PS_3_NI
GENERICD AV31 5.1K_F
RG156 1 2 10K_F r0201 r0201 RG146 1 2 NI R0402
GENERICE_HPD4 AU25 HPD4
AU17 AV23 HPD5 R0402 ns
70 SVC GPIO_SVC GENERICF_HPD5
PS_0_NI 5.1K_F

1
GPIO_8_ROMSO
70 SVD
AV17 GPIO_SVD GENERICG AM29 RG151 1 2 I-DIS PINSTRA P_BIF_CLK_PM_ EN
The CLKREQB power management capability is enabled
70 SVT AR17 GPIO_SVT 5.1K_F
RG152 1 2 NI R0402
SVC SVD V HPD1 AV21 HPD1
AN34 DDCVGACLK
R0402 ns
B 5.1K_F GPIO_9_ROMSI B
AP31 DDCVGADATA RG157 1 2 NI RESERV ED normal operation
0 0 1.1 5.1K_F ns
1V8_AON RG158 1 2 I-DIS R0402

R0402
5.1K_F GPIO_11
0 1 1.0 RG159 1 2 NI PINSTRAP_ROM_CONFIG [0]
DISABLE ROM SETTING
5.1K_F ns
GPU_CLKREQ#_R RG160 1 2 NI R0402
CLKREQB AV40
GPU_WAKEB ns
2

AY13 AU40 R0402

1 0 0.9 TEST_PG WAKEB
GPU_EVENT# 6 5.1K_F GPIO_12
RG161 RG162 BA13 TEST_PG_BACO RG163 1 2 NI PINSTRAP_ROM_CONFIG [1]
DISABLE ROM SETTING
1K_J 1K_J 5.1K_F ns
RG165 1 2 NI R0402
1 1 0.8 ns
R0201 R0201 DIGON AC40 R0402
5.1K_F GPIO_13
RG166 1 2 NI PINSTRAP_ROM_CONFIG [2] DISABLE ROM SETTING
1

TEST_PG
BL_ENABLE AC37 HEADLESS MODE 5.1K_F ns
RG167 1 2 I-DIS R0402
K41 RSVD#K41 BL_PWM_DIM AC38
TEST_PG_BACO
R34 R0402
RSVD#R34
5.1K_F GPIO_15
W34 HSYNC RG171 1 2 NI normal operation

2
HSY NC RESERV ED
2

VSY NC W35 VSYNC 5.1K_F ns

RG168 RG169 RG170 RG172 1 2 I-DIS R0402
RG312
10K_J 10K_J 10K_J HPD1 R0402
10K_J 5.1K_F GPIO_20
SWAPLOCKA AG34 r0201 r0201 r0201 RG173 1 2 I-DIS PINSTRA P_TX_DEEMPH_ EN
r0201 half swing usage.
SWAPLOCKB AE34 5.1K_F
ns RG174 1 2 NI R0402
AR29 RG181 1 2 100K_F R0201

1
GENLK_CLK
NI
ns
1

GENLK_VSY NC AP29 R0402

5.1K_F GPIO_22_ROMCSB
RG175 1 2 NI PINSTRA P_BIOS_RO M_ EN
DISABLE
5.1K_F ns
REV 0.91 RG176 1 2 I-DIS R0402

+VDD33 HPD2 R0402

DBGDATA_[15..0] 5.1K_F GPIO_29
UG1K 15 RG178 1 2 I-DIS PINSTRA P_BIF_V GA _DIS does not drive any displays (headless)
symbol11 +VDD33 5.1K_F
DBGDATA_0 RG179 1 2 NI R0402

2
DBGDATA_0 L40 15 0 RG187 1 2 100K_F R0201
DBGDATA_1 L41 15
DBGDATA_1
1 RG010 R0402 ns
DBGDATA_2 5.1K_F
DBGDATA_2 M40 15 2
10K_J RG182 1 2 NI HSYNC SPECIAL USAGE
DBGDATA_3
DBGDATA_3 M41 15 3
SOT23-3 5.1K_F ns
DBGDATA_4 R0402 RG184 1 2 NI R0402
DBGDATA_4 N40 15 4
DBGDATA_5 ns
1

DBGDATA_5 N41 15 5 HPD3 R0402

5.1K_F

1
DBGDATA_6
P40 15 6 RG185 1 2 NI VSYNC
G

DBGDATA_6 SPECIAL USAGE

DBGDATA_7 GPU_CLKREQ#_R
DBGDATA_7 P41 15 7
7 GPU_CLKREQ# 3 2 5.1K_F ns
DBGDATA_8 RG186 1 2 NI R0402
R40 15 8 RG190 1 2 100K_F R0201
D

DBGDATA_8

DBGDATA_9 R41 15
DBGDATA_9
9 R0402 ns
DBGDATA_10 DBGDATA_[15..0]

2
DBGDATA_10 T40 15 10 L2N7002LT1G 15
DBGDATA_11
DBGDATA_11 T41 15 11 QX17 RG020 1V8_AON
DBGDATA_12
DBGDATA_12 U40 15 12
10K_J
DBGDATA_13 5.1K_F DBGDATA_0
DBGDATA_13 U41 15 13
R0402 HPD4 RG188 1 2 I-DIS 15 0
PINSTRAP_AUD_PORT_CONN [0]
DBGDATA_14
DBGDATA_14 V40 15 14 5.1K_F 111: No usable endpoints
DBGDATA_15 1 2 0_J ns RG189 1 2 NI R0402
110: One usable endpoint
DBGDATA_15 V41 15 15
RG572 R0402 NI
ns
1

ns RG195 1 2 100K_F R0201 R0402 101: Two usable endpoints

C 5.1K_F DBGDATA_1 100: Three usable endpoints C
REV 0.91 1.8V 200MHz NI RG191 1 2 I-DIS 15 1
PINSTRAP_AUD_PORT_CONN [1]
5.1K_F 011: Four usable endpoints
RG192 1 2 NI R0402 010: Five usable endpoints
ns 001: Six usable endpoints
HPD5 R0402
000: All endpoints are usable
5.1K_F DBGDATA_2
RG193 1 2 I-DIS
TP10034
TP10035
TP10036
TP10037
TP10038
TP10039
TP10041
TP10040

15 2
PINSTRAP_AUD_PORT_CONN [2]
5.1K_F
RG194 1 2 NI R0402
RG202 1 2 100K_F R0201
R0402 ns
5.1K_F DBGDATA_3
RG196 1 2 15 3
PINSTRAP_BOARD_CONFIG [0]
5.1K_F VRAM_ID
RG197 1 2 R0402

1V8_AON VRAM_ID R0402

5.1K_F DBGDATA_4
RG200 1 2 15 4
PINSTRAP_BOARD_CONFIG [1]
BOARD_CONFIG[2:0] CONFIG 0
PN? 5.1K_F VRAM_ID
YG1 RG201 1 2 R0402

GPU_XTALIN VRAM_ID R0402

FB5002 1 2 4 VDD OUT 3 RG6922 1 2 5.1K_F DBGDATA_5
fb0402
RG204 1 2 15 5
PINSTRAP_BOARD_CONFIG [2]
SHORT_0402 5.1K_F
120ohm/100MHz,-400MA 1 2 RG205 1 2 R0402 VRAM_ID
E/D GND VRAM_ID R0402
100MHZ 5.1K_F DBGDATA_6
Keep clock path as RG206 1 2 I-DIS 15 6
1

PINSTRAP_SMBUS_ADDR [0]
CG446 CRY4_3225
short as possible. 5.1K_F
0.1UF/10V,X5R I-DIS
RG207 1 2 NI R0402
UG1F
C0402
symbol6 BA39
GPU_XTALIN
R0402 ns
2

XTALIN
5.1K_F DBGDATA_7
RG209 1 2 NI 15 7
PINSTRAP_SMBUS_ADDR [1]
5.1K_F ns
RG210 1 2 I-DIS R0402

R0402

0x40: DNI the pull-up resistors on both balls.

0x41: Install pull-up resistor only on DBGDATA_6. If there is no address conflicts on the platform, use 0x41 as slave address for compatibility with past products.
0x42: Install pull-up resistor only on DBGDATA_7.
0x43: install pull-up resistors on both balls.
GPU_XTALOUT
XTALOUT AY39
TP10127

PLLCHARZ_L
PLLCHARZ_L AV15
PLLCHARZ_H TP10042
PLLCHARZ_H AU15
TP10043

REV 0.91 ANALOGIO AY38 ANALOGIO RG213 1 2 16.2K_F R0402

ns
NI
D D

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Date: Wednesday, August 21, 2019

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Bitland Information Technology Co.,Ltd.

Sheet 76 of 87
Rev
1.3

PROPERTY NOTE: this document contains information confidential and property to

Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 1 2 3 4 5

A A

ASIC - TMDP (A/B)

UG1G
symbol7

AY32
ASIC - TMDP (C/D)
TX2P_DPB0P

TX2M_DPB0N BA32

UG1H
TX1P_DPB1P AY31
symbol8

BA31 TX2P_DPD0P AY22

TX1M_DPB1N

AY30 TX2M_DPD0N BA22

TX0P_DPB2P

BA30 TX1P_DPD1P AY21

TX0M_DPB2N

AY28 TX1M_DPD1N BA21

TXCBP_DPB3P

BA28 TX0P_DPD2P AY20

TXCBM_DPB3N

TX0M_DPD2N BA20

TXCDP_DPD3P AY19 ASIC - TMDP (E)

TXCDM_DPD3N BA19
UG1O
AUX1P AY11 symbol15

AM21 TX2P_DPE0P AY18

DDCAUX3P
AUX1N BA11
AP21 TX2M_DPE0N BA18
DDCAUX3N
B B
TX1P_DPE1P AY16

DDC1CLK AY10 TX1M_DPE1N BA16

DDC1DATA BA10 TX0P_DPE2P AY15

TX0M_DPE2N BA15

TXCEP_DPE3P AY14

AY36 TXCEM_DPE3N BA14

TX5P_DPA0P

TX5M_DPA0N BA36

TX4P_DPA1P AY35

BA35 TX5P_DPC0P AY27

TX4M_DPA1N

AY34 TX5M_DPC0N BA27

TX3P_DPA2P
DDCAUX5P AU27
BA34 TX4P_DPC1P AY26
TX3M_DPA2N
DDCAUX5N AV27
AY33 TX4M_DPC1N BA26
TXCAP_DPA3P
REV 0.91

BA33 TX3P_DPC2P AY25 I-DIS

TXCAM_DPA3N

TX3M_DPC2N BA25

TXCCP_DPC3P AY24
RG215 1 2 150.0_F r0201 BA12 AUX_ZVSS
TXCCM_DPC3N BA24
I-DIS
AUX2P AP19
C DDCAUX4P AR23 C
AUX2N AM19

REV 0.91 DDCAUX4N AP23

I-DIS

DDC2CLK AV19

DDC2DATA AU19
REV 0.91

I-DIS

D D

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Date: Wednesday, August 21, 2019 Sheet 77 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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A A

B B

C C

D D

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Page Name

Vinafix.com
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Size Project Name Re v
C
Veneno 1.3
Date: Wednesday, August 21, 2019 Sheet 78 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

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 5 4 3 2 1

VDDC
D D

VDDCI
UG1I UG1L UG1M
N13 VDDC#0 symbol9 VDDCI#0 L13 symbol12 symbol13
N15 VDDC#1 VDDCI#1 L17 A2 VSS#0 VSS#58 J39 AA5 VSS#115 VSS#171 AN40

CG143

CG144

CG139
N21 L21 A5 J40 AA10 AN41
1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R
VDDC#2 VDDCI#2 VSS#1 VSS#59 VSS#116 VSS#172

CG147
1UF/6.3V,X5R

1UF/6.3V,X5R
2

2
CG136 CG137 CG138 CG142 N23 L25 A9 J41 AA17 AP13
2

2
VDDC#3 VDDCI#3 VSS#2 VSS#60 VSS#117 VSS#173
CG146
N29 VDDC#4 VDDCI#4 L29 A13 VSS#3 VSS#61 K21 AA19 VSS#118 VSS#174 AP17
C0201 C0201 C0201 C0201 N31 VDDC#5 VDDCI#5 N11 A17 VSS#4 VSS#62 K25 AA25 VSS#119 VSS#175 AR3
C0201
1

1
C0201

C0201

C0201

C0201
R13 U11 A21 K29 AA27 AR7
1

1
VDDC#6 VDDCI#6 VSS#5 VSS#63 VSS#120 VSS#176
R15 VDDC#7 VDDCI#7 AA11 A25 VSS#6 VSS#64 K40 AA32 VSS#121 VSS#177 AR11
R21 VDDC#8 VDDCI#8 AE11 A29 VSS#7 VSS#65 L3 AA39 VSS#122 VSS#178 AR19
R23 VDDC#9 A33 VSS#8 VSS#66 L7 AC3 VSS#123 VSS#179 AR21
R29 VDDC#10 A37 VSS#9 VSS#67 L11 AC7 VSS#124 VSS#180 AR25
CG141

R31 A40 L15 AC11 AR27

C0201 CG145

VDDC#11 VSS#10 VSS#68 VSS#125 VSS#181

1UF/6.3V,X5R

1UF/6.3V,X5R

U13 B1 L19 AC17 AR31

2

VDDC#12 VSS#11 VSS#69 VSS#126 VSS#182

U15 VDDC#13 B40 VSS#12 VSS#70 L23 AC19 VSS#127 VSS#183 AR35
U21 VDDC#14 B41 VSS#13 VSS#71 L27 AC25 VSS#128 VSS#184 AR39
C0201

U23 C5 L31 AC27 AU1

CG140

CG148
1

22uF/6.3V,X5R

22uF/6.3V,X5R
VDDC#15 VSS#14 VSS#72 VSS#129 VSS#185
U29 C7 L35 AC39 AU3

1
VDDC#16 VSS#15 VSS#73 VSS#130 VSS#186
U31 VDDC#17 C9 VSS#16 VSS#74 L39 AE1 VSS#131 VSS#187 AU9
W13 VDDC#18 C11 VSS#17 VSS#75 N1 AE3 VSS#132 VSS#188 AU23

C0603

C0603
CG150

CG151

CG152

CG153
22uF/6.3V,X5R

22uF/6.3V,X5R

22uF/6.3V,X5R

22uF/6.3V,X5R

W15 C13 N3 AE5 AU29

2
VDDC#19 VSS#18 VSS#76 VSS#133 VSS#189
CG149
22uF/6.3V,X5R

W21 VDDC#20 C15 VSS#19 VSS#77 N5 AE10 VSS#134 VSS#190 AW3

1

W23 VDDC#21 C17 VSS#20 VSS#78 N17 AE17 VSS#135 VSS#191 AW5
C0603

C0603

C0603

C0603

W29 VDDC#22 C19 VSS#21 VSS#79 N19 AE19 VSS#136 VSS#192 AW7
2

2
C0603

W31 VDDC#23 C21 VSS#22 VSS#80 N25 AE25 VSS#137 VSS#193 AW9
2

AA13 VDDC#24 C23 VSS#23 VSS#81 N27 AE27 VSS#138 VSS#194 AW11
AA15 VDDC#25 C25 VSS#24 VSS#82 N32 AE32 VSS#139 VSS#195 AW13
AA21 VDDC#26 C27 VSS#25 VSS#83 N37 AE35 VSS#140 VSS#196 AW15
AA23 VDDC#27 C29 VSS#26 VSS#84 N39 AE39 VSS#141 VSS#197 AW17
CG154

CG155

CG156
22uF/6.3V,X5R

22uF/6.3V,X5R

22uF/6.3V,X5R

AA29 VDDC#28 C31 VSS#27 VSS#85 R3 AG3 VSS#142 VSS#198 AW19

1

AA31 VDDC#29 C33 VSS#28 VSS#86 R7 AG7 VSS#143 VSS#199 AW21

ns AC13 VDDC#30 C35 VSS#29 VSS#87 R11 AG11 VSS#144 VSS#200 AW23
C0603

C0603

C0603

AC15 VDDC#31 C37 VSS#30 VSS#88 R17 AG17 VSS#145 VSS#201 AW25
2

AC21 VDDC#32 C39 VSS#31 VSS#89 R19 AG19 VSS#146 VSS#202 AW27
C C
AC23 VDDC#33 E1 VSS#32 VSS#90 R25 AG25 VSS#147 VSS#203 AW29
AC29 VDDC#34 E3 VSS#33 VSS#91 R27 AG27 VSS#148 VSS#204 AW31
AC31 VDDC#35 E4 VSS#34 VSS#92 R32 AG39 VSS#149 VSS#205 AW33
AE13 VDDC#36 E9 VSS#35 VSS#93 R35 AG40 VSS#150 VSS#206 AW35
AE15 VDDC#37 E13 VSS#36 VSS#94 R39 AG41 VSS#151 VSS#207 AW37
AE21 VDDC#38 E17 VSS#37 VSS#95 U1 AJ1 VSS#152 VSS#208 AW39
AE23 VDDC#39 E21 VSS#38 VSS#96 U3 AJ3 VSS#153 VSS#209 AY1
AE29 VDDC#40 E25 VSS#39 VSS#97 U5 AJ5 VSS#154 VSS#210 AY2
AE31 VDDC#41 E29 VSS#40 VSS#98 U17 AJ10 VSS#155 VSS#211 AY9
AG13 VDDC#42 E39 VSS#41 VSS#99 U19 AJ11 VSS#156 VSS#212 AY12
AG15 VDDC#43 E41 VSS#42 VSS#100 U25 AJ35 VSS#157 VSS#213 AY17
AG21 VDDC#44 G3 VSS#43 VSS#101 U27 AJ39 VSS#158 VSS#214 AY23
AG23 VDDC#45 G7 VSS#44 VSS#102 U32 AL3 VSS#159 VSS#215 AY29
AG29 VDDC#46 G11 VSS#45 VSS#103 U37 AL7 VSS#160 VSS#216 AY37
AG31 VDDC#47 G15 VSS#46 VSS#104 U39 AL10 VSS#161 VSS#217 AY40
AJ13 VDDC#48 G19 VSS#47 VSS#105 W3 AL11 VSS#162 VSS#218 AY41
AJ15 VDDC#49 G23 VSS#48 VSS#106 W7 AL32 VSS#163 VSS#219 BA2
AJ17 VDDC#50 G27 VSS#49 VSS#107 W11 AL35 VSS#164 VSS#220 BA5
AJ19 VDDC#51 G31 VSS#50 VSS#108 W17 AL39 VSS#165 VSS#221 BA9
AJ21 VDDC#52 G35 VSS#51 VSS#109 W19 AN1 VSS#166 VSS#222 BA17
AJ23 VDDC#53 G39 VSS#52 VSS#110 W25 AN3 VSS#167 VSS#223 BA23
AJ25 VDDC#54 J1 VSS#53 VSS#111 W27 AN7 VSS#168 VSS#224 BA29
AJ27 VDDC#55 J3 VSS#54 VSS#112 W39 AN35 VSS#169 VSS#225 BA37
AJ29 VDDC#56 J5 VSS#55 VSS#113 AA1 AN39 VSS#170 VSS#226 BA40
AJ31 VDDC#57 J34 VSS#56 VSS#114 AA3
AL13 VDDC#58 J37 VSS#57
AL15 VDDC#59
REV 0.91
AL17 REV 0.91
VDDC#60
AL19 VDDC#61
AL21 VDDC#62
AL23 VDDC#63
AL25 C3
VDDC#64 FB_VMEMIO
FB_VMEMIO 69
AL27 AV13
VDDC#65 FB_VDDCI
FB_VDDCI 70
AL29 AR13
VDDC#66 FB_VDDC
FB_VDDC 70
AL31 AU13
VDDC#67 FB_VSS
FB_VSSC 70
REV 0.91

B B

+VMEMIO 1V8_AON
UG1N
symbol14

K11 VMEMIO#0 VDD_18#0 AM15

K13 AP15
CG162

CG163

CG164
1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

VMEMIO#1 VDD_18#1
2

K19 AR15
CG157

CG158

CG159

CG160

CG161
1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

VMEMIO#2 VDD_18#2
2

K23 VMEMIO#3
K27
C0201

C0201

C0201

VMEMIO#4
1

K31
C0201

C0201

C0201

C0201

C0201

VMEMIO#5
1

L10 VMEMIO#6 For cost effective designs where VDDCI and VDD_08
N10 VMEMIO#7
VDDCI
W10 VMEMIO#8 are supplied by one regulator, have the VDDCI and
AC10 VMEMIO#9
AG10 VDD_08 balls joined on a unified power plane.
CG165

CG166

CG167

CG168

CG169
1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

VMEMIO#10
2

VDD_08#0 AC32
VDD_08#1 AG32
AG35
CG170

CG171

CG172

CG173

CG174

CG175

CG176
C0201

C0201

C0201

C0201

C0201

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

VDD_08#2
1

VDD_08#3 AJ32
VDD_08#4 AJ34
AL34
C0201

C0201

C0201

C0201

C0201

C0201

C0201

VDD_08#5
1

1
CG177

CG178
22uF/6.3V,X5R

22uF/6.3V,X5R

VDD_08 W32
1

1
C0603

C0603

VSS AM23
2

VSS AM17
REV 0.91

A A

Bitland Information Technology Co.,Ltd.

Page Name

Vinafix.com
79
Size Project Name Re v
C
Veneno 1.3
Date: Thursday, August 22, 2019 Sheet 79 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

COMPONENTS SHOWN ARE EXAMPLES ONLY

GDDR5 Memory Channel A x32 mode
MF=0 AND NOT NECESSARILY QUALIFIED

DQA0_[31..0]
MF=1 UG5
+MVDD

DQA1_[31..0]
UG7
+MVDD +VMEMIO +MVDD

2
75 DQA0_[31..0]

2
DQA0_10 DQA1_18
30 M2 DQ31__DQ7 VDDQ_B1 B1 75 DQA1_[31..0] 26 M2 DQ31__DQ7 VDDQ_B1 B1
DQA0_11 DQA1_22 R11539
27 M4 DQ30__DQ6 VDDQ_B3 B3 27 M4 DQ30__DQ6 VDDQ_B3 B3 R11538
DQA0_9
N2 B12
DQA1_19
N2 B12 0_J
31
DQA0_8
DQ29__DQ5 VDDQ_B12 24
DQA1_21
DQ29__DQ5 VDDQ_B12 0_J
26 N4 DQ28__DQ4 VDDQ_B14 B14 25 N4 DQ28__DQ4 VDDQ_B14 B14 R0402
29
DQA0_12
T2 DQ27__DQ3 VDDQ_D1 D1 31
DQA1_16
T2 DQ27__DQ3 VDDQ_D1 D1
R0402 ns
DQA0_14 DQA1_23
T4 D3 T4 D3 20190215:Follow AMD design guide,

1
25 28
DQ26__DQ2 VDDQ_D3 DQ26__DQ2 VDDQ_D3

1
28
DQA0_15
V2 DQ25__DQ1 VDDQ_D12 D12 30
DQA1_17
V2 DQ25__DQ1 VDDQ_D12 D12 Change VRAM CLK PU from '+MVDD' to '+VMEMIO'
DQA0_13 DQA1_20
24 V4 DQ24__DQ0 VDDQ_D14 D14 29 V4 DQ24__DQ0 VDDQ_D14 D14
DQA0_2 DQA1_29
D 17 M13 DQ23__DQ15 VDDQ_E5 E5 17 M13 DQ23__DQ15 VDDQ_E5 E5 D
DQA0_0 DQA1_28
18 M11 DQ22__DQ14 VDDQ_E10 E10 16 M11 DQ22__DQ14 VDDQ_E10 E10
DQA0_3 DQA1_30
16 N13 DQ21__DQ13 VDDQ_F1 F1 19 N13 DQ21__DQ13 VDDQ_F1 F1
DQA0_1 DQA1_26
19 N11 DQ20__DQ12 VDDQ_F3 F3 18 N11 DQ20__DQ12 VDDQ_F3 F3
R11149 1 2 60.4_F R0201 I-DIS
23
DQA0_4
T13 DQ19__DQ11 VDDQ_F12 F12 21
DQA1_25
T13 DQ19__DQ11 VDDQ_F12 F12 75,80 CLKA1B
DQA0_6 DQA1_27
21 T11 F14 22 T11 F14 R11153 1 2 60.4_F R0201 I-DIS
DQA0_7
DQ18__DQ10 VDDQ_F14
DQA1_31
DQ18__DQ10 VDDQ_F14 75,80 CLKA1
22 V13 DQ17__DQ9 VDDQ_G2 G2 20 V13 DQ17__DQ9 VDDQ_G2 G2
R11292 1 2 60.4_F R0201 I-DIS
20
DQA0_5
V11 DQ16__DQ8 VDDQ_G13 G13 23
DQA1_24
V11 DQ16__DQ8 VDDQ_G13 G13 75,80 CLKA0B
DQA0_21 DQA1_11
15 F13 H3 15 F13 H3 R11291 1 2 60.4_F R0201 I-DIS
DQA0_20
DQ15__DQ23 VDDQ_H3
DQA1_9
DQ15__DQ23 VDDQ_H3 75,80 CLKA0
12 F11 DQ14__DQ22 VDDQ_H12 H12 12 F11 DQ14__DQ22 VDDQ_H12 H12
DQA0_22 DQA1_10
14 E13 DQ13__DQ21 VDDQ_K3 K3 14 E13 DQ13__DQ21 VDDQ_K3 K3
DQA0_23 DQA1_8
13 E11 DQ12__DQ20 VDDQ_K12 K12 13 E11 DQ12__DQ20 VDDQ_K12 K12
DQA0_18 DQA1_15
8 B13 DQ11__DQ19 VDDQ_L2 L2 10 B13 DQ11__DQ19 VDDQ_L2 L2
DQA0_17 DQA1_13
11 B11 DQ10__DQ18 VDDQ_L13 L13 11 B11 DQ10__DQ18 VDDQ_L13 L13
DQA0_19 DQA1_12
10
9
DQA0_16
A13
A11
DQ9__DQ17 VDDQ_M1 M1
M3
9
8
DQA1_14
A13
A11
DQ9__DQ17 VDDQ_M1 M1
M3
+MVDD
DQ8__DQ16 VDDQ_M3 DQ8__DQ16 VDDQ_M3
DQA0_26 DQA1_2
7 F2 DQ7__DQ31 VDDQ_M12 M12 2 F2 DQ7__DQ31 VDDQ_M12 M12
DQA0_25 DQA1_0
5 F4 DQ6__DQ30 VDDQ_M14 M14 4 F4 DQ6__DQ30 VDDQ_M14 M14
DQA0_31 DQA1_1
6 E2 DQ5__DQ29 VDDQ_N5 N5 3 E2 DQ5__DQ29 VDDQ_N5 N5
DQA0_27 DQA1_3
4 E4 N10 6 E4 N10

2
DQ4__DQ28 VDDQ_N10 DQ4__DQ28 VDDQ_N10
DQA0_30 DQA1_6
0 B2 DQ3__DQ27 VDDQ_P1 P1 0 B2 DQ3__DQ27 VDDQ_P1 P1

C10960
1UF/6.3V,X5R
DQA0_24 DQA1_4
3 B4 P3 7 B4 P3

2
DQ2__DQ26 VDDQ_P3 DQ2__DQ26 VDDQ_P3
DQA0_28 DQA1_5 R11294
1 A2 DQ1__DQ25 VDDQ_P12 P12 1 A2 DQ1__DQ25 VDDQ_P12 P12
2
DQA0_29
A4 DQ0__DQ24 VDDQ_P14 P14 5
DQA1_7
A4 DQ0__DQ24 VDDQ_P14 P14 2.37k_F ns

C0201
T1 T1

1
VDDQ_T1 VDDQ_T1
T3 T3

1
VDDQ_T3 VDDQ_T3
VDDQ_T12 T12 VDDQ_T12 T12 R0402
MAA1_[8..0] VREFC_A0 NI
T14 T14 I-DIS
VDDQ_T14 VDDQ_T14
MAA0_[8..0] 75 MAA1_[8..0]
75 MAA0_[8..0]

2
MAA0_8 MAA1_8
8 J5 RFU_A12_NC 8 J5 RFU_A12_NC

C10959
1UF/6.3V,X5R
MAA0_7 MAA1_0
7 K4 C5 0 K4 C5

2
A7_A8__A0_A10 VDD_C5 A7_A8__A0_A10 VDD_C5
MAA0_6 MAA1_1 R11293
6 K5 A6_A11__A1_A9 VDD_C10 C10 1 K5 A6_A11__A1_A9 VDD_C10 C10
5
MAA0_5
K10 D11 2
MAA1_3
K10 D11 5.49K_F
A5_BA1__A3_BA3 VDD_D11 A5_BA1__A3_BA3 VDD_D11

C0201
MAA0_4 MAA1_2
K11 G1 K11 G1

1
4 3
A4_BA2__A2_BA0 VDD_G1 A4_BA2__A2_BA0 VDD_G1
MAA0_3 MAA1_5
3 H10 A3_BA3__A5_BA1 VDD_G4 G4 4 H10 A3_BA3__A5_BA1 VDD_G4 G4

1
MAA0_2 MAA1_4
2 H11 A2_BA0__A4_BA2 VDD_G11 G11 5 H11 A2_BA0__A4_BA2 VDD_G11 G11
MAA0_1 MAA1_6
R0402 I-DIS
1 H5 A1_A9__A6_A11 VDD_G14 G14 6 H5 A1_A9__A6_A11 VDD_G14 G14 I-DIS
MAA0_0 MAA1_7
0 H4 A0_A10__A7_A8 VDD_L1 L1 7 H4 A0_A10__A7_A8 VDD_L1 L1
C C
VDD_L4 L4 VDD_L4 L4
VDD_L11 L11 VDD_L11 L11
VDD_L14 L14 VDD_L14 L14
D4 WCK01__WCK23 VDD_P11 P11 D4 WCK01__WCK23 VDD_P11 P11 20190228:AMD suggest NI C10960 and C10897
75 WCKA0_1 75 WCKA1_0
D5 WCK01#__WCK23# VDD_R5 R5 D5 WCK01#__WCK23# VDD_R5 R5
75 WCKA0B_1 75 WCKA1B_0
P4
VDD_R10 R10
P4
VDD_R10 R10
+MVDD
WCK23__WCK01 WCK23__WCK01
75 WCKA0_0 75 WCKA1_1
P5 WCK23#__WCK01# P5 WCK23#__WCK01#
75 WCKA0B_0 75 WCKA1B_1
VSSQ_A1 A1 VSSQ_A1 A1

2
R2 EDC3__EDC0 VSSQ_A3 A3 R2 EDC3__EDC0 VSSQ_A3 A3
75 EDCA0_1 75 EDCA1_2

C10897
1UF/6.3V,X5R
R13 A12 R13 A12

2
EDC2__EDC1 VSSQ_A12 EDC2__EDC1 VSSQ_A12
75 EDCA0_0 75 EDCA1_3
C13 EDC1__EDC2 VSSQ_A14 A14 C13 EDC1__EDC2 VSSQ_A14 A14 R11162
75 EDCA0_2 75 EDCA1_1 ns
C2 EDC0__EDC3 VSSQ_C1 C1 C2 EDC0__EDC3 VSSQ_C1 C1 2.37k_F
75 EDCA0_3 75 EDCA1_0

C0201
C3 C3

1
VSSQ_C3 VSSQ_C3
P2 DBI3#__DBI0# VSSQ_C4 C4 P2 DBI3#__DBI0# VSSQ_C4 C4
75 DDBIA0_1 75 DDBIA1_2 VREFC_A1

1
P13 DBI2#__DBI1# VSSQ_C11 C11 P13 DBI2#__DBI1# VSSQ_C11 C11
75 DDBIA0_0 75 DDBIA1_3 R0402 NI
D13 C12 D13 C12 I-DIS
75 DDBIA0_2 DBI1#__DBI2# VSSQ_C12
75 DDBIA1_1 DBI1#__DBI2# VSSQ_C12

C10898
75 DDBIA0_3 D2 C14 D2 C14

1UF/6.3V,X5R
DBI0#__DBI3# VSSQ_C14 DBI0#__DBI3# VSSQ_C14
75 DDBIA1_0

2
VSSQ_E1 E1 VSSQ_E1 E1
R11165
VSSQ_E3 E3 VSSQ_E3 E3
E12 E12 5.49K_F

C0201
VSSQ_E12 VSSQ_E12

1
75 RASA0B G3 RAS#__CAS# VSSQ_E14 E14 G3 RAS#__CAS# VSSQ_E14 E14
75 CASA1B
75 CASA0B L3 CAS#__RAS# VSSQ_F5 F5 L3 CAS#__RAS# VSSQ_F5 F5
75 RASA1B

1
VSSQ_F10 F10 VSSQ_F10 F10 I-DIS
R0402
VSSQ_H2 H2 VSSQ_H2 H2 I-DIS
J3 CKE# VSSQ_H13 H13 J3 CKE# VSSQ_H13 H13
81 CKEA0 81 CKEA1
J11 CK# VSSQ_K2 K2 J11 CK# VSSQ_K2 K2
75,80 CLKA0B 75,80 CLKA1B
J12 CK VSSQ_K13 K13 J12 CK VSSQ_K13 K13
75,80 CLKA0 75,80 CLKA1
VSSQ_M5 M5 VSSQ_M5 M5
VSSQ_M10 M10 VSSQ_M10 M10
75 CSA0B_0 G12 CS#__WE# VSSQ_N1 N1 G12 CS#__WE# VSSQ_N1 N1
75 WEA1B
75 WEA0B L12 WE#__CS# VSSQ_N3 N3 L12 WE#__CS# VSSQ_N3 N3
75 CSA1B_0
VSSQ_N12 N12 VSSQ_N12 N12
VSSQ_N14 N14 VSSQ_N14 N14
ZQ_A0 ZQ_A1
R111581 2 120.0_F J13 ZQ VSSQ_R1 R1 R111591 2 120.0_F J13 ZQ VSSQ_R1 R1
R0402 SEN_A0 R0402 SEN_A1
J10 SEN VSSQ_R3 R3 J10 SEN VSSQ_R3 R3
I-DIS VSSQ_R4 R4 I-DIS VSSQ_R4 R4
B VSSQ_R11 R11 VSSQ_R11 R11 B
J2 RESET# VSSQ_R12 R12 J2 RESET# VSSQ_R12 R12
80,81 DRAM_RST_A MF_A0 80,81 DRAM_RST_A MF_A1
J1 R14 J1 R14
MF VSSQ_R14
VSSQ_V1 V1 +MVDD MF VSSQ_R14
VSSQ_V1 V1
VSSQ_V3 V3 VSSQ_V3 V3
VSSQ_V12 V12 VSSQ_V12 V12
VSSQ_V14 V14 VSSQ_V14 V14
A5 Vpp_NC A5 Vpp_NC
RG461
RG230 2 2.37k_F ns R0402
1 NI V5 R0402 2 1 2.37k_F ns NI V5
+MVDD Vpp_NC1 +MVDD Vpp_NC1
RG234 1 22.49K_F R0402ns NI VSS_B5 B5 RG460 1 2 2.49K_F R0402 ns NI VSS_B5 B5
CG179 2 1 C0201 ns NI 6 VREFD1_A0 A10 VREFD1 VSS_B10 B10 2 CG444 C0201 ns NI
1 6 VREFD1_A1 A10 VREFD1 VSS_B10 B10
1UF/6.3V,X5R V10 VREFD2 VSS_D10 D10 1UF/6.3V,X5R V10 VREFD2 VSS_D10 D10
RG458
RG238 2 1 2.37k_F ns R0402 NI G5 R0402 2 1 2.37k_F ns NI G5
+MVDD VSS_G5 +MVDD VSS_G5
RG242 1 2 2.49K_F R0402 ns NI VSS_G10 G10 RG459 1 2 2.49K_F R0402 ns NI VSS_G10 G10
CG183 2 1 C0201 ns NI 6 VREFD2_A0 VSS_H1 H1 2 1 CG445 C0201 ns 6 VREFD2_A1 VSS_H1 H1
1UF/6.3V,X5R VSS_H14 H14 1UF/6.3V,X5R NI VSS_H14 H14
VSS_K1 K1 VSS_K1 K1
VREFC_A0 J14 K14
VREFC_A1 J14 K14
VREFC VSS_K14 VREFC VSS_K14
VSS_L5 L5 VSS_L5 L5
VSS_L10 L10 VSS_L10 L10
VSS_P10 P10 VSS_P10 P10
ADBIA0 J4 ABI# VSS_T5 T5 ADBIA1 J4 ABI# VSS_T5 T5
75 ADBIA0 75 ADBIA1
VSS_T10 T10 VSS_T10 T10

I-DIS I-DIS
Decoupling caps for clamshell configuration
+MVDD
8 x 0.1uF per DRAM
1 x 10uF per 2 clamshell DRAMs 8 x 1uF per 2 clamshell DRAMs
0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R
C0201 CG442

C0201 CG438

C0201 CG440

C0201 CG441

C0201 CG436

CG437

CG443

CG439
+MVDD
CG426
10uF/6.3V,X5R

1
1

ns ns

C0201

C0201

C0201
C0402
0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

0.1uF/10V,X5R

2
C0201 CG425

C0201 CG429

C0201 CG420

C0201 CG413

C0201 CG428

C0201 CG422

C0201 CG417

CG419

2
CG414
10uF/6.3V,X5R

I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS

1

A I-DIS A
Decoupling caps for single-sided configuration
C0201

1 x 10uF per DRAM

C0402

C0201 CG431

CG406

CG410

CG408

CG416

CG412

CG409

CG430
2

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R
8 x 1uF per DRAM
2

2
I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS 8 x 0.1uF per DRAM
I-DIS
C0201

C0201

C0201

C0201

C0201

C0201

C0201
Bitland Information Technology Co.,Ltd.
1

1
C0201 CG427

CG418

CG421

CG415

CG423

CG424

CG411

CG407
1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R

1UF/6.3V,X5R
2

Page Name
I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS
80

Vinafix.com
Size
C0201

C0201

C0201

C0201

C0201

C0201

C0201

Project Name Re v
1

C
Veneno 1.3
I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS I-DIS Date: Wednesday, August 21, 2019 Sheet 80 of 87
PROPERTY NOTE: this document contains information confidential and property to
Bitland Technology Co.,Ltd. and shall not be reproduced or transferred to other
documents or disclosed to others or used for any purpose other than that for which it
was obtained with the expressed written consent of Bitland

5 4 3 2 1

Vinafix.com
 5 4 3 2 1

+MVDD +MVDD +VDD33 +MVDD

2
1
CG6928 R11535 RG6928
CG6931 1 2 I-DIS
0.1uF/25V,X5R 1K_J 10K_J C0201
C0402 r0201 0.1uF/10V,X5R
R0402 20190428：A MD suggesti on
，r eser v e PX_ E N a t UG690 5 PI N1
I-DIS

2
RG6941 2 I-DIS 1 10K_J
U9041 +VMEMIO

1
r0201

5
PI2DDR321 UG6905

2
R11611 1 2 178K_J PX_EN_R 1

P
6,69 PX_EN ns
R0402 A DRSRF_ENb

VDD

GND
4
9 I-DIS Y DRSRF_ENb 81
C0 R11527 1 2 0_J 2
D 5 8 76 GPU_GPIO_16 B D

G
SEL B0 DRAM_RST_A 80 R0402

2
10 4
75 DRAM_RST_A_GPU A0 NC1 SN74AUP1G08DCKR

1
3 CG6934

3
81 DRSRF_ENb EN sc70-5
0.1UF/10V,X5R ns RG6929 RG6927

NC3

NC2
C0402 ns 10K_J 100K_J

2
R0402
TQFN10_0D4_1D3X1D6
I-DIS r0201

7
NI I-DIS

1
R11530 1 ns 2 0_J
Close to U9041 R0402

+VDD33

+MVDD +MVDD

2
R11604

2
33.0_J
+V3P3A
1
CG6929 R11536 R0805
0.1uF/25V,X5R 1K_J
C0402
R0402
I-DIS
2

1
U9042

2
1
PI2DDR321

2
Q8934B R11605

6
VDD

GND
L2N7002DW1T1G 20K_F 20190423:Fix +VMEMIO leakage issue at BOMA mode,
9
C0 D SOT363
R0402
follow AMD suggetion,Add Discharge schematic for VDD33
5 8
SEL B0 CKEA0 80 I-DIS
10 4
75 CKEA0_GPU A0 NC1 G 2

1
3
81 DRSRF_ENb EN S
NC3

NC2

Q8934A

3
TQFN10_0D4_1D3X1D6 L2N7002DW1T1G
1

D SOT363
I-DIS
R11531 1 ns 2 0_J G 5
R0402 +VDD33_EN 64,69
C Close to U9042 S C

4
+MVDD +MVDD
2
1

CG6930 R11537
0.1uF/25V,X5R 1K_J
C0402
I-DIS
2

R0402

U9043
1

PI2DDR321 +V3P3A
6

2
VDD

GND

9
C0
5 8

2
SEL B0 CKEA1 80
10 4
75 CKEA1_GPU A0 NC1 RG6942
3 SHORT_0402
81 DRSRF_ENb EN
NC3

NC2

1
TQFN10_0D4_1D3X1D6
1

2
R11532 1 ns 2 0_J
R0402 CG6933
Close to U9043 0.1uF/10V,X5R OR Gate

1
C0201
I-DIS

U9045
5 1
VRAM_EN_R_U9045 1 2
R11548
VCC A VRAM_EN_R 69
BOMACO_EN_U9045 SHORT_0402
2 R11526 1 2
VRAM_EN_U9045 B BOMACO_EN 50,81
RG6938 1 2 4 SHORT_0402
69 VRAM_EN Y
SHORT_0402 3
GND
B B
SN74LVC1G32DCKR
sc70-5

+V3P3A
+MVDD
+V3P3A

2
RG6932
10K_J

2
r0201
C0402
2

RG6943 I-DIS
U9044 0.1uF/10V,X5R 10K_J
EM5201BJ-45 C10975 20190218 note: nsr0201

1
1

SOT23-6 ns U9044 enable 'on' Active high SYS_CS_CTR

GND
1 6 R11525 2 1 81 SYS_CS_CTR 20190423:Reserve GPIO for BOMACO_EN
GND ON SYS_CS_CTR 81
1

SHORT_0402 NI Q8932A 0_J 2 1 R11609

2 5 R11555 1 I-DIS 2 0_J R0402 WLAN_DET_N 6,43

3
VIN VBIAS +V3P3SX L2N7002DW1T1G
R11551 1 2 0_J R0402 NI +V3P3A R11556 1 2 0_J SOT363
I-DIS R0402
ns BOMACO_EN_U9045 ns D
3 4
+VMEMIO R0402 Q8932B I-DIS
NC VOUT
6

NI L2N7002DW1T1G G 5
I-DIS D SOT363 BOMACO_EN 50,81
1

C10977 I-DIS
S
1

1UF/6.3V,X5R C10974 C10976 G 2 R11552 1 2 0_J

4
C0402 0.1uF/10V,X5R 0.1uF/10V,X5R ns SYS_CS_CTR 81
S
2

I-DIS C0402 C0402 R0402

2

I-DIS I-DIS NI
1

GND
GND GND
A
R115291 ns 2 0.005_F R0805 A

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