International University

School of Electrical Engineering

DIGITAL LOGIC DESIGN LABORATORY

IT009IU

Introduction Simulation
Software and Logic Gates

Submitted by
[Tạ Thanh Vũ– ITITIU21352]
[Lê Ngọc Đăng Khoa– IT]

Date Submitted: [9/4/2024]

Date Performed: [27/3/2024]
Lab Section: [1]
Course Instructor: [Đỗ Ngọc Hùng]

GRADING GUIDELINE FOR LAB REPORT

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 Number Content Score Comment
Format (max 9%)
- Font type Yes No
1
- Font size Yes No

- Lab title Yes No

- Page number Yes No

- Table of contents Yes No

- Header/Footer Yes No

- List of figures (if exists) Yes No

- List of tables (if exists) Yes No

- Lab report structure Yes No

2 English Grammar and Spelling (max 6%)

- Grammar Yes No

- Spelling Yes No

3 Data and Result Analysis (max 85%)

Total Score

Signature:

Date:

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Table of Contents

List of Figures ........................................................................................….….............................. 2

List of Tables .................................................................................................……....................... 2
Nomenclature ...........................................................................................................…….…....... 2
Theoretical Background .............................................................................................…….......... 3
Experimental Procedure.............................................................................................……........... 3
Experimental Results ........................................................................................................……... 4
Discussion of Results ................................................................................................................... 4
List of Figures
Figure 1 –………………………….……...…………………………………………………… x
Figure 2 – …………………………………………………………………..……………...….. x
Figure 3 – ……………………………………………………………………………………... x
Figure 4 –………………………………………….………………………..……………...….. x
Figure 5 – ……………………………………………………………………………………... x
Figure 6 – ……………............................................................................................................... x

List of Tables
Table 1 – ……………………………………..……………………........................................... x
Table 2 – ……………………………………..……………………........................................... x
Table 3 – ……………………………………..……………………........................................... x

Nomenclature
VDD = DC Voltage Source
Vdd = AC Volatge Source
Iref = Reference Current
Etc.

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Theoretical Background

Experimental Procedure

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Experimental Results
1. Design the circuit that can detect BCD number:
The circuit that detects BCD number includes 4 inputs (A, B, C, D) and 1 output Y. The output Y
is HIGH when the BCD numbers in the inputs.
- Build the truth table and the expression

D C B A Y
0 0 0 0 1
0 0 0 1 1
0 0 1 0 1
0 0 1 1 1
0 1 0 0 1
0 1 0 1 1
0 1 1 0 1
0 1 1 1 1
1 0 0 0 1
1 0 0 1 1
1 0 1 0 0
1 0 1 1 0
1 1 0 0 0
1 1 0 1 0
1 1 1 0 0
1 1 1 1 0

K-map
DC 00 01 11 10
BA
00 1 1 1 1
01 1 1 1 1

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 11
10 1 1

The expression: D’+B’C’=D’+ (B+C)’

Implement the circuit via simulation software and paste the result in here

The inputs A, B, C, D wire up to switches and concurrently connect to BCD to 7 segment (in
SimulIDE named as 7 Seg BCD shown as below)
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 Figure 1. BCD 7-Seg
Implement the circuit via simulation software and paste the result in here:

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Make comment on the results

2. Design the Comparator from logic gates and IC

a. Build a one-bit comparator from logic gates
Construct one-bit comparator (2 inputs, 3 outputs) which are shown in the truth table below:

Input Output
A B A=B A<B A>B
0 0 1 0 0
0 1 0 1 0
1 0 0 0 1
1 1 1 0 0
Write down the expressions for 3 outputs:
(A=B) = A’B’ + AB
A B 0 1
0 1 0
1 0 1
Expression: A’B’+AB =(A+B)’+AB
A<B = A’B
A B 0 1

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 0 0 1
1 0 0
Expression: A’B
A>B = AB’
A B 0 1
0 0 0
1 1 0
Expression: AB’
Implement the circuit via simulation software and paste the result in here

Make comment on the results

b. Build a 4-BIT comparator - IC 74HC85

The 4-Bit comparator IC 74HC85 is shown as below

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 Figure 2. 4bit Comparators - IC 74HC85
- A and B are connected to data switches and Outputs are connect to LEDs
- Implement the circuit via simulation software and paste the result in here

- Fill in the truth table of IC 74HC85.

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 Comparing Input Cascading Input Output
A3,B3 A2,B2 A1,B1 A0,B0 A > A<B A=B A>B A<B A=B
B
A3>B3 X X X X X X 1 0 0
A3<B3 X X X X X X 0 1 0
A3 =B3 A2>B2 X X X X X 1 0 0
A3 =B3 A2<B2 X X X X X 0 1 0
A3 =B3 A2=B2 A1>B1 X X X X 1 0 0
A3 =B3 A2=B2 A1<B1 X X X X 0 1 0
A3 =B3 A2=B2 A1=B1 A0>B0 X X X 1 0 0
A3 =B3 A2=B2 A1=B1 A0<B0 X X X 0 1 0
A3 =B3 A2=B2 A1=B1 A0=B0 1 0 0 1 0 0
A3 =B3 A2=B2 A1=B1 A0=B0 0 1 0 0 1 0
A3 =B3 A2=B2 A1=B1 A0=B0 X X 1 0 0 1
A3 =B3 A2=B2 A1=B1 A0=B0 0 0 0 1 1 0
A3 =B3 A2=B2 A1=B1 A0=B0 1 1 0 0 0 0

Make comment on results

c. Design eight-bit comparator using IC 74HC85 (simulation)

Data of X and Y are driven using switches.

Implement the circuit via simulation software and paste the result in here

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The true table:

Result
A B
LED1 LED2 LED3
0101 0101 0101 0111 1 0 0
1111 0101 0101 0111 1 0 0
1111 0101 1111 0100 0 0 1
1001 0110 0101 1000 0 0 1
1111 0100 1101 1101 0 0 1
0110 1100 0110 1100 0 0 1
Make comment on results and give a brief explanation of the cascading connection

3. Design the Parity Generator and Parity Checker

a. Build a 3-bit parity generator and parity checker only using XOR gate (simulation)
- Describe the purpose of parity bit:
- Fulfill the truth table
A B C Even Output Odd Output
0 0 0 0 1

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 0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 1 1
1 1 0 0 1
1 1 1 1 0
- Write the expressions
A ⊕ B⊕ C

A ⊕ (B⊕C)’
- Using K-map to simplify the expressions
00 01 11 10
BC
A
0 1 1
1 1 1
- Express: AB’C’ +ABC+ A’B’C + A’BC’ =A(B’C’+ BC) + A’(B’C+BA’) = A ⊕ B⊕ C
BC 00 01 11 10
A
0 1 1
1 1 1

A’B’C’+AB’C+A’BC+A’BC’ = =A’(B’C’+BC) + A(B’C+BC’)

=A’(B⊕C)’+A(B⊕C) = A⊕(B⊕C)’
- Implement the circuit via simulate software or DLD kit (using IC
74HC86-quad2-input XOR gate)

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Make the comment on the operation of the parity generator

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b. Build a 4-bit parity generator and parity checker only using XOR gate (simulation)
Fulfill the truth table
A B C D Even Output Odd Output
0 0 0 0 0 1
0 0 0 1 1 0
0 0 1 0 1 0
0 0 1 1 0 1
0 1 0 0 1 0
0 1 0 1 0 1
0 1 1 0 0 1
0 1 1 1 1 0
1 0 0 0 1 0
1 0 0 1 0 1
1 0 1 0 0 1
1 0 1 1 1 0
1 1 0 0 0 1
1 1 0 1 1 0
1 1 1 0 1 0
1 1 1 1 0 1
Using K-map to simplify the expressions
EVEN
CD 00 01 11 10
AB
00 1 1
01 1 1
11 1 1
10 1 1

Expression: A’B’C’D+A’B’CD’+A’BC’D’+A’BCD+ABC’D+ABCD’+AB’C’D’+AB’CD
=A’B’(C’D+CD’) +A’B(C’D’+CD)+AB(C’D+CD’)+AB’(C’D’+CD)
=(C’D+CD’)(A’B’+AB) + (C’D’+ CD)(A’B+AB’)
= (C⊕D)(A⊕B)’ + (C⊕D)’(A⊕B)= (C⊕D) ⊕(A⊕B)
ODD
CD 00 01 11 10

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 AB
00 1 1
01 1 1
11 1 1
10 1 1

Expression: A’B’C’D’ + A’B’CD +A’BC’D + A’BCD’ + ABC’D’ +ABCD + AB’C’D +

AB’CD’
=A’B’(C’D’+CD)+A’B(C’D+CD’)+AB(C’D’+CD)+AB’(C’D+CD’)
=(A’B’+AB)(C’D’+CD)+ (A’B+AB’)(CD’+C’D)
= (A⊕B)’(C⊕D)’+(A⊕B)(C⊕D) =( (A⊕B) ⊕(C⊕D))’
Implement the circuit via simulation software and paste the result in here
1. Even:

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 2. Odd:

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 3. Using IC 74HC86 (quad 2-input XOR gate) via simulation software

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Comment on the operation of the parity checker
Discussion of Results

In the discussion, you should point out how your experimental results compare with theory, and suggest
and explain reasons for deviations. Discuss the sources of error in this section.

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