CYT4BF

T RAV E O ™ T 2 G 3 2 - b i t A u tom ot i ve M CU
Based on Arm® Cortex®-M7 dual
General description
CYT4BF is a family of TRAVEO™ T2G microcontrollers targeted at automotive systems such as high-end
body-control units. CYT4BF has two Arm® Cortex®-M7 CPUs for primary processing, and an Arm® Cortex®-M0+ CPU
for peripheral and security processing. These devices contain embedded peripherals supporting Controller Area
Network with Flexible Data rate (CAN FD), Local Interconnect Network (LIN), Gigabit Ethernet, and FlexRay.
TRAVEO™ T2G devices are manufactured on an advanced 40-nm process. CYT4BF incorporates a low-power flash
memory, multiple high-performance analog and digital peripherals, and enables the creation of a secure
computing platform.

Features
• CPU subsystem
- Two 350-MHz 32-bit Arm® Cortex®-M7 CPUs, each with
• Single-cycle multiply
• Single/double-precision floating point unit (FPU)
• 16-KB data cache, 16-KB instruction cache
• Memory protection unit (MPU)
• 16-KB instruction and 16-KB data tightly-coupled memories (TCM)
- 100-MHz 32-bit Arm® Cortex® M0+ CPU with
• Single-cycle multiply
• Memory protection unit (MPU)
- Inter-processor communication in hardware
- Three DMA controllers
• Peripheral DMA controller #0 (P-DMA0) with 143 channels
• Peripheral DMA controller #1 (P-DMA1) with 65 channels
• Memory DMA controller (M-DMA0) with 8 channels
• Integrated memories
- 8384 KB of code-flash with an additional 256 KB of work-flash
• Read-While-Write (RWW) allows updating the code-flash/work-flash while executing from it
• Single- and dual-bank modes (specifically for Firmware update Over The Air [FOTA])
• Flash programming through SWD/JTAG interface
- 1024-KB of SRAM with selectable retention granularity
• Cryptography engine
- Supports Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM)
- Secure boot and authentication
• Using digital signature verification
• Using fast secure boot
- AES: 128-bit blocks, 128-/192-/256-bit keys
- 3DES: 64-bit blocks, 64-bit key
- Vector unit supporting asymmetric key cryptography such as Rivest-Shamir-Adleman (RSA) and Elliptic Curve
(ECC)
- SHA-1/2/3: SHA-512, SHA-256, SHA-160 with variable length input data
- CRC: supports CCITT CRC16 and IEEE-802.3 CRC32
- True random number generator (TRNG) and pseudo random number generator (PRNG)
- Galois/Counter Mode (GCM)

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Features

• Functional safety for ASIL-B

- Memory protection unit (MPU)
- Shared memory protection unit (SMPU)
- Peripheral protection unit (PPU)
- Watchdog timer (WDT)
- Multi-counter watchdog timer (MCWDT)
- Low-voltage detector (LVD)
- Brown-out detection (BOD)
- Over-voltage detection (OVD)
- Clock supervisor (CSV)
- Hardware error correction (SECDED ECC) on all safety-critical memories (SRAM, flash, TCM)
• Low-Power 2.7-V to 5.5-V operation
- Low-power Active, Sleep, Low-power Sleep, DeepSleep, and Hibernate modes for fine-grained power
management
- Configurable options for robust BOD
• Two threshold levels (2.7 V and 3.0 V) for BOD on VDDD and VDDA
• One threshold level (1.1 V) for BOD on VCCD
• Wakeup
- Up to two pins to wake from Hibernate mode
- Up to 240 GPIO pins to wake from Sleep modes
- Event Generator, SCB, watchdog timer, RTC alarms to wake from DeepSleep modes
• Clocks
- Internal main oscillator (IMO)
- Internal low-speed oscillator (ILO)
- External crystal oscillator (ECO)
- Watch crystal oscillator (WCO)
- Phase-locked loop (PLL)
- Frequency-locked loop (FLL)
• Communication interfaces
- Up to 10 CAN FD channels
• Increased data rate (up to 8 Mbps) compared to classic CAN, limited by physical layer topology and
transceivers
• Compliant to ISO 11898-1:2015
• Supports all the requirements of Bosch CAN FD Specification V1.0 for non-ISO CAN FD
• ISO 16845:2015 certificate available
- Up to 11 runtime-reconfigurable SCB (serial communication block) channels, each configurable as I2C, SPI,
or UART
- Up to 20 independent LIN channels
• LIN protocol compliant with ISO 17987
- Up to two 10/100/1000 Mbps Ethernet MAC interfaces conforming to IEEE-802.3az
• Supports the following PHY interfaces:
Media-independent interface (MII)
Reduced media-independent interface (RMII)
Gigabit media-independent interface (GMII)
Reduced gigabit media-independent interface (RGMII)
• Compliant with IEEE-802.1BA Audio Video Bridging (AVB)
• Compliant with IEEE-1588 Precision Time Protocol (PTP)
- FlexRay interface (V2.1) configurable for single or dual data-channels for fault tolerance, supporting data rates
up to 10 Mbps

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Features

• External memory interface

- One SPI (single, dual, quad, or octal) or HYPERBUS™ interface
- On-the-fly encryption and decryption
- Execute-In-Place (XIP) from external memory
• SDHC interface
- One Secure Digital High Capacity (SDHC) interface supporting embedded MultiMediaCard (eMMC), Secure
Digital (SD), or SDIO (Secure Digital Input Output)
• Compliant to eMMC 5.1, SD 6.0, and SDIO 4.10 specifications
- Data rates up to SD High Speed 50 MHz, or eMMC 52 MHz DDR
• Audio interface
- Three Inter-IC Sound (I2S) Interfaces for connecting digital audio devices
- I2S, left justified, or time division multiplexed (TDM) audio formats
- Independent transmit or receive operation, each in master or slave mode
• Timers
- Up to 102 16-bit and 16 32-bit timer/counter pulse-width modulator (TCPWM) blocks
• Up to 15 16-bit counters for motor control
• Up to 87 16-bit counters and 16 32-bit counters for regular operations
• Supports timer, capture, quadrature decoding, pulse-width modulation (PWM), PWM with dead time
(PWM_DT), pseudo-random PWM (PWM_PR), and shift-register (SR) modes
- Up to 16 Event Generation (EVTGEN) timers supporting cyclic wakeup from DeepSleep
• Events trigger a specific device operation (such as execution of an interrupt handler, a SAR ADC conversion,
and so on)
• Real time clock (RTC)
- Year/Month/Date, Day-of-week, Hour:Minute:Second fields
- 12- and 24-hour formats
- Automatic leap-year correction
• I/O
- Up to 240 programmable I/Os
- Three I/O types
• GPIO Standard (GPIO_STD)
• GPIO Enhanced (GPIO_ENH)
• High-Speed I/O Standard (HSIO_STD)
• Regulators
- Generates a 1.1-V nominal core supply from a 2.7-V to 5.5-V input supply
- Three regulators:
• DeepSleep
• Core internal
• Core external
• Programmable analog
- Three SAR A/D converters with up to 99 external channels (96 I/Os + 3 I/Os for motor control)
• Each ADC supports 32 logical channels, with 32 + 1 physical connections. Any external channel can be
connected to any logical channel in the respective SAR.
- Each ADC supports 12-bit resolution and sampling rates of up to 1 Msps
- Each ADC also supports six internal analog inputs like
• Bandgap reference to establish absolute voltage levels
• Calibrated diode for junction temperature calculations
• Two AMUXBUS inputs and two direct connections to monitor supply levels

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Features

- Each ADC supports addressing of external multiplexers

- Each ADC has a sequencer supporting autonomous scanning of configured channels
- Synchronized sampling of all ADCs for motor-sense applications
• Smart I/O
- Up to five Smart I/O blocks, which can perform Boolean operations on signals going to and from I/Os
- Up to 36 I/Os (GPIO_STD) supported
• Debug interface
- JTAG controller and interface compliant to IEEE-1149.1-2001
- Arm® SWD (serial wire debug) port
- Supports Arm® Embedded Trace Macrocell (ETM) Trace
• Data trace using SWD
• Instruction and data trace using JTAG
• Compatible with industry-standard tools
- GHS MULTI or IAR EWARM for code development and debugging
• Packages
- 176-TEQFP, 24 × 24 × 1.7 mm (max), 0.5-mm lead pitch
- 272-BGA, 16 × 16 × 1.7 mm (max), 0.8-mm ball pitch
- 320-BGA, 17 × 17 × 1.7 mm (max), 0.8-mm ball pitch
• Certification
- Qualified for automotive application according to AEC-Q100

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Table of contents

Table of contents
General description ...........................................................................................................................1
Features ...........................................................................................................................................1
Table of contents ...............................................................................................................................5
1 Features list ...................................................................................................................................6
1.1 Communication peripheral instance list ...............................................................................................................8
2 Blocks and functionality..................................................................................................................9
Architecture block diagram ................................................................................................................9
3 Functional description ..................................................................................................................10
3.1 CPU subsystem .....................................................................................................................................................10
3.1.1 CPU .....................................................................................................................................................................10
3.1.2 DMA controllers..................................................................................................................................................10
3.1.3 Flash ...................................................................................................................................................................10
3.1.4 SRAM...................................................................................................................................................................10
3.1.5 ROM ....................................................................................................................................................................10
3.1.6 Cryptography accelerator for security..............................................................................................................10
3.2 System resources..................................................................................................................................................11
3.2.1 Power system .....................................................................................................................................................11
3.2.2 Regulators ..........................................................................................................................................................11
3.2.3 Clock system ......................................................................................................................................................13
3.2.4 Reset ...................................................................................................................................................................14
3.2.5 Watchdog timer..................................................................................................................................................14
3.2.6 Power modes .....................................................................................................................................................14
3.3 Peripherals ............................................................................................................................................................15
3.3.1 Peripheral clock dividers ...................................................................................................................................15
3.3.2 Peripheral protection unit.................................................................................................................................15
3.3.3 12-bit SAR ADC ...................................................................................................................................................15
3.3.4 Timer/counter/PWM (TCPWM) block ................................................................................................................16
3.3.5 Serial communication blocks (SCB)..................................................................................................................16
3.3.6 CAN FD ................................................................................................................................................................17
3.3.7 Local interconnect network (LIN) .....................................................................................................................17
3.3.8 FlexRay interface................................................................................................................................................17
3.3.9 Ethernet MAC......................................................................................................................................................17
3.3.10 External memory interface..............................................................................................................................17
3.3.11 SDHC interface .................................................................................................................................................18
3.3.12 Audio interface.................................................................................................................................................18
3.3.13 One-time-programmable (OTP) eFuse ...........................................................................................................18
3.3.14 Event generator ...............................................................................................................................................18
3.3.15 Trigger multiplexer ..........................................................................................................................................18
3.4 I/Os.........................................................................................................................................................................18
3.4.1 Port nomenclature.............................................................................................................................................19
3.4.2 GPIO Standard (GPIO_STD) ...............................................................................................................................19
3.4.3 GPIO Enhanced (GPIO_ENH) .............................................................................................................................19
3.4.4 HSIO Standard (HSIO_STD) ...............................................................................................................................19
3.4.5 Smart I/O ............................................................................................................................................................19
4 CYT4BF address map .....................................................................................................................20
5 Flash base address map.................................................................................................................22
6 Peripheral I/O map........................................................................................................................23
7 CYT4BF clock diagram ...................................................................................................................25
8 CYT4BF CPU start-up sequence ......................................................................................................26
9 Pin assignment .............................................................................................................................27
10 High-speed I/O matrix connections ...............................................................................................31

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Based on Arm® Cortex®-M7 dual
Table of contents

11 Package pin list and alternate functions .......................................................................................32

12 Power pin assignments................................................................................................................40
13 Alternate function pin assignments ..............................................................................................41
14 Pin mux descriptions ...................................................................................................................50
15 Interrupts and wake-up assignments............................................................................................53
16 Core interrupt types ....................................................................................................................66
17 Trigger multiplexer .....................................................................................................................67
18 Triggers group inputs ..................................................................................................................68
19 Triggers group outputs ................................................................................................................73
20 Triggers one-to-one.....................................................................................................................74
21 Peripheral clocks ........................................................................................................................80
22 Faults.........................................................................................................................................85
23 Peripheral protection unit fixed structure pairs.............................................................................88
24 Bus masters.............................................................................................................................. 104
25 Miscellaneous configuration ...................................................................................................... 105
26 Development support................................................................................................................ 107
26.1 Documentation .................................................................................................................................................107
26.1.1 Software User Guide ......................................................................................................................................107
26.1.2 Technical Reference Manual .........................................................................................................................107
26.2 Tools ..................................................................................................................................................................107
27 Electrical specifications............................................................................................................. 108
27.1 Absolute maximum ratings ..............................................................................................................................108
27.2 Device-level specifications ...............................................................................................................................112
27.3 DC specifications...............................................................................................................................................113
27.4 Reset specifications ..........................................................................................................................................118
27.5 I/O ......................................................................................................................................................................120
27.6 Analog peripherals............................................................................................................................................126
27.6.1 SAR ADC ..........................................................................................................................................................126
27.6.2 Calculating the impact of neighboring pins .................................................................................................127
27.6.3 Temperature sensor ......................................................................................................................................131
27.6.4 Voltage divider accuracy ...............................................................................................................................131
27.7 AC specifications ...............................................................................................................................................132
27.8 Digital peripherals.............................................................................................................................................133
27.9 Memory..............................................................................................................................................................144
27.10 System resources............................................................................................................................................146
27.10.1 SWD interface ..............................................................................................................................................158
27.11 Clock specifications ........................................................................................................................................160
27.12 Clock timing diagrams..................................................................................................................................169
27.13 Ethernet specifications...................................................................................................................................171
27.13.1 Minimum bus frequency requirements ......................................................................................................176
27.14 SDHC specifications........................................................................................................................................177
27.15 FlexRay specifications ....................................................................................................................................182
27.16 Audio subsystem specifications.....................................................................................................................183
27.17 Serial memory interface specifications .........................................................................................................189
28 Ordering information ................................................................................................................ 196
28.1 Part number nomenclature..............................................................................................................................197
29 Packaging ................................................................................................................................ 199
30 Appendix.................................................................................................................................. 203
30.1 Bootloading or end-of-line programming .......................................................................................................203
30.2 External IP revisions..........................................................................................................................................205
31 Acronyms ................................................................................................................................. 206
32 Errata ...................................................................................................................................... 208

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Table of contents

Revision history ............................................................................................................................ 215

Revision history change log ............................................................................................................ 217

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Features list

1 Features list
Table 1-1 CYT4BF feature list for all packages
Packages
Features
176-TEQFP 272-BGA 320-BGA
CPU
Core Two 32-bit Arm® Cortex®-M7 CPUs and a 32-bit Arm® Cortex® M0+ CPU
Functional safety ASIL-B
Operating voltage 2.7 V to 5.5 V
Operating voltage for HSIO_STD Not supported 2.7 V to 3.6 V
Core voltage 1.05 V to 1.15 V
Operating frequency Arm® Cortex®-M7 350 MHz (max for each) and Arm® Cortex®-M0+ 100
MHz (max)
MPU, PPU Supported
FPU Supports both single (32-bit) and double (64-bit) precision
DSP-MUL/DIV/MAC Supported by Arm® Cortex®-M7 CPUs
TCM 16-KB instruction and 16-KB data for each Cortex®-M7 CPU
Memory
Code-flash 8384 KB (8128 KB + 256 KB)
Work-flash 256 KB (192 KB + 64 KB)
SRAM (configurable for retention) 1024 KB
ROM 64 KB
Communication interfaces
CAN0 (CAN-FD: Up to 8 Mbps) 5 ch
CAN1 (CAN-FD: Up to 8 Mbps) 5 ch
CAN RAM 40 KB per instance (5 ch), 80 KB in total
Serial communication block (SCB/UART) 10 ch 11 ch
2
Serial communication block (SCB/I C) 10 ch 11 ch
Serial communication block (SCB/SPI) 10 ch 11 ch
LIN 17 ch 20 ch
1 ch × 10/100 2 ch (option) × 10/100/1000
ETH0: MII/RMII on
GPIO_STD,
ETH0: MII/RMII on ETH1: MII/RMII/GMII/
Ethernet MAC ETH0: MII/RMII on GPIO_STD, RGMII on HSIO_STD
GPIO_STD ETH1: RGMII on ETH0: RGMII on
HSIO_STD HSIO_STD,
ETH1: RGMII on
HSIO_STD
FlexRay 1 interface of FlexRay supporting ch A and ch B (option)
Memory interfaces
eMMC/SD 1 ch (GPIO_STD at 26 MHz) 1 ch (HSIO_STD at 50 MHz, GPIO_STD at 26 MHz)

Single SPI / Dual SPI / Quad SPI / Octal SPI 1 ch (GPIO_STD at 32 MHz) 1 ch (HSIO_STD at 100 MHz, GPIO_STD at 32 MHz)
/ HYPERBUS™

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Features list

Table 1-1 CYT4BF feature list for all packages (continued)

Packages
Features
176-TEQFP 272-BGA 320-BGA
Timers
RTC 1 ch
TCPWM (16-bit) (Motor control) 15 ch (TCPWM0/3, TCPWM1/12)
TCPWM (16-bit) 87 ch (TCPWM0/3, TCPWM1/84)
TCPWM (32-bit) 16 ch (TCPWM0/3, TCPWM1/13)
External interrupts 148 220 240
Analog
3 Units (SAR0/32, SAR1/32, SAR2/32 logical channels)
81 external channels
12-bit, 1 Msps SAR ADC (SAR0/24 ch, 96 external channels
SAR1/32 ch, SAR2/25 (each SAR supports 32 ch)
ch)
18 ch (6 per ADC) Internal sampling
Motor Control Input 3 ch (synchronous sampling of one channel on each of the 3 ADCs)
Security
Flash security (program/work read pro-
Supported
tection)
Flash chip erase enable Configurable
eSHE / HSM By separate firmware[1]
Audio
I2S / TDM Tx 3 ch, Rx 3 ch
System
DMA controller P-DMA0 with 143 channels (16 general purpose), P-DMA1 with 65
channels (8 general purpose), and M-DMA0 with 8 channels
Internal Main Oscillator 8 MHz
Internal Low speed Oscillator 32.768 kHz (nominal)
PLL Input: 3.988 to 33.34 MHz, PLL output: up to 350 MHz
FLL Input: 0.25 to 80 MHz, FLL output: up to 100 MHz
Watchdog Timer and Multi-counter Supported (WDT + 3× MCWDT)
Watchdog Timer MCWDT#0 tied to CM0+, MCWDT#1 to CM7_0, MCWDT#2 to CM7_1

Clock Supervisor Supported

Cyclic wakeup from DeepSleep Supported
GPIO_STD 144 187 191
GPIO_ENH 4
HSIO_STD Not supported 29 45
Smart I/O (Blocks) 5 blocks, mapped through 36 I/Os
Low-voltage detect Two, 26 selectable levels
Maximum ambient temperature 105 °C for S-grade, 125 °C for E-grade

Note
1. Enhanced Secure Hardware Extension (eSHE) and Hardware Security Module (HSM) support are enabled by third-party firmware.

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Features list

Table 1-1 CYT4BF feature list for all packages (continued)

Packages
Features
176-TEQFP 272-BGA 320-BGA
Debug interface SWD/JTAG
Debug trace Arm® Cortex®-M7 ETB size of 8 KB, Arm® Cortex® M0+ MTB size of 4 KB

1.1 Communication peripheral instance list

The following table lists the instances supported under each package for communication peripherals, based on
the minimum pins needed for the functionality.

Table 1-2 Communication peripheral instance list

Module 176-TEQFP 272-BGA 320-BGA Minimum pin functions
CAN0 0/1/2/3/4 0/1/2/3/4 0/1/2/3/4 TX, RX
CAN1 0/1/2/3/4 0/1/2/3/4 0/1/2/3/4 TX, RX
LIN0 0 to 16 0 to 19 0 to 19 TX, RX
SCB/UART 0 to 9 0 to 10 0 to 10 TX, RX
SCB/I2C 0 to 9 0 to 10 0 to 10 SCL, SDA
SCB/SPI 0 to 9 0 to 10 0 to 10 MISO, MOSI, SCK, SELECT0

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Blocks and functionality

2 Blocks and functionality

Architecture block diagram
ITCM DTCM CPU Subsystem
16 KB 16 KB
CYT4BF ITCM DTCM
16 KB SWJ/ETM/ITM/CTI
16 KB
MXS40-HT SWJ/ETM/ITM/CTI
ASIL-B Cortex M7 SWJ/MTB/CTI
eCT FLASH SRAM0 SRAM1 SRAM2 CRYPTO Arm

143 Channel
Arm Cortex M7 ROM

M-DMA0
350 MHz

P-DMA0

P-DMA1
65 Channel

8 Channel
8384 KB Code-flash 512 KB 256 KB 256 KB AES,SHA,CRC,
350 MHz
FPU D$ I$
+ 256 KB Work-flash TRNG,RSA,ECC Cortex M0+ 64 KB
(SP/DP)
FPU D$16KB I$ 16KB 100 MHz
AHBP NVIC, MPU, AXI AHBS SRAM SRAM SRAM
System Resources (SP/DP) 16 KB 16 KB 8 KB $
Initiator/MMIO ROM Controller
Controller Controller Controller MUL, NVIC, MPU
AHBP NVIC, MPU, AXI AHBS FLASH Controller
Power
Sleep Control
POR BOD
OVD LVD System Interconnect (Multi Layer AXI/AHB, IPC, MPU/SMPU)
REF
PWRSYS-HT
LDO PCLK Peripheral Interconnect (MMIO,PPU)

Serial Memory Interface (Hyperbus, Single SPI,

Clock
Clock Control

Dual SPI, Quad SPI, Octal SPI)

2xILO WDT
Prog.

10/100/1000 Ethernet + AVB

3x MCWDT
IMO ECO Analog
TIMER,CTR,QD, PWM

SD/SDIO/eMMC
FLL CSV

Event Generator
118x TCPWM
I2S/TDM In/Out

I2C,SPI,UART,LIN

I2C,SPI,UART,LIN

1x FLEXRAY
SAR

CAN-FD Interface

FlexRay Interface
3x AUDIOSS

1x SMIF
10x CANFD
4xPLL

2x ETH

SDHC
EVTGEN
10x SCB
ADC

20x LIN

1x SCB
LIN/UART

eFUSE
Reset
IOSS GPIO

(12-bit)
Reset Control
XRES
Test
TestMode Entry x3
Digital DFT
Analog DFT

SARMUX
WCO 96 ch
RTC

Power Modes High-Speed I/O Matrix, Smart I/O, Boundary Scan

Active/Sleep 5x Smart IO
LowePowerActive/Sleep
Up to 191x GPIO_STD, 4x GPIO_ENH, 45x HSIO_STD
DeepSleep
Hibernate I/O Subsystem

The Architecture block diagram shows the CYT4BF architecture, giving a simplified view of the interconnection
between subsystems and blocks. CYT4BF has four major subsystems: CPU, system resources, peripherals, and
I/O[2, 3, 4]. The color-coding shows the lowest power mode where the particular block is still functional.
CYT4BF provides extensive support for programming, testing, debugging, and tracing of both hardware and
firmware.
Debug-on-chip functionality enables in-system debugging using the production device. It does not require
special interfaces, debugging pods, simulators, or emulators.
The JTAG interface is fully compatible with industry-standard third-party probes such as I-jet, J-Link, and GHS.
The debug circuits are enabled by default.
CYT4BF provides a high level of security with robust flash protection and the ability to disable features such as
debug.
Additionally, each device interface can be permanently disabled for applications concerned with phishing
attacks from a maliciously reprogrammed device or attempts to defeat security by starting and interrupting flash
programming sequences. All programming, debug, and test interfaces are disabled when maximum device
security is enabled.

Notes
2. GPIO_STD supports 2.7 V to 5.5 V VDDIO range.
3. GPIO_ENH supports 2.7 V to 5.5 V VDDIO range with higher currents at lower voltages.
4. HSIO_STD supports 2.7 V to 3.6 V VDDIO range with high-speed signalling and programmable drive strength.

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TRAVEO™ T2G 32-bit Automotive MCU
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Functional description

3 Functional description
3.1 CPU subsystem
3.1.1 CPU
The CYT4BF CPU subsystem contains a 32-bit Arm® Cortex®-M0+ CPU with MPU, and two 32-bit Arm® Cortex®-M7
CPUs, each with MPU, single/double-precision FPU, and 16-KB data and instruction caches. This subsystem also
includes P-/M-DMA controllers, a cryptographic accelerator, 8384 KB of code-flash, 256 KB of work-flash, 1024 KB
of SRAM, and 64 KB of ROM.
The Cortex-M0+ CPU provides a secure, un-interruptible boot function. This guarantees that, following
completion of the boot function, system integrity is valid and privileges are enforced. Shared resources (flash,
SRAM, peripherals, and so on) can be accessed through bus arbitration, and exclusive accesses are supported by
an inter-processor communication (IPC) mechanism using hardware semaphores.
Each Cortex-M7 CPU has 16 KB of instruction and 16 KB of data TCM with programmable read wait states. Each
TCM is clocked by the associated Cortex-M7 CPU clock.

3.1.2 DMA controllers

CYT4BF has three DMA controllers: P-DMA0 with 16 general purpose and 127 dedicated channels, P-DMA1 with 8
general purpose and 57 dedicated channels, and M-DMA0 with eight channels. P-DMA is used for
peripheral-to-memory and memory-to-peripheral data transfers and provides low latency for a large number of
channels. Each P-DMA controller uses a single data-transfer engine that is shared by the associated channels.
General purpose channels have a rich interconnect matrix including P-DMA cross triggering which enables
demanding data-transfer scenarios. Dedicated channels have a single triggering input (such as an ADC channel)
to handle common transfer needs. M-DMA is used for memory-to-memory data transfers and provides high
memory bandwidth for a small number of channels. M-DMA uses a dedicated data-transfer engine for each
channel. They support independent accesses to peripherals using the AHB multi-layer bus.

3.1.3 Flash
CYT4BF has 8384 KB (8128 KB with a 32-KB sector size, and 256 KB with an 8-KB sector size) of code-flash with an
additional work-flash of 256 KB (192 KB with a 2-KB sector size, and 64 KB with a 128-B sector size). Work-flash is
optimized for reprogramming many more times than code-flash. Code-flash supports Read-While-Write (RWW)
operation allowing flash to be updated while the CPU is active. Both the code-flash and work-flash areas support
dual-bank operation for over-the-air (OTA) programming.

3.1.4 SRAM
CYT4BF has 1024 KB of SRAM with three independent controllers. SRAM0 provides DeepSleep retention in 32-KB
increments while SRAM1/2 are selectable between fully retained and not retained.

3.1.5 ROM
CYT4BF has 64 KB of ROM that contains boot and configuration routines. This ROM enables secure boot and
authentication of user flash to guarantee a secure system.

3.1.6 Cryptography accelerator for security

The cryptography accelerator implements (3)DES block cipher, AES block cipher, SHA hash, cyclic redundancy
check, pseudo random number generation, true random number generation, galois/counter mode, and a vector
unit to support asymmetric key cryptography such as RSA and ECC.

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

3.2 System resources

3.2.1 Power system
The power system ensures that the supply voltage levels meet the requirements of each power mode, and
provides a full-system reset when these levels are not valid. Internal power-on reset (POR) guarantees full-chip
reset during the initial power ramp.
Three BOD circuits monitor the external supply voltages (VDDD, VDDA, VCCD). The BOD on VDDD and VCCD is initially
enabled and cannot be disabled. The BOD on VDDA is initially disabled and can be enabled by the user. For the
external supplies VDDD and VDDA, BOD circuits are software-configurable with two settings; a 2.7-V minimum
voltage that is robust for all internal signaling, and a 3.0-V minimum voltage, which is also robust for all I/O
specifications (which are guaranteed at 2.7 V). The BOD on VCCD is provided as a safety measure and is not a
robust detector.
Three over-voltage detection (OVD) circuits are provided for monitoring external supplies (VDDD, VDDA, VCCD), and
overcurrent detection circuits (OCD) for monitoring internal and external regulators. OVD thresholds on VDDD and
VDDA are configurable with two settings; a 5.0-V and 5.5-V maximum voltage.
Two voltage detection circuits are provided to monitor the external supply voltage (VDDD) for falling and rising
levels, each configurable for one of the 26 selectable levels.
All BOD, OVD, and OCD circuits on VDDD and VCCD generate a reset, because these protect the CPUs and fault logic.
The BOD and OVD circuits on VDDA can be configured to generate either a reset, or a fault.

3.2.2 Regulators
CYT4BF contains three regulators that provide power to the low-voltage core transistors: DeepSleep, core
internal, and core external. These regulators accept a 2.7-V to 5.5-V VDDD supply and provide a low-noise 1.1-V
supply to various parts of the device. These regulators are automatically enabled and disabled by hardware and
firmware when switching between power modes. The core internal and core external regulators operate in Active
mode, and provide power to the CPU subsystem and associated peripherals.

3.2.2.1 DeepSleep
The DeepSleep regulator is used to maintain power in a small number of blocks when in DeepSleep mode.
These blocks include the ILO and WDT timers, BOD detector, SCB0, SRAM memories, Smart I/O, and other
configuration memories. The DeepSleep regulator is enabled when in DeepSleep mode, and the core internal
regulator is disabled. It is disabled when XRES_L is asserted (LOW) and when the core internal regulator is
disabled.

3.2.2.2 Core internal

The core internal regulator supports load currents up to 300 mA, and is operational during device start-up
(boot process), and in Active/Sleep modes.

3.2.2.3 Core external[5]

To support worst-case loading, with both M7 CPUs and the M0+ CPU at their maximum clock frequency and all
integrated peripherals operating, a core external regulator is required, capable of load currents up to 600 mA.
While the control and monitor circuits for the core external regulator are internal to CYT4BF, the power
regulating element (NPN pass transistor, PMIC, or LDO) is external. This reduces the overall power dissipation
within the CYT4BF package, while maintaining a well-regulated core supply.

Note
5. When CYT4BF is in Hibernate mode, the GPIO used to control the core external regulator are High-Z. This may require an external
pull-up or pull-down resistor to disable the external regulator and configure it for minimum operating current.

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

The core external regulator may be implemented with either an external NPN pass transistor, PMIC, or linear
regulator (LDO). Each implementation requires different external components on the PCB, and different
connections to CYT4BF for both regulation and control.

Vpwr
(2.7-5.5V)

VDDD 10 uF

NPN transistor
TRAVEOTM T2G Emitter Follower

ZXT849K
DRV_VOUT etc

EXT_PS_CTL0 0.1Ω
1/4W
1%

EXT_PS_CTL1

Core supply rail

VCCD

CS1

Figure 3-1 Sample core external regulator with NPN transistor

2.7V – 5.5V Power rail

VDDD

Vin

Core supply rail

Switching node VCCD

External R1 CS1 TRAVEOTM T2G

PMIC
Enable
Feedback DRV_VOUT
(EN)
(FB) VD DD or
EXT_PS_CTL1

R2

Power Good Power Good

EXT_PS_CTL0 EXT_PS_CTL1
(PG)

- PMIC EN pin polarity is HIGH for enable. PMIC PG pin polarity is HIGH for power good.
- If EN pin of PMIC does not have the internal pull-down resistor, an external pull-down resistor must be placed to keep the PMIC disabled during power-on reset.
- See the Electrical Specifications section for more information on CS1.
- Output voltage setting resistors (R1, R2) are needed according to the selected PMIC.

Figure 3-2 Sample core external regulator with PMIC/LDO

Both the core internal and core external regulators require an external bulk storage capacitor connected to the
VCCD pin. This capacitor provides charge under the dynamic loads of the low-voltage core transistors.

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

3.2.3 Clock system

The CYT4BF clock system provides clocks to all subsystems that require them, and glitch-free switching between
different clock sources. In addition, the clock system ensures that no metastable conditions occur.
The clock system for CYT4BF consists of the 8-MHz IMO, two ILOs, four watchdog timers, four PLLs, an FLL, five
clock supervisors (CSV), a 8- to 33.34-MHz ECO, and a 32.768-kHz WCO.
The clock system supports three main clock domains: CLK_HF, CLK_SLOW, and CLK_LF.
• CLK_HFx are the Active mode clocks. Each can use any of the high frequency clock sources including IMO,
EXT_CLK, ECO, FLL, or PLL
• CLK_SLOW provides a reference clock for the Cortex®-CM0+ CPU, Crypto, P-/M-DMA, and other slow infra-
structure blocks of CPU subsystem
• CLK_LF is a DeepSleep domain clock and provides a reference clock for the MCWDT or RTC modules. The
reference clock for the CLK_LF domain is either disabled or selectable from ILO0, ILO1, or WCO.
Table 3-1 CLK_HF destinations
Name Description
CLK_HF0 CPUSS (Memories, CLK_SLOW, Peripherals)
CLK_HF1 CPUSS (Cortex-M7 CPU 0, 1)
CLK_HF2 CAN FD, FlexRay, LIN, TCPWM, SCB, SAR
CLK_HF3 Event Generator
CLK_HF4 Ethernet Internal Clock
CLK_HF5 Audio Subsystem (I2S), Ethernet TSU
CLK_HF6 SDHC Interface, SMIF

3.2.3.1 IMO clock source

The IMO is the frequency reference in CYT4BF when no external reference is available or enabled. The IMO
operates at a frequency of around 8 MHz.

3.2.3.2 ILO clock source

An ILO is a low-power oscillator, nominally 32.768 kHz, which generates clocks for a watchdog timer when in
DeepSleep mode. There are two ILOs to ensure clock supervisor (CSV) capability in DeepSleep mode. ILO-driven
counters can be calibrated to the IMO, WCO, or ECO to improve their accuracy. ILO1 is also used for clock super-
vision.

3.2.3.3 PLL and FLL

A PLL (one of the two 200 MHz and two 400 MHz) or FLL may be used to generate high-speed clocks from the IMO,
ECO, or an EXT_CLK. The FLL provides a much faster lock than the PLL (5 µs instead of 45 µs) in exchange for a
small amount (±2%) of frequency error[6]. The 400-MHz PLL supports spread spectrum clock generation (SSCG)
with down spreading.

3.2.3.4 Clock supervisor

Each clock supervisor (CSV) allows one clock (reference) to supervise the behavior of another clock (monitored).
Each CSV has counters for both the monitored and reference clocks. Parameters for each counter determine the
frequency of the reference clock as well as the upper and lower frequency limits of the monitored clock. If the
frequency range comparator detects a stopped clock or a clock outside the specified frequency range, an
abnormal state is signaled and either a reset or an interrupt is generated.

Note
6. Operation of reference-timed peripherals (like a UART) with an FLL-based reference is not recommended due the allowed frequency error.

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

3.2.3.5 EXT_CLK
One of three GPIO_STD I/Os can be used to provide an external clock input of up to 80 MHz. This clock can be used
as the source clock for either the PLL or FLL, or can be used directly by the CLK_HF domain.

3.2.3.6 ECO
The ECO provides high-frequency clocking using an external crystal connected to the ECO_IN and ECO_OUT pins.
It supports fundamental mode (non-overtone) quartz crystals, in the range of 8 to 33.34 MHz. When used in
conjunction with the PLL, it generates CPU and peripheral clocks up to device’s maximum frequency. ECO
accuracy depends on the selected crystal. If the ECO is disabled, the associated pins can be used for any of the
available I/O functions.

3.2.3.7 WCO
The WCO is a low-power, watch-crystal oscillator intended for real-time-clock applications. It requires an external
32.768-kHz crystal connected to the WCO_IN and WCO_OUT pins. The WCO can also be configured as a clock
reference for CLK_LF, which is the clock source for the MCWDT and RTC.

3.2.4 Reset
CYT4BF can be reset from a variety of sources, including software. Most reset events are asynchronous and
guarantee reversion to a known state. The reset cause (POR, BOD, OVD, overcurrent, XRES_L, WDT, MCWDT,
software reset, fault, CSV, Hibernate wakeup, debug) is recorded in a register, which is sticky through reset and
allows software to determine the cause of the reset. An XRES_L pin is available for external reset.

3.2.5 Watchdog timer

CYT4BF has one watchdog timer (WDT) and three multi-counter watchdog timers (MCWDT).
The WDT is a free-running counter clocked only by ILO0, which allows it to be used as a wakeup source from
Hibernate. Watchdog operation is possible during all power modes. To prevent a device reset from a WDT
timeout, the WDT must be serviced during a configured window. A watchdog reset is recorded in the reset cause
register.
An MCWDT is available for each of the CPU cores. These timers provide more capabilities than the WDT, and are
only available in Active, Sleep, and DeepSleep modes. These timers have multiple counters that can be used
separately or cascaded to trigger interrupts and/or resets. They are clocked from ILO0 or the WCO.

3.2.6 Power modes

CYT4BF has six power modes.
• Active – all peripherals are available
• Low-Power Active (LPACTIVE) – Low-power profile of Active mode where all peripherals and the CPUs are
available, but with limited capability
• Sleep – all peripherals except the CPUs are available
• Low-Power Sleep (LPSLEEP) – Low-power profile of Sleep mode where all peripherals except the CPUs are
available, but with limited capability
• DeepSleep – only peripherals which work with CLK_LF are available
• Hibernate – the device and I/O states are frozen, the device resets on wakeup

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

3.3 Peripherals
3.3.1 Peripheral clock dividers
Integer and fractional clock dividers are provided for peripheral and timing purposes.
Table 3-2 Clock dividers - CPUSS Group (Nr. 0)
Divider type Instances Description
div_8 4 Integer divider, 8 bits
div_16 3 Integer divider, 16 bits
div_24_5 1 Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)

Table 3-3 Clock dividers - COMM Group (Nr. 1)

Divider type Instances Description
div_8 19 Integer divider, 8 bits
div_16 20 Integer divider, 16 bits
div_24_5 21 Fractional divider, 24.5 bits (24 integer bits, 5 fractional bits)

3.3.2 Peripheral protection unit

The Peripheral Protection Unit (PPU) controls and monitors unauthorized access from all masters (CPU,
P-/M-DMA, CRYPTO, and any enabled debug interface) to the peripherals. It allows or restricts data transfers on
the bus infrastructure. The access rules are enforced based on specific properties of a transfer, such as an address
range for the transfer and access attributes (such as read/write, user/privilege, and secure/non-secure).

3.3.3 12-bit SAR ADC

CYT4BF contains three 1-Msps SAR ADCs. These ADCs can be clocked at up to 26.67 MHz and provide a 12-bit result
in 26 clock cycles. The references for all three SAR ADCs come from a dedicated pair of inputs: VREFH and VREFL[7].
CYT4BF supports up to 117 logical ADC channels, and external inputs from up to 99 I/Os. Each ADC also supports
six internal connections for diagnostic and monitoring purposes. The number of ADC channels (per ADC and
package type) are listed in Table 1-1.
Each ADC has a sequencer, which autonomously cycles through the configured channels (sequencer scan) with
zero-switching overhead (that is, the aggregate sampling bandwidth, when clocked at 26.67 MHz, is equal to 1
Msps whether it is for a single channel or distributed over several channels). The sequencer switching is
controlled through a state machine or firmware. The sequencer prioritizes trigger requests, enables the
appropriate analog channel, controls ADC sampling, initiates ADC data conversion, manages results, and initiates
subsequent conversions for repetitive or group conversions without CPU intervention.
Each SAR ADC has an analog multiplexer used to connect the signals to be measured to the ADC. It has 32
GPIO_STD inputs, one special GPIO_STD input for motor-sense, and six additional inputs to measure internal
signals such as a band-gap reference, a temperature sensor, and power supplies. The device supports
synchronous sampling of one motor-sense channel on each of the three ADCs.
CYT4BF has one temperature sensor that is shared by all three ADCs. The temperature sensor must only be
sampled by one ADC at a time. Software post processing is required to convert the temperature sensor reading
into kelvin or Celsius values.
To accommodate signals with varying source impedances and frequencies, you can have different sample times
programmed for each channel. Each ADC also supports range comparison, which allows fast detection of
out-of-range values without having to wait for a sequencer scan to complete and for the CPU firmware to evaluate
the measurement for out-of-range values.
The ADCs are not usable in DeepSleep and Hibernate modes as they require a high-speed clock. The ADC input
reference voltage VREFH range is 2.7 V to VDDA and VREFL is VSSA.

Note
7. VREF_L prevents IR drops in the VSSIO and VSSA paths from impacting the measurements. VREF_L, when properly connected, reduces
or removes the impact of IR drops in the VSSIO and VSSA paths from measurements.

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

3.3.4 Timer/counter/PWM (TCPWM) block

The TCPWM block consists of 16-bit (102 channels) and 32-bit (16 channels) counters with user-programmable
period. Fifteen of the 16-bit counters are optimized for motor-control operations. Each TCPWM counter contains
a capture register to record the count at the time of an event, a period register (used to either stop or auto-reload
the counter when its count is equal to the period register), and compare registers to generate signals that are
used as PWM duty-cycle outputs.
Each counter within the TCPWM block supports several functional modes such as timer, capture, quadrature,
PWM, PWM with dead-time insertion (PWM_DT, 8-bit), pseudo-random PWM (PWM_PR), and shift-register.
In motor-control applications, the counter within the TCPWM block supports enhanced quadrature mode with
features such as asymmetric PWM generation, dead-time insertion (16-bit), and association of different dead
times for PWM output signals.
The TCPWM block also provides true and complement outputs, with programmable offset between them, to
allow their use as deadband complementary PWM outputs. The TCPWM block also has a kill input (only for the
PWM mode) to force outputs to a predetermined state; for example, this may be used in motor-drive systems
when an overcurrent state is detected and the PWMs driving the FETs need to be shut off immediately (no time
for software intervention).

3.3.5 Serial communication blocks (SCB)

CYT4BF contains 11 serial communication blocks, each configurable to support I2C, UART, or SPI.

3.3.5.1 I2C interface

An SCB can be configured to implement a full I2C master (capable of multi-master arbitration) or slave
interface. Each SCB configured for I2C can operate at speeds of up to 1 Mbps (Fast-mode Plus) and has flexible
buffering options to reduce the interrupt overhead and latency of the CPU. In addition, each SCB supports FIFO
buffering for receive and transmit data, which, by increasing the time for the CPU to read the data, reduces the
need for clock stretching. The I2C interface is compatible with Standard, Fast-mode, and Fast-mode Plus
devices as specified in the NXP I2C-bus specification and user manual (UM10204). The I2C-bus I/O is
implemented with GPIO in open-drain modes[8, 9].

3.3.5.2 UART interface

When configured as a UART, each SCB provides a full-featured UART with maximum signalling rate determined
by the configured peripheral-clock frequency and over-sampling rate. It supports infrared interface (IrDA) and
SmartCard (ISO 7816) protocols, which are minor variants of the UART protocol. It also supports the 9-bit
multiprocessor mode that allows the addressing of peripherals connected over common Rx and Tx lines.
Common UART functions such as parity, number of stop bits, break detect, and frame error are supported.
FIFO buffering of transmit and receive data allows greater CPU service latencies to be tolerated.
The LIN protocol is supported by the UART. LIN is based on a single-master multi-slave topology. There is one
master node and multiple slave nodes on the LIN bus. The SCB UART supports only LIN slave functionality.
Compared to the dedicated LIN blocks, an SCB/UART used for LIN requires a higher level of software
interaction and increased CPU load.

3.3.5.3 SPI interface

The SPI configuration supports full Motorola SPI, TI Synchronous Serial Protocol (SSP, essentially adds a start
pulse that is used to synchronize SPI-based codecs), and National Microwire (a half-duplex form of SPI). The
SPI interface can use the FIFO. The SPI interface operates with up to a 12.5-MHz SPI Clock. SCB also supports
EZSPI[9] mode.

Notes
8. This is not 100% compliant with the I2C-bus specification; I/Os are not overvoltage-tolerant, do not support the 20-mA sink require-
ment of Fast-mode Plus, and violate the leakage specification when no power is applied.
9. Only Port 0 with the slew rate control enabled meets the minimum fall time requirement.
10.The Easy SPI (EZSPI) protocol is based on the Motorola SPI protocol operating in any mode (0, 1, 2, or 3). It allows communication
between master and slave while reducing the need for CPU intervention.

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

SCB0 supports the following additional features:

• Operable as a slave in DeepSleep mode
• I2C slave EZ (EZI2C[11]) mode with up to 256-B data buffer for multi-byte communication without CPU
intervention
• I2C slave externally-clocked operations
• Command/response mode with a 512-B data buffer for multi-byte communication without CPU intervention

3.3.6 CAN FD
CYT4BF contains two CAN FD controller blocks, each supporting five CAN FD channels. All CAN FD controllers are
compliant with the ISO 11898-1:2015 standard; an ISO 16845:2015 certificate is available. It also implements the
time-triggered CAN (TTCAN) protocol specified in ISO 11898-4 (TTCAN protocol levels 1 and 2) completely in
hardware. All functions concerning the handling of messages are implemented by the Rx and Tx handlers. The Rx
handler manages message acceptance filtering, transfer of received messages from the CAN core to a message
RAM, and provides receive-message status. The Tx handler is responsible for the transfer of transmit messages
from the message RAM to the CAN core, and provides transmit-message status.

3.3.7 Local interconnect network (LIN)

CYT4BF contains up to 20 LIN blocks. Each block supports transmission/reception of data following the LIN
protocol according to ISO standard 17987. Each LIN block connects to an external transceiver through a 3-pin
interface (including an enable function) and supports master and slave functionality. Each block also supports
classic and enhanced checksum, along with break detection during message reception and wake-up signaling.
Break detection, sync field, checksum calculations, and error interrupts are handled in hardware.

3.3.8 FlexRay interface

CYT4BF supports one FlexRay interface with channel A and an optional channel B, conforming to FlexRay
protocol specification 2.1, and supports up to a 10-Mbps data rate. Message buffers are configurable as Tx, Rx, or
RXFIFO, and are filtered based on FrameID, cycle count, and message ID.

3.3.9 Ethernet MAC

CYT4BF supports two Ethernet channels with transfer rates of 10, 100, or 1000 Mbps[12]. The input/output frames
and flow control are complaint to the Ethernet/IEEE 802.3az standard and also IEEE-1588 precision-time protocol
(PTP). CYT4BF supports full-duplex data transport using external PHY devices. The MAC supports glue-free
connection to PHYs through IEEE standard MII, RMII, GMII, and RGMII interfaces. The device also supports
Audio-Video Bridging (AVB). The MAC supports standard 6-byte programmable addresses. Module uses AXI
interface for DMA access.

3.3.10 External memory interface

In addition to the internal flash memory, CYT4BF supports direct connection to as much as 128-MB of external
flash or RAM memory. This connection is made through either a HYPERBUS™ or serial peripheral interface (SPI).
HYPERBUS™ allows connection to HyperFlash and HyperRAM devices, while SPI (single, dual, quad, or octal SPI)
can connect with serial flash memory. Code stored in memory connected through this interface allows
execute-in-place (XIP) operation, which does not require the instructions to be first copied to internal memory,
and on-the-fly encryption and decryption for environments requiring secure external data and code.

Notes
11.The Easy I2C (EZI2C) protocol is a unique communication scheme built on top of the I2C protocol by Cypress. It uses a meta protocol
around the standard I2C protocol to communicate to an I2C slave using indexed memory transfers. This reduces the need for CPU
intervention.
12.Only 10/100 Mbps is available in the 176-TEQFP packaged devices.

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

3.3.11 SDHC interface

CYT4BF supports one Secure Digital High Capacity (SDHC) interface, which conforms to Secure Digital (SD) 6.0,
Secure Digital Input Output (SDIO) 4.10, and Embedded Multimedia Card (eMMC) 5.1 specifications, along with
Host Control Interface (HCI) 4.2 specification. The interface supports System DMA (SDMA), Advance DMA (ADMA2,
ADMA3), and command queuing (CQ) features. This interface supports data rates of SD DS (Default Speed, 4-bits
at 25 MHz), SD HS (High Speed, 4-bits at 50 MHz, and eMMC 52-MHz DDR (8-bits at 52-MHz card clock).

3.3.12 Audio interface

CYT4BF supports three instances of Inter-IC Sound Bus (I2S) interface to connect to digital audio devices.
Supports I2S Left Justified (LJ), and eight-channel Time Division Multiplexed (TDM) digital audio interface
formats in both master and slave modes with independent operations in receive and transmit directions.

3.3.13 One-time-programmable (OTP) eFuse

CYT4BF contains a 1024-bit OTP eFuse memory that can be used to store and access a unique and unalterable
identifier or serial number for each device. eFuses are also used to control the device life-cycle (manufacturing,
programming, normal operation, end-of-life, and so on) and the security state. Of the 1024 bits, 192 are available
for user purposes.

3.3.14 Event generator

The event generator supports generation of interrupts and triggers in Active mode and interrupts in DeepSleep
mode. The event generators are used to trigger a specific device operation (execution of an interrupt handler, a
SAR ADC conversion, and so on) and to provide a cyclic wakeup mechanism from DeepSleep mode. They provide
CPU-free triggers for device functions, and reduce CPU involvement in triggering device functions, thus reducing
overall power consumption and processing overhead.

3.3.15 Trigger multiplexer

CYT4BF supports connecting various peripherals using trigger signals. Triggers are used to inform a peripheral of
the occurrence of an event or change of state. These triggers are used to affect or initiate some action in other
peripherals. The trigger multiplexer is used to route triggers from a source peripheral to a destination. Triggers
provide active logic functionality and are typically supported in Active mode.

3.4 I/Os
CYT4BF has up to 240 programmable I/Os.
The I/Os are organized as logical entities called ports, which are a maximum of 8 bits wide. During power-on, and
reset, the I/Os are forced to the High-Z state. During the Hibernate mode, I/Os are frozen.
Every I/O can generate an interrupt (if enabled) and each port has an interrupt request (IRQ) and interrupt service
routine (ISR) associated with it.
I/O port power source mapping is listed in Table 3-4. The associated supply determines the VOH, VOL, VIH, and VIL
levels when configured for CMOS and Automotive thresholds.

Table 3-4 I/O port power source

Supply pins Ports
VDDD P0, P1, P2, P3, P4, P5, P16, P17, P18, P19, P20, P21, P22, P23, P28, P29, P30, P31
VDDIO_1 P6, P7, P8, P9, P32
VDDIO_2 P10, P11, P12, P13, P14, P15
VDDIO_3 P24, P25
VDDIO_4 P26, P27, P33, P34

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Functional description

3.4.1 Port nomenclature

Px.y describes a particular bit “y” available within an I/O port “x.”
For example, P4.2 reads “port 4, bit 2”.
Each I/O implements the following:
• Programmable drive mode
- High impedance
- Resistive pull-up
- Resistive pull-down
- Open drain with strong pull-down
- Open drain with strong pull-up
- Strong pull-up or pull-down
- Weak pull-up or pull-down
CYT4BF has three types of programmable I/Os: GPIO Standard, GPIO Enhanced, and HSIO Standard.

3.4.2 GPIO Standard (GPIO_STD)

Supports standard automotive signaling across the 2.7-V to 5.5-V VDDIO range. GPIO Standard I/Os have multiple
configurable drive levels, drive modes, and selectable input levels.

3.4.3 GPIO Enhanced (GPIO_ENH)

Supports extended functionality automotive signaling across the 2.7-V to 5.5-V VDDIO range with higher currents
at lower voltages (full I2C timing support, slew-rate control).
Both GPIO_STD and GPIO_ENH implement the following:
• Configurable input threshold (CMOS, TTL, or Automotive)
• Hold mode for latching previous state (used for retaining the I/O state in DeepSleep mode)
• Analog input mode (input and output buffers disabled)

3.4.4 HSIO Standard (HSIO_STD)

These I/Os are optimized exclusively for high-speed signaling and do not support slew-rate control, DeepSleep
operation, POR mode control, analog connections, or non-CMOS signaling levels. HSIO_STD supports high-speed
peripherals such as QSPI, HYPERBUS™, Ethernet, and SDHC controller. HSIO_STD also supports programmable
drive strength. These I/Os are available only in Active mode and retain state in DeepSleep mode.

3.4.5 Smart I/O

Smart I/O allows Boolean operations on signals going to the I/O from the subsystems of the chip or on signals
coming into the chip. CYT4BF has five Smart I/O blocks. Operation can be synchronous or asynchronous and the
blocks operate in all device power modes except for Hibernate.

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Based on Arm® Cortex®-M7 dual
CYT4BF address map

4 CYT4BF address map

The CYT4BF microcontroller supports the memory spaces shown in Figure 4-1.
• 8384 KB (8128 KB + 256 KB) of code-flash, used in the single- or dual-bank mode based on the associated bit in
the flash control register
- Single-bank mode: 8384 KB
- Dual-bank mode: 4192 KB per bank
• 256 KB (192 KB + 64 KB) of work-flash, used in the single- or dual-bank mode based on the associated bit in the
flash control register
- Single-bank mode: 256 KB
- Dual-bank mode: 128 KB per bank
• 64 KB of secure ROM
• 1024 KB of SRAM (First 2 KB is reserved for internal usage)
• 16 KB of Instruction TCM for each Cortex-M7 CPU
• 16 KB of Data TCM for each Cortex-M7 CPU
• 128 MB SMIF XIP

Datasheet 22 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
CYT4BF address map

0xFFFF FFFF

Arm System
Space CPU & Debug Registers

0xE000 0000
Reserved
0xA011 3FFF
0xA011 0000 16 KB CM7_1 DTCM Core CM7_1 Data TCM
Reserved
0xA010 3FFF
0xA010 0000 16 KB CM7_1 ITCM Core CM7_1 Instruction TCM
Reserved
0xA001 3FFF
0xA001 0000 16 KB CM7_0 DTCM Core CM7_0 Data TCM
Reserved
0xA000 3FFF
0xA000 0000 16 KB CM7_0 ITCM Core CM7_0 Instruction TCM
Reserved
0x67FF FFFF
128 MB SMIF_XIP Serial Memory Interface XIP
0x6000 0000
Reserved
0x43FF FFFF
Peripheral
Mainly used for on-chip peripherals;
Interconnect or
e.g., AHB or APB peripherals
Memory map
0x4000 0000
Reserved
0x280F FFFF
0x280C 0000
256 KB SRAM2
0x280B FFFF General purpose RAM,
0x2808 0000
256 KB SRAM1 mainly used for data
0x2807 FFFF
510 KB SRAM0
0x2800 0800 2 KB
0x2800 0000
Reserved CM7 internal address map for its
0x2000 3FFF
0x2000 0000 16 KB CM7 DTCM Data TCM
Reserved Used to store manufacture specific
0x1780 7FFF Alternate Flash
0x1780 0000 32 KB Supervisory data like flash protection settings, trim
Reserved settings, device addresses, serial numbers,
0x1700 7FFF
0x1700 0000 32 KB Flash Supervisory calibration data, etc.
Reserved
0x1403 FFFF
64 KB
0x1403 0000 (128B Small Sectors) Work flash used for long
0x1402 FFFF Work flash
192 KB term data retention
(2 KB Large Sectors)
0x1400 0000
Reserved
0x1082 FFFF
256 KB
0x107F 0000 (8 KB Small Sectors)
0x107E FFFF

8128 KB Code flash Mainly used for user program code

(32 KB Large
Sectors)

0x1000 0000
Reserved Secured Boot ROM to set user specified
0x0100 FFFF
0x0100 0000 64 KB ROM Mirror protection levels, trim and configuration
Reserved data, code authentication, jump to user mode, etc.
0x0000 FFFF
0x0000 0000 64 KB ROM
CM7 internal address map for its instruction TCM.
0x0000 3FFF
0x0000 0000 16 KB CM7 ITCM The address overlaps with portion of ROM region.

Figure 4-1 CYT4BF address map[13, 14]

Notes
13.The size representation is not up to scale.
14.First 2KB of SRAM is reserved, not available for users. User must keep the power of first 32-KB block of SRAM0 in enabled or retained in
all Active, LP Active, Sleep, LP Sleep, DeepSleep modes.

Datasheet 23 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Flash base address map

5 Flash base address map

Table 5-1 through Table 5-6 give information about the sector mapping of the code- and work-flash regions
along with their respective base addresses.
Table 5-1 Code-flash address mapping in single-bank mode
Large Sectors Small Sectors
Code-flash Size (KB) Large Sector Base Address Small Sector Base Address
(LS) (SS)
8384 32 KB × 254 8 KB × 32 0x1000 0000 0x107F 0000

Table 5-2 Work-flash address mapping in single-bank mode

Work-flash Size
(KB) Large Sectors Small Sectors Large Sector Base Address Small Sector Base Address

256 2 KB × 96 128 B × 512 0x1400 0000 0x1403 0000

Table 5-3 Code-flash address mapping in dual-bank mode (Mapping A)

Second Second
First Half First Half
Code-flash First First Second Second Half Half SS
LS Base SS Base
Size (KB) Half LS Half SS Half LS Half SS Address Address
LS Base Base
Address Address
8384 32 KB × 127 8 KB × 16 32 KB × 127 8 KB × 16 0x1000 0000 0x103F 8000 0x1200 0000 0x123F 8000

Table 5-4 Code-flash address mapping in dual-bank mode (Mapping B)

Second Second
First Half First Half
Code-flash First First Second Second Half Half SS
LS Base SS Base
Size (KB) Half LS Half SS Half LS Half SS Address Address
LS Base Base
Address Address
8384 32 KB × 127 8 KB × 16 32 KB × 127 8 KB × 16 0x1200 0000 0x123F 8000 0x1000 0000 0x103F 8000

Table 5-5 Work-flash address mapping in dual-bank mode (Mapping A)

Second Second
First Half First Half
Work-flash First First Second Second LS Base SS Base
Half Half SS
Size (KB) Half LS Half SS Half LS Half SS Address Address
LS Base Base
Address Address
256 2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1400 0000 0x1401 8000 0x1500 0000 0x1501 8000

Table 5-6 Work-flash address mapping in dual-bank mode (Mapping B)

Second Second
First Half First Half
Work-flash First First Second Second LS Base SS Base
Half Half SS
Size (KB) Half LS Half SS Half LS Half SS LS Base Base
Address Address
Address Address
256 2 KB × 48 128 B × 256 2 KB × 48 128 B × 256 0x1500 0000 0x1501 8000 0x1400 0000 0x1401 8000

Datasheet 24 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral I/O map

6 Peripheral I/O map

Table 6-1 CYT4BF peripheral I/O map
Base Instance
Section Description Instances Group Slave
Address Size
Peripheral interconnect 0x4000 0000
Peripheral group (0, 1, 2, 3, 4, 5, 6, 8, 9) 0x4000 4000 9 0x40
PERI 0 0
Peripheral trigger group 0x4000 8000 13 0x400
Peripheral 1:1 trigger group 0x4000 C000 14 0x400
Peripheral interconnect, master interface 0x4002 0000
PERI_MS PERI Programmable PPU 0x4002 0000 10[15] 0x40 0 1
PERI Fixed PPU 0x4002 0800 700 0x40
PERI_PCLK Peripheral Clock Groups 0x4004 0000 2 0x2000 0 2
CRYPTO Cryptography component 0x4010 0000 1 0
CPUSS CPU subsystem (CPUSS) 0x4020 0000 2 0
Fault structure subsystem 0x4021 0000
FAULT 2 1
Fault structures 0x4021 0000 4 0x100
Inter process communication 0x4022 0000
IPC IPC structures 0x4022 0000 8 0x20 2 2
IPC interrupt structures 0x4022 1000 8 0x20
Protection 0x4023 0000
PROT Shared memory protection unit structures 0x4023 2000 16 0x40 2 3
Memory protection unit structures 0x4023 4000 16 0x400
FLASHC Flash controller 0x4024 0000 2 4
System Resources Sub-System Core Registers 0x4026 0000
Clock Supervision High Frequency 0x4026 1400 8 0x10
Clock Supervision Reference Frequency 0x4026 1710 1
Clock Supervision Low Frequency 0x4026 1720 1
SRSS 2 5
Clock Supervision Internal Low Frequency 0x4026 1730 1
Clock PLL 400 MHz 0x4026 1900 2 0x10
Multi Counter WDT 0x4026 8000 3 0x100
Free Running WDT 0x4026 C000 1
SRSS Backup Domain/RTC 0x4027 0000
BACKUP 2 6
Backup Register 0x4027 1000 4 0x04
P-DMA0 Controller 0x4028 0000
2 7
P-DMA0 channel structures 0x4028 8000 143 0x40
P-DMA
P-DMA1 Controller 0x4029 0000
2 8
P-DMA1 channel structures 0x4029 8000 65 0x40
M-DMA0 Controller 0x402A 0000
M-DMA 2 9
M-DMA0 channels 0x402A 1000 8 0x100
eFUSE eFUSE Customer Data (192 bits) 0x402C 0868 6 0x04 2 10
HSIOM High-Speed I/O Matrix (HSIOM) 0x4030 0000 35 0x10 3 0
GPIO GPIO port control/configuration 0x4031 0000 35 0x80 3 1

Note
15.These Programmable PPUs are configured by the Boot ROM and are available for the user based on the access rights. Refer to the
device-specific TRM to know more about the configuration of these programmable PPUs.

Datasheet 25 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral I/O map

Table 6-1 CYT4BF peripheral I/O map (continued)

Base Instance
Section Description Instances Group Slave
Address Size
Programmable I/O configuration 0x4032 0000
SMARTIO 3 2
SMARTIO port configuration 0x4032 0C00 5 0x100
Timer/Counter/PWM 0 (TCPWM0) 0x4038 0000
TCPWM0 Group #0 (16-bit) 0x4038 0000 3 0x80
TCPWM 3 3
TCPWM0 Group #1 (16-bit, Motor control) 0x4038 8000 3 0x80
TCPWM0 Group #2 (32-bit) 0x4039 0000 3 0x80
Event generator 0 (EVTGEN0) 0x403F 0000
EVTGEN 3 4
Event generator 0 comparator structures 0x403F 0800 16 0x20
Serial Memory Interface 0 (SMIF0) 0x4042 0000
SMIF 4 0
SMIF0 Devices 0x4042 0800 1 0x80
Secure Digital High Capacity 0 (SDHC0) 0x4046 0000
SDHC SDHC0 Wrap 0x4046 0000 4 1
SDHC0 Core 0x4046 1000
ETH Ethernet 0 (ETH0) 0x4048 0000 2 0x10000 4 2
Local Interconnect Network 0 (LIN0) 0x4050 0000
LIN 5 0
LIN0 Channels 0x4050 8000 20 0x100
CAN0 controller 0x4052 0000 5 0x200
5 1
Message RAM CAN0 0x4053 0000 0xA000
TTCANFD
CAN1 controller 0x4054 0000 5 0x200
5 2
Message RAM CAN1 0x4055 0000 0xA000
FLEXRAY FlexRay 0 0x4056 0000 5 3
Timer/Counter/PWM 1 (TCPWM1) 0x4058 0000
TCPWM1 Group #0 (16-bit) 0x4058 0000 84 0x80
TCPWM 5 4
TCPWM1 Group #1 (16-bit, Motor control) 0x4058 8000 12 0x80
TCPWM1 Group #2 (32-bit) 0x4059 0000 13 0x80
2
SCB Serial Communications Block (SPI/UART/I C) 0x4060 0000 11 0x10000 6 0-10
2 2
IS I S Audio Subsystem 0x4080 0000 3 0x1000 8 0-2
Programmable Analog Subsystem (PASS0) 0x4090 0000
SAR0 channel controller 0x4090 0000
SAR1 channel controller 0x4090 1000
SAR PASS SAR2 channel controller 0x4090 2000 9 0
SAR0 channel structures 0x4090 0800 32 0x40
SAR1 channel structures 0x4090 1800 32 0x40
SAR2 channel structures 0x4090 2800 32 0x40

Datasheet 26 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
CYT4BF clock diagram

7 CYT4BF clock diagram

IMO EXT_CLK ECO WCO ILO0 ILO1

ECO LS LS LS
Prescaler

MUX MUX MUX MUX MUX MUX LS

MUX MUX MUX MUX MUX MUX MUX

FLL PLL400#0 PLL400#1 PLL#2 PLL#3 MUX CLK_ILO0

LS
CLK_ CLK_ CLK_ CLK_ CLK_ CLK_
CLK_REF_HF
PATH0 PATH1 PATH2 PATH3 PATH4 PATH5 WDT
MUX

CLK_LF CLK_BAK
RTC
CSV

CLK_ILO0 MUX MUX MUX MUX MUX MUX MUX MUX MCWDT

Predivider Predivider Predivider Predivider Predivider Predivider Predivider Predivider

(1/2/4/8) (1/2/4/8) (1/2/4/8) (1/2/4/8) (1/2/4/8) (1/2/4/8) (1/2/4/8) (1/2/4/8)

CLK_HF0 CLK_HF1 CLK_HF2 CLK_HF3 CLK_HF4 CLK_HF5 CLK_HF6 CLK_HF7

CSV CSV

CSV CSV CSV CSV CSV CSV CSV CSV CLK_ILO0 CLK_LF
CLK_REF_HF

SDHC

AUDIOSS I2S External Clock

Ethernet Tx_CLK, Rx_CLK and REF_CLK to Ethernet PHY

Event Generator

Divider CLK_GR5
(1-256) CAN FD

FLEX-RAY

LIN

TCPWM[1]

Divider CLK_GR6
(1-256) SCB[*] Serial Interface Clock

SCB[0]

Divider CLK_GR9
(1-256) SAR ADC

PCLK_CANFD[x]_CLOCK_CAN[y]
PCLK_FLEXRAY_CLK_FLEXRAY
Peripheral PCLK_LIN_CLOCK_CH_EN[x]
Clock Dividers #1 PCLK_TCPWM1_CLOCKS[x]
PCLK_SCB[x]_CLOCK
PCLK_PASS_CLOCK_SAR[x]

Divider CLK_FAST_0
CM7_0
(1-256)

Divider CLK_FAST_1
CM7_1
(1-256)

SMIF

Divider CLK_MEM
(1-256)
ROM/SRAM/FLASH

CPUSS Fast Infrastructure

Divider CLK_SLOW
(1-256) CM0+
LEGEND 1:
Active Domain
DeepSleep Domain CPUSS Slow Infrastructure
Hibernate Domain
P-DMA / M-DMA

LEGEND 2: Divider CLK_PERI Divider CLK_GR3

Relationship of Monitored Clock and (1-256) (1-256) CRYPTO
Reference Clock
Monitored Clock PERI
Divider CLK_GR4
(1-256)
Reference Clock CSV SRSS

Divider CLK_GR8
EFUSE
(1-256)
LEGEND 3:
One Clock Line
IOSS
Multiple Clock Lines

TCPWM[0]

Peripheral
Clock Dividers #0 CPUSS(DEBUG) TCK/SWDCLK from a Debugger

Divider CLK_TRC_DBG
(1-256) PCLK_SMARTIO[x]_CLOCK
PCLK_TCPWM0_CLOCKS[x]
PCLK_CPUSS_CLOCK_TRACE_IN

Figure 7-1 CYT4BF clock diagram

Datasheet 27 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
CYT4BF CPU start-up sequence

8 CYT4BF CPU start-up sequence

The start-up sequence is described in the following steps:
1. System Reset (@0x0000 0000)
2. CM0+ executes ROM boot (@0x0000 0004)
i. Applies trims
ii. Applies Debug Access port (DAP) access restrictions and system protection from eFuse and supervisory
flash
iii.Authenticates flash boot (only in SECURE life-cycle stage) and transfers control to it
3. CM0+ executes flash boot (from Supervisory flash @0x1700 2000)
i. Debug pins are configured based on the SWD/JTAG spec[16]
ii. Sets CM0+ vector offset register (CM0_VTOR part of the Arm® system space) to the beginning of flash
(@0x1000 0000)
iii.CM0+ branches to its Reset handler
4. CM0+ starts execution of application
i. Moves CM0+ vector table to SRAM (updates CM0+ vector table base)
ii. Sets clocks for CM7_0 (CLK_HF1) and CM7_1 (CLK_HF1)
iii.Sets CM7_0 (CM7_0_VECTOR_TABLE_BASE @0x4020 0200) and CM7_1 (CM7_1_VECTOR_TABLE_BASE
@0x4020 0600) vector tables to the respective locations, also and mentioned in flash (specified in the linker
definition file)
iv.Enables the power for both the CPU cores CM7_0 and CM7_1
v. Disables CPU_WAIT to allow accesses from the debugger
vi.Releases CM7_0 and/or CM7_1 from reset
vii.Continues execution of CM0+ user application
5. CM7_0 and/or CM7_1 executes directly from either code-flash or SRAM
i. CM7_0/CM7_1 branches to its Reset handler
ii. Continues execution of the user application

Note
16.Port configuration of SWD/JTAG pins will be changed from the default GPIO mode to support debugging after the boot process, refer
to Table 11-1 for pin assignments.

Datasheet 28 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin assignment

9 Pin assignment
Note: Thermal pad needs to be connected to VSSD.

DRV_VOUT

XRES_L
VDDD

VCCD

VDDD
VSSD
VSSD

VSSD
P23.2
P23.3

P22.4

P21.7
P23.7
P23.6
P23.5
P23.4

P23.1
P23.0
P22.7
P22.6
P22.5

P22.3

P21.5

P21.4

P20.6

P20.3

P20.0

P19.1
P22.2
P22.1

P21.6

P21.3
P21.2
P21.1
P21.0
P20.7

P20.5
P20.4

P20.2
P20.1

P19.4
P19.3
P19.2

P19.0
170
176

171

164

159
175
174
173
172

169
168
167
166
165

163
162
161
160

158
157
156
155
154
153
152
151
150
149
148

146
145
144
143
142
141
140
139
138
137
136
135
134
133
147
VSSD 1 132 VDDD
P0.0 2 131 P18.7
P0.1 3 130 P18.6
P0.2 4 129 P18.5
P0.3 5 128 P18.4
P1.0 6 127 P18.3
P1.1 7 126 P18.2
P1.2 8 125 P18.1
P1.3 9 124 P18.0
P2.0 10 123 P17.7
P2.1 11 122 P17.6
P2.2 12 121 P17.5
P2.3 13 120 P17.4
P2.4 14 119 P17.3
P2.5 15 118 P17.2
P3.0 16 117 P17.1
P3.1 17 116 P17.0
P3.2 18 115 P16.3
P3.3 19 114 VSSD
P3.4 20 113 VCCD
P3.5 21 112 VCCD
VDDD
VSSD
22
23
176-TEQFP 111
110
VCCD
VDDD
P4.0 24 109 P15.3
P4.1 25 108 P15.2
P4.2 26 107 P15.1
P4.3 27 106 P15.0
P4.4 28 105 P14.7
P5.0 29 104 P14.6
P5.1 30 103 P14.5
P5.2 31 102 P14.4
P5.3 32 101 P14.3
P5.4 33 100 P14.2
P5.5 34 99 P14.1
P6.0 35 98 P14.0
P6.1 36 97 P13.7
P6.2 37 96 P13.6
P6.3 38 95 P13.5
P6.4 39 94 P13.4
P6.5 40 93 P13.3
P6.6 41 92 P13.2
P6.7 42 91 P13.1
VDDD 43 90 P13.0
VDDIO_1 44 89 VSSD
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSSD
VCCD
VCCD
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
P8.2
P8.3
P8.4
P9.0
P9.1
P9.2
P9.3
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
VREFL
VSSA
VDDA
VREFH
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
VDDIO_2

Figure 9-1 176-TEQFP pin assignment

Datasheet 29 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin assignment

PWM1_26/PWM1_M_3_N/TC1_26_TR0/TC1_M_3_TR1/ETH0_RXD_1 (0)/TC1_H_0_TR1/SCB2_MOSI (1)/SCB2_SDA (1)/SCB2_TX (1)/CAN1_3_RX/FAULT_OUT_3/ADC[2]_25

PWM1_37/PWM1_38_N/TC1_37_TR0/TC1_38_TR1/PWM1_34/PWM1_35_N/ETH0_RX_CTL (0)/TC1_35_TR1/TC1_34_TR0/LIN0_RX/CAN1_1_TX/TRACE_DATA_0 (1)
PWM1_22/PWM1_23_N/TC1_22_TR0/TC1_23_TR1/EXT_CLK/LIN9_EN/TC1_H_9_TR1/SCB2_SEL0 (2)/CAL_SUP_NZ/SWJ_SWDOE_TDI/HIBERNATE_WAKEUP[1]

PWM1_M_3/PWM1_50_N/TC1_M_3_TR0/TC1_50_TR1/ETH0_RXD_0 (0)/TC1_H_0_TR0/SCB2_MISO (1)/SCB2_RX (1)/CAN1_3_TX/FAULT_OUT_2/ADC[2]_24

PWM1_27/PWM1_26_N/TC1_27_TR0/TC1_26_TR1/ETH0_RXD_2 (0)/TC1_H_1_TR0/SCB2_CLK (1)/SCB2_SCL (1)/SCB2_RTS (1)/TRIG_IN[28]/ADC[2]_26
PWM1_M_11/PWM1_M_10_N/TC1_M_11_TR0/TC1_M_10_TR1/ETH0_RX_CLK (0)/SCB7_CTS (1)/SCB7_SEL0 (1)/LIN6_TX/FAULT_OUT_3/TRIG_IN[30]
PWM1_25/PWM1_M_11_N/TC1_25_TR0/TC1_M_11_TR1/PWM1_H_9/SCB2_MISO (2)/SCB7_SEL1 (1)/TRIG_DBG[0]/SWJ_SWO_TDO/TRIG_IN[31]

PWM1_33/PWM1_34_N/TC1_33_TR0/TC1_34_TR1/SCB6_TX (1)/SCB6_SDA (1)/SCB6_MOSI (1)/CAN1_1_RX/TRACE_DATA_1 (1)/EXT_PS_CTL0

PWM1_28/PWM1_27_N/TC1_28_TR0/TC1_27_TR1/ETH0_RXD_3 (0)/TC1_H_1_TR1/SCB2_SEL0 (1)/SCB2_CTS (1)/TRIG_IN[29]/ADC[2]_27

PWM1_M_8/PWM1_27_N/TC1_M_8_TR0/TC1_27_TR1/TC1_H_8_TR1/SCB7_RX (1)/LIN14_TX/SCB7_MISO (1)/CAN1_0_TX/FAULT_OUT_0

PWM1_32/PWM1_33_N/TC1_32_TR0/TC1_33_TR1/SCB6_RTS (1)/SCB6_SCL (1)/SCB6_CLK (1)/TRACE_DATA_2 (1)/EXT_PS_CTL1

PWM1_M_9/PWM1_M_8_N/TC1_M_9_TR0/TC1_M_8_TR1/SCB7_TX (1)/SCB7_SDA (1)/SCB7_MOSI (1)/CAN1_0_RX/FAULT_OUT_1
PWM1_M_10/PWM1_M_9_N/TC1_M_10_TR0/TC1_M_9_TR1/SCB7_RTS (1)/SCB7_SCL (1)/SCB7_CLK (1)/LIN6_RX/FAULT_OUT_2
PWM1_24/PWM1_25_N/TC1_24_TR0/TC1_25_TR1/LIN9_RX/PWM1_H_9_N/SCB2_MOSI (2)/SCB7_SEL2 (1)/SWJ_SWCLK_TCLK

PWM1_35/PWM1_36_N/TC1_35_TR0/TC1_36_TR1/SCB6_RX (1)/SCB6_MISO (1)/LIN0_EN/LIN13_TX/CAL_SUP_NZ/RTC_CAL

PWM1_31/PWM1_32_N/TC1_31_TR0/TC1_32_TR1/SCB6_CTS (1)/SCB6_SEL0 (1)/TRACE_DATA_3 (1)/EXT_PS_CTL2
PWM1_23/PWM1_24_N/TC1_23_TR0/TC1_24_TR1/LIN9_TX/TC1_H_9_TR0/SCB2_CLK (2)/SWJ_SWDIO_TMS

PWM1_46/PWM1_47_N/TC1_46_TR0/TC1_47_TR1/SCB1_TX (1)/SCB1_SDA (1)/SCB1_MOSI (1)/CAN1_2_RX

PWM1_30/PWM1_29_N/TC1_30_TR0/TC1_29_TR1/TC1_H_2_TR1/SCB2_SEL2 (1)/LIN5_RX/ADC[2]_29
PWM1_45/PWM1_46_N/TC1_45_TR0/TC1_46_TR1/SCB1_RTS (1)/SCB1_SCL (1)/SCB1_CLK (1)
PWM1_44/PWM1_45_N/TC1_44_TR0/TC1_45_TR1/SCB1_CTS (1)/SCB1_SEL0 (1)/CAN1_4_TX

PWM1_47/PWM1_48_N/TC1_47_TR0/TC1_48_TR1/SCB1_RX (1)/SCB1_MISO (1)/CAN1_2_TX

PWM1_29/PWM1_28_N/TC1_29_TR0/TC1_28_TR1/TC1_H_2_TR0/SCB2_SEL1 (1)/ADC[2]_28
PWM1_29/PWM1_30_N/TC1_29_TR0/TC1_30_TR1/PWM1_H_8/SCB6_SEL2 (1)/LIN7_RX
PWM1_30/PWM1_31_N/TC1_30_TR0/TC1_31_TR1/SCB6_SEL1 (1)/TRACE_CLOCK (1)

PWM1_48/PWM1_49_N/TC1_48_TR0/TC1_49_TR1/TC1_H_3_TR1/LIN5_EN/ADC[2]_31
PWM1_49/PWM1_30_N/TC1_49_TR0/TC1_30_TR1/TC1_H_3_TR0/LIN5_TX/ADC[2]_30
PWM1_27/PWM1_28_N/TC1_27_TR0/TC1_28_TR1/TC1_H_8_TR0/LIN14_RX/LIN7_EN

PWM1_40/PWM1_41_N/TC1_40_TR0/TC1_41_TR1/EXT_CLK/TRIG_DBG[1]/ECO_IN

PWM1_43/PWM1_44_N/TC1_43_TR0/TC1_44_TR1/SCB1_SEL1 (1)/CAN1_4_RX
PWM1_38/PWM1_39_N/TC1_38_TR0/TC1_39_TR1/HIBERNATE_WAKEUP[0]

PWM1_42/PWM1_43_N/TC1_42_TR0/TC1_43_TR1/SCB1_SEL2 (1)/WCO_IN
PWM1_28/PWM1_29_N/TC1_28_TR0/TC1_29_TR1/PWM1_H_8_N/LIN7_TX

PWM1_36/PWM1_37_N/TC1_36_TR0/TC1_37_TR1/LIN0_TX/LIN13_RX

PWM1_41/PWM1_42_N/TC1_41_TR0/TC1_42_TR1/WCO_OUT
PWM1_39/PWM1_40_N/TC1_39_TR0/TC1_40_TR1/ECO_OUT
DRV_VOUT

XRES_L
VDDD

VCCD

VDDD
VSSD
VSSD

VSSD
P23.7
P23.6

P23.3

P23.1

P22.7
P22.6

P22.4
P22.3

P21.7
P21.6

P21.3

P21.1
P21.2

P20.6

P20.2

P20.0
P19.4
P19.3

P19.1
P19.0
P23.5

P23.2
P23.4

P23.0

P22.5

P22.2
P22.1

P21.5

P21.4

P21.0
P20.7

P20.5
P20.4
P20.3

P20.1

P19.2
176
175
174
173
172
171
170
169
168
167
166
165
164
163
162
161
160
159
158
157
156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
VSSD 1 132 VDDD
PWM1_18/PWM1_22_N/TC1_18_TR0/TC1_22_TR1/PWM0_H_0/SCB0_RX (0)/SCB7_SDA (2)/SCB0_MISO (0)/LIN1_RX P0.0 2 131 P18.7 PWM1_50/PWM1_51_N/TC1_50_TR0/TC1_51_TR1/TC0_M_2_TR1/ETH0_TXD_3 (0)/PWM1_H_3_N/CAN1_2_RX/TRACE_DATA_3 (0)/ADC[2]_23
PWM1_17/PWM1_18_N/TC1_17_TR0/TC1_18_TR1/PWM0_H_0_N/SCB0_TX (0)/SCB7_SCL (2)/SCB0_MOSI (0)/LIN1_TX P0.1 3 130 P18.6 PWM1_51/PWM1_52_N/TC1_51_TR0/TC1_52_TR1/TC0_M_2_TR0/ETH0_TXD_2 (0)/PWM1_H_3/SCB1_SEL3 (0)/CAN1_2_TX/TRACE_DATA_2 (0)/ADC[2]_22
PWM1_14/PWM1_17_N/TC1_14_TR0/TC1_17_TR1/TC0_H_0_TR0/SCB0_RTS (0)/SCB0_SCL (0)/SCB0_CLK (0)/SCB4_MISO (2)/LIN1_EN/CAN0_1_TX P0.2 4 129 P18.5 PWM1_52/PWM1_53_N/TC1_52_TR0/TC1_53_TR1/PWM0_M_2_N/ETH0_TXD_1 (0)/PWM1_H_2_N/SCB1_SEL2 (0)/TRACE_DATA_1 (0)/ADC[2]_21
PWM1_13/PWM1_14_N/TC1_13_TR0/TC1_14_TR1/TC0_H_0_TR1/SCB0_CTS (0)/SCB0_SDA (0)/SCB0_SEL0 (0)/SCB4_MOSI (2)/CAN0_1_RX P0.3 5 128 P18.4 PWM1_53/PWM1_54_N/TC1_53_TR0/TC1_54_TR1/PWM0_M_2/ETH0_TXD_0 (0)/PWM1_H_2/SCB1_SEL1 (0)/SCB3_SEL0 (2)/TRACE_DATA_0 (0)/ADC[2]_20
PWM1_12/PWM1_13_N/TC1_12_TR0/TC1_13_TR1/PWM1_H_4/SCB0_SCL (1)/SCB0_MISO (1)/SCB4_CLK (2) P1.0 6 127 P18.3 PWM1_54/PWM1_55_N/TC1_54_TR0/TC1_55_TR1/ETH0_TX_CLK (0)/PWM1_H_1_N/SCB1_CTS (0)/SCB1_SEL0 (0)/SCB3_CLK (2)/TRACE_CLOCK (0)/ADC[2]_19
PWM1_11/PWM1_12_N/TC1_11_TR0/TC1_12_TR1/PWM1_H_5/SCB0_SDA (1)/SCB0_MOSI (1)/SCB4_SEL0 (2) P1.1 7 126 P18.2 PWM1_55/PWM1_M_7_N/TC1_55_TR0/TC1_M_7_TR1/ETH0_TX_ER (0)/PWM1_H_1/SCB1_RTS (0)/SCB1_SCL (0)/SCB1_CLK (0)/SCB3_MOSI (1)/ADC[2]_18
PWM1_10/PWM1_11_N/TC1_10_TR0/TC1_11_TR1/PWM1_H_6/SCB0_CLK (1)/LIN0_RX/TRIG_IN[0] P1.2 8 125 P18.1 PWM1_M_7/PWM1_M_6_N/TC1_M_7_TR0/TC1_M_6_TR1/ETH0_TX_CTL (0)/PWM1_H_0_N/SCB1_TX (0)/SCB1_SDA (0)/SCB1_MOSI (0)/SCB3_MISO (1)/FAULT_OUT_1/ADC[2]_17
PWM1_8/PWM1_10_N/TC1_8_TR0/TC1_10_TR1/PWM1_H_7/SCB0_SEL0 (1)/LIN0_TX/TRIG_IN[1] P1.3 9 124 P18.0 PWM1_M_6/PWM1_M_5_N/TC1_M_6_TR0/TC1_M_5_TR1/ETH0_REF_CLK (0)/PWM1_H_0/SCB1_RX (0)/SCB1_MISO (0)/LIN12_TX/FAULT_OUT_0/ADC[2]_16
PWM1_7/PWM1_8_N/TC1_7_TR0/TC1_8_TR1/TC1_H_4_TR0/SCB7_RX (0)/SCB0_SEL1 (0)/SCB7_MISO (0)/LIN0_RX/CAN0_0_TX/SWJ_TRSTN/TRIG_IN[2] P2.0 10 123 P17.7 PWM1_M_5/PWM1_M_4_N/TC1_M_5_TR0/TC1_M_4_TR1/LIN15_EN/LIN12_RX/ADC[2]_15
PWM1_6/PWM1_7_N/TC1_6_TR0/TC1_7_TR1/TC1_H_5_TR0/SCB7_TX (0)/SCB7_SDA (0)/SCB0_SEL2 (0)/SCB7_MOSI (0)/LIN0_TX/CAN0_0_RX/TRIG_IN[3] P2.1 11 122 P17.6 PWM1_M_4/PWM1_56_N/TC1_M_4_TR0/TC1_56_TR1/PWM1_H_2_N/LIN15_TX/SCB3_SEL2 (1)/ADC[2]_14
PWM1_5/PWM1_6_N/TC1_5_TR0/TC1_6_TR1/ETH0_RX_ER (0)/TC1_H_6_TR0/SCB7_RTS (0)/SCB7_SCL (0)/SCB0_SEL3 (0)/SCB7_CLK (0)/LIN0_EN/TRIG_IN[4] P2.2 12 121 P17.5 PWM1_56/PWM1_57_N/TC1_56_TR0/TC1_57_TR1/PWM1_H_2/LIN15_RX/SCB3_SEL1 (1)/ADC[2]_13
PWM1_4/PWM1_5_N/TC1_4_TR0/TC1_5_TR1/ETH0_ETH_TSU_TIMER_CMP_VAL (0)/TC1_H_7_TR0/SCB7_CTS (0)/SCB7_SEL0 (0)/LIN5_RX/TRIG_IN[5] P2.3 13 120 P17.4 PWM1_57/PWM1_58_N/TC1_57_TR0/TC1_58_TR1/PWM1_H_3_N/SCB3_CTS (1)/SCB3_SEL0 (1)/TRIG_IN[27]/ADC[2]_12
PWM1_3/PWM1_4_N/TC1_3_TR0/TC1_4_TR1/PWM1_H_4_N/SCB7_SEL1 (0)/LIN5_TX/TRIG_IN[6] P2.4 14 119 P17.3 PWM1_58/PWM1_59_N/TC1_58_TR0/TC1_59_TR1/PWM1_H_3/SCB3_RTS (1)/SCB3_SCL (1)/SCB3_CLK (1)/TRIG_IN[26]/ADC[2]_11
PWM1_2/PWM1_3_N/TC1_2_TR0/TC1_3_TR1/PWM1_H_5_N/SCB7_SEL2 (0)/LIN5_EN/TRIG_IN[7] P2.5 15 118 P17.2 PWM1_59/PWM1_60_N/TC1_59_TR0/TC1_60_TR1/SCB3_TX (1)/SCB3_SDA (1)/LIN11_EN/ADC[2]_10
PWM1_1/PWM1_2_N/TC1_1_TR0/TC1_2_TR1/ETH0_MDIO (0)/PWM1_H_6_N/SCB6_RX (0)/SCB6_MISO (0)/CAN0_3_TX/TRIG_DBG[0] P3.0 16 117 P17.1 PWM1_60/PWM1_61_N/TC1_60_TR0/TC1_61_TR1/SCB3_RX (1)/LIN11_TX/CAN1_1_RX/ADC[2]_9
PWM1_0/PWM1_1_N/TC1_0_TR0/TC1_1_TR1/ETH0_MDC (0)/PWM1_H_7_N/SCB6_TX (0)/SCB6_SDA (0)/SCB6_MOSI (0)/CAN0_3_RX/TRIG_DBG[1] P3.1 17 116 P17.0 PWM1_61/PWM1_62_N/TC1_61_TR0/TC1_62_TR1/LIN11_RX/CAN1_1_TX/ADC[2]_8
PWM1_M_3/PWM1_0_N/TC1_M_3_TR0/TC1_0_TR1/TC1_H_4_TR1/SCB6_RTS (0)/SCB6_SCL (0)/SCB6_CLK (0) P3.2 18 115 P16.3 PWM1_62/PWM1_62_N/TC1_62_TR0/TC1_62_TR1/PWM1_H_1_N/ADC[2]_3
PWM1_M_2/PWM1_M_3_N/TC1_M_2_TR0/TC1_M_3_TR1/TC1_H_5_TR1/SCB6_CTS (0)/SCB6_SEL0 (0) P3.3 19 114 VSSD
PWM1_M_1/PWM1_M_2_N/TC1_M_1_TR0/TC1_M_2_TR1/TC1_H_6_TR1/SCB6_SEL1 (0)/LIN1_RX P3.4 20 113 VCCD

176-TEQFP
PWM1_M_0/PWM1_M_1_N/TC1_M_0_TR0/TC1_M_1_TR1/TC1_H_7_TR1/SCB6_SEL2 (0)/LIN1_TX P3.5 21 112 VCCD
VDDD 22 111 VCCD
VSSD 23 110 VDDD
PWM1_4/PWM1_M_0_N/TC1_4_TR0/TC1_M_0_TR1/EXT_MUX[0]_0/SCB5_RX (0)/SCB5_MISO (0)/LIN1_RX/TRIG_IN[10] P4.0 24 109 P15.3 PWM1_59/PWM1_58_N/TC1_59_TR0/TC1_58_TR1/AUDIOSS2_RX_SDI/TC1_H_7_TR1/SCB9_CTS (0)/SCB9_SEL0 (0)/ADC[1]_31
PWM1_5/PWM1_4_N/TC1_5_TR0/TC1_4_TR1/EXT_MUX[0]_1/SCB5_TX (0)/SCB5_SDA (0)/SCB5_MOSI (0)/LIN1_TX/TRIG_IN[11] P4.1 25 108 P15.2 PWM1_58/PWM1_57_N/TC1_58_TR0/TC1_57_TR1/AUDIOSS2_RX_WS/TC1_H_7_TR0/SCB9_RTS (0)/SCB9_SCL (0)/SCB9_CLK (0)/ADC[1]_30
PWM1_6/PWM1_5_N/TC1_6_TR0/TC1_5_TR1/EXT_MUX[0]_2/SCB5_RTS (0)/SCB5_SCL (0)/SCB5_CLK (0)/LIN1_EN/TRIG_IN[12] P4.2 26 107 P15.1 PWM1_57/PWM1_56_N/TC1_57_TR0/TC1_56_TR1/AUDIOSS2_RX_SCK/TC1_H_6_TR1/SCB9_TX (0)/SCB9_SDA (0)/SCB9_MOSI (0)/CAN1_3_RX/ADC[1]_29
PWM1_7/PWM1_6_N/TC1_7_TR0/TC1_6_TR1/EXT_MUX[0]_EN/SCB5_CTS (0)/SCB5_SEL0 (0)/CAN0_1_TX/TRIG_IN[13] P4.3 27 106 P15.0 PWM1_56/PWM1_55_N/TC1_56_TR0/TC1_55_TR1/AUDIOSS2_CLK_I2S_IF/TC1_H_6_TR0/SCB9_RX (0)/SCB9_MISO (0)/CAN1_3_TX/ADC[1]_28
PWM1_8/PWM1_7_N/TC1_8_TR0/TC1_7_TR1/LIN15_RX/SCB5_SEL1 (0)/CAN0_1_RX P4.4 28 105 P14.7 PWM1_55/PWM1_54_N/TC1_55_TR0/TC1_54_TR1/TC1_H_5_TR1/LIN14_EN/TRIG_IN[25]/ADC[1]_27
PWM1_9/PWM1_8_N/TC1_9_TR0/TC1_8_TR1/PWM0_M_0/PWM1_H_10/LIN15_TX/SCB5_SEL2 (0)/LIN7_RX/TRIG_IN[38] P5.0 29 104 P14.6 PWM1_54/PWM1_53_N/TC1_54_TR0/TC1_53_TR1/TC1_H_5_TR0/LIN14_TX/TRIG_IN[24]/ADC[1]_26
PWM1_10/PWM1_9_N/TC1_10_TR0/TC1_9_TR1/PWM0_M_0_N/PWM1_H_10_N/SCB9_SEL3 (1)/LIN7_TX/TRIG_IN[39] P5.1 30 103 P14.5 PWM1_53/PWM1_52_N/TC1_53_TR0/TC1_52_TR1/AUDIOSS2_TX_SDO/TC1_H_4_TR1/SCB2_SEL2 (0)/LIN14_RX/ADC[1]_25
PWM1_11/PWM1_10_N/TC1_11_TR0/TC1_10_TR1/TC0_M_0_TR0/TC1_H_10_TR0/LIN10_RX/LIN7_EN P5.2 31 102 P14.4 PWM1_52/PWM1_51_N/TC1_52_TR0/TC1_51_TR1/AUDIOSS2_TX_WS/TC1_H_4_TR0/SCB2_SEL1 (0)/LIN6_EN/ADC[1]_24
PWM1_12/PWM1_11_N/TC1_12_TR0/TC1_11_TR1/TC0_M_0_TR1/TC1_H_10_TR1/LIN10_TX/LIN2_RX P5.3 32 101 P14.3 PWM1_51/PWM1_50_N/TC1_51_TR0/TC1_50_TR1/TC0_M_1_TR1/PWM1_H_7_N/SCB2_SEL0 (0)/SCB2_CTS (0)/LIN6_TX/ADC[1]_23
PWM1_13/PWM1_12_N/TC1_13_TR0/TC1_12_TR1/LIN9_RX/PWM1_H_11/LIN2_TX P5.4 33 100 P14.2 PWM1_50/PWM1_49_N/TC1_50_TR0/TC1_49_TR1/TC0_M_1_TR0/PWM1_H_7/SCB2_CLK (0)/SCB2_SCL (0)/SCB2_RTS (0)/LIN6_RX/ADC[1]_22
PWM1_14/PWM1_13_N/TC1_14_TR0/TC1_13_TR1/LIN9_TX/PWM1_H_11_N/LIN2_EN P5.5 34 99 P14.1 PWM1_49/PWM1_48_N/TC1_49_TR0/TC1_48_TR1/PWM0_M_1_N/AUDIOSS2_TX_SCK/PWM1_H_6_N/SCB2_MOSI (0)/SCB2_SDA (0)/SCB2_TX (0)/CAN1_0_RX/ADC[1]_21
PWM1_M_0/PWM1_14_N/TC1_M_0_TR0/TC1_14_TR1/PWM0_0/LIN9_EN/TC1_H_11_TR0/SCB4_RX (0)/SCB4_MISO (0)/LIN3_RX/ADC[0]_0 P6.0 35 98 P14.0 PWM1_48/PWM1_47_N/TC1_48_TR0/TC1_47_TR1/PWM0_M_1/AUDIOSS2_MCLK/PWM1_H_6/SCB2_MISO (0)/SCB2_RX (0)/CAN1_0_TX/ADC[1]_20
PWM1_0/PWM1_M_0_N/TC1_0_TR0/TC1_M_0_TR1/TC1_H_11_TR1/SCB4_TX (0)/SCB4_SDA (0)/SCB4_MOSI (0)/LIN3_TX/ADC[0]_1 P6.1 36 97 P13.7 PWM1_47/PWM1_M_11_N/TC1_47_TR0/TC1_M_11_TR1/AUDIOSS1_RX_SDI/PWM1_H_5_N/TRIG_IN[23]/ADC[1]_19
PWM1_M_1/PWM1_0_N/TC1_M_1_TR0/TC1_0_TR1/PWM0_0_N/SDHC_CARD_MECH_WRITE_PROT (0)/PWM1_H_12/SCB4_RTS (0)/SCB4_SCL (0)/SCB4_CLK (0)/LIN3_EN/CAN0_2_TX/ADC[0]_2 P6.2 37 96 P13.6 PWM1_M_11/PWM1_46_N/TC1_M_11_TR0/TC1_46_TR1/LIN8_EN/AUDIOSS1_RX_WS/PWM1_H_5/SCB3_SEL3 (0)/TRIG_IN[22]/ADC[1]_18
PWM1_1/PWM1_M_1_N/TC1_1_TR0/TC1_M_1_TR1/SPIHB_CLK (0)/SDHC_CARD_CMD (0)/PWM1_H_12_N/SCB4_CTS (0)/SCB4_SEL0 (0)/LIN4_RX/CAN0_2_RX/CAL_SUP_NZ/ADC[0]_3 P6.3 38 95 P13.5 PWM1_46/PWM1_M_10_N/TC1_46_TR0/TC1_M_10_TR1/LIN8_TX/AUDIOSS1_RX_SCK/PWM1_H_4_N/SCB3_SEL2 (0)/ADC[1]_17
PWM1_M_2/PWM1_1_N/TC1_M_2_TR0/TC1_1_TR1/TC0_0_TR0/SPIHB_RWDS (0)/SDHC_CLK_CARD (0)/TC1_H_12_TR0/SCB4_SEL1 (0)/LIN4_TX/ADC[0]_4 P6.4 39 94 P13.4 PWM1_M_10/PWM1_45_N/TC1_M_10_TR0/TC1_45_TR1/LIN8_RX/AUDIOSS1_CLK_I2S_IF/PWM1_H_4/LIN2_TX/SCB3_SEL1 (0)/ADC[1]_16
PWM1_2/PWM1_M_2_N/TC1_2_TR0/TC1_M_2_TR1/TC0_0_TR1/SPIHB_SEL0 (0)/SDHC_CARD_DETECT_N (0)/TC1_H_12_TR1/SCB4_SEL2 (0)/LIN4_EN/ADC[0]_5 P6.5 40 93 P13.3 PWM1_45/PWM1_M_9_N/TC1_45_TR0/TC1_M_9_TR1/AUDIOSS1_TX_SDO/EXT_MUX[2]_EN/SCB3_CTS (0)/LIN2_RX/SCB3_SEL0 (0)/ADC[1]_15
PWM1_M_3/PWM1_2_N/TC1_M_3_TR0/TC1_2_TR1/SCB4_SEL3 (0)/TRIG_IN[8]/ADC[0]_6 P6.6 41 92 P13.2 PWM1_M_9/PWM1_44_N/TC1_M_9_TR0/TC1_44_TR1/PWM0_2/AUDIOSS1_TX_WS/EXT_MUX[2]_2/SCB3_RTS (0)/SCB3_SCL (0)/LIN3_EN/SCB3_CLK (0)/ADC[1]_14
PWM1_3/PWM1_M_3_N/TC1_3_TR0/TC1_M_3_TR1/TRIG_IN[9]/ADC[0]_7 P6.7 42 91 P13.1 PWM1_44/PWM1_M_8_N/TC1_44_TR0/TC1_M_8_TR1/PWM0_2_N/AUDIOSS1_TX_SCK/EXT_MUX[2]_1/SCB3_TX (0)/SCB3_SDA (0)/LIN3_TX/SCB3_MOSI (0)/ADC[1]_13
VDDD 43 90 P13.0 PWM1_M_8/PWM1_43_N/TC1_M_8_TR0/TC1_43_TR1/TC0_2_TR0/AUDIOSS1_MCLK/EXT_MUX[2]_0/SCB3_RX (0)/LIN3_RX/SCB3_MISO (0)/ADC[1]_12
VDDIO_1 44 89 VSSD
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
VSSD
VCCD
VCCD
P7.0
P7.1
P7.2
P7.3
P7.4
P7.5
P7.6
P7.7
P8.0
P8.1
P8.2
P8.3
P8.4
P9.0
P9.1
P9.2
P9.3
P10.0
P10.1
P10.2
P10.3
P10.4
P10.5
P10.6
P10.7
P11.0
P11.1
P11.2
VREFL
VSSA
VDDA
VREFH
P12.0
P12.1
P12.2
P12.3
P12.4
P12.5
P12.6
P12.7
VDDIO_2
PWM1_M_4/PWM1_3_N/TC1_M_4_TR0/TC1_3_TR1/PWM0_1/SPIHB_SEL1 (0)/SDHC_CARD_IF_PWR_EN (0)/SCB5_RX (1)/SCB5_MISO (1)/LIN4_RX/ADC[0]_16
PWM1_15/PWM1_M_4_N/TC1_15_TR0/TC1_M_4_TR1/SPIHB_DATA0 (0)/SDHC_CARD_DAT_3TO0_0 (0)/SCB5_TX (1)/SCB5_SDA (1)/SCB5_MOSI (1)/LIN4_TX/ADC[0]_17
PWM1_M_5/PWM1_15_N/TC1_M_5_TR0/TC1_15_TR1/PWM0_1_N/SPIHB_DATA1 (0)/SDHC_CARD_DAT_3TO0_1 (0)/SCB5_RTS (1)/SCB5_SCL (1)/SCB5_CLK (1)/LIN4_EN/ADC[0]_18
PWM1_16/PWM1_M_5_N/TC1_16_TR0/TC1_M_5_TR1/TC0_1_TR0/SPIHB_DATA2 (0)/SDHC_CARD_DAT_3TO0_2 (0)/SCB5_CTS (1)/SCB5_SEL0 (1)/CAN0_4_TX/ADC[0]_19
PWM1_M_6/PWM1_16_N/TC1_M_6_TR0/TC1_16_TR1/TC0_1_TR1/SPIHB_DATA3 (0)/SDHC_CARD_DAT_3TO0_3 (0)/SCB5_SEL1 (1)/CAN0_4_RX/ADC[0]_20
PWM1_17/PWM1_M_6_N/TC1_17_TR0/TC1_M_6_TR1/PWM0_H_2/SPIHB_DATA4 (0)/SDHC_CARD_DAT_7TO4_0 (0)/LIN10_RX/SCB5_SEL2 (1)/ADC[0]_21
PWM1_M_7/PWM1_17_N/TC1_M_7_TR0/TC1_17_TR1/LIN10_TX/TRIG_IN[16]/ADC[0]_22
PWM1_18/PWM1_M_7_N/TC1_18_TR0/TC1_M_7_TR1/LIN10_EN/TRIG_IN[17]/ADC[0]_23
PWM1_19/PWM1_18_N/TC1_19_TR0/TC1_18_TR1/PWM0_H_2_N/SPIHB_DATA5 (0)/SDHC_CARD_DAT_7TO4_1 (0)/PWM1_H_8/LIN2_RX/CAN0_0_TX
PWM1_20/PWM1_19_N/TC1_20_TR0/TC1_19_TR1/TC0_H_2_TR0/SPIHB_DATA6 (0)/SDHC_CARD_DAT_7TO4_2 (0)/PWM1_H_8_N/LIN2_TX/CAN0_0_RX/TRIG_IN[14]/ADC[0]_24
PWM1_21/PWM1_20_N/TC1_21_TR0/TC1_20_TR1/TC0_H_2_TR1/SPIHB_DATA7 (0)/SDHC_CARD_DAT_7TO4_3 (0)/TC1_H_8_TR0/LIN2_EN/TRIG_IN[15]/ADC[0]_25
PWM1_22/PWM1_21_N/TC1_22_TR0/TC1_21_TR1/TC1_H_8_TR1/LIN16_RX/TRIG_DBG[0]/ADC[0]_26
PWM1_23/PWM1_22_N/TC1_23_TR0/TC1_22_TR1/LIN16_TX/TRIG_DBG[1]/ADC[0]_27
PWM1_24/PWM1_23_N/TC1_24_TR0/TC1_23_TR1/PWM1_H_9/LIN16_EN/ADC[0]_28
PWM1_25/PWM1_24_N/TC1_25_TR0/TC1_24_TR1/PWM1_H_9_N/LIN12_RX/ADC[0]_29
PWM1_26/PWM1_25_N/TC1_26_TR0/TC1_25_TR1/TC1_H_9_TR0/LIN12_TX/ADC[0]_30
PWM1_27/PWM1_26_N/TC1_27_TR0/TC1_26_TR1/TC1_H_9_TR1/LIN12_EN/ADC[0]_31
PWM1_28/PWM1_27_N/TC1_28_TR0/TC1_27_TR1/PWM1_H_10/SCB4_RX (1)/SCB4_MISO (1)/LIN7_RX/TRIG_IN[18]
PWM1_29/PWM1_28_N/TC1_29_TR0/TC1_28_TR1/PWM1_H_10_N/SCB4_TX (1)/SCB4_SDA (1)/SCB4_MOSI (1)/LIN7_TX/TRIG_IN[19]
PWM1_30/PWM1_29_N/TC1_30_TR0/TC1_29_TR1/LIN8_RX/TC1_H_10_TR0/SCB4_RTS (1)/SCB4_SCL (1)/SCB4_CLK (1)/FLEXRAY_RXDA
PWM1_31/PWM1_30_N/TC1_31_TR0/TC1_30_TR1/LIN8_TX/TC1_H_10_TR1/SCB4_CTS (1)/SCB4_SEL0 (1)/FLEXRAY_TXDA
PWM1_32/PWM1_31_N/TC1_32_TR0/TC1_31_TR1/LIN8_EN/PWM1_H_11/SCB4_SEL1 (1)/FLEXRAY_TXENA_N/ADC[1]_0
PWM1_33/PWM1_32_N/TC1_33_TR0/TC1_32_TR1/PWM1_H_11_N/SCB4_SEL2 (1)/LIN13_RX/FLEXRAY_RXDB/ADC[1]_1
PWM1_33_N/TC1_33_TR1/PWM1_34/TC1_H_11_TR0/TC1_34_TR0/LIN13_TX/FLEXRAY_TXDB/ADC[1]_2
PWM1_35/PWM1_34_N/TC1_35_TR0/TC1_34_TR1/TC1_H_11_TR1/LIN13_EN/FLEXRAY_TXENB_N/ADC[1]_3
PWM1_61/PWM1_62_N/TC1_61_TR0/TC1_62_TR1/AUDIOSS0_MCLK/ADC[0]_M
PWM1_60/PWM1_61_N/TC1_60_TR0/TC1_61_TR1/AUDIOSS0_TX_SCK/ADC[1]_M
PWM1_59/PWM1_60_N/TC1_59_TR0/TC1_60_TR1/AUDIOSS0_TX_WS/ADC[2]_M

PWM1_36/TC1_36_TR0/PWM0_H_1/PWM1_35_N/AUDIOSS0_TX_SDO/SCB8_RX (0)/TC1_35_TR1/SCB8_MISO (0)/CAN0_2_TX/TRIG_IN[20]/ADC[1]_4

PWM1_37/PWM1_36_N/TC1_37_TR0/TC1_36_TR1/PWM0_H_1_N/AUDIOSS0_CLK_I2S_IF/SCB8_TX (0)/SCB8_SDA (0)/SCB8_MOSI (0)/LIN6_EN/CAN0_2_RX/TRIG_IN[21]/ADC[1]_5
PWM1_38/PWM1_37_N/TC1_38_TR0/TC1_37_TR1/TC0_H_1_TR0/AUDIOSS0_RX_SCK/EXT_MUX[1]_EN/SCB8_RTS (0)/SCB8_SCL (0)/SCB8_CLK (0)/LIN6_RX/ADC[1]_6
PWM1_39/PWM1_38_N/TC1_39_TR0/TC1_38_TR1/TC0_H_1_TR1/AUDIOSS0_RX_WS/EXT_MUX[1]_0/SCB8_CTS (0)/SCB8_SEL0 (0)/LIN6_TX/ADC[1]_7
PWM1_40/PWM1_39_N/TC1_40_TR0/TC1_39_TR1/TC0_2_TR1/AUDIOSS0_RX_SDI/EXT_MUX[1]_1/SCB8_SEL1 (0)/CAN1_1_TX/ADC[1]_8
PWM1_41/PWM1_40_N/TC1_41_TR0/TC1_40_TR1/EXT_MUX[1]_2/CAN1_1_RX/ADC[1]_9
PWM1_42/PWM1_41_N/TC1_42_TR0/TC1_41_TR1/ADC[1]_10
PWM1_43/PWM1_42_N/TC1_43_TR0/TC1_42_TR1/ADC[1]_11

Figure 9-2 176-TEQFP pin assignment with alternate functions

Datasheet 30 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin assignment

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

A VSSD P6.5 P6.2 P31.2 P31.0 P5.0 P4.4 P4.0 P29.5 P29.1 P29.0 P3.1 P3.0 P2.0 P1.1 P1.0 P0.2 VSSD

B P6.7 P6.6 P6.3 P6.0 P31.1 P5.1 P30.0 P4.1 P29.6 P29.2 P3.5 P3.2 P2.4 P2.1 P1.2 P0.3 P0.1 P0.0

C P32.0 P32.1 P6.4 P6.1 P5.4 P5.2 P30.1 P4.2 P29.7 P29.3 P3.6 P3.3 P2.5 P2.2 P1.3 P28.7 P28.6 P28.5

D P32.2 P32.3 P32.4 P32.5 P5.5 P5.3 P30.2 P4.3 VSSD P29.4 P3.7 P3.4 P2.6 P2.3 P1.4 P28.4 P28.3 P28.2

E P7.0 P7.1 P32.6 P32.7 P28.1 P28.0 P23.7 P23.6

F P7.2 P7.3 P7.4 P7.5 VCCD P30.3 VDDD VDDIO VDDIO VDDIO
_1 _1 _1
P2.7 VCCD P23.5 P23.4 P23.3 P22.3

G P7.6 P7.7 P8.0 P8.1 P8.2 VSSD VSSD P23.2 P23.1 P23.0 P22.7 P22.2

H P9.0 P9.1 P8.3 P8.4 VDDIO

_3
VSSIO
_3
VSSD VSSD VSSD VDDD P22.6 P22.5 P22.4 P22.1

DRV_
J P9.2 P9.3 P24.0 P24.1 VDDIO
_3
VSSIO
_3
VSSD VSSD VSSD VDDD VSSD P21.7 P21.6
VOUT

XRES_
K P24.2 P24.3 P24.4 P25.0 VREFH VREFL VSSD VSSD VSSD VDDD P20.7 P20.6 P21.5
L

L P25.1 P25.2 P25.3 P25.4 VDDA VSSA VSSIO

_4
VSSIO
_4
VSSD
_1
VDDD P20.5 P20.4 P21.4 VSSD
_2

M P10.0 P25.5 P25.6 P25.7 P11.0 VSSD VSSD P20.3 P20.2 P20.1 P21.2 P21.3

N P10.1 P10.2 P10.3 P10.4 VCCD P14.5 VDDIO VDDIO VDDIO

_2 _4 _4
VDDD P16.7 VCCD P19.4 P20.0 P21.0 P21.1

P P10.5 P10.6 P10.7 P11.1 P18.7 P19.3 P19.2 VSSD

_2

R P12.0 P12.1 P12.2 P11.2 VSSD P14.4 P14.7 P26.1 P26.5 P27.1 P27.5 P27.7 P16.5 VSSD P18.6 P18.5 P19.1 P19.0

T P12.3 P12.4 P12.5 P13.5 P13.7 P14.3 P14.6 P26.0 P26.4 P27.0 P27.4 P27.6 P16.4 P16.6 P17.4 P18.4 P18.3 P18.2

U P12.6 P12.7 P13.2 P13.4 P13.6 P14.2 P15.1 P15.3 P26.3 P26.7 P27.3 P16.1 P16.3 P17.1 P17.3 P17.6 P18.1 P18.0

V VSSD P13.0 P13.1 P13.3 P14.0 P14.1 P15.0 P15.2 P26.2 P26.6 P27.2 P16.0 P16.2 P17.0 P17.2 P17.5 P17.7 VSSD

Figure 9-3 272-BGA ball map

Datasheet 31 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin assignment

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
A VSSD P6.2 P6.0 P5.3 P5.0 P30.1 P4.5 P4.1 P4.0 P29.2 P29.0 P3.2 P3.0 P2.2 P2.0 P1.1 P1.0 P0.0 P28.7 VSSD

B P6.3 P6.4 P6.1 P5.4 P5.1 P30.2 P4.6 P4.2 P29.5 P29.3 P29.1 P3.3 P3.1 P2.3 P2.1 P1.2 P0.2 P0.1 P28.6 P28.5

C P6.5 P6.6 VSSD P5.5 P5.2 P30.3 P30.0 P4.3 P29.6 VSSD P3.6 P3.4 P2.6 P2.4 P1.4 P1.3 P0.3 VSSD P28.4 P28.3

D P6.7 P32.0 P32.1 P28.2 P28.1 P23.5

E P32.3 P32.4 P32.5 P32.2 P31.2 P31.0 P4.4 P29.7 P29.4 P3.7 P3.5 P2.7 P2.5 P1.5 P28.0 P23.4 P23.3 P23.2

F P7.0 P7.1 P32.6 P32.7 VCCD P31.1 VDDD VDDD VDDIO VDDIO VDDIO VDDIO
_1 _1 _1 _1
P1.6 VCCD P23.6 P23.1 P23.0 P22.3

G P7.2 P7.3 P7.4 P7.5 P7.6 P23.7 P22.7 P22.5 P22.4 P22.2

H P8.0 P8.1 P8.2 P7.7 VDDIO

_3
VSSIO
_3
VSSD VSSD VSSD VSSD VSSD VDDD P22.6 P21.7 P21.6 P22.1

DRV_
J P8.3 P8.4 P9.2 P9.3 VDDIO
_3
VSSIO
_3
VSSD VSSD VSSD VSSD VSSD VDDD P20.7 VSSD P21.5
VOUT

K P9.0 P9.1 P24.0 P10.0 VDDIO

_3
VSSIO
_3
VSSD VSSD VSSD VSSD VSSD VDDD P20.6 VSSD P21.4 XRES_L

L P24.1 P24.2 P24.3 P10.1 VDDIO

_3
VSSIO
_3
VSSD VSSD VSSD VSSD VSSD VDDD P20.5 P20.4 P20.3 VSSD
_2

M P24.4 P25.0 P25.1 P10.2 VREFH VREFL VSSD VSSD VSSD VSSD VSSD VDDD P20.2 P20.1 P21.2 P21.3

N P25.2 P25.3 P25.4 P10.3 VDDA VSSA VSSIO

_4
VSSIO
_4
VSSIO
_4
VSSD VSSD
_1
VDDD P19.4 P20.0 P21.0 P21.1

P P25.5 P25.6 P25.7 P11.0 P11.1 P19.3 P19.2 P19.1 P19.0 VSSD
_2

R P10.4 P10.5 P10.6 P11.2 VCCD P14.6 VDDIO VDDIO VDDIO VDDIO
_2 _4 _4 _4
VDDD VDDD P17.3 VCCD P18.7 P34.7 P34.6 P34.5

T P10.7 P12.0 P12.1 P14.1 P14.5 P14.7 P15.3 P16.0 P16.1 P16.2 P16.3 P16.4 P17.2 P18.5 P18.6 P34.4 P34.3 P34.2

U P12.2 P12.3 P12.4 P34.1 P34.0 P33.7

V P12.5 P12.6 VSSD VSSD P14.0 P14.4 P15.2 P26.2 P26.5 P27.0 P27.3 P27.5 P27.7 P17.1 VSSD P18.0 P33.1 P33.3 P33.6 P33.5

W P12.7 P13.1 P13.3 P13.5 P13.7 P14.3 P15.1 P26.1 P26.4 P26.7 P27.2 P27.4 P27.6 P17.0 P17.5 P17.7 P18.2 P33.0 P33.2 P33.4

Y VSSD P13.0 P13.2 P13.4 P13.6 P14.2 P15.0 P26.0 P26.3 P26.6 P27.1 P16.5 P16.6 P16.7 P17.4 P17.6 P18.1 P18.3 P18.4 VSSD

Figure 9-4 320-BGA ball map

Datasheet 32 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
High-speed I/O matrix connections

10 High-speed I/O matrix connections

Table 10-1 HSIOM connections reference
Name Number Description
HSIOM_SEL_GPIO 0 GPIO controls 'out'
HSIOM_SEL_GPIO_DSI 1
HSIOM_SEL_DSI_DSI 2
HSIOM_SEL_DSI_GPIO 3
HSIOM_SEL_AMUXA 4 Reserved
HSIOM_SEL_AMUXB 5
HSIOM_SEL_AMUXA_DSI 6
HSIOM_SEL_AMUXB_DSI 7
HSIOM_SEL_ACT_0 8 Active functionality 0
HSIOM_SEL_ACT_1 9 Active functionality 1
HSIOM_SEL_ACT_2 10 Active functionality 2
HSIOM_SEL_ACT_3 11 Active functionality 3
HSIOM_SEL_DS_0 12 DeepSleep functionality 0
HSIOM_SEL_DS_1 13 DeepSleep functionality 1
HSIOM_SEL_DS_2 14 DeepSleep functionality 2
HSIOM_SEL_DS_3 15 DeepSleep functionality 3
HSIOM_SEL_ACT_4 16 Active functionality 4
HSIOM_SEL_ACT_5 17 Active functionality 5
HSIOM_SEL_ACT_6 18 Active functionality 6
HSIOM_SEL_ACT_7 19 Active functionality 7
HSIOM_SEL_ACT_8 20 Active functionality 8
HSIOM_SEL_ACT_9 21 Active functionality 9
HSIOM_SEL_ACT_10 22 Active functionality 10
HSIOM_SEL_ACT_11 23 Active functionality 11
HSIOM_SEL_ACT_12 24 Active functionality 12
HSIOM_SEL_ACT_13 25 Active functionality 13
HSIOM_SEL_ACT_14 26 Active functionality 14
HSIOM_SEL_ACT_15 27 Active functionality 15
HSIOM_SEL_DS_4 28 DeepSleep functionality 4
HSIOM_SEL_DS_5 29 DeepSleep functionality 5
HSIOM_SEL_DS_6 30 DeepSleep functionality 6
HSIOM_SEL_DS_7 31 DeepSleep functionality 7

Datasheet 33 002-21617 Rev. *M

2024-01-25
 11 Package pin list and alternate functions

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Most pins have alternate functionality, as specified in Table 11-1.
Port 11 has the following additional features,
• Ability to pass full-level analog signals to the SAR without clipping to VDDIO in cases where VDDIO < VDDA
• Ability to simultaneously capture all three ADC signals with highest priority (ADC[0:2]_M)
• Lower noise, for the most sensitive sensors
Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O [20, 21]
Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P0.0 A18 B18 2 GPIO_ENH SCB0_MISO (0)
P0.1 B18 B17 3 GPIO_ENH SCB0_MOSI (0)
P0.2 B17 A17 4 GPIO_ENH SCB0_SCL (0) SCB0_CLK (0)
P0.3 C17 B16 5 GPIO_ENH SCB0_SDA (0) SCB0_SEL0 (0)
P1.0 A17 A16 6 GPIO_STD SCB0_SCL (1) SCB0_MISO (1)
P1.1 A16 A15 7 GPIO_STD SCB0_SDA (1) SCB0_MOSI (1)
34

P1.2 B16 B15 8 GPIO_STD SCB0_CLK (1)

P1.3 C16 C15 9 GPIO_STD SCB0_SEL0 (1)
P1.4 C15 D15 NA GPIO_STD
P1.5 E15 NA NA GPIO_STD
P1.6 F14 NA NA GPIO_STD
P2.0 A15 A14 10 GPIO_STD SWJ_TRSTN SCB0_SEL1 (0)
P2.1 B15 B14 11 GPIO_STD SCB0_SEL2 (0)
P2.2 A14 C14 12 GPIO_STD SCB0_SEL3 (0)
P2.3 B14 D14 13 GPIO_STD
P2.4 C14 B13 14 GPIO_STD
P2.5 E14 C13 15 GPIO_STD
P2.6 C13 D13 NA GPIO_STD
P2.7 E13 F12 NA GPIO_STD
002-21617 Rev. *M

Notes
17.HCon refers to High Speed I/O matrix connection reference as per Table 10-1.
18.DeepSleep ordering (DS #0, DS #1, DS #2) does not have any impact on choosing any alternate functions; the HSIOM module handles the individual alternate function assignment.
2024-01-25

19.All port pin functions available in DeepSleep mode are also available in Active mode.
20.Refer to Table 14-1 for more information on pin multiplexer abbreviations used.
21.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".
 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)[20, 21]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P3.0 A13 A13 16 GPIO_STD
P3.1 B13 A12 17 GPIO_STD
P3.2 A12 B12 18 GPIO_STD
P3.3 B12 C12 19 GPIO_STD
P3.4 C12 D12 20 GPIO_STD
P3.5 E12 B11 21 GPIO_STD
P3.6 C11 C11 NA GPIO_STD
P3.7 E11 D11 NA GPIO_STD
P4.0 A9 A8 24 GPIO_STD
P4.1 A8 B8 25 GPIO_STD
P4.2 B8 C8 26 GPIO_STD
P4.3 C8 D8 27 GPIO_STD
P4.4 E8 A7 28 GPIO_STD
35

P4.5 A7 NA NA GPIO_STD
P4.6 B7 NA NA GPIO_STD
P5.0 A5 A6 29 GPIO_STD
P5.1 B5 B6 30 GPIO_STD
P5.2 C5 C6 31 GPIO_STD
P5.3 A4 D6 32 GPIO_STD
P5.4 B4 C5 33 GPIO_STD
P5.5 C4 D5 34 GPIO_STD
P6.0 A3 B4 35 GPIO_STD ADC[0]_0
P6.1 B3 C4 36 GPIO_STD ADC[0]_1
P6.2 A2 A3 37 GPIO_STD ADC[0]_2
P6.3 B1 B3 38 GPIO_STD ADC[0]_3
P6.4 B2 C3 39 GPIO_STD ADC[0]_4
P6.5 C1 A2 40 GPIO_STD ADC[0]_5
002-21617 Rev. *M

P6.6 C2 B2 41 GPIO_STD ADC[0]_6

P6.7 D1 B1 42 GPIO_STD ADC[0]_7
2024-01-25

P7.0 F1 E1 48 GPIO_STD ADC[0]_16

P7.1 F2 E2 49 GPIO_STD ADC[0]_17
 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)[20, 21]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P7.2 G1 F1 50 GPIO_STD ADC[0]_18
P7.3 G2 F2 51 GPIO_STD ADC[0]_19
P7.4 G3 F3 52 GPIO_STD ADC[0]_20
P7.5 G5 F4 53 GPIO_STD ADC[0]_21
P7.6 G6 G1 54 GPIO_STD ADC[0]_22
P7.7 H5 G2 55 GPIO_STD ADC[0]_23
P8.0 H1 G3 56 GPIO_STD
P8.1 H2 G4 57 GPIO_STD ADC[0]_24
P8.2 H3 G6 58 GPIO_STD ADC[0]_25
P8.3 J1 H3 59 GPIO_STD ADC[0]_26
P8.4 J2 H4 60 GPIO_STD ADC[0]_27
P9.0 K1 H1 61 GPIO_STD ADC[0]_28
P9.1 K2 H2 62 GPIO_STD ADC[0]_29
36

P9.2 J3 J1 63 GPIO_STD ADC[0]_30

P9.3 J5 J2 64 GPIO_STD ADC[0]_31
P10.0 K5 M1 65 GPIO_STD
P10.1 L5 N1 66 GPIO_STD
P10.2 M5 N2 67 GPIO_STD
P10.3 N5 N3 68 GPIO_STD
P10.4 R1 N4 69 GPIO_STD ADC[1]_0
P10.5 R2 P1 70 GPIO_STD ADC[1]_1
P10.6 R3 P2 71 GPIO_STD ADC[1]_2
P10.7 T1 P3 72 GPIO_STD ADC[1]_3
P11.0 P5 M6 73 GPIO_STD ADC[0]_M
P11.1 P6 P4 74 GPIO_STD ADC[1]_M
P11.2 R5 R4 75 GPIO_STD ADC[2]_M
P12.0 T2 R1 80 GPIO_STD ADC[1]_4 SMARTIO12_0
002-21617 Rev. *M

P12.1 T3 R2 81 GPIO_STD ADC[1]_5 SMARTIO12_1

P12.2 U1 R3 82 GPIO_STD ADC[1]_6 SMARTIO12_2
2024-01-25

P12.3 U2 T1 83 GPIO_STD ADC[1]_7 SMARTIO12_3

P12.4 U3 T2 84 GPIO_STD ADC[1]_8 SMARTIO12_4
 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)[20, 21]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P12.5 V1 T3 85 GPIO_STD ADC[1]_9 SMARTIO12_5
P12.6 V2 U1 86 GPIO_STD ADC[1]_10 SMARTIO12_6
P12.7 W1 U2 87 GPIO_STD ADC[1]_11 SMARTIO12_7
P13.0 Y2 V2 90 GPIO_STD ADC[1]_12 SMARTIO13_0
P13.1 W2 V3 91 GPIO_STD ADC[1]_13 SMARTIO13_1
P13.2 Y3 U3 92 GPIO_STD ADC[1]_14 SMARTIO13_2
P13.3 W3 V4 93 GPIO_STD ADC[1]_15 SMARTIO13_3
P13.4 Y4 U4 94 GPIO_STD ADC[1]_16 SMARTIO13_4
P13.5 W4 T4 95 GPIO_STD ADC[1]_17 SMARTIO13_5
P13.6 Y5 U5 96 GPIO_STD ADC[1]_18 SMARTIO13_6
P13.7 W5 T5 97 GPIO_STD ADC[1]_19 SMARTIO13_7
P14.0 V5 V5 98 GPIO_STD ADC[1]_20 SMARTIO14_0
P14.1 T5 V6 99 GPIO_STD ADC[1]_21 SMARTIO14_1
37

P14.2 Y6 U6 100 GPIO_STD ADC[1]_22 SMARTIO14_2

P14.3 W6 T6 101 GPIO_STD ADC[1]_23 SMARTIO14_3
P14.4 V6 R6 102 GPIO_STD ADC[1]_24 SMARTIO14_4
P14.5 T6 N7 103 GPIO_STD ADC[1]_25 SMARTIO14_5
P14.6 R7 T7 104 GPIO_STD ADC[1]_26 SMARTIO14_6
P14.7 T7 R7 105 GPIO_STD ADC[1]_27 SMARTIO14_7
P15.0 Y7 V7 106 GPIO_STD ADC[1]_28 SMARTIO15_0
P15.1 W7 U7 107 GPIO_STD ADC[1]_29 SMARTIO15_1
P15.2 V7 V8 108 GPIO_STD ADC[1]_30 SMARTIO15_2
P15.3 T8 U8 109 GPIO_STD ADC[1]_31 SMARTIO15_3
P16.0 T9 V12 NA GPIO_STD ADC[2]_0
P16.1 T10 U12 NA GPIO_STD ADC[2]_1
P16.2 T11 V13 NA GPIO_STD ADC[2]_2
P16.3 T12 U13 115 GPIO_STD ADC[2]_3
002-21617 Rev. *M

P16.4 T13 T13 NA GPIO_STD ADC[2]_4

P16.5 Y12 R13 NA GPIO_STD ADC[2]_5
2024-01-25

P16.6 Y13 T14 NA GPIO_STD ADC[2]_6

P16.7 Y14 N12 NA GPIO_STD ADC[2]_7
 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)[20, 21]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P17.0 W14 V14 116 GPIO_STD ADC[2]_8 SMARTIO17_0
P17.1 V14 U14 117 GPIO_STD ADC[2]_9 SMARTIO17_1
P17.2 T14 V15 118 GPIO_STD ADC[2]_10 SMARTIO17_2
P17.3 R14 U15 119 GPIO_STD ADC[2]_11 SMARTIO17_3
P17.4 Y15 T15 120 GPIO_STD ADC[2]_12 SMARTIO17_4
P17.5 W15 V16 121 GPIO_STD ADC[2]_13 SMARTIO17_5
P17.6 Y16 U16 122 GPIO_STD ADC[2]_14 SMARTIO17_6
P17.7 W16 V17 123 GPIO_STD ADC[2]_15 SMARTIO17_7
P18.0 V16 U18 124 GPIO_STD ADC[2]_16
P18.1 Y17 U17 125 GPIO_STD ADC[2]_17
P18.2 W17 T18 126 GPIO_STD ADC[2]_18
P18.3 Y18 T17 127 GPIO_STD ADC[2]_19
P18.4 Y19 T16 128 GPIO_STD ADC[2]_20
38

P18.5 T15 R16 129 GPIO_STD ADC[2]_21

P18.6 T16 R15 130 GPIO_STD ADC[2]_22
P18.7 R16 P15 131 GPIO_STD ADC[2]_23
P19.0 P19 R18 134 GPIO_STD ADC[2]_24
P19.1 P18 R17 135 GPIO_STD ADC[2]_25
P19.2 P16 P17 136 GPIO_STD ADC[2]_26
P19.3 P15 P16 137 GPIO_STD ADC[2]_27
P19.4 N16 N15 138 GPIO_STD ADC[2]_28
P20.0 N18 N16 139 GPIO_STD ADC[2]_29
P20.1 M18 M16 140 GPIO_STD ADC[2]_30
P20.2 M16 M15 141 GPIO_STD ADC[2]_31
P20.3 L19 M13 142 GPIO_STD
P20.4 L18 L16 143 GPIO_STD
P20.5 L16 L15 144 GPIO_STD
002-21617 Rev. *M

P20.6 K16 K16 145 GPIO_STD

P20.7 J16 K15 146 GPIO_STD
2024-01-25

P21.0 N19 N17 147 GPIO_STD WCO_IN[22]

P21.1 N20 N18 148 GPIO_STD WCO_OUT[22]
 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)[20, 21]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P21.2 M19 M17 149 GPIO_STD ECO_IN[22]
P21.3 M20 M18 150 GPIO_STD ECO_OUT[22]
P21.4[23] K19 L17 151 GPIO_STD HIBERNATE_WAKEUP[0]
P21.5 J19 K17 157 GPIO_STD
P21.6 H19 J17 158 GPIO_STD
P21.7 H18 J16 159 GPIO_STD RTC_CAL
P22.1 H20 H18 161 GPIO_STD EXT_PS_CTL0
P22.2 G20 G18 162 GPIO_STD EXT_PS_CTL1
P22.3 F20 F18 163 GPIO_STD EXT_PS_CTL2
P22.4 G19 H17 164 GPIO_STD
P22.5 G18 H16 165 GPIO_STD
P22.6 H16 H15 166 GPIO_STD
P22.7 G16 G17 167 GPIO_STD
39

P23.0 F19 G16 168 GPIO_STD

P23.1 F18 G15 169 GPIO_STD
P23.2 E20 G13 170 GPIO_STD
P23.3 E19 F17 171 GPIO_STD
P23.4 E18 F16 172 GPIO_STD SWJ_SWO_TDO
P23.5 D20 F15 173 GPIO_STD SWJ_SWCLK_TCLK
P23.6 F16 E18 174 GPIO_STD SWJ_SWDIO_TMS
P23.7 G15 E17 175 GPIO_STD SWJ_SWDOE_TDI HIBERNATE_WAKEUP[1]
P24.0 K3 J3 NA HSIO_STD
P24.1 L1 J4 NA HSIO_STD
P24.2 L2 K1 NA HSIO_STD
P24.3 L3 K2 NA HSIO_STD
P24.4 M1 K3 NA HSIO_STD
P25.0 M2 K4 NA HSIO_STD
002-21617 Rev. *M

Notes
2024-01-25

22.I/O pins that support an oscillator function (WCO or ECO) must be configured for high-impedance if the oscillator is enabled.
23.This I/O has increased leakage to ground when the VDDD supply is below the POR threshold.
 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)[20, 21]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P25.1 M3 L1 NA HSIO_STD
P25.2 N1 L2 NA HSIO_STD
P25.3 N2 L3 NA HSIO_STD
P25.4 N3 L4 NA HSIO_STD
P25.5 P1 M2 NA HSIO_STD
P25.6 P2 M3 NA HSIO_STD
P25.7 P3 M4 NA HSIO_STD
P26.0 Y8 T8 NA HSIO_STD
P26.1 W8 R8 NA HSIO_STD
P26.2 V8 V9 NA HSIO_STD
P26.3 Y9 U9 NA HSIO_STD
P26.4 W9 T9 NA HSIO_STD
P26.5 V9 R9 NA HSIO_STD
40

P26.6 Y10 V10 NA HSIO_STD

P26.7 W10 U10 NA HSIO_STD
P27.0 V10 T10 NA HSIO_STD
P27.1 Y11 R10 NA HSIO_STD
P27.2 W11 V11 NA HSIO_STD
P27.3 V11 U11 NA HSIO_STD
P27.4 W12 T11 NA HSIO_STD
P27.5 V12 R11 NA HSIO_STD
P27.6 W13 T12 NA HSIO_STD
P27.7 V13 R12 NA HSIO_STD
P28.0 E16 E16 NA GPIO_STD
P28.1 D19 E15 NA GPIO_STD
P28.2 D18 D18 NA GPIO_STD
P28.3 C20 D17 NA GPIO_STD
002-21617 Rev. *M

P28.4 C19 D16 NA GPIO_STD

P28.5 B20 C18 NA GPIO_STD
2024-01-25

P28.6 B19 C17 NA GPIO_STD

P28.7 A19 C16 NA GPIO_STD
 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)[20, 21]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P29.0 A11 A11 NA GPIO_STD
P29.1 B11 A10 NA GPIO_STD
P29.2 A10 B10 NA GPIO_STD
P29.3 B10 C10 NA GPIO_STD
P29.4 E10 D10 NA GPIO_STD
P29.5 B9 A9 NA GPIO_STD
P29.6 C9 B9 NA GPIO_STD
P29.7 E9 C9 NA GPIO_STD
P30.0 C7 B7 NA GPIO_STD
P30.1 A6 C7 NA GPIO_STD
P30.2 B6 D7 NA GPIO_STD
P30.3 C6 F7 NA GPIO_STD
P31.0 E7 A5 NA GPIO_STD
41

P31.1 F7 B5 NA GPIO_STD
P31.2 E6 A4 NA GPIO_STD
P32.0 D2 C1 NA GPIO_STD ADC[0]_8
P32.1 D3 C2 NA GPIO_STD ADC[0]_9
P32.2 E5 D1 NA GPIO_STD ADC[0]_10
P32.3 E1 D2 NA GPIO_STD ADC[0]_11
P32.4 E2 D3 NA GPIO_STD ADC[0]_12
P32.5 E3 D4 NA GPIO_STD ADC[0]_13
P32.6 F3 E3 NA GPIO_STD ADC[0]_14
P32.7 F5 E4 NA GPIO_STD ADC[0]_15
P33.0 W18 NA NA HSIO_STD
P33.1 V17 NA NA HSIO_STD
P33.2 W19 NA NA HSIO_STD
P33.3 V18 NA NA HSIO_STD
002-21617 Rev. *M

P33.4 W20 NA NA HSIO_STD

P33.5 V20 NA NA HSIO_STD
2024-01-25

P33.6 V19 NA NA HSIO_STD

P33.7 U20 NA NA HSIO_STD
 Table 11-1 Pin selector and alternate pin functions in DeepSleep (DS) mode, Analog, Smart I/O (continued)[20, 21]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Package pin list and alternate functions

Package I/O Type DeepSleep Mapping
Name 320-BGA 272-BGA 176-TEQFP HCon#0[17] HCon#14 HCon#29 HCon#30 Analog SMARTIO
Pin Pin Pin DS #0[18, 19] DS #1 DS #2
P34.0 U19 NA NA HSIO_STD
P34.1 U18 NA NA HSIO_STD
P34.2 T20 NA NA HSIO_STD
P34.3 T19 NA NA HSIO_STD
P34.4 T18 NA NA HSIO_STD
P34.5 R20 NA NA HSIO_STD
P34.6 R19 NA NA HSIO_STD
P34.7 R18 NA NA HSIO_STD
XRES_L K20 K18 152
DRV_VOUT J20 J18 160
42
002-21617 Rev. *M
2024-01-25
 12 Power pin assignments

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Power pin assignments

Table 12-1 Power pin assignments
Package
Pin Name Remarks
320-BGA 272-BGA 176-TEQFP
VDDD F8, F9, H15, J15, K15, L15, M15, N15, R12, F8, H13, J13, K13, L13, N11 176, 153, 132, 110, 43, 22 Main digital supply
R13
VSSD A1, A20, C3, C10, C18, H9, H10, H11, H12, A1, A18, D9, G7, G12, H9, H10, H11, J9, 155, 154, 133, 114, 89, 45, 23, Main digital ground
H13, J9, J10, J11, J12, J13, J18, K9, K10, J10, J11, J15, K9, K10, K11, M7, M12, 1
K11, K12, K13, K18, L9, L10, L11, L12, L13, R5, R14, V1, V18
M9, M10, M11, M12, M13, N12, V3, V4, V15,
Y1, Y20
VSSD_1 N13 L11 NA Digital Ground
VSSD_2 L20, P20 L18, P18 NA Noise guard for ECO inputs
VDDIO_1 F10, F11, F12, F13 F9, F10, F11 44 I/O supply (except analog I/Os on VDDA)
VDDIO_2 R8 N8 88 I/O supply (except analog I/Os on VDDA)
VDDIO_3 H6, J6, K6, L6 H6, J6 NA I/O supply for high speed domain#0 (HSIO_STD), P24, P25
VDDIO_4 R9, R10, R11 N9, N10 NA I/O supply for high speed domain#1 (HSIO_STD), P26, P27, P33, P34
VSSIO_3 H8, J8, K8, L8 H8, J8 NA HSIO ground
VSSIO_4 N9, N10, N11 L9, L10 NA HSIO ground
43

[24]
VCCD F6, F15, R6, R15 F6, F13, N6, N13 46, 47, 111, 112, 113, 156 Main regulated supply. Driven by LDO regulator (either internal LDO or external
LDO/PMIC)
VREFH M6 K6 79 High reference voltage for SAR ADCs
VREFL M8 K8 76 Low reference voltage for SAR ADCs
VDDA N6 L6 78 Main analog supply for SAR ADCs
VSSA N8 L8 77 Main analog ground

Note
002-21617 Rev. *M

24.The VCCD pins must be connected together to ensure a low-impedance connection. (see the requirement in Figure 27-2)
2024-01-25
 13 Alternate function pin assignments

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Table 13-1 Alternate pin functions in Active mode [19, 27, 28]
Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P0.0 PWM1_18 PWM1_22_N TC1_18_TR0 TC1_22_TR1 SCB0_RX (0) SCB7_SDA (2) LIN1_RX PWM0_H_0

P0.1 PWM1_17 PWM1_18_N TC1_17_TR0 TC1_18_TR1 SCB0_TX (0) SCB7_SCL (2) LIN1_TX PWM0_H_0_N

P0.2 PWM1_14 PWM1_17_N TC1_14_TR0 TC1_17_TR1 SCB0_RTS (0) SCB4_MISO (2) LIN1_EN CAN0_1_TX TC0_H_0_TR0

P0.3 PWM1_13 PWM1_14_N TC1_13_TR0 TC1_14_TR1 SCB0_CTS (0) SCB4_MOSI (2) CAN0_1_RX TC0_H_0_TR1

P1.0 PWM1_12 PWM1_13_N TC1_12_TR0 TC1_13_TR1 PWM1_H_4 SCB4_CLK (2)

P1.1 PWM1_11 PWM1_12_N TC1_11_TR0 TC1_12_TR1 PWM1_H_5 SCB4_SEL0 (2)

P1.2 PWM1_10 PWM1_11_N TC1_10_TR0 TC1_11_TR1 PWM1_H_6 LIN0_RX TRIG_IN[0]

P1.3 PWM1_8 PWM1_10_N TC1_8_TR0 TC1_10_TR1 PWM1_H_7 LIN0_TX TRIG_IN[1]

P1.4 PWM1_71 PWM1_70_N TC1_71_TR0 TC1_70_TR1 SCB8_RX (1) SCB8_MISO (1) LIN8_RX

P1.5 SCB8_TX (1) SCB8_SDA (1) SCB8_MOSI (1) LIN8_TX

P1.6 SCB8_RTS (1) SCB8_SCL (1) SCB8_CLK (1) LIN8_EN

44

P2.0 PWM1_7 PWM1_8_N TC1_7_TR0 TC1_8_TR1 TC1_H_4_TR0 SCB7_RX (0) SCB7_MISO (0) LIN0_RX CAN0_0_TX TRIG_IN[2]

P2.1 PWM1_6 PWM1_7_N TC1_6_TR0 TC1_7_TR1 TC1_H_5_TR0 SCB7_TX (0) SCB7_SDA (0) SCB7_MOSI (0) LIN0_TX CAN0_0_RX TRIG_IN[3]

P2.2 PWM1_5 PWM1_6_N TC1_5_TR0 TC1_6_TR1 TC1_H_6_TR0 SCB7_RTS (0) SCB7_SCL (0) SCB7_CLK (0) LIN0_EN ETH0_RX_ER (0) TRIG_IN[4]

P2.3 PWM1_4 PWM1_5_N TC1_4_TR0 TC1_5_TR1 TC1_H_7_TR0 SCB7_CTS (0) SCB7_SEL0 (0) LIN5_RX ETH0_ETH_TSU_- TRIG_IN[5]
TIMER_CMP_VAL
(0)

P2.4 PWM1_3 PWM1_4_N TC1_3_TR0 TC1_4_TR1 PWM1_H_4_N SCB7_SEL1 (0) LIN5_TX TRIG_IN[6]

P2.5 PWM1_2 PWM1_3_N TC1_2_TR0 TC1_3_TR1 PWM1_H_5_N SCB7_SEL2 (0) LIN5_EN TRIG_IN[7]

P2.6 PWM1_72 PWM1_71_N TC1_72_TR0 TC1_71_TR1 SCB8_CTS (1) SCB8_SEL0 (1)

P2.7 PWM1_73 PWM1_72_N TC1_73_TR0 TC1_72_TR1 SCB8_SEL1 (1) LIN11_RX

P3.0 PWM1_1 PWM1_2_N TC1_1_TR0 TC1_2_TR1 PWM1_H_6_N SCB6_RX (0) SCB6_MISO (0) CAN0_3_TX ETH0_MDIO (0) TRIG_DBG
[0]

P3.1 PWM1_0 PWM1_1_N TC1_0_TR0 TC1_1_TR1 PWM1_H_7_N SCB6_TX (0) SCB6_SDA (0) SCB6_MOSI (0) CAN0_3_RX ETH0_MDC (0) TRIG_DBG
[1]

P3.2 PWM1_M_3 PWM1_0_N TC1_M_3_TR0 TC1_0_TR1 TC1_H_4_TR1 SCB6_RTS (0) SCB6_SCL (0) SCB6_CLK (0)

P3.3 PWM1_M_2 PWM1_M_3_N TC1_M_2_TR0 TC1_M_3_TR1 TC1_H_5_TR1 SCB6_CTS (0) SCB6_SEL0 (0)

P3.4 PWM1_M_1 PWM1_M_2_N TC1_M_1_TR0 TC1_M_2_TR1 TC1_H_6_TR1 SCB6_SEL1 (0) LIN1_RX

002-21617 Rev. *M

Notes
2024-01-25

25.High Speed I/O matrix connection (HCon) reference as per Table 10-1.
26.Active Mode ordering (ACT #0, ACT #1, and so on) does not have any impact on configuring alternate functions; the HSIOM module handles the alternate function assignments.
27.Refer to Table 14-1 for more information on pin multiplexer abbreviations used.
28.For any function marked with an identifier (n), the AC timing is only guaranteed within the respective group "n".
 Table 13-1 Alternate pin functions in Active mode (continued)[19, 27, 28]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P3.5 PWM1_M_0 PWM1_M_1_N TC1_M_0_TR0 TC1_M_1_TR1 TC1_H_7_TR1 SCB6_SEL2 (0) LIN1_TX

P3.6 PWM1_74 PWM1_73_N TC1_74_TR0 TC1_73_TR1 SCB8_SEL2 (0) LIN11_TX CAN1_2_TX

P3.7 PWM1_75 PWM1_74_N TC1_75_TR0 TC1_74_TR1 LIN11_EN CAN1_2_RX

P4.0 PWM1_4 PWM1_M_0_N TC1_4_TR0 TC1_M_0_TR1 EXT_MUX[0]_0 SCB5_RX (0) SCB5_MISO (0) LIN1_RX TRIG_IN[10]

P4.1 PWM1_5 PWM1_4_N TC1_5_TR0 TC1_4_TR1 EXT_MUX[0]_1 SCB5_TX (0) SCB5_SDA (0) SCB5_MOSI (0) LIN1_TX TRIG_IN[11]

P4.2 PWM1_6 PWM1_5_N TC1_6_TR0 TC1_5_TR1 EXT_MUX[0]_2 SCB5_RTS (0) SCB5_SCL (0) SCB5_CLK (0) LIN1_EN TRIG_IN[12]

P4.3 PWM1_7 PWM1_6_N TC1_7_TR0 TC1_6_TR1 EXT_MUX[0]_EN SCB5_CTS (0) SCB5_SEL0 (0) CAN0_1_TX TRIG_IN[13]

P4.4 PWM1_8 PWM1_7_N TC1_8_TR0 TC1_7_TR1 LIN15_RX SCB5_SEL1 (0) CAN0_1_RX

P4.5 SCB9_RX (1) SCB9_MISO (1) TRIG_IN[32]

P4.6 SCB9_TX (1) SCB9_SDA (1) SCB9_MOSI (1) TRIG_IN[33]

P5.0 PWM1_9 PWM1_8_N TC1_9_TR0 TC1_8_TR1 PWM1_H_10 LIN15_TX SCB5_SEL2 (0) LIN7_RX PWM0_M_0 TRIG_IN[38]

P5.1 PWM1_10 PWM1_9_N TC1_10_TR0 TC1_9_TR1 PWM1_H_10_N SCB9_SEL3 (1) LIN7_TX PWM0_M_0_N TRIG_IN[39]

P5.2 PWM1_11 PWM1_10_N TC1_11_TR0 TC1_10_TR1 TC1_H_10_TR0 LIN10_RX LIN7_EN TC0_M_0_TR0

45

P5.3 PWM1_12 PWM1_11_N TC1_12_TR0 TC1_11_TR1 TC1_H_10_TR1 LIN10_TX LIN2_RX TC0_M_0_TR1

P5.4 PWM1_13 PWM1_12_N TC1_13_TR0 TC1_12_TR1 PWM1_H_11 LIN2_TX LIN9_RX

P5.5 PWM1_14 PWM1_13_N TC1_14_TR0 TC1_13_TR1 PWM1_H_11_N LIN2_EN LIN9_TX

P6.0 PWM1_M_0 PWM1_14_N TC1_M_0_TR0 TC1_14_TR1 TC1_H_11_TR0 SCB4_RX (0) SCB4_MISO (0) LIN3_RX PWM0_0 LIN9_EN

P6.1 PWM1_0 PWM1_M_0_N TC1_0_TR0 TC1_M_0_TR1 TC1_H_11_TR1 SCB4_TX (0) SCB4_SDA (0) SCB4_MOSI (0) LIN3_TX

P6.2 PWM1_M_1 PWM1_0_N TC1_M_1_TR0 TC1_0_TR1 PWM1_H_12 SCB4_RTS (0) SCB4_SCL (0) SCB4_CLK (0) LIN3_EN CAN0_2_TX PWM0_0_N SDHC_CARD_-
MECH_WRITE_PROT
(0)

P6.3 PWM1_1 PWM1_M_1_N TC1_1_TR0 TC1_M_1_TR1 PWM1_H_12_N SCB4_CTS (0) SCB4_SEL0 (0) LIN4_RX CAN0_2_RX SPIHB_CL SDHC_CARD_CMD (0) CAL_SUP_
K (0) NZ

P6.4 PWM1_M_2 PWM1_1_N TC1_M_2_TR0 TC1_1_TR1 TC1_H_12_TR0 SCB4_SEL1 (0) LIN4_TX TC0_0_TR0 SPIHB_R SDHC_CLK_CARD (0)
WDS (0)

P6.5 PWM1_2 PWM1_M_2_N TC1_2_TR0 TC1_M_2_TR1 TC1_H_12_TR1 SCB4_SEL2 (0) LIN4_EN TC0_0_TR1 SPIHB_SE SDHC_CARD_DE-
L0 (0) TECT_N (0)

P6.6 PWM1_M_3 PWM1_2_N TC1_M_3_TR0 TC1_2_TR1 SCB4_SEL3 (0) TRIG_IN[8]

P6.7 PWM1_3 PWM1_M_3_N TC1_3_TR0 TC1_M_3_TR1 TRIG_IN[9]

P7.0 PWM1_M_4 PWM1_3_N TC1_M_4_TR0 TC1_3_TR1 SCB5_RX (1) SCB5_MISO (1) LIN4_RX PWM0_1 SPIHB_SE SDHC_CARD_IF_P-
L1 (0) WR_EN (0)
002-21617 Rev. *M

P7.1 PWM1_15 PWM1_M_4_N TC1_15_TR0 TC1_M_4_TR1 SCB5_TX (1) SCB5_SDA (1) SCB5_MOSI (1) LIN4_TX SPIHB_- SDHC_CARD_DAT_3-
DATA0 (0) TO0_0 (0)

P7.2 PWM1_M_5 PWM1_15_N TC1_M_5_TR0 TC1_15_TR1 SCB5_RTS (1) SCB5_SCL (1) SCB5_CLK (1) LIN4_EN PWM0_1_N SPIHB_- SDHC_CARD_DAT_3-
2024-01-25

DATA1 (0) TO0_1 (0)

P7.3 PWM1_16 PWM1_M_5_N TC1_16_TR0 TC1_M_5_TR1 SCB5_CTS (1) SCB5_SEL0 (1) CAN0_4_TX TC0_1_TR0 SPIHB_- SDHC_CARD_DAT_3-
DATA2 (0) TO0_2 (0)
 Table 13-1 Alternate pin functions in Active mode (continued)[19, 27, 28]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P7.4 PWM1_M_6 PWM1_16_N TC1_M_6_TR0 TC1_16_TR1 SCB5_SEL1 (1) CAN0_4_RX TC0_1_TR1 SPIHB_- SDHC_CARD_DAT_3-
DATA3 (0) TO0_3 (0)

P7.5 PWM1_17 PWM1_M_6_N TC1_17_TR0 TC1_M_6_TR1 LIN10_RX SCB5_SEL2 (1) PWM0_H_2 SPIHB_- SDHC_CARD_DAT_7-
DATA4 (0) TO4_0 (0)

P7.6 PWM1_M_7 PWM1_17_N TC1_M_7_TR0 TC1_17_TR1 LIN10_TX TRIG_IN[16]

P7.7 PWM1_18 PWM1_M_7_N TC1_18_TR0 TC1_M_7_TR1 LIN10_EN TRIG_IN[17]

P8.0 PWM1_19 PWM1_18_N TC1_19_TR0 TC1_18_TR1 PWM1_H_8 LIN2_RX CAN0_0_TX PWM0_H_2_N SPIHB_- SDHC_CARD_DAT_7-
DATA5 (0) TO4_1 (0)

P8.1 PWM1_20 PWM1_19_N TC1_20_TR0 TC1_19_TR1 PWM1_H_8_N LIN2_TX CAN0_0_RX TC0_H_2_TR0 SPIHB_- SDHC_CARD_DAT_7- TRIG_IN[14]
DATA6 (0) TO4_2 (0)

P8.2 PWM1_21 PWM1_20_N TC1_21_TR0 TC1_20_TR1 TC1_H_8_TR0 LIN2_EN TC0_H_2_TR1 SPIHB_- SDHC_CARD_DAT_7- TRIG_IN[15]
DATA7 (0) TO4_3 (0)

P8.3 PWM1_22 PWM1_21_N TC1_22_TR0 TC1_21_TR1 TC1_H_8_TR1 LIN16_RX TRIG_DBG

[0]

P8.4 PWM1_23 PWM1_22_N TC1_23_TR0 TC1_22_TR1 LIN16_TX TRIG_DBG

[1]
P9.0 PWM1_24 PWM1_23_N TC1_24_TR0 TC1_23_TR1 PWM1_H_9 LIN16_EN

P9.1 PWM1_25 PWM1_24_N TC1_25_TR0 TC1_24_TR1 PWM1_H_9_N LIN12_RX

46

P9.2 PWM1_26 PWM1_25_N TC1_26_TR0 TC1_25_TR1 TC1_H_9_TR0 LIN12_TX

P9.3 PWM1_27 PWM1_26_N TC1_27_TR0 TC1_26_TR1 TC1_H_9_TR1 LIN12_EN

P10.0 PWM1_28 PWM1_27_N TC1_28_TR0 TC1_27_TR1 PWM1_H_10 SCB4_RX (1) SCB4_MISO (1) LIN7_RX TRIG_IN[18]

P10.1 PWM1_29 PWM1_28_N TC1_29_TR0 TC1_28_TR1 PWM1_H_10_N SCB4_TX (1) SCB4_SDA (1) SCB4_MOSI (1) LIN7_TX TRIG_IN[19]

P10.2 PWM1_30 PWM1_29_N TC1_30_TR0 TC1_29_TR1 TC1_H_10_TR0 SCB4_RTS (1) SCB4_SCL (1) SCB4_CLK (1) LIN8_RX FLEXRAY_R
XDA

P10.3 PWM1_31 PWM1_30_N TC1_31_TR0 TC1_30_TR1 TC1_H_10_TR1 SCB4_CTS (1) SCB4_SEL0 (1) LIN8_TX FLEXRAY_T
XDA

P10.4 PWM1_32 PWM1_31_N TC1_32_TR0 TC1_31_TR1 PWM1_H_11 SCB4_SEL1 (1) LIN8_EN FLEXRAY_T
XENA_N

P10.5 PWM1_33 PWM1_32_N TC1_33_TR0 TC1_32_TR1 PWM1_H_11_N SCB4_SEL2 (1) LIN13_RX FLEXRAY_R
XDB

P10.6 PWM1_33_N TC1_33_TR1 TC1_H_11_TR0 TC1_34_TR0 LIN13_TX PWM1_34 FLEXRAY_T

XDB

P10.7 PWM1_35 PWM1_34_N TC1_35_TR0 TC1_34_TR1 TC1_H_11_TR1 LIN13_EN FLEXRAY_T

XENB_N

P11.0 PWM1_61 PWM1_62_N TC1_61_TR0 TC1_62_TR1 AUDIOSS0_MCLK

P11.1 PWM1_60 PWM1_61_N TC1_60_TR0 TC1_61_TR1 AUDIOSS0_TX_SCK

P11.2 PWM1_59 PWM1_60_N TC1_59_TR0 TC1_60_TR1 AUDIOSS0_TX_WS

002-21617 Rev. *M

P12.0 PWM1_36 TC1_36_TR0 SCB8_RX (0) TC1_35_TR1 SCB8_MISO (0) CAN0_2_TX PWM0_H_1 PWM1_35 AUDIOSS0_TX_SDO TRIG_IN[20]
_N
2024-01-25

P12.1 PWM1_37 PWM1_36_N TC1_37_TR0 TC1_36_TR1 SCB8_TX (0) SCB8_SDA (0) SCB8_MOSI (0) LIN6_EN CAN0_2_RX PWM0_H_1_N AUDIOSS0_- TRIG_IN[21]
CLK_I2S_IF

P12.2 PWM1_38 PWM1_37_N TC1_38_TR0 TC1_37_TR1 EXT_MUX[1]_EN SCB8_RTS (0) SCB8_SCL (0) SCB8_CLK (0) LIN6_RX TC0_H_1_TR0 AUDIOSS0_RX_SCK
 Table 13-1 Alternate pin functions in Active mode (continued)[19, 27, 28]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P12.3 PWM1_39 PWM1_38_N TC1_39_TR0 TC1_38_TR1 EXT_MUX[1]_0 SCB8_CTS (0) SCB8_SEL0 (0) LIN6_TX TC0_H_1_TR1 AUDIOSS0_RX_WS

P12.4 PWM1_40 PWM1_39_N TC1_40_TR0 TC1_39_TR1 EXT_MUX[1]_1 SCB8_SEL1 (0) CAN1_1_TX TC0_2_TR1 AUDIOSS0_RX_SDI

P12.5 PWM1_41 PWM1_40_N TC1_41_TR0 TC1_40_TR1 EXT_MUX[1]_2 CAN1_1_RX

P12.6 PWM1_42 PWM1_41_N TC1_42_TR0 TC1_41_TR1

P12.7 PWM1_43 PWM1_42_N TC1_43_TR0 TC1_42_TR1

P13.0 PWM1_M_8 PWM1_43_N TC1_M_8_TR0 TC1_43_TR1 EXT_MUX[2]_0 SCB3_RX (0) LIN3_RX SCB3_MISO (0) TC0_2_TR0 AUDIOSS1_MCLK

P13.1 PWM1_44 PWM1_M_8_N TC1_44_TR0 TC1_M_8_TR1 EXT_MUX[2]_1 SCB3_TX (0) SCB3_SDA (0) LIN3_TX SCB3_MOSI (0) PWM0_2_N AUDIOSS1_TX_SCK

P13.2 PWM1_M_9 PWM1_44_N TC1_M_9_TR0 TC1_44_TR1 EXT_MUX[2]_2 SCB3_RTS (0) SCB3_SCL (0) LIN3_EN SCB3_CLK (0) PWM0_2 AUDIOSS1_TX_WS

P13.3 PWM1_45 PWM1_M_9_N TC1_45_TR0 TC1_M_9_TR1 EXT_MUX[2]_EN SCB3_CTS (0) LIN2_RX SCB3_SEL0 (0) AUDIOSS1_TX_SDO

P13.4 PWM1_M_1 PWM1_45_N TC1_M_10_TR0 TC1_45_TR1 PWM1_H_4 LIN2_TX SCB3_SEL1 (0) LIN8_RX AUDIOSS1_-
0 CLK_I2S_IF

P13.5 PWM1_46 PWM1_M_10_ TC1_46_TR0 TC1_M_10_TR PWM1_H_4_N SCB3_SEL2 (0) LIN8_TX AUDIOSS1_RX_SCK
N 1

P13.6 PWM1_M_1 PWM1_46_N TC1_M_11_TR0 TC1_46_TR1 PWM1_H_5 SCB3_SEL3 (0) LIN8_EN AUDIOSS1_RX_WS TRIG_IN[22]
1
47

P13.7 PWM1_47 PWM1_M_11_ TC1_47_TR0 TC1_M_11_TR PWM1_H_5_N AUDIOSS1_RX_SDI TRIG_IN[23]

N 1

P14.0 PWM1_48 PWM1_47_N TC1_48_TR0 TC1_47_TR1 PWM1_H_6 SCB2_MISO (0) SCB2_RX (0) CAN1_0_TX PWM0_M_1 AUDIOSS2_MCLK

P14.1 PWM1_49 PWM1_48_N TC1_49_TR0 TC1_48_TR1 PWM1_H_6_N SCB2_MOSI (0) SCB2_SDA (0) SCB2_TX (0) CAN1_0_RX PWM0_M_1_N AUDIOSS2_TX_SCK

P14.2 PWM1_50 PWM1_49_N TC1_50_TR0 TC1_49_TR1 PWM1_H_7 SCB2_CLK (0) SCB2_SCL (0) SCB2_RTS (0) LIN6_RX TC0_M_1_TR0

P14.3 PWM1_51 PWM1_50_N TC1_51_TR0 TC1_50_TR1 PWM1_H_7_N SCB2_SEL0 (0) SCB2_CTS (0) LIN6_TX TC0_M_1_TR1

P14.4 PWM1_52 PWM1_51_N TC1_52_TR0 TC1_51_TR1 TC1_H_4_TR0 SCB2_SEL1 (0) LIN6_EN AUDIOSS2_TX_WS

P14.5 PWM1_53 PWM1_52_N TC1_53_TR0 TC1_52_TR1 TC1_H_4_TR1 SCB2_SEL2 (0) LIN14_RX AUDIOSS2_TX_SDO

P14.6 PWM1_54 PWM1_53_N TC1_54_TR0 TC1_53_TR1 TC1_H_5_TR0 LIN14_TX TRIG_IN[24]

P14.7 PWM1_55 PWM1_54_N TC1_55_TR0 TC1_54_TR1 TC1_H_5_TR1 LIN14_EN TRIG_IN[25]

P15.0 PWM1_56 PWM1_55_N TC1_56_TR0 TC1_55_TR1 TC1_H_6_TR0 SCB9_RX (0) SCB9_MISO (0) CAN1_3_TX AUDIOSS2_-
CLK_I2S_IF

P15.1 PWM1_57 PWM1_56_N TC1_57_TR0 TC1_56_TR1 TC1_H_6_TR1 SCB9_TX (0) SCB9_SDA (0) SCB9_MOSI (0) CAN1_3_RX AUDIOSS2_RX_SCK

P15.2 PWM1_58 PWM1_57_N TC1_58_TR0 TC1_57_TR1 TC1_H_7_TR0 SCB9_RTS (0) SCB9_SCL (0) SCB9_CLK (0) AUDIOSS2_RX_WS

P15.3 PWM1_59 PWM1_58_N TC1_59_TR0 TC1_58_TR1 TC1_H_7_TR1 SCB9_CTS (0) SCB9_SEL0 (0) AUDIOSS2_RX_SDI
002-21617 Rev. *M

P16.0 PWM1_60 PWM1_59_N TC1_60_TR0 TC1_59_TR1 PWM1_H_0 SCB9_SEL1 (0) LIN11_RX

P16.1 PWM1_61 PWM1_60_N TC1_61_TR0 TC1_60_TR1 PWM1_H_0_N SCB9_SEL2 (0) LIN11_TX

2024-01-25

P16.2 PWM1_62 PWM1_61_N TC1_62_TR0 TC1_61_TR1 PWM1_H_1 SCB9_SEL3 (0) LIN11_EN

P16.3 PWM1_62 PWM1_62_N TC1_62_TR0 TC1_62_TR1 PWM1_H_1_N

 Table 13-1 Alternate pin functions in Active mode (continued)[19, 27, 28]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P16.4 PWM1_68 PWM1_69_N TC1_68_TR0 TC1_69_TR1

P16.5 PWM1_67 PWM1_68_N TC1_67_TR0 TC1_68_TR1

P16.6 PWM1_66 PWM1_67_N TC1_66_TR0 TC1_67_TR1

P16.7 PWM1_65 PWM1_66_N TC1_65_TR0 TC1_66_TR1

P17.0 PWM1_61 PWM1_62_N TC1_61_TR0 TC1_62_TR1 LIN11_RX CAN1_1_TX

P17.1 PWM1_60 PWM1_61_N TC1_60_TR0 TC1_61_TR1 SCB3_RX (1) LIN11_TX CAN1_1_RX

P17.2 PWM1_59 PWM1_60_N TC1_59_TR0 TC1_60_TR1 SCB3_TX (1) SCB3_SDA (1) LIN11_EN

P17.3 PWM1_58 PWM1_59_N TC1_58_TR0 TC1_59_TR1 PWM1_H_3 SCB3_RTS (1) SCB3_SCL (1) SCB3_CLK (1) TRIG_IN[26]

P17.4 PWM1_57 PWM1_58_N TC1_57_TR0 TC1_58_TR1 PWM1_H_3_N SCB3_CTS (1) SCB3_SEL0 (1) TRIG_IN[27]

P17.5 PWM1_56 PWM1_57_N TC1_56_TR0 TC1_57_TR1 PWM1_H_2 LIN15_RX SCB3_SEL1 (1)

P17.6 PWM1_M_4 PWM1_56_N TC1_M_4_TR0 TC1_56_TR1 PWM1_H_2_N LIN15_TX SCB3_SEL2 (1)

P17.7 PWM1_M_5 PWM1_M_4_N TC1_M_5_TR0 TC1_M_4_TR1 LIN15_EN LIN12_RX

P18.0 PWM1_M_6 PWM1_M_5_N TC1_M_6_TR0 TC1_M_5_TR1 PWM1_H_0 SCB1_RX (0) SCB1_MISO (0) LIN12_TX ETH0_REF_CLK FAULT_O
48

(0) UT_0

P18.1 PWM1_M_7 PWM1_M_6_N TC1_M_7_TR0 TC1_M_6_TR1 PWM1_H_0_N SCB1_TX (0) SCB1_SDA (0) SCB1_MOSI (0) SCB3_MISO (1) ETH0_TX_CTL (0) FAULT_O
UT_1

P18.2 PWM1_55 PWM1_M_7_N TC1_55_TR0 TC1_M_7_TR1 PWM1_H_1 SCB1_RTS (0) SCB1_SCL (0) SCB1_CLK (0) SCB3_MOSI (1) ETH0_TX_ER (0)

P18.3 PWM1_54 PWM1_55_N TC1_54_TR0 TC1_55_TR1 PWM1_H_1_N SCB1_CTS (0) SCB1_SEL0 (0) SCB3_CLK (2) ETH0_TX_CLK (0) TRACE_-
CLOCK (0)

P18.4 PWM1_53 PWM1_54_N TC1_53_TR0 TC1_54_TR1 PWM1_H_2 SCB1_SEL1 (0) SCB3_SEL0 (2) PWM0_M_2 ETH0_TXD_0 (0) TRACE_-
DATA_0 (0)

P18.5 PWM1_52 PWM1_53_N TC1_52_TR0 TC1_53_TR1 PWM1_H_2_N SCB1_SEL2 (0) PWM0_M_2_N ETH0_TXD_1 (0) TRACE_-
DATA_1 (0)

P18.6 PWM1_51 PWM1_52_N TC1_51_TR0 TC1_52_TR1 PWM1_H_3 SCB1_SEL3 (0) CAN1_2_TX TC0_M_2_TR0 ETH0_TXD_2 (0) TRACE_-
DATA_2 (0)

P18.7 PWM1_50 PWM1_51_N TC1_50_TR0 TC1_51_TR1 PWM1_H_3_N CAN1_2_RX TC0_M_2_TR1 ETH0_TXD_3 (0) TRACE_-
DATA_3 (0)

P19.0 PWM1_M_3 PWM1_50_N TC1_M_3_TR0 TC1_50_TR1 TC1_H_0_TR0 SCB2_MISO (1) SCB2_RX (1) CAN1_3_TX ETH0_RXD_0 (0) FAULT_O
UT_2

P19.1 PWM1_26 PWM1_M_3_N TC1_26_TR0 TC1_M_3_TR1 TC1_H_0_TR1 SCB2_MOSI (1) SCB2_SDA (1) SCB2_TX (1) CAN1_3_RX ETH0_RXD_1 (0) FAULT_O
UT_3

P19.2 PWM1_27 PWM1_26_N TC1_27_TR0 TC1_26_TR1 TC1_H_1_TR0 SCB2_CLK (1) SCB2_SCL (1) SCB2_RTS (1) ETH0_RXD_2 (0) TRIG_IN[28]

P19.3 PWM1_28 PWM1_27_N TC1_28_TR0 TC1_27_TR1 TC1_H_1_TR1 SCB2_SEL0 (1) SCB2_CTS (1) ETH0_RXD_3 (0) TRIG_IN[29]

P19.4 PWM1_29 PWM1_28_N TC1_29_TR0 TC1_28_TR1 TC1_H_2_TR0 SCB2_SEL1 (1)

002-21617 Rev. *M

P20.0 PWM1_30 PWM1_29_N TC1_30_TR0 TC1_29_TR1 TC1_H_2_TR1 SCB2_SEL2 (1) LIN5_RX

2024-01-25

P20.1 PWM1_49 PWM1_30_N TC1_49_TR0 TC1_30_TR1 TC1_H_3_TR0 LIN5_TX

P20.2 PWM1_48 PWM1_49_N TC1_48_TR0 TC1_49_TR1 TC1_H_3_TR1 LIN5_EN

 Table 13-1 Alternate pin functions in Active mode (continued)[19, 27, 28]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P20.3 PWM1_47 PWM1_48_N TC1_47_TR0 TC1_48_TR1 SCB1_RX (1) SCB1_MISO (1) CAN1_2_TX

P20.4 PWM1_46 PWM1_47_N TC1_46_TR0 TC1_47_TR1 SCB1_TX (1) SCB1_SDA (1) SCB1_MOSI (1) CAN1_2_RX

P20.5 PWM1_45 PWM1_46_N TC1_45_TR0 TC1_46_TR1 SCB1_RTS (1) SCB1_SCL (1) SCB1_CLK (1)

P20.6 PWM1_44 PWM1_45_N TC1_44_TR0 TC1_45_TR1 SCB1_CTS (1) SCB1_SEL0 (1) CAN1_4_TX

P20.7 PWM1_43 PWM1_44_N TC1_43_TR0 TC1_44_TR1 SCB1_SEL1 (1) CAN1_4_RX

P21.0 PWM1_42 PWM1_43_N TC1_42_TR0 TC1_43_TR1 SCB1_SEL2 (1)

P21.1 PWM1_41 PWM1_42_N TC1_41_TR0 TC1_42_TR1

P21.2 PWM1_40 PWM1_41_N TC1_40_TR0 TC1_41_TR1 EXT_CLK TRIG_DBG

[1]

P21.3 PWM1_39 PWM1_40_N TC1_39_TR0 TC1_40_TR1

P21.4 PWM1_38 PWM1_39_N TC1_38_TR0 TC1_39_TR1

P21.5 PWM1_37 PWM1_38_N TC1_37_TR0 TC1_38_TR1 TC1_35_TR1 TC1_34_TR0 LIN0_RX CAN1_1_TX PWM1_34 PWM1_35 ETH0_RX_CTL (0) TRACE_-
_N DATA_0 (1)

P21.6 PWM1_36 PWM1_37_N TC1_36_TR0 TC1_37_TR1 LIN0_TX LIN13_RX

49

P21.7 PWM1_35 PWM1_36_N TC1_35_TR0 TC1_36_TR1 SCB6_RX (1) SCB6_MISO (1) LIN0_EN LIN13_TX CAL_SUP_
NZ

P22.1 PWM1_33 PWM1_34_N TC1_33_TR0 TC1_34_TR1 SCB6_TX (1) SCB6_SDA (1) SCB6_MOSI (1) CAN1_1_RX TRACE_-
DATA_1 (1)

P22.2 PWM1_32 PWM1_33_N TC1_32_TR0 TC1_33_TR1 SCB6_RTS (1) SCB6_SCL (1) SCB6_CLK (1) TRACE_-
DATA_2 (1)

P22.3 PWM1_31 PWM1_32_N TC1_31_TR0 TC1_32_TR1 SCB6_CTS (1) SCB6_SEL0 (1) TRACE_-
DATA_3 (1)

P22.4 PWM1_30 PWM1_31_N TC1_30_TR0 TC1_31_TR1 SCB6_SEL1 (1) TRACE_-

CLOCK (1)

P22.5 PWM1_29 PWM1_30_N TC1_29_TR0 TC1_30_TR1 PWM1_H_8 SCB6_SEL2 (1) LIN7_RX

P22.6 PWM1_28 PWM1_29_N TC1_28_TR0 TC1_29_TR1 PWM1_H_8_N LIN7_TX

P22.7 PWM1_27 PWM1_28_N TC1_27_TR0 TC1_28_TR1 TC1_H_8_TR0 LIN14_RX LIN7_EN

P23.0 PWM1_M_8 PWM1_27_N TC1_M_8_TR0 TC1_27_TR1 TC1_H_8_TR1 SCB7_RX (1) LIN14_TX SCB7_MISO (1) CAN1_0_TX FAULT_O
UT_0

P23.1 PWM1_M_9 PWM1_M_8_N TC1_M_9_TR0 TC1_M_8_TR1 SCB7_TX (1) SCB7_SDA (1) SCB7_MOSI (1) CAN1_0_RX FAULT_O
UT_1

P23.2 PWM1_M_1 PWM1_M_9_N TC1_M_10_TR0 TC1_M_9_TR1 SCB7_RTS (1) SCB7_SCL (1) SCB7_CLK (1) LIN6_RX FAULT_O
0 UT_2

P23.3 PWM1_M_1 PWM1_M_10_ TC1_M_11_TR0 TC1_M_10_TR SCB7_CTS (1) SCB7_SEL0 (1) LIN6_TX ETH0_RX_CLK (0) TRIG_IN[30] FAULT_O
1 N 1 UT_3
002-21617 Rev. *M

P23.4 PWM1_25 PWM1_M_11_ TC1_25_TR0 TC1_M_11_TR PWM1_H_9 SCB2_MISO (2) SCB7_SEL1 (1) TRIG_IN[31] TRIG_DBG
N 1 [0]

P23.5 PWM1_24 PWM1_25_N TC1_24_TR0 TC1_25_TR1 PWM1_H_9_N SCB2_MOSI (2) SCB7_SEL2 (1) LIN9_RX
2024-01-25

P23.6 PWM1_23 PWM1_24_N TC1_23_TR0 TC1_24_TR1 TC1_H_9_TR0 SCB2_CLK (2) LIN9_TX

 Table 13-1 Alternate pin functions in Active mode (continued)[19, 27, 28]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P23.7 PWM1_22 PWM1_23_N TC1_22_TR0 TC1_23_TR1 TC1_H_9_TR1 SCB2_SEL0 (2) EXT_CLK LIN9_EN CAL_SUP_
NZ

P24.0 LIN16_RX EXT_CLK SDHC_CARD_DE-

TECT_N (1)

P24.1 SPIHB_CL SDHC_CARD_-

K (1) MECH_WRITE_PROT
(1)

P24.2 SPIHB_R SDHC_CLK_CARD (1)

WDS (1)

P24.3 LIN16_TX SPIHB_SE SDHC_CARD_CMD (1)

L0 (1)

P24.4 LIN16_EN SPIHB_SE SDHC_CARD_IF_P-

L1 (1) WR_EN (1)

P25.0 SPIHB_- SDHC_CARD_DAT_3-

DATA0 (1) TO0_0 (1)

P25.1 SPIHB_- SDHC_CARD_DAT_3-

DATA1 (1) TO0_1 (1)

P25.2 SPIHB_- SDHC_CARD_DAT_3-

DATA2 (1) TO0_2 (1)

P25.3 SPIHB_- SDHC_CARD_DAT_3-

DATA3 (1) TO0_3 (1)
50

P25.4 SPIHB_- SDHC_CARD_DAT_7-

DATA4 (1) TO4_0 (1)

P25.5 SPIHB_- SDHC_CARD_DAT_7-

DATA5 (1) TO4_1 (1)

P25.6 SPIHB_- SDHC_CARD_DAT_7-

DATA6 (1) TO4_2 (1)

P25.7 SPIHB_- SDHC_CARD_DAT_7-

DATA7 (1) TO4_3 (1)

P26.0 ETH1_REF
_CLK (0)

P26.1 ETH1_TX_
CTL (0)

P26.2 ETH1_TX_
CLK (0)

P26.3 ETH1_TXD
_0 (0)

P26.4 ETH1_TXD
_1 (0)

P26.5 ETH1_TXD
_2 (0)

P26.6 ETH1_TXD
_3 (0)
002-21617 Rev. *M

P26.7 ETH1_RXD
_0 (0)
P27.0 ETH1_RXD
2024-01-25

_1 (0)

P27.1 ETH1_RXD
_2 (0)
 Table 13-1 Alternate pin functions in Active mode (continued)[19, 27, 28]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P27.2 ETH1_RXD
_3 (0)

P27.3 ETH1_RX_
CTL (0)

P27.4 ETH1_RX_
CLK (0)

P27.5 ETH1_MDI
O (0)

P27.6 ETH1_MD
C (0)

P27.7 ETH1_ETH
_TSU_-
TIMER_C-
MP_VAL
(0)

P28.0 PWM1_63 PWM1_65_N TC1_63_TR0 TC1_65_TR1 PWM1_H_12 SCB10_RX (0) SCB10_MISO (0)

P28.1 PWM1_64 PWM1_63_N TC1_64_TR0 TC1_63_TR1 PWM1_H_12_N SCB10_TX (0) SCB10_SDA (0) SCB10_MOSI (0) LIN17_RX

P28.2 PWM1_65 PWM1_64_N TC1_65_TR0 TC1_64_TR1 TC1_H_12_TR0 SCB10_RTS (0) SCB10_SCL (0) SCB10_CLK (0) LIN17_TX

P28.3 PWM1_66 PWM1_65_N TC1_66_TR0 TC1_65_TR1 TC1_H_12_TR1 SCB10_CTS (0) SCB10_SEL0 (0) LIN17_EN
51

P28.4 PWM1_67 PWM1_66_N TC1_67_TR0 TC1_66_TR1 SCB10_SEL1 (0) LIN18_RX

P28.5 PWM1_68 PWM1_67_N TC1_68_TR0 TC1_67_TR1 SCB10_SEL2 (0) LIN18_TX

P28.6 PWM1_69 PWM1_68_N TC1_69_TR0 TC1_68_TR1 SCB10_SEL3 (0) LIN18_EN

P28.7 PWM1_70 PWM1_69_N TC1_70_TR0 TC1_69_TR1 LIN19_RX

P29.0 PWM1_76 PWM1_75_N TC1_76_TR0 TC1_75_TR1 LIN19_TX

P29.1 PWM1_77 PWM1_76_N TC1_77_TR0 TC1_76_TR1 LIN19_EN

P29.2 PWM1_78 PWM1_77_N TC1_78_TR0 TC1_77_TR1

P29.3 PWM1_79 PWM1_78_N TC1_79_TR0 TC1_78_TR1

P29.4 PWM1_80 PWM1_79_N TC1_80_TR0 TC1_79_TR1

P29.5 PWM1_81 PWM1_80_N TC1_81_TR0 TC1_80_TR1

P29.6 PWM1_82 PWM1_81_N TC1_82_TR0 TC1_81_TR1

P29.7 PWM1_83 PWM1_82_N TC1_83_TR0 TC1_82_TR1

P30.0 PWM1_83 PWM1_83_N TC1_83_TR0 TC1_83_TR1 SCB9_RTS (1) SCB9_SCL (1) SCB9_CLK (1) TRIG_IN[34]

P30.1 PWM1_82 PWM1_83_N TC1_82_TR0 TC1_83_TR1 SCB9_CTS (1) SCB9_SEL0 (1) LIN16_RX TRIG_IN[35]
002-21617 Rev. *M

P30.2 PWM1_81 PWM1_82_N TC1_81_TR0 TC1_82_TR1 SCB9_SEL1 (1) LIN16_TX CAN1_3_TX TRIG_IN[36]

P30.3 PWM1_80 PWM1_81_N TC1_80_TR0 TC1_81_TR1 SCB9_SEL2 (1) LIN16_EN CAN1_3_RX TRIG_IN[37]
2024-01-25

P31.0 PWM1_79 PWM1_80_N TC1_79_TR0 TC1_80_TR1 LIN17_RX

P31.1 PWM1_78 PWM1_79_N TC1_78_TR0 TC1_79_TR1 LIN17_TX

 Table 13-1 Alternate pin functions in Active mode (continued)[19, 27, 28]

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Alternate function pin assignments

Active Mapping
Pin
HCon#8[25] HCon#9 HCon#10 HCon#11 HCon#16 HCon#17 HCon#18 HCon#19 HCon#20 HCon#21 HCon#22 HCon#23 HCon#24 HCon#25 HCon#26 HCon#27

Name ACT #0[26] ACT #1 ACT #2 ACT #3 ACT #4 ACT #5 ACT #6 ACT #7 ACT #8 ACT #9 ACT #10 ACT #11 ACT #12 ACT #13 ACT #14 ACT #15

P31.2 PWM1_77 PWM1_78_N TC1_77_TR0 TC1_78_TR1 LIN17_EN

P32.0 PWM1_76 PWM1_77_N TC1_76_TR0 TC1_77_TR1 SCB10_RX (1) SCB10_MISO (1) TRIG_IN[40]

P32.1 PWM1_75 PWM1_76_N TC1_75_TR0 TC1_76_TR1 SCB10_TX (1) SCB10_SDA (1) SCB10_MOSI (1) TRIG_IN[41]

P32.2 PWM1_74 PWM1_75_N TC1_74_TR0 TC1_75_TR1 SCB10_RTS (1) SCB10_SCL (1) SCB10_CLK (1) LIN18_RX TRIG_IN[42]

P32.3 PWM1_73 PWM1_74_N TC1_73_TR0 TC1_74_TR1 SCB10_CTS (1) SCB10_SEL0 (1) LIN18_TX TRIG_IN[43]

P32.4 PWM1_72 PWM1_73_N TC1_72_TR0 TC1_73_TR1 LIN10_RX SCB10_SEL1 (1) LIN18_EN TRIG_IN[44]

P32.5 PWM1_71 PWM1_72_N TC1_71_TR0 TC1_72_TR1 LIN10_TX SCB10_SEL2 (1) LIN19_RX TRIG_IN[45]

P32.6 PWM1_70 PWM1_71_N TC1_70_TR0 TC1_71_TR1 LIN10_EN SCB10_SEL3 (1) LIN19_TX CAN1_4_TX TRIG_IN[46]

P32.7 PWM1_69 PWM1_70_N TC1_69_TR0 TC1_70_TR1 LIN19_EN CAN1_4_RX TRIG_IN[47]

P33.0 ETH0_REF_CLK
(1)

P33.1 ETH0_TX_CTL (1) ETH1_TX_

ER (0)

P33.2 ETH0_TX_CLK (1)

52

P33.3 ETH0_TXD_0 (1) ETH1_TXD

_4 (0)

P33.4 ETH0_TXD_1 (1) ETH1_TXD

_5 (0)

P33.5 ETH0_TXD_2 (1) ETH1_TXD

_6 (0)

P33.6 ETH0_TXD_3 (1) ETH1_TXD

_7 (0)

P33.7 ETH0_RXD_0 (1) ETH1_RXD

_4 (0)

P34.0 ETH0_RXD_1 (1) ETH1_RXD

_5 (0)

P34.1 ETH0_RXD_2 (1) ETH1_RXD

_6 (0)

P34.2 ETH0_RXD_3 (1) ETH1_RXD

_7 (0)

P34.3 ETH0_RX_CTL (1) ETH1_RX_

ER (0)

P34.4 ETH0_RX_CLK (1)

P34.5 ETH0_MDIO (1)

P34.6 ETH0_MDC (1)

002-21617 Rev. *M

P34.7 ETH0_ETH_TSU_-
TIMER_CMP_VAL
(1)
2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin mux descriptions

14 Pin mux descriptions

Table 14-1 Pin mux descriptions
Sl. No. Pin Module Description
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR line out, x-TCPWM block,
1 PWMx_y TCPWM
y-counter number
TCPWM 16-bit PWM (no motor control), PWM_DT and PWM_PR complementary line out
2 PWMx_y_N TCPWM
(N), x-TCPWM block, y-counter number
3 PWMx_M_y TCPWM TCPWM 16-bit PWM with motor control line out, x-TCPWM block, y-counter number
TCPWM 16-bit PWM with motor control complementary line out (N), x-TCPWM block,
4 PWMx_M_y_N TCPWM y-counter number
5 PWMx_H_y TCPWM TCPWM 32-bit PWM, PWM_DT and PWM_PR line out, x-TCPWM block, y-counter number
TCPWM 32-bit PWM, PWM_DT and PWM_PR complementary line out (N), x-TCPWM block,
6 PWMx_H_y_N TCPWM
y-counter number
TCPWM 16-bit dedicated counter input triggers, x-TCPWM block, y-counter number,
7 TCx_y_TRz TCPWM
z-trigger number
TCPWM 16-bit dedicated counter input triggers with motor control, x-TCPWM block,
8 TCx_M_y_TRz TCPWM
y-counter number, z-trigger number
TCPWM 32-bit dedicated counter input triggers, x-TCPWM block, y-counter number,
9 TCx_H_y_TRz TCPWM
z-trigger number
10 SCBx_RX SCB UART Receive, x-SCB block
11 SCBx_TX SCB UART Transmit, x-SCB block
12 SCBx_RTS SCB UART Request to Send (Handshake), x-SCB block
13 SCBx_CTS SCB UART Clear to Send (Handshake), x-SCB block
14 SCBx_SDA SCB I2C Data line, x-SCB block
15 SCBx_SCL SCB I2C Clock line, x-SCB block
16 SCBx_MISO SCB SPI Master Input Slave Output, x-SCB block
17 SCBx_MOSI SCB SPI Master Output Slave Input, x-SCB block
18 SCBx_CLK SCB SPI Serial Clock, x-SCB block
19 SCBx_SELy SCB SPI Slave Select, x-SCB block, y-select line
20 LINx_RX LIN LIN Receive line, x-LIN block
21 LINx_TX LIN LIN Transmit line, x-LIN block
22 LINx_EN LIN LIN Enable line, x-LIN block
23 CANx_y_TX CANFD CAN Transmit line, x-CAN block, y-channel number
24 CANx_y_RX CANFD CAN Receive line, x-CAN block, y-channel number
25 SPIHB_CLK SMIF SMIF interface clock
26 SPIHB_RWDS SMIF SMIF (SPI/HYPERBUS™) read-write-data-strobe line
27 SPIHB_SELx SMIF SMIF (SPI/HYPERBUS™) memory select line, x-select line number
28 SPIHB_DATAx SMIF SMIF (SPI/HYPERBUS™) memory data read and write line, x-0 to 7 data lines
29 ETHx_RX_ER Ethernet Ethernet receive error indication line, x-ETH module number
ETHx_ETH_TSU_TIMER_
30 Ethernet Ethernet time stamp unit timer compare indication line, x-ETH module number
CMP_VAL
31 ETHx_MDIO Ethernet Ethernet management data input/output (MDIO) interface to PHY, x-ETH module number
32 ETHx_MDC Ethernet Ethernet management data clock (MDC) line, x-ETH module number
33 ETHx_REF_CLK Ethernet Ethernet reference clock line, x-ETH module number
34 ETHx_TX_CTL Ethernet Ethernet transmit control line, x-ETH module number
35 ETHx_TX_ER Ethernet Ethernet transmit error indication line, x-ETH module number
36 ETHx_TX_CLK Ethernet Ethernet transmit clock line, x-ETH module number
37 ETHx_TXD_y Ethernet Ethernet transmit data line, x-ETH module number, y-transmit channel number
38 ETHx_RXD_y Ethernet Ethernet receive data line, x-ETH module number, y-receive channel number
39 ETHx_RX_CTL Ethernet Ethernet receive control line, x-ETH module number
40 ETHx_RX_CLK Ethernet Ethernet receive clock line, x-ETH module number

Datasheet 53 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Pin mux descriptions

Table 14-1 Pin mux descriptions (continued)

Sl. No. Pin Module Description
SDHC_CARD_-
41 MECH_WRITE_PROT SDHC SDHC mechanical write protect

42 SDHC_CARD_CMD SDHC SDHC command line

43 SDHC_CLK_CARD SDHC SDHC clock line
44 SDHC_CARD_DETECT_N SDHC SDHC interface insertion or removal detection line
45 SDHC_CARD_IF_PWR_EN SDHC SDHC interface power cycle line
46 SDHC_CARD_DAT_3TO0_x SDHC SDHC lower 4-bits of the data
47 SDHC_CARD_DAT_7TO4_x SDHC SDHC upper 4-bits of the data in 8-bit mode
48 AUDIOSSx_MCLK AUDIOSS AudioSS master clock out, x-AudioSS block
49 AUDIOSSx_TX_SCK AUDIOSS I2S serial clock for transmitter, x-AudioSS block
50 AUDIOSSx_TX_WS AUDIOSS I2S word select for transmitter, x-AudioSS block
51 AUDIOSSx_TX_SDO AUDIOSS I2S serial data output for transmitter, x-AudioSS block
52 AUDIOSSx_CLK_I2S_IF AUDIOSS I2S clock supplied from external I2S bus host, x-AudioSS block
53 AUDIOSSx_RX_SCK AUDIOSS I2S serial clock for receiver, x-AudioSS block
54 AUDIOSSx_RX_WS AUDIOSS I2S word select for receiver, x-AudioSS block
55 AUDIOSSx_RX_SDI AUDIOSS I2S serial data input for receiver, x-AudioSS block
56 FLEXRAY_RXDx FlexRay FlexRay data receive line, x-module channel reference A or B
57 FLEXRAY_TXDx FlexRay FlexRay data transmit line, x-module channel reference A or B
58 FLEXRAY_TXENx_N FlexRay FlexRay transmit enable line, x-module channel reference A or B
59 CAL_SUP_NZ System ETAS Calibration support line
60 FAULT_OUT_x SRSS Fault output line x-0 to 3
61 TRACE_DATA_x SRSS Trace dataout line x-0 to 3
62 TRACE_CLOCK SRSS Trace clock line
63 RTC_CAL SRSS RTC RTC calibration clock input
64 SWJ_TRSTN SRSS JTAG Test reset line (Active low)
65 SWJ_SWO_TDO SRSS JTAG Test data output/SWO (Serial Wire Output)
66 SWJ_SWCLK_TCLK SRSS JTAG Test clock/SWD clock (Serial Wire Clock)
67 SWJ_SWDIO_TMS SRSS JTAG Test mode select/SWD data (Serial Wire Data Input/Output)
68 SWJ_SWDOE_TDI SRSS JTAG Test data input
69 HIBERNATE_WAKEUP[x] SRSS Hibernate wakeup line x-0 to 1
70 EXT_CLK SRSS External clock input or output
REGHC control line, Transistor mode/Positive terminal of the current sense resistor, PMIC
71 EXT_PS_CTL0 SRSS REGHC
mode/Power good input from PMIC
REGHC control line, Transistor mode/Negative terminal of the current sense resistor, PMIC
72 EXT_PS_CTL1 SRSS REGHC
mode/Enable output for PMIC
REGHC control line, Transistor mode/unused, PMIC mode/Reset threshold adjustment for
73 EXT_PS_CTL2 SRSS REGHC
some PMICs
74 ADC[x]_y PASS SAR SAR, channel, x-SAR number, y-channel number
75 ADC[x]_M PASS SAR SAR motor control input, x-SAR number
76 EXT_MUX[x]_y PASS SAR External SAR MUX inputs, x-MUX number, y-MUX input 0 to 2
77 EXT_MUX[x]_EN PASS SAR External SAR MUX enable line
78 TRIG_IN[x] HSIOM HSIOM_IO_INPUT[x] of trigger inputs, x-0 to 47
79 TRIG_DBG[x] HSIOM HSIOM_IO_OUTPUT[x] of trigger outputs, x-0 to 1
80 WCO_IN SRSS Watch crystal oscillator input
81 WCO_OUT SRSS Watch crystal oscillator output
82 ECO_IN SRSS External crystal oscillator input
83 ECO_OUT SRSS External crystal oscillator output

Datasheet 54 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

15 Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources
Interrupt Source Power Mode Description
0 cpuss_interrupts_ipc_0_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #0
1 cpuss_interrupts_ipc_1_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #1
2 cpuss_interrupts_ipc_2_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #2
3 cpuss_interrupts_ipc_3_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #3
4 cpuss_interrupts_ipc_4_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #4
5 cpuss_interrupts_ipc_5_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #5
6 cpuss_interrupts_ipc_6_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #6
7 cpuss_interrupts_ipc_7_IRQn DeepSleep CPUSS Inter Process Communication Interrupt #7
8 cpuss_interrupts_fault_0_IRQn DeepSleep CPUSS Fault Structure #0 Interrupt
9 cpuss_interrupts_fault_1_IRQn DeepSleep CPUSS Fault Structure #1 Interrupt
10 cpuss_interrupts_fault_2_IRQn DeepSleep CPUSS Fault Structure #2 Interrupt
11 cpuss_interrupts_fault_3_IRQn DeepSleep CPUSS Fault Structure #3 Interrupt
12 srss_interrupt_backup_IRQn DeepSleep BACKUP domain Interrupt
13 srss_interrupt_mcwdt_0_IRQn DeepSleep Multi Counter Watchdog Timer #0 interrupt
14 srss_interrupt_mcwdt_1_IRQn DeepSleep Multi Counter Watchdog Timer #1 interrupt
15 srss_interrupt_mcwdt_2_IRQn DeepSleep Multi Counter Watchdog Timer #2 interrupt
16 srss_interrupt_wdt_IRQn DeepSleep Hardware Watchdog Timer interrupt
17 srss_interrupt_IRQn DeepSleep Other combined Interrupts for SRSS (LVD, CLKCAL)
18 scb_0_interrupt_IRQn DeepSleep SCB0 interrupt (DeepSleep capable)
19 evtgen_0_interrupt_dpslp_IRQn DeepSleep Event gen DeepSleep domain interrupt
20 ioss_interrupt_vdd_IRQn DeepSleep I/O Supply (VDDIO, VDDA, VDDD) state change Interrupt
21 ioss_interrupt_gpio_dpslp_IRQn DeepSleep Consolidated Interrupt for GPIO_STD and GPIO_ENH, all ports
22 ioss_interrupts_gpio_dpslp_0_IRQn DeepSleep GPIO_ENH Port #0 Interrupt
23 ioss_interrupts_gpio_dpslp_1_IRQn DeepSleep GPIO_STD Port #1 Interrupt
24 ioss_interrupts_gpio_dpslp_2_IRQn DeepSleep GPIO_STD Port #2 Interrupt
25 ioss_interrupts_gpio_dpslp_3_IRQn DeepSleep GPIO_STD Port #3 Interrupt
26 ioss_interrupts_gpio_dpslp_4_IRQn DeepSleep GPIO_STD Port #4 Interrupt
27 ioss_interrupts_gpio_dpslp_5_IRQn DeepSleep GPIO_STD Port #5 Interrupt
28 ioss_interrupts_gpio_dpslp_6_IRQn DeepSleep GPIO_STD Port #6 Interrupt
29 ioss_interrupts_gpio_dpslp_7_IRQn DeepSleep GPIO_STD Port #7 Interrupt
30 ioss_interrupts_gpio_dpslp_8_IRQn DeepSleep GPIO_STD Port #8 Interrupt
31 ioss_interrupts_gpio_dpslp_9_IRQn DeepSleep GPIO_STD Port #9 Interrupt
32 ioss_interrupts_gpio_dpslp_10_IRQn DeepSleep GPIO_STD Port #10 Interrupt
33 ioss_interrupts_gpio_dpslp_11_IRQn DeepSleep GPIO_STD Port #11 Interrupt
34 ioss_interrupts_gpio_dpslp_12_IRQn DeepSleep GPIO_STD Port #12 Interrupt
35 ioss_interrupts_gpio_dpslp_13_IRQn DeepSleep GPIO_STD Port #13 Interrupt
36 ioss_interrupts_gpio_dpslp_14_IRQn DeepSleep GPIO_STD Port #14 Interrupt
37 ioss_interrupts_gpio_dpslp_15_IRQn DeepSleep GPIO_STD Port #15 Interrupt
38 ioss_interrupts_gpio_dpslp_16_IRQn DeepSleep GPIO_STD Port #16 Interrupt
39 ioss_interrupts_gpio_dpslp_17_IRQn DeepSleep GPIO_STD Port #17 Interrupt
40 ioss_interrupts_gpio_dpslp_18_IRQn DeepSleep GPIO_STD Port #18 Interrupt
41 ioss_interrupts_gpio_dpslp_19_IRQn DeepSleep GPIO_STD Port #19 Interrupt
42 ioss_interrupts_gpio_dpslp_20_IRQn DeepSleep GPIO_STD Port #20 Interrupt

Datasheet 55 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
43 ioss_interrupts_gpio_dpslp_21_IRQn DeepSleep GPIO_STD Port #21 Interrupt
44 ioss_interrupts_gpio_dpslp_22_IRQn DeepSleep GPIO_STD Port #22 Interrupt
45 ioss_interrupts_gpio_dpslp_23_IRQn DeepSleep GPIO_STD Port #23 Interrupt
46 ioss_interrupts_gpio_dpslp_28_IRQn DeepSleep GPIO_STD Port #28 Interrupt
47 ioss_interrupts_gpio_dpslp_29_IRQn DeepSleep GPIO_STD Port #29 Interrupt
48 ioss_interrupts_gpio_dpslp_30_IRQn DeepSleep GPIO_STD Port #30 Interrupt
49 ioss_interrupts_gpio_dpslp_31_IRQn DeepSleep GPIO_STD Port #31 Interrupt
50 ioss_interrupts_gpio_dpslp_32_IRQn DeepSleep GPIO_STD Port #32 Interrupt
51 ioss_interrupts_gpio_act_IRQn Active Consolidated Interrupt for HSIO_STD, All Ports
52 ioss_interrupts_gpio_act_24_IRQn Active HSIO_STD Port #24 Interrupt
53 ioss_interrupts_gpio_act_25_IRQn Active HSIO_STD Port #25 Interrupt
54 ioss_interrupts_gpio_act_26_IRQn Active HSIO_STD Port #26 Interrupt
55 ioss_interrupts_gpio_act_27_IRQn Active HSIO_STD Port #27 Interrupt
56 ioss_interrupts_gpio_act_33_IRQn Active HSIO_STD Port #33 Interrupt
57 ioss_interrupts_gpio_act_34_IRQn Active HSIO_STD Port #34 Interrupt
58 cpuss_interrupt_crypto_IRQn Active CRYPTO Accelerator Interrupt
59 cpuss_interrupt_fm_IRQn Active Flash Macro Interrupt
60 cpuss_interrupts_cm7_0_fp_IRQn Active CM7_0 Floating Point operation fault
61 cpuss_interrupts_cm7_1_fp_IRQn Active CM7_1 Floating Point operation fault
62 cpuss_interrupts_cm0_cti_0_IRQn Active CM0+ CTI (Cross Trigger Interface) #0
63 cpuss_interrupts_cm0_cti_1_IRQn Active CM0+ CTI #1
64 cpuss_interrupts_cm7_0_cti_0_IRQn Active CM7_0 CTI #0
65 cpuss_interrupts_cm7_0_cti_1_IRQn Active CM7_0 CTI #1
66 cpuss_interrupts_cm7_1_cti_0_IRQn Active CM7_1 CTI #0
67 cpuss_interrupts_cm7_1_cti_1_IRQn Active CM7_1 CTI #1
68 evtgen_0_interrupt_IRQn Active Event gen Active domain Interrupt
69 canfd_0_interrupt0_IRQn Active CAN0, Consolidated Interrupt #0 for all five channels
70 canfd_0_interrupt1_IRQn Active CAN0, Consolidated Interrupt #1 for all five channels
71 canfd_1_interrupt0_IRQn Active CAN1, Consolidated Interrupt #0 for all five channels
72 canfd_1_interrupt1_IRQn Active CAN1, Consolidated Interrupt #1 for all five channels
73 canfd_0_interrupts0_0_IRQn Active CAN0, Interrupt #0, Channel #0
74 canfd_0_interrupts0_1_IRQn Active CAN0, Interrupt #0, Channel #1
75 canfd_0_interrupts0_2_IRQn Active CAN0, Interrupt #0, Channel #2
76 canfd_0_interrupts0_3_IRQn Active CAN0, Interrupt #0, Channel #3
77 canfd_0_interrupts0_4_IRQn Active CAN0, Interrupt #0, Channel #4
78 canfd_0_interrupts1_0_IRQn Active CAN0, Interrupt #1, Channel #0
79 canfd_0_interrupts1_1_IRQn Active CAN0, Interrupt #1, Channel #1
80 canfd_0_interrupts1_2_IRQn Active CAN0, Interrupt #1, Channel #2
81 canfd_0_interrupts1_3_IRQn Active CAN0, Interrupt #1, Channel #3
82 canfd_0_interrupts1_4_IRQn Active CAN0, Interrupt #1, Channel #4
83 canfd_1_interrupts0_0_IRQn Active CAN1, Interrupt #0, Channel #0
84 canfd_1_interrupts0_1_IRQn Active CAN1, Interrupt #0, Channel #1
85 canfd_1_interrupts0_2_IRQn Active CAN1, Interrupt #0, Channel #2
86 canfd_1_interrupts0_3_IRQn Active CAN1, Interrupt #0, Channel #3
87 canfd_1_interrupts0_4_IRQn Active CAN1, Interrupt #0, Channel #4

Datasheet 56 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
88 canfd_1_interrupts1_0_IRQn Active CAN1, Interrupt #1, Channel #0
89 canfd_1_interrupts1_1_IRQn Active CAN1, Interrupt #1, Channel #1
90 canfd_1_interrupts1_2_IRQn Active CAN1, Interrupt #1, Channel #2
91 canfd_1_interrupts1_3_IRQn Active CAN1, Interrupt #1, Channel #3
92 canfd_1_interrupts1_4_IRQn Active CAN1, Interrupt #1, Channel #4
93 lin_0_interrupts_0_IRQn Active LIN0, Channel #0 Interrupt
94 lin_0_interrupts_1_IRQn Active LIN0, Channel #1 Interrupt
95 lin_0_interrupts_2_IRQn Active LIN0, Channel #2 Interrupt
96 lin_0_interrupts_3_IRQn Active LIN0, Channel #3 Interrupt
97 lin_0_interrupts_4_IRQn Active LIN0, Channel #4 Interrupt
98 lin_0_interrupts_5_IRQn Active LIN0, Channel #5 Interrupt
99 lin_0_interrupts_6_IRQn Active LIN0, Channel #6 Interrupt
100 lin_0_interrupts_7_IRQn Active LIN0, Channel #7 Interrupt
101 lin_0_interrupts_8_IRQn Active LIN0, Channel #8 Interrupt
102 lin_0_interrupts_9_IRQn Active LIN0, Channel #9 Interrupt
103 lin_0_interrupts_10_IRQn Active LIN0, Channel #10 Interrupt
104 lin_0_interrupts_11_IRQn Active LIN0, Channel #11 Interrupt
105 lin_0_interrupts_12_IRQn Active LIN0, Channel #12 Interrupt
106 lin_0_interrupts_13_IRQn Active LIN0, Channel #13 Interrupt
107 lin_0_interrupts_14_IRQn Active LIN0, Channel #14 Interrupt
108 lin_0_interrupts_15_IRQn Active LIN0, Channel #15 Interrupt
109 lin_0_interrupts_16_IRQn Active LIN0, Channel #16 Interrupt
110 lin_0_interrupts_17_IRQn Active LIN0, Channel #17 Interrupt
111 lin_0_interrupts_18_IRQn Active LIN0, Channel #18 Interrupt
112 lin_0_interrupts_19_IRQn Active LIN0, Channel #19 Interrupt
113 scb_1_interrupt_IRQn Active SCB1 Interrupt
114 scb_2_interrupt_IRQn Active SCB2 Interrupt
115 scb_3_interrupt_IRQn Active SCB3 Interrupt
116 scb_4_interrupt_IRQn Active SCB4 Interrupt
117 scb_5_interrupt_IRQn Active SCB5 Interrupt
118 scb_6_interrupt_IRQn Active SCB6 Interrupt
119 scb_7_interrupt_IRQn Active SCB7 Interrupt
120 scb_8_interrupt_IRQn Active SCB8 Interrupt
121 scb_9_interrupt_IRQn Active SCB9 Interrupt
122 scb_10_interrupt_IRQn Active SCB10 Interrupt
123 pass_0_interrupts_sar_0_IRQn Active SAR0, Logical Channel #0 Interrupt
124 pass_0_interrupts_sar_1_IRQn Active SAR0, Logical Channel #1 Interrupt
125 pass_0_interrupts_sar_2_IRQn Active SAR0, Logical Channel #2 Interrupt
126 pass_0_interrupts_sar_3_IRQn Active SAR0, Logical Channel #3 Interrupt
127 pass_0_interrupts_sar_4_IRQn Active SAR0, Logical Channel #4 Interrupt
128 pass_0_interrupts_sar_5_IRQn Active SAR0, Logical Channel #5 Interrupt
129 pass_0_interrupts_sar_6_IRQn Active SAR0, Logical Channel #6 Interrupt
130 pass_0_interrupts_sar_7_IRQn Active SAR0, Logical Channel #7 Interrupt
131 pass_0_interrupts_sar_8_IRQn Active SAR0, Logical Channel #8 Interrupt
132 pass_0_interrupts_sar_9_IRQn Active SAR0, Logical Channel #9 Interrupt

Datasheet 57 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
133 pass_0_interrupts_sar_10_IRQn Active SAR0, Logical Channel #10 Interrupt
134 pass_0_interrupts_sar_11_IRQn Active SAR0, Logical Channel #11 Interrupt
135 pass_0_interrupts_sar_12_IRQn Active SAR0, Logical Channel #12 Interrupt
136 pass_0_interrupts_sar_13_IRQn Active SAR0, Logical Channel #13 Interrupt
137 pass_0_interrupts_sar_14_IRQn Active SAR0, Logical Channel #14 Interrupt
138 pass_0_interrupts_sar_15_IRQn Active SAR0, Logical Channel #15 Interrupt
139 pass_0_interrupts_sar_16_IRQn Active SAR0, Logical Channel #16 Interrupt
140 pass_0_interrupts_sar_17_IRQn Active SAR0, Logical Channel #17 Interrupt
141 pass_0_interrupts_sar_18_IRQn Active SAR0, Logical Channel #18 Interrupt
142 pass_0_interrupts_sar_19_IRQn Active SAR0, Logical Channel #19 Interrupt
143 pass_0_interrupts_sar_20_IRQn Active SAR0, Logical Channel #20 Interrupt
144 pass_0_interrupts_sar_21_IRQn Active SAR0, Logical Channel #21 Interrupt
145 pass_0_interrupts_sar_22_IRQn Active SAR0, Logical Channel #22 Interrupt
146 pass_0_interrupts_sar_23_IRQn Active SAR0, Logical Channel #23 Interrupt
147 pass_0_interrupts_sar_24_IRQn Active SAR0, Logical Channel #24 Interrupt
148 pass_0_interrupts_sar_25_IRQn Active SAR0, Logical Channel #25 Interrupt
149 pass_0_interrupts_sar_26_IRQn Active SAR0, Logical Channel #26 Interrupt
150 pass_0_interrupts_sar_27_IRQn Active SAR0, Logical Channel #27 Interrupt
151 pass_0_interrupts_sar_28_IRQn Active SAR0, Logical Channel #28 Interrupt
152 pass_0_interrupts_sar_29_IRQn Active SAR0, Logical Channel #29 Interrupt
153 pass_0_interrupts_sar_30_IRQn Active SAR0, Logical Channel #30 Interrupt
154 pass_0_interrupts_sar_31_IRQn Active SAR0, Logical Channel #31 Interrupt
155 pass_0_interrupts_sar_32_IRQn Active SAR1, Logical Channel #0 Interrupt
156 pass_0_interrupts_sar_33_IRQn Active SAR1, Logical Channel #1 Interrupt
157 pass_0_interrupts_sar_34_IRQn Active SAR1, Logical Channel #2 Interrupt
158 pass_0_interrupts_sar_35_IRQn Active SAR1, Logical Channel #3 Interrupt
159 pass_0_interrupts_sar_36_IRQn Active SAR1, Logical Channel #4 Interrupt
160 pass_0_interrupts_sar_37_IRQn Active SAR1, Logical Channel #5 Interrupt
161 pass_0_interrupts_sar_38_IRQn Active SAR1, Logical Channel #6 Interrupt
162 pass_0_interrupts_sar_39_IRQn Active SAR1, Logical Channel #7 Interrupt
163 pass_0_interrupts_sar_40_IRQn Active SAR1, Logical Channel #8 Interrupt
164 pass_0_interrupts_sar_41_IRQn Active SAR1, Logical Channel #9 Interrupt
165 pass_0_interrupts_sar_42_IRQn Active SAR1, Logical Channel #10 Interrupt
166 pass_0_interrupts_sar_43_IRQn Active SAR1, Logical Channel #11 Interrupt
167 pass_0_interrupts_sar_44_IRQn Active SAR1, Logical Channel #12 Interrupt
168 pass_0_interrupts_sar_45_IRQn Active SAR1, Logical Channel #13 Interrupt
169 pass_0_interrupts_sar_46_IRQn Active SAR1, Logical Channel #14 Interrupt
170 pass_0_interrupts_sar_47_IRQn Active SAR1, Logical Channel #15 Interrupt
171 pass_0_interrupts_sar_48_IRQn Active SAR1, Logical Channel #16 Interrupt
172 pass_0_interrupts_sar_49_IRQn Active SAR1, Logical Channel #17 Interrupt
173 pass_0_interrupts_sar_50_IRQn Active SAR1, Logical Channel #18 Interrupt
174 pass_0_interrupts_sar_51_IRQn Active SAR1, Logical Channel #19 Interrupt
175 pass_0_interrupts_sar_52_IRQn Active SAR1, Logical Channel #20 Interrupt
176 pass_0_interrupts_sar_53_IRQn Active SAR1, Logical Channel #21 Interrupt
177 pass_0_interrupts_sar_54_IRQn Active SAR1, Logical Channel #22 Interrupt

Datasheet 58 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
178 pass_0_interrupts_sar_55_IRQn Active SAR1, Logical Channel #23 Interrupt
179 pass_0_interrupts_sar_56_IRQn Active SAR1, Logical Channel #24 Interrupt
180 pass_0_interrupts_sar_57_IRQn Active SAR1, Logical Channel #25 Interrupt
181 pass_0_interrupts_sar_58_IRQn Active SAR1, Logical Channel #26 Interrupt
182 pass_0_interrupts_sar_59_IRQn Active SAR1, Logical Channel #27 Interrupt
183 pass_0_interrupts_sar_60_IRQn Active SAR1, Logical Channel #28 Interrupt
184 pass_0_interrupts_sar_61_IRQn Active SAR1, Logical Channel #29 Interrupt
185 pass_0_interrupts_sar_62_IRQn Active SAR1, Logical Channel #30 Interrupt
186 pass_0_interrupts_sar_63_IRQn Active SAR1, Logical Channel #31 Interrupt
187 pass_0_interrupts_sar_64_IRQn Active SAR2, Logical Channel #0 Interrupt
188 pass_0_interrupts_sar_65_IRQn Active SAR2, Logical Channel #1 Interrupt
189 pass_0_interrupts_sar_66_IRQn Active SAR2, Logical Channel #2 Interrupt
190 pass_0_interrupts_sar_67_IRQn Active SAR2, Logical Channel #3 Interrupt
191 pass_0_interrupts_sar_68_IRQn Active SAR2, Logical Channel #4 Interrupt
192 pass_0_interrupts_sar_69_IRQn Active SAR2, Logical Channel #5 Interrupt
193 pass_0_interrupts_sar_70_IRQn Active SAR2, Logical Channel #6 Interrupt
194 pass_0_interrupts_sar_71_IRQn Active SAR2, Logical Channel #7 Interrupt
195 pass_0_interrupts_sar_72_IRQn Active SAR2, Logical Channel #8 Interrupt
196 pass_0_interrupts_sar_73_IRQn Active SAR2, Logical Channel #9 Interrupt
197 pass_0_interrupts_sar_74_IRQn Active SAR2, Logical Channel #10 Interrupt
198 pass_0_interrupts_sar_75_IRQn Active SAR2, Logical Channel #11 Interrupt
199 pass_0_interrupts_sar_76_IRQn Active SAR2, Logical Channel #12 Interrupt
200 pass_0_interrupts_sar_77_IRQn Active SAR2, Logical Channel #13 Interrupt
201 pass_0_interrupts_sar_78_IRQn Active SAR2, Logical Channel #14 Interrupt
202 pass_0_interrupts_sar_79_IRQn Active SAR2, Logical Channel #15 Interrupt
203 pass_0_interrupts_sar_80_IRQn Active SAR2, Logical Channel #16 Interrupt
204 pass_0_interrupts_sar_81_IRQn Active SAR2, Logical Channel #17 Interrupt
205 pass_0_interrupts_sar_82_IRQn Active SAR2, Logical Channel #18 Interrupt
206 pass_0_interrupts_sar_83_IRQn Active SAR2, Logical Channel #19 Interrupt
207 pass_0_interrupts_sar_84_IRQn Active SAR2, Logical Channel #20 Interrupt
208 pass_0_interrupts_sar_85_IRQn Active SAR2, Logical Channel #21 Interrupt
209 pass_0_interrupts_sar_86_IRQn Active SAR2, Logical Channel #22 Interrupt
210 pass_0_interrupts_sar_87_IRQn Active SAR2, Logical Channel #23 Interrupt
211 pass_0_interrupts_sar_88_IRQn Active SAR2, Logical Channel #24 Interrupt
212 pass_0_interrupts_sar_89_IRQn Active SAR2, Logical Channel #25 Interrupt
213 pass_0_interrupts_sar_90_IRQn Active SAR2, Logical Channel #26 Interrupt
214 pass_0_interrupts_sar_91_IRQn Active SAR2, Logical Channel #27 Interrupt
215 pass_0_interrupts_sar_92_IRQn Active SAR2, Logical Channel #28 Interrupt
216 pass_0_interrupts_sar_93_IRQn Active SAR2, Logical Channel #29 Interrupt
217 pass_0_interrupts_sar_94_IRQn Active SAR2, Logical Channel #30 Interrupt
218 pass_0_interrupts_sar_95_IRQn Active SAR2, Logical Channel #31 Interrupt
219 cpuss_interrupts_dmac_0_IRQn Active CPUSS M-DMA0, Channel #0 Interrupt
220 cpuss_interrupts_dmac_1_IRQn Active CPUSS M-DMA0, Channel #1 Interrupt
221 cpuss_interrupts_dmac_2_IRQn Active CPUSS M-DMA0, Channel #2 Interrupt
222 cpuss_interrupts_dmac_3_IRQn Active CPUSS M-DMA0, Channel #3 Interrupt

Datasheet 59 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
223 cpuss_interrupts_dmac_4_IRQn Active CPUSS M-DMA0, Channel #4 Interrupt
224 cpuss_interrupts_dmac_5_IRQn Active CPUSS M-DMA0, Channel #5 Interrupt
225 cpuss_interrupts_dmac_6_IRQn Active CPUSS M-DMA0, Channel #6 Interrupt
226 cpuss_interrupts_dmac_7_IRQn Active CPUSS M-DMA0, Channel #7 Interrupt
227 cpuss_interrupts_dw0_0_IRQn Active CPUSS P-DMA0, Channel #0 Interrupt
228 cpuss_interrupts_dw0_1_IRQn Active CPUSS P-DMA0, Channel #1 Interrupt
229 cpuss_interrupts_dw0_2_IRQn Active CPUSS P-DMA0, Channel #2 Interrupt
230 cpuss_interrupts_dw0_3_IRQn Active CPUSS P-DMA0, Channel #3 Interrupt
231 cpuss_interrupts_dw0_4_IRQn Active CPUSS P-DMA0, Channel #4 Interrupt
232 cpuss_interrupts_dw0_5_IRQn Active CPUSS P-DMA0, Channel #5 Interrupt
233 cpuss_interrupts_dw0_6_IRQn Active CPUSS P-DMA0, Channel #6 Interrupt
234 cpuss_interrupts_dw0_7_IRQn Active CPUSS P-DMA0, Channel #7 Interrupt
235 cpuss_interrupts_dw0_8_IRQn Active CPUSS P-DMA0, Channel #8 Interrupt
236 cpuss_interrupts_dw0_9_IRQn Active CPUSS P-DMA0, Channel #9 Interrupt
237 cpuss_interrupts_dw0_10_IRQn Active CPUSS P-DMA0, Channel #10 Interrupt
238 cpuss_interrupts_dw0_11_IRQn Active CPUSS P-DMA0, Channel #11 Interrupt
239 cpuss_interrupts_dw0_12_IRQn Active CPUSS P-DMA0, Channel #12 Interrupt
240 cpuss_interrupts_dw0_13_IRQn Active CPUSS P-DMA0, Channel #13 Interrupt
241 cpuss_interrupts_dw0_14_IRQn Active CPUSS P-DMA0, Channel #14 Interrupt
242 cpuss_interrupts_dw0_15_IRQn Active CPUSS P-DMA0, Channel #15 Interrupt
243 cpuss_interrupts_dw0_16_IRQn Active CPUSS P-DMA0, Channel #16 Interrupt
244 cpuss_interrupts_dw0_17_IRQn Active CPUSS P-DMA0, Channel #17 Interrupt
245 cpuss_interrupts_dw0_18_IRQn Active CPUSS P-DMA0, Channel #18 Interrupt
246 cpuss_interrupts_dw0_19_IRQn Active CPUSS P-DMA0, Channel #19 Interrupt
247 cpuss_interrupts_dw0_20_IRQn Active CPUSS P-DMA0, Channel #20 Interrupt
248 cpuss_interrupts_dw0_21_IRQn Active CPUSS P-DMA0, Channel #21 Interrupt
249 cpuss_interrupts_dw0_22_IRQn Active CPUSS P-DMA0, Channel #22 Interrupt
250 cpuss_interrupts_dw0_23_IRQn Active CPUSS P-DMA0, Channel #23 Interrupt
251 cpuss_interrupts_dw0_24_IRQn Active CPUSS P-DMA0, Channel #24 Interrupt
252 cpuss_interrupts_dw0_25_IRQn Active CPUSS P-DMA0, Channel #25 Interrupt
253 cpuss_interrupts_dw0_26_IRQn Active CPUSS P-DMA0, Channel #26 Interrupt
254 cpuss_interrupts_dw0_27_IRQn Active CPUSS P-DMA0, Channel #27 Interrupt
255 cpuss_interrupts_dw0_28_IRQn Active CPUSS P-DMA0, Channel #28 Interrupt
256 cpuss_interrupts_dw0_29_IRQn Active CPUSS P-DMA0, Channel #29 Interrupt
257 cpuss_interrupts_dw0_30_IRQn Active CPUSS P-DMA0, Channel #30 Interrupt
258 cpuss_interrupts_dw0_31_IRQn Active CPUSS P-DMA0, Channel #31 Interrupt
259 cpuss_interrupts_dw0_32_IRQn Active CPUSS P-DMA0, Channel #32 Interrupt
260 cpuss_interrupts_dw0_33_IRQn Active CPUSS P-DMA0, Channel #33 Interrupt
261 cpuss_interrupts_dw0_34_IRQn Active CPUSS P-DMA0, Channel #34 Interrupt
262 cpuss_interrupts_dw0_35_IRQn Active CPUSS P-DMA0, Channel #35 Interrupt
263 cpuss_interrupts_dw0_36_IRQn Active CPUSS P-DMA0, Channel #36 Interrupt
264 cpuss_interrupts_dw0_37_IRQn Active CPUSS P-DMA0, Channel #37 Interrupt
265 cpuss_interrupts_dw0_38_IRQn Active CPUSS P-DMA0, Channel #38 Interrupt
266 cpuss_interrupts_dw0_39_IRQn Active CPUSS P-DMA0, Channel #39 Interrupt
267 cpuss_interrupts_dw0_40_IRQn Active CPUSS P-DMA0, Channel #40 Interrupt

Datasheet 60 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
268 cpuss_interrupts_dw0_41_IRQn Active CPUSS P-DMA0, Channel #41 Interrupt
269 cpuss_interrupts_dw0_42_IRQn Active CPUSS P-DMA0, Channel #42 Interrupt
270 cpuss_interrupts_dw0_43_IRQn Active CPUSS P-DMA0, Channel #43 Interrupt
271 cpuss_interrupts_dw0_44_IRQn Active CPUSS P-DMA0, Channel #44 Interrupt
272 cpuss_interrupts_dw0_45_IRQn Active CPUSS P-DMA0, Channel #45 Interrupt
273 cpuss_interrupts_dw0_46_IRQn Active CPUSS P-DMA0, Channel #46 Interrupt
274 cpuss_interrupts_dw0_47_IRQn Active CPUSS P-DMA0, Channel #47 Interrupt
275 cpuss_interrupts_dw0_48_IRQn Active CPUSS P-DMA0, Channel #48 Interrupt
276 cpuss_interrupts_dw0_49_IRQn Active CPUSS P-DMA0, Channel #49 Interrupt
277 cpuss_interrupts_dw0_50_IRQn Active CPUSS P-DMA0, Channel #50 Interrupt
278 cpuss_interrupts_dw0_51_IRQn Active CPUSS P-DMA0, Channel #51 Interrupt
279 cpuss_interrupts_dw0_52_IRQn Active CPUSS P-DMA0, Channel #52 Interrupt
280 cpuss_interrupts_dw0_53_IRQn Active CPUSS P-DMA0, Channel #53 Interrupt
281 cpuss_interrupts_dw0_54_IRQn Active CPUSS P-DMA0, Channel #54 Interrupt
282 cpuss_interrupts_dw0_55_IRQn Active CPUSS P-DMA0, Channel #55 Interrupt
283 cpuss_interrupts_dw0_56_IRQn Active CPUSS P-DMA0, Channel #56 Interrupt
284 cpuss_interrupts_dw0_57_IRQn Active CPUSS P-DMA0, Channel #57 Interrupt
285 cpuss_interrupts_dw0_58_IRQn Active CPUSS P-DMA0, Channel #58 Interrupt
286 cpuss_interrupts_dw0_59_IRQn Active CPUSS P-DMA0, Channel #59 Interrupt
287 cpuss_interrupts_dw0_60_IRQn Active CPUSS P-DMA0, Channel #60 Interrupt
288 cpuss_interrupts_dw0_61_IRQn Active CPUSS P-DMA0, Channel #61 Interrupt
289 cpuss_interrupts_dw0_62_IRQn Active CPUSS P-DMA0, Channel #62 Interrupt
290 cpuss_interrupts_dw0_63_IRQn Active CPUSS P-DMA0, Channel #63 Interrupt
291 cpuss_interrupts_dw0_64_IRQn Active CPUSS P-DMA0, Channel #64 Interrupt
292 cpuss_interrupts_dw0_65_IRQn Active CPUSS P-DMA0, Channel #65 Interrupt
293 cpuss_interrupts_dw0_66_IRQn Active CPUSS P-DMA0, Channel #66 Interrupt
294 cpuss_interrupts_dw0_67_IRQn Active CPUSS P-DMA0, Channel #67 Interrupt
295 cpuss_interrupts_dw0_68_IRQn Active CPUSS P-DMA0, Channel #68 Interrupt
296 cpuss_interrupts_dw0_69_IRQn Active CPUSS P-DMA0, Channel #69 Interrupt
297 cpuss_interrupts_dw0_70_IRQn Active CPUSS P-DMA0, Channel #70 Interrupt
298 cpuss_interrupts_dw0_71_IRQn Active CPUSS P-DMA0, Channel #71 Interrupt
299 cpuss_interrupts_dw0_72_IRQn Active CPUSS P-DMA0, Channel #72 Interrupt
300 cpuss_interrupts_dw0_73_IRQn Active CPUSS P-DMA0, Channel #73 Interrupt
301 cpuss_interrupts_dw0_74_IRQn Active CPUSS P-DMA0, Channel #74 Interrupt
302 cpuss_interrupts_dw0_75_IRQn Active CPUSS P-DMA0, Channel #75 Interrupt
303 cpuss_interrupts_dw0_76_IRQn Active CPUSS P-DMA0, Channel #76 Interrupt
304 cpuss_interrupts_dw0_77_IRQn Active CPUSS P-DMA0, Channel #77 Interrupt
305 cpuss_interrupts_dw0_78_IRQn Active CPUSS P-DMA0, Channel #78 Interrupt
306 cpuss_interrupts_dw0_79_IRQn Active CPUSS P-DMA0, Channel #79 Interrupt
307 cpuss_interrupts_dw0_80_IRQn Active CPUSS P-DMA0, Channel #80 Interrupt
308 cpuss_interrupts_dw0_81_IRQn Active CPUSS P-DMA0, Channel #81 Interrupt
309 cpuss_interrupts_dw0_82_IRQn Active CPUSS P-DMA0, Channel #82 Interrupt
310 cpuss_interrupts_dw0_83_IRQn Active CPUSS P-DMA0, Channel #83 Interrupt
311 cpuss_interrupts_dw0_84_IRQn Active CPUSS P-DMA0, Channel #84 Interrupt
312 cpuss_interrupts_dw0_85_IRQn Active CPUSS P-DMA0, Channel #85 Interrupt

Datasheet 61 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
313 cpuss_interrupts_dw0_86_IRQn Active CPUSS P-DMA0, Channel #86 Interrupt
314 cpuss_interrupts_dw0_87_IRQn Active CPUSS P-DMA0, Channel #87 Interrupt
315 cpuss_interrupts_dw0_88_IRQn Active CPUSS P-DMA0, Channel #88 Interrupt
316 cpuss_interrupts_dw0_89_IRQn Active CPUSS P-DMA0, Channel #89 Interrupt
317 cpuss_interrupts_dw0_90_IRQn Active CPUSS P-DMA0, Channel #90 Interrupt
318 cpuss_interrupts_dw0_91_IRQn Active CPUSS P-DMA0, Channel #91 Interrupt
319 cpuss_interrupts_dw0_92_IRQn Active CPUSS P-DMA0, Channel #92 Interrupt
320 cpuss_interrupts_dw0_93_IRQn Active CPUSS P-DMA0, Channel #93 Interrupt
321 cpuss_interrupts_dw0_94_IRQn Active CPUSS P-DMA0, Channel #94 Interrupt
322 cpuss_interrupts_dw0_95_IRQn Active CPUSS P-DMA0, Channel #95 Interrupt
323 cpuss_interrupts_dw0_96_IRQn Active CPUSS P-DMA0, Channel #96 Interrupt
324 cpuss_interrupts_dw0_97_IRQn Active CPUSS P-DMA0, Channel #97 Interrupt
325 cpuss_interrupts_dw0_98_IRQn Active CPUSS P-DMA0, Channel #98 Interrupt
326 cpuss_interrupts_dw0_99_IRQn Active CPUSS P-DMA0, Channel #99 Interrupt
327 cpuss_interrupts_dw0_100_IRQn Active CPUSS P-DMA0, Channel #100 Interrupt
328 cpuss_interrupts_dw0_101_IRQn Active CPUSS P-DMA0, Channel #101 Interrupt
329 cpuss_interrupts_dw0_102_IRQn Active CPUSS P-DMA0, Channel #102 Interrupt
330 cpuss_interrupts_dw0_103_IRQn Active CPUSS P-DMA0, Channel #103 Interrupt
331 cpuss_interrupts_dw0_104_IRQn Active CPUSS P-DMA0, Channel #104 Interrupt
332 cpuss_interrupts_dw0_105_IRQn Active CPUSS P-DMA0, Channel #105 Interrupt
333 cpuss_interrupts_dw0_106_IRQn Active CPUSS P-DMA0, Channel #106 Interrupt
334 cpuss_interrupts_dw0_107_IRQn Active CPUSS P-DMA0, Channel #107 Interrupt
335 cpuss_interrupts_dw0_108_IRQn Active CPUSS P-DMA0, Channel #108 Interrupt
336 cpuss_interrupts_dw0_109_IRQn Active CPUSS P-DMA0, Channel #109 Interrupt
337 cpuss_interrupts_dw0_110_IRQn Active CPUSS P-DMA0, Channel #110 Interrupt
338 cpuss_interrupts_dw0_111_IRQn Active CPUSS P-DMA0, Channel #111 Interrupt
339 cpuss_interrupts_dw0_112_IRQn Active CPUSS P-DMA0, Channel #112 Interrupt
340 cpuss_interrupts_dw0_113_IRQn Active CPUSS P-DMA0, Channel #113 Interrupt
341 cpuss_interrupts_dw0_114_IRQn Active CPUSS P-DMA0, Channel #114 Interrupt
342 cpuss_interrupts_dw0_115_IRQn Active CPUSS P-DMA0, Channel #115 Interrupt
343 cpuss_interrupts_dw0_116_IRQn Active CPUSS P-DMA0, Channel #116 Interrupt
344 cpuss_interrupts_dw0_117_IRQn Active CPUSS P-DMA0, Channel #117 Interrupt
345 cpuss_interrupts_dw0_118_IRQn Active CPUSS P-DMA0, Channel #118 Interrupt
346 cpuss_interrupts_dw0_119_IRQn Active CPUSS P-DMA0, Channel #119 Interrupt
347 cpuss_interrupts_dw0_120_IRQn Active CPUSS P-DMA0, Channel #120 Interrupt
348 cpuss_interrupts_dw0_121_IRQn Active CPUSS P-DMA0, Channel #121 Interrupt
349 cpuss_interrupts_dw0_122_IRQn Active CPUSS P-DMA0, Channel #122 Interrupt
350 cpuss_interrupts_dw0_123_IRQn Active CPUSS P-DMA0, Channel #123 Interrupt
351 cpuss_interrupts_dw0_124_IRQn Active CPUSS P-DMA0, Channel #124 Interrupt
352 cpuss_interrupts_dw0_125_IRQn Active CPUSS P-DMA0, Channel #125 Interrupt
353 cpuss_interrupts_dw0_126_IRQn Active CPUSS P-DMA0, Channel #126 Interrupt
354 cpuss_interrupts_dw0_127_IRQn Active CPUSS P-DMA0, Channel #127 Interrupt
355 cpuss_interrupts_dw0_128_IRQn Active CPUSS P-DMA0, Channel #128 Interrupt
356 cpuss_interrupts_dw0_129_IRQn Active CPUSS P-DMA0, Channel #129 Interrupt
357 cpuss_interrupts_dw0_130_IRQn Active CPUSS P-DMA0, Channel #130 Interrupt

Datasheet 62 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
358 cpuss_interrupts_dw0_131_IRQn Active CPUSS P-DMA0, Channel #131 Interrupt
359 cpuss_interrupts_dw0_132_IRQn Active CPUSS P-DMA0, Channel #132 Interrupt
360 cpuss_interrupts_dw0_133_IRQn Active CPUSS P-DMA0, Channel #133 Interrupt
361 cpuss_interrupts_dw0_134_IRQn Active CPUSS P-DMA0, Channel #134 Interrupt
362 cpuss_interrupts_dw0_135_IRQn Active CPUSS P-DMA0, Channel #135 Interrupt
363 cpuss_interrupts_dw0_136_IRQn Active CPUSS P-DMA0, Channel #136 Interrupt
364 cpuss_interrupts_dw0_137_IRQn Active CPUSS P-DMA0, Channel #137 Interrupt
365 cpuss_interrupts_dw0_138_IRQn Active CPUSS P-DMA0, Channel #138 Interrupt
366 cpuss_interrupts_dw0_139_IRQn Active CPUSS P-DMA0, Channel #139 Interrupt
367 cpuss_interrupts_dw0_140_IRQn Active CPUSS P-DMA0, Channel #140 Interrupt
368 cpuss_interrupts_dw0_141_IRQn Active CPUSS P-DMA0, Channel #141 Interrupt
369 cpuss_interrupts_dw0_142_IRQn Active CPUSS P-DMA0, Channel #142 Interrupt
370 cpuss_interrupts_dw1_0_IRQn Active CPUSS P-DMA1, Channel #0 Interrupt
371 cpuss_interrupts_dw1_1_IRQn Active CPUSS P-DMA1, Channel #1 Interrupt
372 cpuss_interrupts_dw1_2_IRQn Active CPUSS P-DMA1, Channel #2 Interrupt
373 cpuss_interrupts_dw1_3_IRQn Active CPUSS P-DMA1, Channel #3 Interrupt
374 cpuss_interrupts_dw1_4_IRQn Active CPUSS P-DMA1, Channel #4 Interrupt
375 cpuss_interrupts_dw1_5_IRQn Active CPUSS P-DMA1, Channel #5 Interrupt
376 cpuss_interrupts_dw1_6_IRQn Active CPUSS P-DMA1, Channel #6 Interrupt
377 cpuss_interrupts_dw1_7_IRQn Active CPUSS P-DMA1, Channel #7 Interrupt
378 cpuss_interrupts_dw1_8_IRQn Active CPUSS P-DMA1, Channel #8 Interrupt
379 cpuss_interrupts_dw1_9_IRQn Active CPUSS P-DMA1, Channel #9 Interrupt
380 cpuss_interrupts_dw1_10_IRQn Active CPUSS P-DMA1, Channel #10 Interrupt
381 cpuss_interrupts_dw1_11_IRQn Active CPUSS P-DMA1, Channel #11 Interrupt
382 cpuss_interrupts_dw1_12_IRQn Active CPUSS P-DMA1, Channel #12 Interrupt
383 cpuss_interrupts_dw1_13_IRQn Active CPUSS P-DMA1, Channel #13 Interrupt
384 cpuss_interrupts_dw1_14_IRQn Active CPUSS P-DMA1, Channel #14 Interrupt
385 cpuss_interrupts_dw1_15_IRQn Active CPUSS P-DMA1, Channel #15 Interrupt
386 cpuss_interrupts_dw1_16_IRQn Active CPUSS P-DMA1, Channel #16 Interrupt
387 cpuss_interrupts_dw1_17_IRQn Active CPUSS P-DMA1, Channel #17 Interrupt
388 cpuss_interrupts_dw1_18_IRQn Active CPUSS P-DMA1, Channel #18 Interrupt
389 cpuss_interrupts_dw1_19_IRQn Active CPUSS P-DMA1, Channel #19 Interrupt
390 cpuss_interrupts_dw1_20_IRQn Active CPUSS P-DMA1, Channel #20 Interrupt
391 cpuss_interrupts_dw1_21_IRQn Active CPUSS P-DMA1, Channel #21 Interrupt
392 cpuss_interrupts_dw1_22_IRQn Active CPUSS P-DMA1, Channel #22 Interrupt
393 cpuss_interrupts_dw1_23_IRQn Active CPUSS P-DMA1, Channel #23 Interrupt
394 cpuss_interrupts_dw1_24_IRQn Active CPUSS P-DMA1, Channel #24 Interrupt
395 cpuss_interrupts_dw1_25_IRQn Active CPUSS P-DMA1, Channel #25 Interrupt
396 cpuss_interrupts_dw1_26_IRQn Active CPUSS P-DMA1, Channel #26 Interrupt
397 cpuss_interrupts_dw1_27_IRQn Active CPUSS P-DMA1, Channel #27 Interrupt
398 cpuss_interrupts_dw1_28_IRQn Active CPUSS P-DMA1, Channel #28 Interrupt
399 cpuss_interrupts_dw1_29_IRQn Active CPUSS P-DMA1, Channel #29 Interrupt
400 cpuss_interrupts_dw1_30_IRQn Active CPUSS P-DMA1, Channel #30 Interrupt
401 cpuss_interrupts_dw1_31_IRQn Active CPUSS P-DMA1, Channel #31 Interrupt
402 cpuss_interrupts_dw1_32_IRQn Active CPUSS P-DMA1, Channel #32 Interrupt

Datasheet 63 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
403 cpuss_interrupts_dw1_33_IRQn Active CPUSS P-DMA1, Channel #33 Interrupt
404 cpuss_interrupts_dw1_34_IRQn Active CPUSS P-DMA1, Channel #34 Interrupt
405 cpuss_interrupts_dw1_35_IRQn Active CPUSS P-DMA1, Channel #35 Interrupt
406 cpuss_interrupts_dw1_36_IRQn Active CPUSS P-DMA1, Channel #36 Interrupt
407 cpuss_interrupts_dw1_37_IRQn Active CPUSS P-DMA1, Channel #37 Interrupt
408 cpuss_interrupts_dw1_38_IRQn Active CPUSS P-DMA1, Channel #38 Interrupt
409 cpuss_interrupts_dw1_39_IRQn Active CPUSS P-DMA1, Channel #39 Interrupt
410 cpuss_interrupts_dw1_40_IRQn Active CPUSS P-DMA1, Channel #40 Interrupt
411 cpuss_interrupts_dw1_41_IRQn Active CPUSS P-DMA1, Channel #41 Interrupt
412 cpuss_interrupts_dw1_42_IRQn Active CPUSS P-DMA1, Channel #42 Interrupt
413 cpuss_interrupts_dw1_43_IRQn Active CPUSS P-DMA1, Channel #43 Interrupt
414 cpuss_interrupts_dw1_44_IRQn Active CPUSS P-DMA1, Channel #44 Interrupt
415 cpuss_interrupts_dw1_45_IRQn Active CPUSS P-DMA1, Channel #45 Interrupt
416 cpuss_interrupts_dw1_46_IRQn Active CPUSS P-DMA1, Channel #46 Interrupt
417 cpuss_interrupts_dw1_47_IRQn Active CPUSS P-DMA1, Channel #47 Interrupt
418 cpuss_interrupts_dw1_48_IRQn Active CPUSS P-DMA1, Channel #48 Interrupt
419 cpuss_interrupts_dw1_49_IRQn Active CPUSS P-DMA1, Channel #49 Interrupt
420 cpuss_interrupts_dw1_50_IRQn Active CPUSS P-DMA1, Channel #50 Interrupt
421 cpuss_interrupts_dw1_51_IRQn Active CPUSS P-DMA1, Channel #51 Interrupt
422 cpuss_interrupts_dw1_52_IRQn Active CPUSS P-DMA1, Channel #52 Interrupt
423 cpuss_interrupts_dw1_53_IRQn Active CPUSS P-DMA1, Channel #53 Interrupt
424 cpuss_interrupts_dw1_54_IRQn Active CPUSS P-DMA1, Channel #54 Interrupt
425 cpuss_interrupts_dw1_55_IRQn Active CPUSS P-DMA1, Channel #55 Interrupt
426 cpuss_interrupts_dw1_56_IRQn Active CPUSS P-DMA1, Channel #56 Interrupt
427 cpuss_interrupts_dw1_57_IRQn Active CPUSS P-DMA1, Channel #57 Interrupt
428 cpuss_interrupts_dw1_58_IRQn Active CPUSS P-DMA1, Channel #58 Interrupt
429 cpuss_interrupts_dw1_59_IRQn Active CPUSS P-DMA1, Channel #59 Interrupt
430 cpuss_interrupts_dw1_60_IRQn Active CPUSS P-DMA1, Channel #60 Interrupt
431 cpuss_interrupts_dw1_61_IRQn Active CPUSS P-DMA1, Channel #61 Interrupt
432 cpuss_interrupts_dw1_62_IRQn Active CPUSS P-DMA1, Channel #62 Interrupt
433 cpuss_interrupts_dw1_63_IRQn Active CPUSS P-DMA1, Channel #63 Interrupt
434 cpuss_interrupts_dw1_64_IRQn Active CPUSS P-DMA1, Channel #64 Interrupt
435 tcpwm_1_interrupts_0_IRQn Active TCPWM1 Group #0, Counter #0 Interrupt
436 tcpwm_1_interrupts_1_IRQn Active TCPWM1 Group #0, Counter #1 Interrupt
437 tcpwm_1_interrupts_2_IRQn Active TCPWM1 Group #0, Counter #2 Interrupt
438 tcpwm_1_interrupts_3_IRQn Active TCPWM1 Group #0, Counter #3 Interrupt
439 tcpwm_1_interrupts_4_IRQn Active TCPWM1 Group #0, Counter #4 Interrupt
440 tcpwm_1_interrupts_5_IRQn Active TCPWM1 Group #0, Counter #5 Interrupt
441 tcpwm_1_interrupts_6_IRQn Active TCPWM1 Group #0, Counter #6 Interrupt
442 tcpwm_1_interrupts_7_IRQn Active TCPWM1 Group #0, Counter #7 Interrupt
443 tcpwm_1_interrupts_8_IRQn Active TCPWM1 Group #0, Counter #8 Interrupt
444 tcpwm_1_interrupts_9_IRQn Active TCPWM1 Group #0, Counter #9 Interrupt
445 tcpwm_1_interrupts_10_IRQn Active TCPWM1 Group #0, Counter #10 Interrupt
446 tcpwm_1_interrupts_11_IRQn Active TCPWM1 Group #0, Counter #11 Interrupt
447 tcpwm_1_interrupts_12_IRQn Active TCPWM1 Group #0, Counter #12 Interrupt

Datasheet 64 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
448 tcpwm_1_interrupts_13_IRQn Active TCPWM1 Group #0, Counter #13 Interrupt
449 tcpwm_1_interrupts_14_IRQn Active TCPWM1 Group #0, Counter #14 Interrupt
450 tcpwm_1_interrupts_15_IRQn Active TCPWM1 Group #0, Counter #15 Interrupt
451 tcpwm_1_interrupts_16_IRQn Active TCPWM1 Group #0, Counter #16 Interrupt
452 tcpwm_1_interrupts_17_IRQn Active TCPWM1 Group #0, Counter #17 Interrupt
453 tcpwm_1_interrupts_18_IRQn Active TCPWM1 Group #0, Counter #18 Interrupt
454 tcpwm_1_interrupts_19_IRQn Active TCPWM1 Group #0, Counter #19 Interrupt
455 tcpwm_1_interrupts_20_IRQn Active TCPWM1 Group #0, Counter #20 Interrupt
456 tcpwm_1_interrupts_21_IRQn Active TCPWM1 Group #0, Counter #21 Interrupt
457 tcpwm_1_interrupts_22_IRQn Active TCPWM1 Group #0, Counter #22 Interrupt
458 tcpwm_1_interrupts_23_IRQn Active TCPWM1 Group #0, Counter #23 Interrupt
459 tcpwm_1_interrupts_24_IRQn Active TCPWM1 Group #0, Counter #24 Interrupt
460 tcpwm_1_interrupts_25_IRQn Active TCPWM1 Group #0, Counter #25 Interrupt
461 tcpwm_1_interrupts_26_IRQn Active TCPWM1 Group #0, Counter #26 Interrupt
462 tcpwm_1_interrupts_27_IRQn Active TCPWM1 Group #0, Counter #27 Interrupt
463 tcpwm_1_interrupts_28_IRQn Active TCPWM1 Group #0, Counter #28 Interrupt
464 tcpwm_1_interrupts_29_IRQn Active TCPWM1 Group #0, Counter #29 Interrupt
465 tcpwm_1_interrupts_30_IRQn Active TCPWM1 Group #0, Counter #30 Interrupt
466 tcpwm_1_interrupts_31_IRQn Active TCPWM1 Group #0, Counter #31 Interrupt
467 tcpwm_1_interrupts_32_IRQn Active TCPWM1 Group #0, Counter #32 Interrupt
468 tcpwm_1_interrupts_33_IRQn Active TCPWM1 Group #0, Counter #33 Interrupt
469 tcpwm_1_interrupts_34_IRQn Active TCPWM1 Group #0, Counter #34 Interrupt
470 tcpwm_1_interrupts_35_IRQn Active TCPWM1 Group #0, Counter #35 Interrupt
471 tcpwm_1_interrupts_36_IRQn Active TCPWM1 Group #0, Counter #36 Interrupt
472 tcpwm_1_interrupts_37_IRQn Active TCPWM1 Group #0, Counter #37 Interrupt
473 tcpwm_1_interrupts_38_IRQn Active TCPWM1 Group #0, Counter #38 Interrupt
474 tcpwm_1_interrupts_39_IRQn Active TCPWM1 Group #0, Counter #39 Interrupt
475 tcpwm_1_interrupts_40_IRQn Active TCPWM1 Group #0, Counter #40 Interrupt
476 tcpwm_1_interrupts_41_IRQn Active TCPWM1 Group #0, Counter #41 Interrupt
477 tcpwm_1_interrupts_42_IRQn Active TCPWM1 Group #0, Counter #42 Interrupt
478 tcpwm_1_interrupts_43_IRQn Active TCPWM1 Group #0, Counter #43 Interrupt
479 tcpwm_1_interrupts_44_IRQn Active TCPWM1 Group #0, Counter #44 Interrupt
480 tcpwm_1_interrupts_45_IRQn Active TCPWM1 Group #0, Counter #45 Interrupt
481 tcpwm_1_interrupts_46_IRQn Active TCPWM1 Group #0, Counter #46 Interrupt
482 tcpwm_1_interrupts_47_IRQn Active TCPWM1 Group #0, Counter #47 Interrupt
483 tcpwm_1_interrupts_48_IRQn Active TCPWM1 Group #0, Counter #48 Interrupt
484 tcpwm_1_interrupts_49_IRQn Active TCPWM1 Group #0, Counter #49 Interrupt
485 tcpwm_1_interrupts_50_IRQn Active TCPWM1 Group #0, Counter #50 Interrupt
486 tcpwm_1_interrupts_51_IRQn Active TCPWM1 Group #0, Counter #51 Interrupt
487 tcpwm_1_interrupts_52_IRQn Active TCPWM1 Group #0, Counter #52 Interrupt
488 tcpwm_1_interrupts_53_IRQn Active TCPWM1 Group #0, Counter #53 Interrupt
489 tcpwm_1_interrupts_54_IRQn Active TCPWM1 Group #0, Counter #54 Interrupt
490 tcpwm_1_interrupts_55_IRQn Active TCPWM1 Group #0, Counter #55 Interrupt
491 tcpwm_1_interrupts_56_IRQn Active TCPWM1 Group #0, Counter #56 Interrupt
492 tcpwm_1_interrupts_57_IRQn Active TCPWM1 Group #0, Counter #57 Interrupt

Datasheet 65 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
493 tcpwm_1_interrupts_58_IRQn Active TCPWM1 Group #0, Counter #58 Interrupt
494 tcpwm_1_interrupts_59_IRQn Active TCPWM1 Group #0, Counter #59 Interrupt
495 tcpwm_1_interrupts_60_IRQn Active TCPWM1 Group #0, Counter #60 Interrupt
496 tcpwm_1_interrupts_61_IRQn Active TCPWM1 Group #0, Counter #61 Interrupt
497 tcpwm_1_interrupts_62_IRQn Active TCPWM1 Group #0, Counter #62 Interrupt
498 tcpwm_1_interrupts_63_IRQn Active TCPWM1 Group #0, Counter #63 Interrupt
499 tcpwm_1_interrupts_64_IRQn Active TCPWM1 Group #0, Counter #64 Interrupt
500 tcpwm_1_interrupts_65_IRQn Active TCPWM1 Group #0, Counter #65 Interrupt
501 tcpwm_1_interrupts_66_IRQn Active TCPWM1 Group #0, Counter #66 Interrupt
502 tcpwm_1_interrupts_67_IRQn Active TCPWM1 Group #0, Counter #67 Interrupt
503 tcpwm_1_interrupts_68_IRQn Active TCPWM1 Group #0, Counter #68 Interrupt
504 tcpwm_1_interrupts_69_IRQn Active TCPWM1 Group #0, Counter #69 Interrupt
505 tcpwm_1_interrupts_70_IRQn Active TCPWM1 Group #0, Counter #70 Interrupt
506 tcpwm_1_interrupts_71_IRQn Active TCPWM1 Group #0, Counter #71 Interrupt
507 tcpwm_1_interrupts_72_IRQn Active TCPWM1 Group #0, Counter #72 Interrupt
508 tcpwm_1_interrupts_73_IRQn Active TCPWM1 Group #0, Counter #73 Interrupt
509 tcpwm_1_interrupts_74_IRQn Active TCPWM1 Group #0, Counter #74 Interrupt
510 tcpwm_1_interrupts_75_IRQn Active TCPWM1 Group #0, Counter #75 Interrupt
511 tcpwm_1_interrupts_76_IRQn Active TCPWM1 Group #0, Counter #76 Interrupt
512 tcpwm_1_interrupts_77_IRQn Active TCPWM1 Group #0, Counter #77 Interrupt
513 tcpwm_1_interrupts_78_IRQn Active TCPWM1 Group #0, Counter #78 Interrupt
514 tcpwm_1_interrupts_79_IRQn Active TCPWM1 Group #0, Counter #79 Interrupt
515 tcpwm_1_interrupts_80_IRQn Active TCPWM1 Group #0, Counter #80 Interrupt
516 tcpwm_1_interrupts_81_IRQn Active TCPWM1 Group #0, Counter #81 Interrupt
517 tcpwm_1_interrupts_82_IRQn Active TCPWM1 Group #0, Counter #82 Interrupt
518 tcpwm_1_interrupts_83_IRQn Active TCPWM1 Group #0, Counter #83 Interrupt
519 tcpwm_0_interrupts_0_IRQn Active TCPWM0 Group #0, Counter #0 Interrupt
520 tcpwm_0_interrupts_1_IRQn Active TCPWM0 Group #0, Counter #1 Interrupt
521 tcpwm_0_interrupts_2_IRQn Active TCPWM0 Group #0, Counter #2 Interrupt
522 tcpwm_1_interrupts_256_IRQn Active TCPWM1 Group #1, Counter #0 Interrupt
523 tcpwm_1_interrupts_257_IRQn Active TCPWM1 Group #1, Counter #1 Interrupt
524 tcpwm_1_interrupts_258_IRQn Active TCPWM1 Group #1, Counter #2 Interrupt
525 tcpwm_1_interrupts_259_IRQn Active TCPWM1 Group #1, Counter #3 Interrupt
526 tcpwm_1_interrupts_260_IRQn Active TCPWM1 Group #1, Counter #4 Interrupt
527 tcpwm_1_interrupts_261_IRQn Active TCPWM1 Group #1, Counter #5 Interrupt
528 tcpwm_1_interrupts_262_IRQn Active TCPWM1 Group #1, Counter #6 Interrupt
529 tcpwm_1_interrupts_263_IRQn Active TCPWM1 Group #1, Counter #7 Interrupt
530 tcpwm_1_interrupts_264_IRQn Active TCPWM1 Group #1, Counter #8 Interrupt
531 tcpwm_1_interrupts_265_IRQn Active TCPWM1 Group #1, Counter #9 Interrupt
532 tcpwm_1_interrupts_266_IRQn Active TCPWM1 Group #1, Counter #10 Interrupt
533 tcpwm_1_interrupts_267_IRQn Active TCPWM1 Group #1, Counter #11 Interrupt
534 tcpwm_0_interrupts_256_IRQn Active TCPWM0 Group #1, Counter #0 Interrupt
535 tcpwm_0_interrupts_257_IRQn Active TCPWM0 Group #1, Counter #1 Interrupt
536 tcpwm_0_interrupts_258_IRQn Active TCPWM0 Group #1, Counter #2 Interrupt
537 tcpwm_1_interrupts_512_IRQn Active TCPWM1 Group #2, Counter #0 Interrupt

Datasheet 66 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Interrupts and wake-up assignments

Table 15-1 Peripheral interrupt assignments and wake-up sources (continued)

Interrupt Source Power Mode Description
538 tcpwm_1_interrupts_513_IRQn Active TCPWM1 Group #2, Counter #1 Interrupt
539 tcpwm_1_interrupts_514_IRQn Active TCPWM1 Group #2, Counter #2 Interrupt
540 tcpwm_1_interrupts_515_IRQn Active TCPWM1 Group #2, Counter #3 Interrupt
541 tcpwm_1_interrupts_516_IRQn Active TCPWM1 Group #2, Counter #4 Interrupt
542 tcpwm_1_interrupts_517_IRQn Active TCPWM1 Group #2, Counter #5 Interrupt
543 tcpwm_1_interrupts_518_IRQn Active TCPWM1 Group #2, Counter #6 Interrupt
544 tcpwm_1_interrupts_519_IRQn Active TCPWM1 Group #2, Counter #7 Interrupt
545 tcpwm_1_interrupts_520_IRQn Active TCPWM1 Group #2, Counter #8 Interrupt
546 tcpwm_1_interrupts_521_IRQn Active TCPWM1 Group #2, Counter #9 Interrupt
547 tcpwm_1_interrupts_522_IRQn Active TCPWM1 Group #2, Counter #10 Interrupt
548 tcpwm_1_interrupts_523_IRQn Active TCPWM1 Group #2, Counter #11 Interrupt
549 tcpwm_1_interrupts_524_IRQn Active TCPWM1 Group #2, Counter #12 Interrupt
550 tcpwm_0_interrupts_512_IRQn Active TCPWM0 Group #2, Counter #0 Interrupt
551 tcpwm_0_interrupts_513_IRQn Active TCPWM0 Group #2, Counter #1 Interrupt
552 tcpwm_0_interrupts_514_IRQn Active TCPWM0 Group #2, Counter #2 Interrupt
553 flexray_0_interrupt0_IRQn Active FlexRay0 interrupt #0
554 flexray_0_interrupt1_IRQn Active FlexRay0 interrupt #1
555 smif_0_interrupt_IRQn Active SMIF0 (QSPI) interrupt
556 eth_0_interrupt_eth_IRQn Active Ethernet0 interrupt
557 eth_0_interrupt_eth_q2_IRQn Active Ethernet0 interrupt for dma_priority_queue2
558 eth_0_interrupt_eth_q1_IRQn Active Ethernet0 interrupt for dma_priority_queue1
559 eth_1_interrupt_eth_IRQn Active Ethernet1 interrupt
560 eth_1_interrupt_eth_q2_IRQn Active Ethernet1 interrupt for dma_priority_queue2
561 eth_1_interrupt_eth_q1_IRQn Active Ethernet1 interrupt for dma_priority_queue1
562 sdhc_0_interrupt_general_IRQn Active SDHC0 general interrupt
563 sdhc_0_interrupt_wakeup_IRQn Active SDHC0 wakeup interrupt
564 audioss_0_interrupt_i2s_IRQn Active AUDIOSS I2S0 interrupt
565 audioss_1_interrupt_i2s_IRQn Active AUDIOSS I2S1 interrupt
566 audioss_2_interrupt_i2s_IRQn Active AUDIOSS I2S2 interrupt

Datasheet 67 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Core interrupt types

16 Core interrupt types

Table 16-1 Core interrupt types
Interrupt Source Power Mode Description
0 CPUIntIdx0_IRQn[29] DeepSleep CPU User Interrupt #0
1 CPUIntIdx1_IRQn[29] DeepSleep CPU User Interrupt #1
2 CPUIntIdx2_IRQn DeepSleep CPU User Interrupt #2
3 CPUIntIdx3_IRQn DeepSleep CPU User Interrupt #3
4 CPUIntIdx4_IRQn DeepSleep CPU User Interrupt #4
5 CPUIntIdx5_IRQn DeepSleep CPU User Interrupt #5
6 CPUIntIdx6_IRQn DeepSleep CPU User Interrupt #6
7 CPUIntIdx7_IRQn DeepSleep CPU User Interrupt #7
8 Internal0_IRQn Active Internal Software Interrupt #0
9 Internal1_IRQn Active Internal Software Interrupt #1
10 Internal2_IRQn Active Internal Software Interrupt #2
11 Internal3_IRQn Active Internal Software Interrupt #3
12 Internal4_IRQn Active Internal Software Interrupt #4
13 Internal5_IRQn Active Internal Software Interrupt #5
14 Internal6_IRQn Active Internal Software Interrupt #6
15 Internal7_IRQn Active Internal Software Interrupt #7

Note
29.User interrupt cannot be used for CM0+ application, as it is used internally by system calls. Note, this does not impact CM7
application.

Datasheet 68 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Trigger multiplexer

17 Trigger multiplexer
Green number in mux means Mux TriggerGroupNr.
[0:31] [1:32]
P-DMA0: PDMA0_TR_OUT[0:142]
[0:15] [33:48]
P-DMA1: PDMA1_TR_OUT[0:64]
[0:7] [49:56]
M-DMA: MDMA_TR_OUT[0:7]
[0:4] [57:61]
[0:16]
[0:4] [62:66] 0 P-DMA0: PDMA0_TR_IN[0:15]
1 [67]
[0:23] [68:91]
HSIOM: HSIOM_IO_INPUT[0:47]
[0:3] [92:95]
CPUSS: FAULT_TR_OUT[0:3]

[0:2] [1:3]
TCPWM[0]16: TCPWM0_16_TR_OUT0[0:2]
[0:2] [4:6]
TCPWM[0]16M: TCPWM0_16M_TR_OUT0[0:2]
[0:2] [7:9]
TCPWM[0]32: TCPWM0_32_TR_OUT0[0:2]
[0:29] [10:39]
TCPWM[1]16: TCPWM1_16_TR_OUT0[0:83]
[0:11] [40:51] [0:16]
TCPWM[1]16M: TCPWM1_16M_TR_OUT0[0:11] 1 P-DMA0: PDMA0_TR_IN[16:31]
[0:12] [52:64]
TCPWM[1]32: TCPWM1_32_TR_OUT0[0:12]
[0:5] [65:70]
PASS: PASS_GEN_TR_OUT[0:5]
[0:1] [71:72]
CPUSS: CTI_TR_OUT[0:1]
[0:3] [73:76]
EVTGEN: EVTGEN_TR_OUT[0:15]

[0:15] [1:16]
[0:31] [17:48]
[0:16]
[30:83] [49:102] 2 P-DMA1: PDMA1_TR_IN[0:15]
[24:47] [103:126]

[0:2] [1:3]
[0:7]
3 M-DMA: MDMA_TR_IN[0:7]
[0:2] [4:6]

FLEXRAY: FLEXRAY_TT_TR_OUT
[0:31] [1:32]
[0:15] [33:48]
[0:7] [49:56]
[0:2] [57:59]
[0:2] [60:62]
[0:2] [63:65]
[0:15] [66:81] [0:11]
4 TCPWM[0]: TCPWM0_ALL_CNT_TR_IN[0:11]
[0:5] [82:87]
[0:6] [88:94]
1 [95]
SMIF: SMIF_TX_TR_OUT
1 [96]
SMIF: SMIF_RX_TR_OUT
AUDIOSS[0]: I2S0_TX_TR_OUT
AUDIOSS[0]: I2S0_RX_TR_OUT [0],[0],...,[2],[2] [97:102]
:
AUDIOSS[2]: I2S2_TX_TR_OUT
AUDIOSS[2]: I2S2_RX_TR_OUT [0:2] [1:3]
[0:2] [4:6]
[0:2] [7:9]
[0:83] [10:93]
[0:11] [94:105]
[0:12] [106:118]
[0:4] [119:123]
CAN[0]: CAN0_DBG_TR_OUT[0:4]
[0:4] [124:128]
CAN[0]: CAN0_FIFO0_TR_OUT[0:4] [0:11]
[0:4] [129:133] 5 TCPWM[1]: TCPWM1_ALL_CNT_TR_IN[0:11]
CAN[0]: CAN0_FIFO1_TR_OUT[0:4]
[0:4] [134:138]
CAN[1]: CAN1_DBG_TR_OUT[0:4]
[0:4] [139:143]
CAN[1]: CAN1_FIFO0_TR_OUT[0:4]
[0:4] [144:148]
CAN[1]: CAN1_FIFO1_TR_OUT[0:4]
[0:4] [149:153]
CAN[0]: CAN0_TT_TR_OUT[0:4]
[0:4] [154:158]
CAN[1]: CAN1_TT_TR_OUT[0:4]
1 [159]
[4:11] [160:167]

[0:15] [1:16]
1 [17]
SCB[0]: SCB_TX_TR_OUT[0]
1 [18]
SCB[0]: SCB_RX_TR_OUT[0]
1 [19]
SCB[0]: SCB_I2C_SCL_TR_OUT[0]
27 [20:46]
(repeat from [1] to [9])
1 [47]
SCB[10]: SCB_TX_TR_OUT[10]
1 [48]
SCB[10]: SCB_RX_TR_OUT[10] [0:28]
1 [49] 6 TCPWM[1]: TCPWM1_ALL_CNT_TR_IN[12:40]
SCB[10]: SCB_I2C_SCL_TR_OUT[10]
1 [50]
FLEXRAY: FLEXRAY_IBUF_TR_OUT
1 [51]
FLEXRAY: FLEXRAY_OBUF_TR_OUT
[0:5] [52:57]
[0:47] [58:105]
[0:1] [106:107]
[0:3] [108:111]

[0:31] [1:32]
[0:11] [33:44]
[0:12] [45:57] [0:11]
7 PASS: PASS_GEN_TR_IN[0:11]
[0:7] [58:65]
[12:14] [66:68]

[0:4] [1:5] [0:4]

CAN[0]: CAN0_TT_TR_IN[0:4]
[0:4] [6:10] [5:9]
8 CAN[1]: CAN1_TT_TR_IN[0:4]
1 [11] [10]
FLEXRAY: FLEXRAY_TT_TR_IN

[0]
HSIOM: HSIOM_IO_OUTPUT[0]
[1]
HSIOM: HSIOM_IO_OUTPUT[1]
[2:3]
CPUSS: CTI_TR_IN[0:1]
[4]
PERI: PERI_DEBUG_FREEZE_TR_IN
[1:5] [5]
TR_GROUP10_OUTPUT[0:4] PASS: PASS_DEBUG_FREEZE_TR_IN
[6:10] [6]
TR_GROUP11_OUTPUT[0:4] 9 SRSS: SRSS_WDT_DEBUG_FREEZE_TR_IN
[11:15] [7]
TR_GROUP12_OUTPUT[0:4] SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[2]
[8]
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[1]
[9]
SRSS: SRSS_MCWDT_DEBUG_FREEZE_TR_IN[0]
[10]
TCPWM[0]: TCPWM0_DEBUG_FREEZE_TR_IN
[11]
TCPWM[1]: TCPWM1_DEBUG_FREEZE_TR_IN

[0:142] [1:143]
[0:10] [144:154]
[0:10] [155:165]
[0:10] [166:176]
[0:4] [177:181]
[0:4] [182:186]
[0:4] [187:191]
[0:4] [192:196] [0:4]
10 TR_GROUP9_INPUT[1:5]
[0:4] [197:201]
[0:4] [202:206]
[0:4] [207:211]
[0:4] [212:216]
[0:1] [217:218]
[0:3] [219:222]
[0:15] [223:238]

[0:12] [1:13]
[0:2] [14:16]
[0:11] [17:28]
[0:2] [29:31]
[0:83] [32:115]
[0:2] [116:118]
1 [119] [0:4]
11 TR_GROUP9_INPUT[6:10]
1 [120]
1 [121]
1 [122]
1 [123]
[0],[0],...,[2],[2] [124:129]
[0:47] [130:177]

[0:64] [1:65]
[0:7] [66:73]
[0:2] [74:76]
TCPWM[0]16: TCPWM0_16_TR_OUT1[0:2]
[0:2] [77:79]
TCPWM[0]16M: TCPWM0_16M_TR_OUT1[0:2]
[0:2] [80:82] [0:4]
TCPWM[0]32: TCPWM0_32_TR_OUT1[0:2] 12 TR_GROUP9_INPUT[11:15]
[0:83] [83:166]
TCPWM[1]16: TCPWM1_16_TR_OUT1[0:84]
[0:11] [167:178]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[0:11]
[0:12] [179:191]
TCPWM[1]32: TCPWM1_32_TR_OUT1[0:13]
[0:5] [192:197]

Figure 17-1 Trigger multiplexer group[30]

Note
30.The diagram shows only the TRIG_LABEL; the final trigger formation is based on the formula
TRIG_{PREFIX(IN/OUT)}_{MUX_x}_{TRIG_LABEL} and the information provided in Table 18-1, and Table 19-1.

Datasheet 69 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs

18 Triggers group inputs

Table 18-1 Trigger inputs
Input Trigger Description
MUX Group 0: P-DMA0 trigger multiplexer
1:32[31] PDMA0_TR_OUT[0:31] Allow P-DMA0 to chain to itself. Channels 0 - 31 are dedicated for
chaining
33:48 PDMA1_TR_OUT[0:15] Cross connections from P-DMA1 to P-DMA0, Channels 0-15 are
used
49:56 MDMA_TR_OUT[0:7] Cross connections from M-DMA0 to P-DMA0
57:61 CAN0_TT_TR_OUT[0:4] CAN0 Time Trigger Sync Outputs
62:66 CAN1_TT_TR_OUT[0:4] CAN1 Time Trigger Sync Outputs
67 FLEXRAY_TT_TR_OUT FlexRay0 timer trigger
68:91 HSIOM_IO_INPUT[0:23] I/O Inputs
92:95 FAULT_TR_OUT[0:3] Fault events
MUX Group 1: TCPWM to P-DMA0 trigger multiplexer
1:3 TCPWM0_16_TR_OUT0[0:2] 16-bit TCPWM0 counters
4:6 TCPWM0_16M_TR_OUT0[0:2] 16-bit Motor enhanced TCPWM0 counters
7:9 TCPWM0_32_TR_OUT0[0:2] 32-bit TCPWM0 counters
10:39 TCPWM1_16_TR_OUT0[0:29] 16-bit TCPWM1 counters
40:51 TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
52:64 TCPWM1_32_TR_OUT0[0:12] 32-bit TCPWM1 counters
65:70 PASS_GEN_TR_OUT[0:5] PASS SAR events
71:72 CTI_TR_OUT[0:1] Trace events
73:76 EVTGEN_TR_OUT[0:3] Event generator triggers
MUX Group 2: P-DMA1 trigger multiplexer
1:16 PDMA1_TR_OUT[0:15] Allow P-DMA1 to chain to itself. Channels 0–15 are dedicated for
chaining
17:48 PDMA0_TR_OUT[0:31] Cross connections from P-DMA0 to P-DMA1, channels 0–31 are
used.
49:102 TCPWM1_16_TR_OUT0[30:83] 16-bit TCPWM1 counters
103:126 HSIOM_IO_INPUT[24:47] I/O Inputs
MUX Group 3: M-DMA0 trigger multiplexer
1:3 TCPWM0_16_TR_OUT0[0:2] 16-bit TCPWM0 counters
4:6 TCPWM0_16M_TR_OUT0[0:2] 16-bit Motor enhanced TCPWM0 counters
MUX Group 4: TCPWM0 Loop back trigger multiplexer
1:32 PDMA0_TR_OUT[0:31] General-purpose P-DMA0 triggers
33:48 PDMA1_TR_OUT[0:15] General-purpose P-DMA1 triggers
49:56 MDMA_TR_OUT[0:7] M-DMA0 triggers
57:59 TCPWM0_16_TR_OUT0[0:2] 16-bit TCPWM0 counters
60:62 TCPWM0_16M_TR_OUT0[0:2] 16-bit motor enhanced TCPWM0 counters
63:65 TCPWM0_32_TR_OUT0[0:2] 32-bit TCPWM0 counters

Note
31.“x:y” depicts a range starting from ‘x’ through ‘y’.

Datasheet 70 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs

Table 18-1 Trigger inputs (continued)

Input Trigger Description
66:81 TCPWM1_16_TR_OUT0[0:15] 16-bit TCPWM1 counters
82:87 TCPWM1_16M_TR_OUT0[0:5] 16-bit motor enhanced TCPWM1 counters
88:94 TCPWM1_32_TR_OUT0[0:6] 32-bit TCPWM1 counters
95 SMIF_TX_TR_OUT SMIF0 TX trigger
96 SMIF_RX_TR_OUT SMIF0 RX trigger
97 I2S0_TX_TR_OUT I2S0 TX trigger
98 I2S0_RX_TR_OUT I2S0 RX trigger
99 I2S1_TX_TR_OUT I2S1 TX trigger
100 I2S1_RX_TR_OUT I2S1 RX trigger
101 I2S2_TX_TR_OUT I2S2 TX trigger
102 I2S2_RX_TR_OUT I2S2 RX trigger
MUX Group 5: TCPWM1 Loop back trigger multiplexer
1:3 TCPWM0_16_TR_OUT0[0:2] 16-bit TCPWM0 counters
4:6 TCPWM0_16M_TR_OUT0[0:2] 16-bit motor enhanced TCPWM0 counters
7:9 TCPWM0_32_TR_OUT0[0:2] 32-bit TCPWM0 counters
10:93 TCPWM1_16_TR_OUT0[0:83] 16-bit TCPWM1 counters
94:105 TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
106:118 TCPWM1_32_TR_OUT0[0:12] 32-bit TCPWM1 counters
119:123 CAN0_DBG_TR_OUT[0:4] CAN0 M-DMA0 events
124:128 CAN0_FIFO0_TR_OUT[0:4] CAN0 FIFO0 events
129:133 CAN0_FIFO1_TR_OUT[0:4] CAN0 FIFO1 events
134:138 CAN1_DBG_TR_OUT[0:4] CAN1 M-DMA0 events
139:143 CAN1_FIFO0_TR_OUT[0:4] CAN1 FIFO0 events
144:148 CAN1_FIFO1_TR_OUT[0:4] CAN1 FIFO1 events
149:153 CAN0_TT_TR_OUT[0:4] CAN0 TT sync outputs
154:158 CAN1_TT_TR_OUT[0:4] CAN1 TT sync outputs
159 FLEXRAY_TT_TR_OUT FlexRay0 timer trigger
160:167 EVTGEN_TR_OUT[4:11] Event generator triggers
MUX Group 6: TCPWM1 trigger Multiplexer
1:16 TCPWM1_16_TR_OUT1[0:15] 16-bit TCPWM1 counters
17 SCB_TX_TR_OUT[0] SCB0 TX trigger
18 SCB_RX_TR_OUT[0] SCB0 RX trigger
19 SCB_I2C_SCL_TR_OUT[0] SCB0 I2C trigger
20 SCB_TX_TR_OUT[1] SCB1 TX trigger
21 SCB_RX_TR_OUT[1] SCB1 RX trigger
22 SCB_I2C_SCL_TR_OUT[1] SCB1 I2C trigger
23 SCB_TX_TR_OUT[2] SCB2 TX trigger
24 SCB_RX_TR_OUT[2] SCB2 RX trigger
25 SCB_I2C_SCL_TR_OUT[2] SCB2 I2C trigger
26 SCB_TX_TR_OUT[3] SCB3 TX trigger
27 SCB_RX_TR_OUT[3] SCB3 RX trigger

Datasheet 71 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs

Table 18-1 Trigger inputs (continued)

Input Trigger Description
28 SCB_I2C_SCL_TR_OUT[3] SCB3 I2C trigger
29 SCB_TX_TR_OUT[4] SCB4 TX trigger
30 SCB_RX_TR_OUT[4] SCB4 RX trigger
31 SCB_I2C_SCL_TR_OUT[4] SCB4 I2C trigger
32 SCB_TX_TR_OUT[5] SCB5 TX trigger
33 SCB_RX_TR_OUT[5] SCB5 RX trigger
34 SCB_I2C_SCL_TR_OUT[5] SCB5 I2C trigger
35 SCB_TX_TR_OUT[6] SCB6 TX trigger
36 SCB_RX_TR_OUT[6] SCB6 RX trigger
37 SCB_I2C_SCL_TR_OUT[6] SCB6 I2C trigger
38 SCB_TX_TR_OUT[7] SCB7 TX trigger
39 SCB_RX_TR_OUT[7] SCB7 RX trigger
40 SCB_I2C_SCL_TR_OUT[7] SCB7 I2C trigger
41 SCB_TX_TR_OUT[8] SCB8 TX trigger
42 SCB_RX_TR_OUT[8] SCB8 RX trigger
43 SCB_I2C_SCL_TR_OUT[8] SCB8 I2C trigger
44 SCB_TX_TR_OUT[9] SCB9 TX trigger
45 SCB_RX_TR_OUT[9] SCB9 RX trigger
46 SCB_I2C_SCL_TR_OUT[9] SCB9 I2C trigger
47 SCB_TX_TR_OUT[10] SCB10 TX trigger
48 SCB_RX_TR_OUT[10] SCB10 RX trigger
49 SCB_I2C_SCL_TR_OUT[10] SCB10 I2C trigger
50 FLEXRAY_IBUF_TR_OUT FlexRay IBUF trigger
51 FLEXRAY_OBUF_TR_OUT FlexRay OBUF trigger
52:57 PASS_GEN_TR_OUT[0:5] PASS SAR ADC events
58:105 HSIOM_IO_INPUT[0:47] I/O Inputs
106:107 CTI_TR_IN[0:1] CPUSS CTI Trace events
108:111 FAULT_TR_OUT[0:3] Fault events
MUX Group 7: PASS trigger multiplexer
1:31 PDMA0_TR_OUT[0:31] General purpose P-DMA0 triggers
32:44 TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
45:57 TCPWM1_32_TR_OUT0[0:12] 32-bit TCPWM1 counters
58:65 HSIOM_IO_INPUT[0:7] I/O Inputs
66:68 EVTGEN_TR_OUT[12:14] Event generator triggers
MUX Group 8: CAN and FLEXRAY TT Sync
1:5 CAN0_TT_TR_OUT[0:4] CAN0 TT sync outputs
6:10 CAN1_TT_TR_OUT[0:4] CAN1 TT sync outputs
11 FLEXRAY_TT_TR_OUT FlexRay timer trigger
MUX Group 9: Debug multiplexer
1:5 TR_GROUP10_OUTPUT[0:4] Output from debug reduction multiplexer #1
6:10 TR_GROUP11_OUTPUT[0:4] Output from debug reduction multiplexer #2

Datasheet 72 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs

Table 18-1 Trigger inputs (continued)

Input Trigger Description
11:15 TR_GROUP12_OUTPUT[0:4] Output from debug reduction multiplexer #3
MUX Group 10: Debug Reduction #1
1:143 PDMA0_TR_OUT[0:142] General purpose P-DMA0 triggers
144:154 SCB_TX_TR_OUT[0:10] SCB TX triggers
155:165 SCB_RX_TR_OUT[0:10] SCB RX triggers
166:176 SCB_I2C_SCL_TR_OUT[0:10] SCB I2C triggers
177:181 CAN0_DBG_TR_OUT[0:4] CAN0 M-DMA0
182:186 CAN0_FIFO0_TR_OUT[0:4] CAN0 FIFO0
187:191 CAN0_FIFO1_TR_OUT[0:4] CAN0 FIFO1
192:196 CAN0_TT_TR_OUT[0:4] CAN0 TT sync outputs
197:201 CAN1_DBG_TR_OUT[0:4] CAN1 M-DMA0
202:206 CAN1_FIFO0_TR_OUT[0:4] CAN1 FIFO0
207:211 CAN1_FIFO1_TR_OUT[0:4] CAN1 FIFO1
212:216 CAN1_TT_TR_OUT[0:4] CAN1 TT sync outputs
217:218 CTI_TR_OUT[0:1] CPUSS CTI trace events
219:222 FAULT_TR_OU[0:3] Fault events
223:238 EVTGEN_TR_OUT[0:15] EVTGEN triggers
MUX Group 11: Debug Reduction #2
1:13 TCPWM1_32_TR_OUT0[0:12] 32-bit TCPWM1 counters
14:16 TCPWM0_32_TR_OUT0[0:2] 32-bit TCPWM0 counters
17:28 TCPWM1_16M_TR_OUT0[0:11] 16-bit Motor enhanced TCPWM1 counters
29:31 TCPWM0_16M_TR_OUT0[0:2] 16-bit Motor enhanced TCPWM0 counters
32:115 TCPWM1_16_TR_OUT0[0:83] 16-bit TCPWM1 counters
116:118 TCPWM0_16_TR_OUT0[0:2] 16-bit TCPWM0 counters
119 SMIF_TX_TR_OUT SMIF TX trigger
120 SMIF_RX_TR_OUT SMIF RX trigger
121 FLEXRAY_TT_TR_OUT FlexRay time trigger output
122 FLEXRAY_IBUF_TR_OUT FlexRay M-DMA0 trans request
123 FLEXRAY_OBUF_TR_OUT FlexRay M-DMA0 trans request
124 I2S0_TX_TR_OUT I2S0 TX trigger
125 I2S0_RX_TR_OUT I2S0 RX trigger
126 I2S1_TX_TR_OUT I2S1 TX trigger
127 I2S1_RX_TR_OUT I2S1 RX trigger
128 I2S2_TX_TR_OUT I2S2 TX trigger
129 I2S2_RX_TR_OUT I2S2 RX trigger
130:177 HSIOM_IO_INPUT[0:47] I/O inputs
MUX Group 12: Debug Reduction #3
1:65 PDMA1_TR_OUT[0:64] General purpose P-DMA1 triggers
66:73 MDMA_TR_OUT[0:7] M-DMA0 triggers
74:76 TCPWM0_16_TR_OUT1[0:2] 16-bit TCPWM0 counters
77:79 TCPWM0_16M_TR_OUT1[0:2] 16-bit Motor enhanced TCPWM0 counters

Datasheet 73 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group inputs

Table 18-1 Trigger inputs (continued)

Input Trigger Description
80:82 TCPWM0_32_TR_OUT1[0:2] 32-bit TCPWM0 counters
83:166 TCPWM1_16_TR_OUT1[0:83] 16-bit TCPWM1 counters
167:178 TCPWM1_16M_TR_OUT1[0:11] 16-bit Motor enhanced TCPWM1 counters
179:191 TCPWM1_32_TR_OUT1[0:12] 32-bit TCPWM1 counters
192:197 PASS_GEN_TR_OUT[0:5] PASS SAR ADC events

Datasheet 74 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers group outputs

19 Triggers group outputs

Table 19-1 Trigger outputs
Output Trigger Description
MUX Group 0: P-DMA0 trigger multiplexer
0:15 PDMA0_TR_IN[0:15] Triggers to P-DMA0[0:15]
MUX Group 1: TCPWM to P-DMA0 trigger multiplexer
0:15 PDMA0_TR_IN[16:31] Triggers to P-DMA0[16:31]
MUX Group 2: P-DMA1 trigger multiplexer
0:15 PDMA1_TR_IN[0:15] Triggers to P-DMA1
MUX Group 3: M-DMA0 trigger multiplexer
0:7 M-DMA_TR_IN[0:7] Triggers to M-DMA0
MUX Group 4: TCPWM0 Loop back trigger multiplexer
0:11 TCPWM0_ALL_CNT_TR_IN[0:11] Triggers to TCPWM0
MUX Group 5: TCPWM1 Loop back trigger multiplexer
0:11 TCPWM1_ALL_CNT_TR_IN[0:11] Triggers to TCPWM1
MUX Group 6: TCPWM1 trigger Multiplexer
0:28 TCPWM1_ALL_CNT_TR_IN[12:40] Triggers to TCPWM1
MUX Group 7: PASS trigger multiplexer
0:11 PASS_GEN_TR_IN[0:11] Triggers to PASS SAR ADCs
MUX Group 8: CAN and FLEXRAY TT Sync
0:4 CAN0_TT_TR_IN[0:4] CAN0 TT Sync Inputs
5:9 CAN1_TT_TR_IN[0:4] CAN1 TT Sync Inputs
10 FLEXRAY_TT_TR_IN FlexRay TT Inputs
MUX Group 9: Debug multiplexer
0 HSIOM_IO_OUTPUT[0] To HSIOM as an output
1 HSIOM_IO_OUTPUT[1] To HSIOM as an output
2:3 CTI_TR_IN[0:1] To the Cross Trigger system
4 PERI_DEBUG_FREEZE_TR_IN Signal to Freeze PERI operation
5 PASS_DEBUG_FREEZE_TR_IN Signal to Freeze SAR ADC operation
6 SRSS_WDT_DEBUG_FREEZE_TR_IN Signal to Freeze WDT operation
SRSS_MCWDT_DEBUG_-
7 FREEZE_TR_IN[2] Signal to Freeze MCWDT2 operation
SRSS_MCWDT_DEBUG_-
8 FREEZE_TR_IN[1] Signal to Freeze MCWDT1 operation
SRSS_MCWDT_DEBUG_-
9 FREEZE_TR_IN[0] Signal to Freeze MCWDT0 operation
10 TCPWM0_DEBUG_FREEZE_TR_IN Signal to Freeze TCPWM0 operation
11 TCPWM1_DEBUG_FREEZE_TR_IN Signal to Freeze TCPWM1 operation
MUX Group 10: Debug Reduction #1
0:4 TR_GROUP9_INPUT[1:5] To main debug multiplexer
MUX Group 11: Debug Reduction #2
0:4 TR_GROUP9_INPUT[6:10] To main debug multiplexer
MUX Group 12: Debug Reduction #3
0:4 TR_GROUP9_INPUT[11:15] To main debug multiplexer

Datasheet 75 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one

20 Triggers one-to-one

One-To-One TriggerGroupNr = 0
CAN[0]: CAN0_DBG_TR_OUT[0] P-DMA0: PDMA0_TR_IN[32]
CAN[0]: CAN0_FIFO0_TR_OUT[0] P-DMA0: PDMA0_TR_IN[33]
CAN[0]: CAN0_FIFO1_TR_OUT[0] P-DMA0: PDMA0_TR_IN[34]
CAN[0]: CAN0_DBG_TR_OUT[1] P-DMA0: PDMA0_TR_IN[35]
CAN[0]: CAN0_FIFO0_TR_OUT[1] P-DMA0: PDMA0_TR_IN[36]
CAN[0]: CAN0_FIFO1_TR_OUT[1] P-DMA0: PDMA0_TR_IN[37]
CAN[0]: CAN0_DBG_TR_OUT[2] P-DMA0: PDMA0_TR_IN[38]
CAN[0]: CAN0_FIFO0_TR_OUT[2] P-DMA0: PDMA0_TR_IN[39]
CAN[0]: CAN0_FIFO1_TR_OUT[2] P-DMA0: PDMA0_TR_IN[40]
CAN[0]: CAN0_DBG_TR_OUT[3] P-DMA0: PDMA0_TR_IN[41]
CAN[0]: CAN0_FIFO0_TR_OUT[3] P-DMA0: PDMA0_TR_IN[42]
CAN[0]: CAN0_FIFO1_TR_OUT[3] P-DMA0: PDMA0_TR_IN[43]
CAN[0]: CAN0_DBG_TR_OUT[4] P-DMA0: PDMA0_TR_IN[44]
CAN[0]: CAN0_FIFO0_TR_OUT[4] P-DMA0: PDMA0_TR_IN[45]
CAN[0]: CAN0_FIFO1_TR_OUT[4] P-DMA0: PDMA0_TR_IN[46]

One-To-One TriggerGroupNr = 1
PASS[0]: PASS0_CH_DONE_TO_PDMA0[0:31] P-DMA0: PDMA0_TR_IN[47:78]
PASS[0]: PASS0_CH_DONE_TO_PDMA0[32:63] P-DMA0: PDMA0_TR_IN[79:110]
PASS[0]: PASS0_CH_DONE_TO_PDMA0[64:95] P-DMA0: PDMA0_TR_IN[111:142]

One-To-One TriggerGroupNr = 2
SCB[0]: SCB0_TX_TR_OUT P-DMA1: PDMA1_TR_IN[16]
SCB[0]: SCB0_RX_TR_OUT P-DMA1: PDMA1_TR_IN[17]
… …
… …
SCB[10]: SCB10_TX_TR_OUT P-DMA1: PDMA1_TR_IN[36]
SCB[10]: SCB10_RX_TR_OUT P-DMA1: PDMA1_TR_IN[37]

One-To-One TriggerGroupNr = 3
SMIF: SMIF_TX_TR_OUT P-DMA1: PDMA1_TR_IN[53]
SMIF: SMIF_RX_TR_OUT P-DMA1: PDMA1_TR_IN[54]

One-To-One TriggerGroupNr = 4
CAN[1]: CAN1_DBG_TR_OUT[0] P-DMA1: PDMA1_TR_IN[38]
CAN[1]: CAN1_FIFO0_TR_OUT[0] P-DMA1: PDMA1_TR_IN[39]
CAN[1]: CAN1_FIFO1_TR_OUT[0] P-DMA1: PDMA1_TR_IN[40]
CAN[1]: CAN1_DBG_TR_OUT[1] P-DMA1: PDMA1_TR_IN[41]
CAN[1]: CAN1_FIFO0_TR_OUT[1] P-DMA1: PDMA1_TR_IN[42]
CAN[1]: CAN1_FIFO1_TR_OUT[1] P-DMA1: PDMA1_TR_IN[43]
CAN[1]: CAN1_DBG_TR_OUT[2] P-DMA1: PDMA1_TR_IN[44]
CAN[1]: CAN1_FIFO0_TR_OUT[2] P-DMA1: PDMA1_TR_IN[45]
CAN[1]: CAN1_FIFO1_TR_OUT[2] P-DMA1: PDMA1_TR_IN[46]
CAN[1]: CAN1_DBG_TR_OUT[3] P-DMA1: PDMA1_TR_IN[47]
CAN[1]: CAN1_FIFO0_TR_OUT[3] P-DMA1: PDMA1_TR_IN[48]
CAN[1]: CAN1_FIFO1_TR_OUT[3] P-DMA1: PDMA1_TR_IN[49]
CAN[1]: CAN1_DBG_TR_OUT[4] P-DMA1: PDMA1_TR_IN[50]
CAN[1]: CAN1_FIFO0_TR_OUT[4] P-DMA1: PDMA1_TR_IN[51]
CAN[1]: CAN1_FIFO1_TR_OUT[4] P-DMA1: PDMA1_TR_IN[52]

One-To-One TriggerGroupNr = 5
AUDIO: AUDIO0_TX_TR_OUT P-DMA1: PDMA1_TR_IN[55]
AUDIO: AUDIO0_RX_TR_OUT P-DMA1: PDMA1_TR_IN[56]
AUDIO: AUDIO1_TX_TR_OUT P-DMA1: PDMA1_TR_IN[57]
AUDIO: AUDIO1_RX_TR_OUT P-DMA1: PDMA1_TR_IN[58]
AUDIO: AUDIO2_TX_TR_OUT P-DMA1: PDMA1_TR_IN[59]
AUDIO: AUDIO2_RX_TR_OUT P-DMA1: PDMA1_TR_IN[60]

One-To-One TriggerGroupNr = 6
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[0:3] TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[0,3,6,9]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[4:31] TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[0:27]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[32:35] TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[1,4,7,10]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[36:63] TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[28:55]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[64:67] TCPWM[1]16M: TCPWM1_16M_ONE_CNT_TR_IN[2,5,8,11]
PASS[0]: PASS0_CH_RANGEVIO_TR_OUT[68:95] TCPWM[1]16: TCPWM1_16_ONE_CNT_TR_IN[56:83]
One-To-One TriggerGroupNr = 7
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[0,3,6,9] PASS[0]: PASS0_CH_TR_IN[0..3]
TCPWM[1]16: TCPWM1_16_TR_OUT1[0:27] PASS[0]: PASS0_CH_TR_IN[4:31]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[1,4,7,10] PASS[0]: PASS0_CH_TR_IN[32:35]
TCPWM[1]16: TCPWM1_16_TR_OUT1[28:55] PASS[0]: PASS0_CH_TR_IN[36:63]
TCPWM[1]16M: TCPWM1_16M_TR_OUT1[2,5,8,11] PASS[0]: PASS0_CH_TR_IN[64:67]
TCPWM[1]16: TCPWM1_16_TR_OUT1[56:83] PASS[0]: PASS0_CH_TR_IN[68:95]

One-To-One TriggerGroupNr = 8

P-DMA1: PDMA1_TR_OUT[38] CAN[1]: CAN1_DBG_TR_ACK[0]

P-DMA1: PDMA1_TR_OUT[41] CAN[1]: CAN1_DBG_TR_ACK[1]
P-DMA1: PDMA1_TR_OUT[44] CAN[1]: CAN1_DBG_TR_ACK[2]
P-DMA1: PDMA1_TR_OUT[47] CAN[1]: CAN1_DBG_TR_ACK[3]
P-DMA1: PDMA1_TR_OUT[50] CAN[1]: CAN1_DBG_TR_ACK[4]

One-To-One TriggerGroupNr = 9
P-DMA0: PDMA0_TR_OUT[32] CAN[0]: CAN0_DBG_TR_ACK[0]
P-DMA0: PDMA0_TR_OUT[35] CAN[0]: CAN0_DBG_TR_ACK[1]
P-DMA0: PDMA0_TR_OUT[38] CAN[0]: CAN0_DBG_TR_ACK[2]
P-DMA0: PDMA0_TR_OUT[41] CAN[0]: CAN0_DBG_TR_ACK[3]
P-DMA0: PDMA0_TR_OUT[44] CAN[0]: CAN0_DBG_TR_ACK[4]

One-To-One TriggerGroupNr = 10
TCPWM[1]16: TCPWM1_16_TR_OUT0[0:19] LIN[0]: LIN0_CMD_TR_IN[0:19]

One-To-One TriggerGroupNr = 11
FLEXRAY: FLEXRAY_IBF_TR_OUT P-DMA1: PDMA1_TR_IN[61]
FLEXRAY: FLEXRAY_OBF_TR_OUT P-DMA1: PDMA1_TR_IN[62]

One-To-One TriggerGroupNr = 12
P-DMA1: PDMA1_TR_OUT[61] P-DMA1: PDMA1_TR_IN[63]
P-DMA1: PDMA1_TR_OUT[62] P-DMA1: PDMA1_TR_IN[64]

One-To-One TriggerGroupNr = 13
P-DMA1: PDMA1_TR_OUT[63] FLEXRAY: FLEXRAY_IBF_TR_IN
P-DMA1: PDMA1_TR_OUT[64] FLEXRAY: FLEXRAY_OBF_TR_IN

Figure 20-1 Triggers one-to-one[32]

Note
32.The diagram shows only the TRIG_LABEL; the final trigger formation is based on the formula TRIG_{PREFIX(IN_1TO1/OUT_1-
TO1)}_{x}_{TRIG_LABEL} and the information provided in Table 20-1 on page 77.

Datasheet 76 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one

Table 20-1 Triggers 1:1

Input Trigger In Trigger Out Description
MUX Group 0: CAN0 to P-DMA0 Triggers

0 CAN0_DBG_TR_OUT[0] PDMA0_TR_IN[32] CAN0, Channel #0 P-DMA0 trigger

1 CAN0_FIFO0_TR_OUT[0] PDMA0_TR_IN[33] CAN0, Channel #0 FIFO0 trigger

2 CAN0_FIFO1_TR_OUT[0] PDMA0_TR_IN[34] CAN0, Channel #0 FIFO1 trigger

3 CAN0_DBG_TR_OUT[1] PDMA0_TR_IN[35] CAN0, Channel #1 P-DMA0 trigger

4 CAN0_FIFO0_TR_OUT[1] PDMA0_TR_IN[36] CAN0, Channel #1 FIFO0 trigger

5 CAN0_FIFO1_TR_OUT[1] PDMA0_TR_IN[37] CAN0, Channel #1 FIFO1 trigger

6 CAN0_DBG_TR_OUT[2] PDMA0_TR_IN[38] CAN0, Channel #2 P-DMA0 trigger

7 CAN0_FIFO0_TR_OUT[2] PDMA0_TR_IN[39] CAN0, Channel #2 FIFO0 trigger

8 CAN0_FIFO1_TR_OUT[2] PDMA0_TR_IN[40] CAN0, Channel #2 FIFO1 trigger

9 CAN0_DBG_TR_OUT[3] PDMA0_TR_IN[41] CAN0, Channel #3 P-DMA0 trigger

10 CAN0_FIFO0_TR_OUT[3] PDMA0_TR_IN[42] CAN0, Channel #3 FIFO0 trigger

11 CAN0_FIFO1_TR_OUT[3] PDMA0_TR_IN[43] CAN0, Channel #3 FIFO1 trigger

12 CAN0_DBG_TR_OUT[4] PDMA0_TR_IN[44] CAN0, Channel #4 P-DMA0 trigger

13 CAN0_FIFO0_TR_OUT[4] PDMA0_TR_IN[45] CAN0, Channel #4 FIFO0 trigger

14 CAN0_FIFO1_TR_OUT[4] PDMA0_TR_IN[46] CAN0, Channel #4 FIFO1 trigger

MUX Group 1: PASS SARx to P-DMA0 direct connect

0:31 PASS0_CH_DONE_TR_OUT[0:31] PDMA0_TR_IN[47:78] PASS SAR0 [0:31] to P-DMA0 direct connect

32:63 PASS0_CH_DONE_TR_OUT[32:63] PDMA0_TR_IN[79:110] PASS SAR1 [0:31] to P-DMA0 direct connect

64:95 PASS0_CH_DONE_TR_OUT[64:95] PDMA0_TR_IN[111:142] PASS SAR2 [0:31] to P-DMA0 direct connect

MUX Group 2: SCBx to P-DMA1 Triggers

0 SCB0_TX_TR_OUT PDMA1_TR_IN[16] SCB0 to P-DMA1 Trigger

1 SCB0_RX_TR_OUT PDMA1_TR_IN[17] SCB0 to P-DMA1 Trigger

2 SCB1_TX_TR_OUT PDMA1_TR_IN[18] SCB1 to P-DMA1 Trigger

3 SCB1_RX_TR_OUT PDMA1_TR_IN[19] SCB1 to P-DMA1 Trigger

4 SCB2_TX_TR_OUT PDMA1_TR_IN[20] SCB2 to P-DMA1 Trigger

5 SCB2_RX_TR_OUT PDMA1_TR_IN[21] SCB2 to P-DMA1 Trigger

6 SCB3_TX_TR_OUT PDMA1_TR_IN[22] SCB3 to P-DMA1 Trigger

7 SCB3_RX_TR_OUT PDMA1_TR_IN[23] SCB3 to P-DMA1 Trigger

8 SCB4_TX_TR_OUT PDMA1_TR_IN[24] SCB4 to P-DMA1 Trigger

9 SCB4_RX_TR_OUT PDMA1_TR_IN[25] SCB4 to P-DMA1 Trigger

10 SCB5_TX_TR_OUT PDMA1_TR_IN[26] SCB5 to P-DMA1 Trigger

11 SCB5_RX_TR_OUT PDMA1_TR_IN[27] SCB5 to P-DMA1 Trigger

12 SCB6_TX_TR_OUT PDMA1_TR_IN[28] SCB6 to P-DMA1 Trigger

13 SCB6_RX_TR_OUT PDMA1_TR_IN[29] SCB6 to P-DMA1 Trigger

14 SCB7_TX_TR_OUT PDMA1_TR_IN[30] SCB7 to P-DMA1 Trigger

15 SCB7_RX_TR_OUT PDMA1_TR_IN[31] SCB7 to P-DMA1 Trigger

16 SCB8_TX_TR_OUT PDMA1_TR_IN[32] SCB8 to P-DMA1 Trigger

17 SCB8_RX_TR_OUT PDMA1_TR_IN[33] SCB8 to P-DMA1 Trigger

18 SCB9_TX_TR_OUT PDMA1_TR_IN[34] SCB9 to P-DMA1 Trigger

19 SCB9_RX_TR_OUT PDMA1_TR_IN[35] SCB9 to P-DMA1 Trigger

20 SCB10_TX_TR_OUT PDMA1_TR_IN[36] SCB10 to P-DMA1 Trigger

21 SCB10_RX_TR_OUT PDMA1_TR_IN[37] SCB10 to P-DMA1 Trigger

Datasheet 77 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one

Table 20-1 Triggers 1:1 (continued)

Input Trigger In Trigger Out Description
MUX Group 3: SMIF0 to P-DMA1 Triggers

0 SMIF_TX_TR_OUT PDMA1_TR_IN[53] SMIF0 to P-DMA1 Trigger

1 SMIF_RX_TR_OUT PDMA1_TR_IN[54] SMIF0 to P-DMA1 Trigger

MUX Group 4: CAN1 to P-DMA1 triggers

0 CAN1_DBG_TR_OUT[0] PDMA1_TR_IN[38] CAN1 Channel #0 P-DMA1 trigger

1 CAN1_FIFO0_TR_OUT[0] PDMA1_TR_IN[39] CAN1 Channel #0 FIFO0 trigger

2 CAN1_FIFO1_TR_OUT[0] PDMA1_TR_IN[40] CAN1 Channel #0 FIFO1 trigger

3 CAN1_DBG_TR_OUT[1] PDMA1_TR_IN[41] CAN1 Channel #1 P-DMA1 trigger

4 CAN1_FIFO0_TR_OUT[1] PDMA1_TR_IN[42] CAN1 Channel #1 FIFO0 trigger

5 CAN1_FIFO1_TR_OUT[1] PDMA1_TR_IN[43] CAN1 Channel #1 FIFO1 trigger

6 CAN1_DBG_TR_OUT[2] PDMA1_TR_IN[44] CAN1 Channel #2 P-DMA1 trigger

7 CAN1_FIFO0_TR_OUT[2] PDMA1_TR_IN[45] CAN1 Channel #2 FIFO0 trigger

8 CAN1_FIFO1_TR_OUT[2] PDMA1_TR_IN[46] CAN1 Channel #2 FIFO1 trigger

9 CAN1_DBG_TR_OUT[3] PDMA1_TR_IN[47] CAN1 Channel #3 P-DMA1 trigger

10 CAN1_FIFO0_TR_OUT[3] PDMA1_TR_IN[48] CAN1 Channel #3 FIFO0 trigger

11 CAN1_FIFO1_TR_OUT[3] PDMA1_TR_IN[49] CAN1 Channel #3 FIFO1 trigger

12 CAN1_DBG_TR_OUT[4] PDMA1_TR_IN[50] CAN1 Channel #4 P-DMA1 trigger

13 CAN1_FIFO0_TR_OUT[4] PDMA1_TR_IN[51] CAN1 Channel #4 FIFO0 trigger

14 CAN1_FIFO1_TR_OUT[4] PDMA1_TR_IN[52] CAN1 Channel #4 FIFO1 trigger

2
MUX Group 5: I Sx to P-DMA1 Triggers

0 AUDIO0_TX_TR_OUT PDMA1_TR_IN[55] I2S0 TX to P-DMA1 trigger

1 AUDIO0_RX_TR_OUT PDMA1_TR_IN[56] I2S0 RX to P-DMA1 trigger

2 AUDIO1_TX_TR_OUT PDMA1_TR_IN[57] I2S1 TX to P-DMA1 trigger

3 AUDIO1_RX_TR_OUT PDMA1_TR_IN[58] I2S1 RX to P-DMA1 trigger

4 AUDIO2_TX_TR_OUT PDMA1_TR_IN[59] I2S2 TX to P-DMA1 trigger

5 AUDIO2_RX_TR_OUT PDMA1_TR_IN[60] I2S2 RX to P-DMA1 trigger

MUX Group 6: PASS SARx to TCPWM1 direct connect

0 PASS0_CH_RANGEVIO_TR_OUT[0] TCPWM1_16M_ONE_CNT_TR_IN[0] SAR0 ch#0[33], range violation to TCPWM1 Group #1 Counter #00 trig = 4

1 PASS0_CH_RANGEVIO_TR_OUT[1] TCPWM1_16M_ONE_CNT_TR_IN[3] SAR0 ch#1, range violation to TCPWM1 Group #1 Counter #03 trig = 4

2 PASS0_CH_RANGEVIO_TR_OUT[2] TCPWM1_16M_ONE_CNT_TR_IN[6] SAR0 ch#2, range violation to TCPWM1 Group #1 Counter #06 trig = 4

3 PASS0_CH_RANGEVIO_TR_OUT[3] TCPWM1_16M_ONE_CNT_TR_IN[9] SAR0 ch#3, range violation to TCPWM1 Group #1 Counter #09 trig = 4

4 PASS0_CH_RANGEVIO_TR_OUT[4] TCPWM1_16_ONE_CNT_TR_IN[0] SAR0 ch#4, range violation to TCPWM1 Group #0 Counter #00 trig = 4

5 PASS0_CH_RANGEVIO_TR_OUT[5] TCPWM1_16_ONE_CNT_TR_IN[1] SAR0 ch#5, range violation to TCPWM1 Group #0 Counter #01 trig = 4

6 PASS0_CH_RANGEVIO_TR_OUT[6] TCPWM1_16_ONE_CNT_TR_IN[2] SAR0 ch#6, range violation to TCPWM1 Group #0 Counter #02 trig = 4

7 PASS0_CH_RANGEVIO_TR_OUT[7] TCPWM1_16_ONE_CNT_TR_IN[3] SAR0 ch#7, range violation to TCPWM1 Group #0 Counter #03 trig = 4

8 PASS0_CH_RANGEVIO_TR_OUT[8] TCPWM1_16_ONE_CNT_TR_IN[4] SAR0 ch#8, range violation to TCPWM1 Group #0 Counter #04 trig = 4

9 PASS0_CH_RANGEVIO_TR_OUT[9] TCPWM1_16_ONE_CNT_TR_IN[5] SAR0 ch#9, range violation to TCPWM1 Group #0 Counter #05 trig = 4

10 PASS0_CH_RANGEVIO_TR_OUT[10] TCPWM1_16_ONE_CNT_TR_IN[6] SAR0 ch#10, range violation to TCPWM1 Group #0 Counter #06 trig = 4

11 PASS0_CH_RANGEVIO_TR_OUT[11] TCPWM1_16_ONE_CNT_TR_IN[7] SAR0 ch#11, range violation to TCPWM1 Group #0 Counter #07 trig = 4

12 PASS0_CH_RANGEVIO_TR_OUT[12] TCPWM1_16_ONE_CNT_TR_IN[8] SAR0 ch#12, range violation to TCPWM1 Group #0 Counter #08 trig = 4

13 PASS0_CH_RANGEVIO_TR_OUT[13] TCPWM1_16_ONE_CNT_TR_IN[9] SAR0 ch#13, range violation to TCPWM1 Group #0 Counter #09 trig = 4

14 PASS0_CH_RANGEVIO_TR_OUT[14] TCPWM1_16_ONE_CNT_TR_IN[10] SAR0 ch#14, range violation to TCPWM1 Group #0 Counter #10 trig = 4

Note
33.Each logical channel of SAR ADC[x] can be connected to any of the SAR ADC[x]_y external pin. (x = 0, or 1, or, 2 and y=0 to max 31)

Datasheet 78 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one

Table 20-1 Triggers 1:1 (continued)

Input Trigger In Trigger Out Description
15 PASS0_CH_RANGEVIO_TR_OUT[15] TCPWM1_16_ONE_CNT_TR_IN[11] SAR0 ch#15, range violation to TCPWM1 Group #0 Counter #11 trig = 4

16 PASS0_CH_RANGEVIO_TR_OUT[16] TCPWM1_16_ONE_CNT_TR_IN[12] SAR0 ch#16, range violation to TCPWM1 Group #0 Counter #12 trig = 4

17 PASS0_CH_RANGEVIO_TR_OUT[17] TCPWM1_16_ONE_CNT_TR_IN[13] SAR0 ch#17, range violation to TCPWM1 Group #0 Counter #13 trig = 4

18 PASS0_CH_RANGEVIO_TR_OUT[18] TCPWM1_16_ONE_CNT_TR_IN[14] SAR0 ch#18, range violation to TCPWM1 Group #0 Counter #14 trig = 4

19 PASS0_CH_RANGEVIO_TR_OUT[19] TCPWM1_16_ONE_CNT_TR_IN[15] SAR0 ch#19, range violation to TCPWM1 Group #0 Counter #15 trig = 4

20 PASS0_CH_RANGEVIO_TR_OUT[20] TCPWM1_16_ONE_CNT_TR_IN[16] SAR0 ch#20, range violation to TCPWM1 Group #0 Counter #16 trig = 4

21 PASS0_CH_RANGEVIO_TR_OUT[21] TCPWM1_16_ONE_CNT_TR_IN[17] SAR0 ch#21, range violation to TCPWM1 Group #0 Counter #17 trig = 4

22 PASS0_CH_RANGEVIO_TR_OUT[22] TCPWM1_16_ONE_CNT_TR_IN[18] SAR0 ch#22, range violation to TCPWM1 Group #0 Counter #18 trig = 4

23 PASS0_CH_RANGEVIO_TR_OUT[23] TCPWM1_16_ONE_CNT_TR_IN[19] SAR0 ch#23, range violation to TCPWM1 Group #0 Counter #19 trig = 4

24 PASS0_CH_RANGEVIO_TR_OUT[24] TCPWM1_16_ONE_CNT_TR_IN[20] SAR0 ch#24, range violation to TCPWM1 Group #0 Counter #20 trig = 4

25 PASS0_CH_RANGEVIO_TR_OUT[25] TCPWM1_16_ONE_CNT_TR_IN[21] SAR0 ch#25, range violation to TCPWM1 Group #0 Counter #21 trig = 4

26 PASS0_CH_RANGEVIO_TR_OUT[26] TCPWM1_16_ONE_CNT_TR_IN[22] SAR0 ch#26, range violation to TCPWM1 Group #0 Counter #22 trig = 4

27 PASS0_CH_RANGEVIO_TR_OUT[27] TCPWM1_16_ONE_CNT_TR_IN[23] SAR0 ch#27, range violation to TCPWM1 Group #0 Counter #23 trig = 4

28 PASS0_CH_RANGEVIO_TR_OUT[28] TCPWM1_16_ONE_CNT_TR_IN[24] SAR0 ch#28, range violation to TCPWM1 Group #0 Counter #24 trig = 4

29 PASS0_CH_RANGEVIO_TR_OUT[29] TCPWM1_16_ONE_CNT_TR_IN[25] SAR0 ch#29, range violation to TCPWM1 Group #0 Counter #25 trig = 4

30 PASS0_CH_RANGEVIO_TR_OUT[30] TCPWM1_16_ONE_CNT_TR_IN[26] SAR0 ch#30, range violation to TCPWM1 Group #0 Counter #26 trig = 4

31 PASS0_CH_RANGEVIO_TR_OUT[31] TCPWM1_16_ONE_CNT_TR_IN[27] SAR0 ch#31, range violation to TCPWM1 Group #0 Counter #27 trig = 4

32 PASS0_CH_RANGEVIO_TR_OUT[32] TCPWM1_16M_ONE_CNT_TR_IN[1] SAR1 ch#0, range violation to TCPWM1 Group #1 Counter #01 trig = 4

33 PASS0_CH_RANGEVIO_TR_OUT[33] TCPWM1_16M_ONE_CNT_TR_IN[4] SAR1 ch#1, range violation to TCPWM1 Group #1 Counter #04 trig = 4

34 PASS0_CH_RANGEVIO_TR_OUT[34] TCPWM1_16M_ONE_CNT_TR_IN[7] SAR1 ch#2, range violation to TCPWM1 Group #1 Counter #07 trig = 4

35 PASS0_CH_RANGEVIO_TR_OUT[35] TCPWM1_16M_ONE_CNT_TR_IN[10] SAR1 ch#3, range violation to TCPWM1 Group #1 Counter #10 trig = 4

36 PASS0_CH_RANGEVIO_TR_OUT[36] TCPWM1_16_ONE_CNT_TR_IN[28] SAR1 ch#4, range violation to TCPWM1 Group #0 Counter #28 trig = 4

37 PASS0_CH_RANGEVIO_TR_OUT[37] TCPWM1_16_ONE_CNT_TR_IN[29] SAR1 ch#5, range violation to TCPWM1 Group #0 Counter #29 trig = 4

38 PASS0_CH_RANGEVIO_TR_OUT[38] TCPWM1_16_ONE_CNT_TR_IN[30] SAR1 ch#6, range violation to TCPWM1 Group #0 Counter #30 trig = 4

39 PASS0_CH_RANGEVIO_TR_OUT[39] TCPWM1_16_ONE_CNT_TR_IN[31] SAR1 ch#7, range violation to TCPWM1 Group #0 Counter #31 trig = 4

40 PASS0_CH_RANGEVIO_TR_OUT[40] TCPWM1_16_ONE_CNT_TR_IN[32] SAR1 ch#8, range violation to TCPWM1 Group #0 Counter #32 trig = 4

41 PASS0_CH_RANGEVIO_TR_OUT[41] TCPWM1_16_ONE_CNT_TR_IN[33] SAR1 ch#9, range violation to TCPWM1 Group #0 Counter #33 trig = 4

42 PASS0_CH_RANGEVIO_TR_OUT[42] TCPWM1_16_ONE_CNT_TR_IN[34] SAR1 ch#10, range violation to TCPWM1 Group #0 Counter #34 trig = 4

43 PASS0_CH_RANGEVIO_TR_OUT[43] TCPWM1_16_ONE_CNT_TR_IN[35] SAR1 ch#11, range violation to TCPWM1 Group #0 Counter #35 trig = 4

44 PASS0_CH_RANGEVIO_TR_OUT[44] TCPWM1_16_ONE_CNT_TR_IN[36] SAR1 ch#12, range violation to TCPWM1 Group #0 Counter #36 trig = 4

45 PASS0_CH_RANGEVIO_TR_OUT[45] TCPWM1_16_ONE_CNT_TR_IN[37] SAR1 ch#13, range violation to TCPWM1 Group #0 Counter #37 trig = 4

46 PASS0_CH_RANGEVIO_TR_OUT[46] TCPWM1_16_ONE_CNT_TR_IN[38] SAR1 ch#14, range violation to TCPWM1 Group #0 Counter #38 trig = 4

47 PASS0_CH_RANGEVIO_TR_OUT[47] TCPWM1_16_ONE_CNT_TR_IN[39] SAR1 ch#15, range violation to TCPWM1 Group #0 Counter #39 trig = 4

48 PASS0_CH_RANGEVIO_TR_OUT[48] TCPWM1_16_ONE_CNT_TR_IN[40] SAR1 ch#16, range violation to TCPWM1 Group #0 Counter #40 trig = 4

49 PASS0_CH_RANGEVIO_TR_OUT[49] TCPWM1_16_ONE_CNT_TR_IN[41] SAR1 ch#17, range violation to TCPWM1 Group #0 Counter #41 trig = 4

50 PASS0_CH_RANGEVIO_TR_OUT[50] TCPWM1_16_ONE_CNT_TR_IN[42] SAR1 ch#18, range violation to TCPWM1 Group #0 Counter #42 trig = 4

51 PASS0_CH_RANGEVIO_TR_OUT[51] TCPWM1_16_ONE_CNT_TR_IN[43] SAR1 ch#19, range violation to TCPWM1 Group #0 Counter #43 trig = 4

52 PASS0_CH_RANGEVIO_TR_OUT[52] TCPWM1_16_ONE_CNT_TR_IN[44] SAR1 ch#20, range violation to TCPWM1 Group #0 Counter #44 trig = 4

53 PASS0_CH_RANGEVIO_TR_OUT[53] TCPWM1_16_ONE_CNT_TR_IN[45] SAR1 ch#21, range violation to TCPWM1 Group #0 Counter #45 trig = 4

54 PASS0_CH_RANGEVIO_TR_OUT[54] TCPWM1_16_ONE_CNT_TR_IN[46] SAR1 ch#22, range violation to TCPWM1 Group #0 Counter #46 trig = 4

55 PASS0_CH_RANGEVIO_TR_OUT[55] TCPWM1_16_ONE_CNT_TR_IN[47] SAR1 ch#23, range violation to TCPWM1 Group #0 Counter #47 trig = 4

56 PASS0_CH_RANGEVIO_TR_OUT[56] TCPWM1_16_ONE_CNT_TR_IN[48] SAR1 ch#24, range violation to TCPWM1 Group #0 Counter #48 trig = 4

57 PASS0_CH_RANGEVIO_TR_OUT[57] TCPWM1_16_ONE_CNT_TR_IN[49] SAR1 ch#25, range violation to TCPWM1 Group #0 Counter #49 trig = 4

58 PASS0_CH_RANGEVIO_TR_OUT[58] TCPWM1_16_ONE_CNT_TR_IN[50] SAR1 ch#26, range violation to TCPWM1 Group #0 Counter #50 trig = 4

59 PASS0_CH_RANGEVIO_TR_OUT[59] TCPWM1_16_ONE_CNT_TR_IN[51] SAR1 ch#27, range violation to TCPWM1 Group #0 Counter #51 trig = 4

Datasheet 79 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one

Table 20-1 Triggers 1:1 (continued)

Input Trigger In Trigger Out Description
60 PASS0_CH_RANGEVIO_TR_OUT[60] TCPWM1_16_ONE_CNT_TR_IN[52] SAR1 ch#28, range violation to TCPWM1 Group #0 Counter #52 trig = 4

61 PASS0_CH_RANGEVIO_TR_OUT[61] TCPWM1_16_ONE_CNT_TR_IN[53] SAR1 ch#29, range violation to TCPWM1 Group #0 Counter #53 trig = 4

62 PASS0_CH_RANGEVIO_TR_OUT[62] TCPWM1_16_ONE_CNT_TR_IN[54] SAR1 ch#30, range violation to TCPWM1 Group #0 Counter #54 trig = 4

63 PASS0_CH_RANGEVIO_TR_OUT[63] TCPWM1_16_ONE_CNT_TR_IN[55] SAR1 ch#31, range violation to TCPWM1 Group #0 Counter #55 trig = 4

64 PASS0_CH_RANGEVIO_TR_OUT[64] TCPWM1_16M_ONE_CNT_TR_IN[2] SAR2 ch#0, range violation to TCPWM1 Group #1 Counter #02 trig = 4

65 PASS0_CH_RANGEVIO_TR_OUT[65] TCPWM1_16M_ONE_CNT_TR_IN[5] SAR2 ch#1, range violation to TCPWM1 Group #1 Counter #05 trig = 4

66 PASS0_CH_RANGEVIO_TR_OUT[66] TCPWM1_16M_ONE_CNT_TR_IN[8] SAR2 ch#2, range violation to TCPWM1 Group #1 Counter #08 trig = 4

67 PASS0_CH_RANGEVIO_TR_OUT[67] TCPWM1_16M_ONE_CNT_TR_IN[11] SAR2 ch#3, range violation to TCPWM1 Group #1 Counter #11 trig = 4

68 PASS0_CH_RANGEVIO_TR_OUT[68] TCPWM1_16_ONE_CNT_TR_IN[56] SAR2 ch#4, range violation to TCPWM1 Group #0 Counter #56 trig = 4

69 PASS0_CH_RANGEVIO_TR_OUT[69] TCPWM1_16_ONE_CNT_TR_IN[57] SAR2 ch#5, range violation to TCPWM1 Group #0 Counter #57 trig = 4

70 PASS0_CH_RANGEVIO_TR_OUT[70] TCPWM1_16_ONE_CNT_TR_IN[58] SAR2 ch#6, range violation to TCPWM1 Group #0 Counter #58 trig = 4

71 PASS0_CH_RANGEVIO_TR_OUT[71] TCPWM1_16_ONE_CNT_TR_IN[59] SAR2 ch#7, range violation to TCPWM1 Group #0 Counter #59 trig = 4

72 PASS0_CH_RANGEVIO_TR_OUT[72] TCPWM1_16_ONE_CNT_TR_IN[60] SAR2 ch#8, range violation to TCPWM1 Group #0 Counter #60 trig = 4

73 PASS0_CH_RANGEVIO_TR_OUT[73] TCPWM1_16_ONE_CNT_TR_IN[61] SAR2 ch#9, range violation to TCPWM1 Group #0 Counter #61 trig = 4

74 PASS0_CH_RANGEVIO_TR_OUT[74] TCPWM1_16_ONE_CNT_TR_IN[62] SAR2 ch#10, range violation to TCPWM1 Group #0 Counter #62 trig = 4

75 PASS0_CH_RANGEVIO_TR_OUT[75] TCPWM1_16_ONE_CNT_TR_IN[63] SAR2 ch#11, range violation to TCPWM1 Group #0 Counter #63 trig = 4

76 PASS0_CH_RANGEVIO_TR_OUT[76] TCPWM1_16_ONE_CNT_TR_IN[64] SAR2 ch#12, range violation to TCPWM1 Group #0 Counter #64 trig = 4

77 PASS0_CH_RANGEVIO_TR_OUT[77] TCPWM1_16_ONE_CNT_TR_IN[65] SAR2 ch#13, range violation to TCPWM1 Group #0 Counter #65 trig = 4

78 PASS0_CH_RANGEVIO_TR_OUT[78] TCPWM1_16_ONE_CNT_TR_IN[66] SAR2 ch#14, range violation to TCPWM1 Group #0 Counter #66 trig = 4

79 PASS0_CH_RANGEVIO_TR_OUT[79] TCPWM1_16_ONE_CNT_TR_IN[67] SAR2 ch#15, range violation to TCPWM1 Group #0 Counter #67 trig = 4

80 PASS0_CH_RANGEVIO_TR_OUT[80] TCPWM1_16_ONE_CNT_TR_IN[68] SAR2 ch#16, range violation to TCPWM1 Group #0 Counter #68 trig = 4

81 PASS0_CH_RANGEVIO_TR_OUT[81] TCPWM1_16_ONE_CNT_TR_IN[69] SAR2 ch#17, range violation to TCPWM1 Group #0 Counter #69 trig = 4

82 PASS0_CH_RANGEVIO_TR_OUT[82] TCPWM1_16_ONE_CNT_TR_IN[70] SAR2 ch#18, range violation to TCPWM1 Group #0 Counter #70 trig = 4

83 PASS0_CH_RANGEVIO_TR_OUT[83] TCPWM1_16_ONE_CNT_TR_IN[71] SAR2 ch#19, range violation to TCPWM1 Group #0 Counter #71 trig = 4

84 PASS0_CH_RANGEVIO_TR_OUT[84] TCPWM1_16_ONE_CNT_TR_IN[72] SAR2 ch#20, range violation to TCPWM1 Group #0 Counter #72 trig = 4

85 PASS0_CH_RANGEVIO_TR_OUT[85] TCPWM1_16_ONE_CNT_TR_IN[73] SAR2 ch#21, range violation to TCPWM1 Group #0 Counter #73 trig = 4

86 PASS0_CH_RANGEVIO_TR_OUT[86] TCPWM1_16_ONE_CNT_TR_IN[74] SAR2 ch#22, range violation to TCPWM1 Group #0 Counter #74 trig = 4

87 PASS0_CH_RANGEVIO_TR_OUT[87] TCPWM1_16_ONE_CNT_TR_IN[75] SAR2 ch#23, range violation to TCPWM1 Group #0 Counter #75 trig = 4

88 PASS0_CH_RANGEVIO_TR_OUT[88] TCPWM1_16_ONE_CNT_TR_IN[76] SAR2 ch#24, range violation to TCPWM1 Group #0 Counter #76 trig = 4

89 PASS0_CH_RANGEVIO_TR_OUT[89] TCPWM1_16_ONE_CNT_TR_IN[77] SAR2 ch#25, range violation to TCPWM1 Group #0 Counter #77 trig = 4

90 PASS0_CH_RANGEVIO_TR_OUT[90] TCPWM1_16_ONE_CNT_TR_IN[78] SAR2 ch#26, range violation to TCPWM1 Group #0 Counter #78 trig = 4

91 PASS0_CH_RANGEVIO_TR_OUT[91] TCPWM1_16_ONE_CNT_TR_IN[79] SAR2 ch#27, range violation to TCPWM1 Group #0 Counter #79 trig = 4

92 PASS0_CH_RANGEVIO_TR_OUT[92] TCPWM1_16_ONE_CNT_TR_IN[80] SAR2 ch#28, range violation to TCPWM1 Group #0 Counter #80 trig = 4

93 PASS0_CH_RANGEVIO_TR_OUT[93] TCPWM1_16_ONE_CNT_TR_IN[81] SAR2 ch#29, range violation to TCPWM1 Group #0 Counter #81 trig = 4

94 PASS0_CH_RANGEVIO_TR_OUT[94] TCPWM1_16_ONE_CNT_TR_IN[82] SAR2 ch#30, range violation to TCPWM1 Group #0 Counter #82 trig = 4

95 PASS0_CH_RANGEVIO_TR_OUT[95] TCPWM1_16_ONE_CNT_TR_IN[83] SAR2 ch#31, range violation to TCPWM1 Group #0 Counter #83 trig = 4

MUX Group 7: TCPWM1 to PASS SARx

0 TCPWM1_16M_TR_OUT1[0] PASS0_CH_TR_IN[0] TCPWM1 Group #1 Counter #00 (PWM1_M_0) to SAR0 ch#0

1 TCPWM1_16M_TR_OUT1[3] PASS0_CH_TR_IN[1] TCPWM1 Group #1 Counter #03 (PWM1_M_3) to SAR0 ch#1

2 TCPWM1_16M_TR_OUT1[6] PASS0_CH_TR_IN[2] TCPWM1 Group #1 Counter #06 (PWM1_M_6) to SAR0 ch#2

3 TCPWM1_16M_TR_OUT1[9] PASS0_CH_TR_IN[3] TCPWM1 Group #1 Counter #09 (PWM1_M_9) to SAR0 ch#3

4:31 TCPWM1_16_TR_OUT1[0:27] PASS0_CH_TR_IN[4:31] TCPWM1 Group #0 Counter #00 through 27 (PWM1_0 to PWM1_27) to SAR0
ch#4 through SAR0 ch#31
32 TCPWM1_16M_TR_OUT1[1] PASS0_CH_TR_IN[32] TCPWM1 Group #1 Counter #01 (PWM1_M_1) to SAR1 ch#0

33 TCPWM1_16M_TR_OUT1[4] PASS0_CH_TR_IN[33] TCPWM1 Group #1 Counter #04 (PWM1_M_4) to SAR1 ch#1

34 TCPWM1_16M_TR_OUT1[7] PASS0_CH_TR_IN[34] TCPWM1 Group #1 Counter #07 (PWM1_M_7) to SAR1 ch#2

Datasheet 80 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Triggers one-to-one

Table 20-1 Triggers 1:1 (continued)

Input Trigger In Trigger Out Description
35 TCPWM1_16M_TR_OUT1[10] PASS0_CH_TR_IN[35] TCPWM1 Group #1 Counter #10 (PWM1_M_10) to SAR1 ch#3

36:63 TCPWM1_16_TR_OUT1[28:55] PASS0_CH_TR_IN[36:63] TCPWM1 Group #0 Counter #28 through 55 (PWM1_28 to PWM1_55) to SAR1
ch#4 through SAR1 ch#31
64 TCPWM1_16M_TR_OUT1[2] PASS0_CH_TR_IN[64] TCPWM1 Group #1 Counter #02 (PWM1_M_2) to SAR2 ch#0

65 TCPWM1_16M_TR_OUT1[5] PASS0_CH_TR_IN[65] TCPWM1 Group #1 Counter #05 (PWM1_M_5) to SAR2 ch#1

66 TCPWM1_16M_TR_OUT1[8] PASS0_CH_TR_IN[66] TCPWM1 Group #1 Counter #08 (PWM1_M_8) to SAR2 ch#2

67 TCPWM1_16M_TR_OUT1[11] PASS0_CH_TR_IN[67] TCPWM1 Group #1 Counter #11 (PWM1_M_11) to SAR2 ch#3

68:95 TCPWM1_16_TR_OUT1[56:83] PASS0_CH_TR_IN[68:95] TCPWM1 Group #0 Counter #56 through 83 (PWM1_56 to PWM1_83) to SAR2
ch#4 through SAR2 ch#31
MUX Group 8: Acknowledge triggers from P-DMA1 to CAN1

0 PDMA1_TR_OUT[38] CAN1_DBG_TR_ACK[0] CAN1 Channel#0 P-DMA1 acknowledge

1 PDMA1_TR_OUT[41] CAN1_DBG_TR_ACK[1] CAN1 Channel#1 P-DMA1 acknowledge

2 PDMA1_TR_OUT[44] CAN1_DBG_TR_ACK[2] CAN1 Channel#2 P-DMA1 acknowledge

3 PDMA1_TR_OUT[47] CAN1_DBG_TR_ACK[3] CAN1 Channel#3 P-DMA1 acknowledge

4 PDMA1_TR_OUT[50] CAN1_DBG_TR_ACK[4] CAN1 Channel#4 P-DMA1 acknowledge

MUX Group 9: Acknowledge triggers from P-DMA0 to CAN0

0 PDMA0_TR_OUT[32] CAN0_DBG_TR_ACK[0] CAN0 Channel#0 P-DMA0 acknowledge

1 PDMA0_TR_OUT[35] CAN0_DBG_TR_ACK[1] CAN0 Channel#1 P-DMA0 acknowledge

2 PDMA0_TR_OUT[38] CAN0_DBG_TR_ACK[2] CAN0 Channel#2 P-DMA0 acknowledge

3 PDMA0_TR_OUT[41] CAN0_DBG_TR_ACK[3] CAN0 Channel#3 P-DMA0 acknowledge

4 PDMA0_TR_OUT[44] CAN0_DBG_TR_ACK[4] CAN0 Channel#4 P-DMA0 acknowledge

MUX Group 10: TCPWM1 to LIN0 triggers

0:19 TCPWM1_16_TR_OUT0[0:19] LIN0_CMD_TR_IN[0:19] TCPWM1 (Group #0 Counter #00 to #19) to LIN0

MUX Group 11: FLEXRAY to P-DMA1 triggers

0 FLEXRAY_IBF_TR_OUT PDMA1_TR_IN[61] FlexRay to P-DMA1

1 FLEXRAY_OBF_TR_OUT PDMA1_TR_IN[62] FlexRay to P-DMA1

MUX Group 12: P-DMA1 TO P-DMA1 triggers

0 PDMA1_TR_OUT[61] PDMA1_TR_IN[63] P-DMA1 to P-DMA1

1 PDMA1_TR_OUT[62] PDMA1_TR_IN[64] P-DMA1 to P-DMA1

MUX Group 13: P-DMA1 TO FLEXRAY triggers

0 PDMA1_TR_OUT[63] FLEXRAY_IBF_TR_IN P-DMA1 to FlexRay

1 PDMA1_TR_OUT[64] FLEXRAY_OBF_TR_IN P-DMA1 to FlexRay

Datasheet 81 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks

21 Peripheral clocks
Table 21-1 Peripheral clock assignments
Output Destination Description
CPUSS root clocks (Group 0)
0 PCLK_CPUSS_CLOCK_TRACE_IN Trace clock
1 PCLK_SMARTIO12_CLOCK Smart I/O #12
2 PCLK_SMARTIO13_CLOCK Smart I/O #13
3 PCLK_SMARTIO14_CLOCK Smart I/O #14
4 PCLK_SMARTIO15_CLOCK Smart I/O #15
5 PCLK_SMARTIO17_CLOCK Smart I/O #17
6 PCLK_TCPWM0_CLOCKS0 TCPWM0 Group #0, Counter #0
7 PCLK_TCPWM0_CLOCKS1 TCPWM0 Group #0, Counter #1
8 PCLK_TCPWM0_CLOCKS2 TCPWM0 Group #0, Counter #2
9 PCLK_TCPWM0_CLOCKS256 TCPWM0 Group #1, Counter #0
10 PCLK_TCPWM0_CLOCKS257 TCPWM0 Group #1, Counter #1
11 PCLK_TCPWM0_CLOCKS258 TCPWM0 Group #1, Counter #2
12 PCLK_TCPWM0_CLOCKS512 TCPWM0 Group #2, Counter #0
13 PCLK_TCPWM0_CLOCKS513 TCPWM0 Group #2, Counter #1
14 PCLK_TCPWM0_CLOCKS514 TCPWM0 Group #2, Counter #2
COMM root clocks (Group 1)
0 PCLK_CANFD0_CLOCK_CAN0 CAN0, Channel #0
1 PCLK_CANFD0_CLOCK_CAN1 CAN0, Channel #1
2 PCLK_CANFD0_CLOCK_CAN2 CAN0, Channel #2
3 PCLK_CANFD0_CLOCK_CAN3 CAN0, Channel #3
4 PCLK_CANFD0_CLOCK_CAN4 CAN0, Channel #4
5 PCLK_CANFD1_CLOCK_CAN0 CAN1, Channel #0
6 PCLK_CANFD1_CLOCK_CAN1 CAN1, Channel #1
7 PCLK_CANFD1_CLOCK_CAN2 CAN1, Channel #2
8 PCLK_CANFD1_CLOCK_CAN3 CAN1, Channel #3
9 PCLK_CANFD1_CLOCK_CAN4 CAN1, Channel #4
10 PCLK_LIN0_CLOCK_CH_EN0 LIN0, Channel #0
11 PCLK_LIN0_CLOCK_CH_EN1 LIN0, Channel #1
12 PCLK_LIN0_CLOCK_CH_EN2 LIN0, Channel #2
13 PCLK_LIN0_CLOCK_CH_EN3 LIN0, Channel #3
14 PCLK_LIN0_CLOCK_CH_EN4 LIN0, Channel #4
15 PCLK_LIN0_CLOCK_CH_EN5 LIN0, Channel #5
16 PCLK_LIN0_CLOCK_CH_EN6 LIN0, Channel #6
17 PCLK_LIN0_CLOCK_CH_EN7 LIN0, Channel #7
18 PCLK_LIN0_CLOCK_CH_EN8 LIN0, Channel #8
19 PCLK_LIN0_CLOCK_CH_EN9 LIN0, Channel #9
20 PCLK_LIN0_CLOCK_CH_EN10 LIN0, Channel #10
21 PCLK_LIN0_CLOCK_CH_EN11 LIN0, Channel #11

Datasheet 82 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks

Table 21-1 Peripheral clock assignments (continued)

Output Destination Description
22 PCLK_LIN0_CLOCK_CH_EN12 LIN0, Channel #12
23 PCLK_LIN0_CLOCK_CH_EN13 LIN0, Channel #13
24 PCLK_LIN0_CLOCK_CH_EN14 LIN0, Channel #14
25 PCLK_LIN0_CLOCK_CH_EN15 LIN0, Channel #15
26 PCLK_LIN0_CLOCK_CH_EN16 LIN0, Channel #16
27 PCLK_LIN0_CLOCK_CH_EN17 LIN0, Channel #17
28 PCLK_LIN0_CLOCK_CH_EN18 LIN0, Channel #18
29 PCLK_LIN0_CLOCK_CH_EN19 LIN0, Channel #19
30 PCLK_SCB0_CLOCK SCB0
31 PCLK_SCB1_CLOCK SCB1
32 PCLK_SCB2_CLOCK SCB2
33 PCLK_SCB3_CLOCK SCB3
34 PCLK_SCB4_CLOCK SCB4
35 PCLK_SCB5_CLOCK SCB5
36 PCLK_SCB6_CLOCK SCB6
37 PCLK_SCB7_CLOCK SCB7
38 PCLK_SCB8_CLOCK SCB8
39 PCLK_SCB9_CLOCK SCB9
40 PCLK_SCB10_CLOCK SCB10
41 PCLK_FLEXRAY0_CLK_FLEXRAY FlexRay0 clock
42 PCLK_PASS0_CLOCK_SAR0 SAR0
43 PCLK_PASS0_CLOCK_SAR1 SAR1
44 PCLK_PASS0_CLOCK_SAR2 SAR2
45 PCLK_TCPWM1_CLOCKS0 TCPWM1 Group #0, Counter #0
46 PCLK_TCPWM1_CLOCKS1 TCPWM1 Group #0, Counter #1
47 PCLK_TCPWM1_CLOCKS2 TCPWM1 Group #0, Counter #2
48 PCLK_TCPWM1_CLOCKS3 TCPWM1 Group #0, Counter #3
49 PCLK_TCPWM1_CLOCKS4 TCPWM1 Group #0, Counter #4
50 PCLK_TCPWM1_CLOCKS5 TCPWM1 Group #0, Counter #5
51 PCLK_TCPWM1_CLOCKS6 TCPWM1 Group #0, Counter #6
52 PCLK_TCPWM1_CLOCKS7 TCPWM1 Group #0, Counter #7
53 PCLK_TCPWM1_CLOCKS8 TCPWM1 Group #0, Counter #8
54 PCLK_TCPWM1_CLOCKS9 TCPWM1 Group #0, Counter #9
55 PCLK_TCPWM1_CLOCKS10 TCPWM1 Group #0, Counter #10
56 PCLK_TCPWM1_CLOCKS11 TCPWM1 Group #0, Counter #11
57 PCLK_TCPWM1_CLOCKS12 TCPWM1 Group #0, Counter #12
58 PCLK_TCPWM1_CLOCKS13 TCPWM1 Group #0, Counter #13
59 PCLK_TCPWM1_CLOCKS14 TCPWM1 Group #0, Counter #14
60 PCLK_TCPWM1_CLOCKS15 TCPWM1 Group #0, Counter #15
61 PCLK_TCPWM1_CLOCKS16 TCPWM1 Group #0, Counter #16
62 PCLK_TCPWM1_CLOCKS17 TCPWM1 Group #0, Counter #17

Datasheet 83 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks

Table 21-1 Peripheral clock assignments (continued)

Output Destination Description
63 PCLK_TCPWM1_CLOCKS18 TCPWM1 Group #0, Counter #18
64 PCLK_TCPWM1_CLOCKS19 TCPWM1 Group #0, Counter #19
65 PCLK_TCPWM1_CLOCKS20 TCPWM1 Group #0, Counter #20
66 PCLK_TCPWM1_CLOCKS21 TCPWM1 Group #0, Counter #21
67 PCLK_TCPWM1_CLOCKS22 TCPWM1 Group #0, Counter #22
68 PCLK_TCPWM1_CLOCKS23 TCPWM1 Group #0, Counter #23
69 PCLK_TCPWM1_CLOCKS24 TCPWM1 Group #0, Counter #24
70 PCLK_TCPWM1_CLOCKS25 TCPWM1 Group #0, Counter #25
71 PCLK_TCPWM1_CLOCKS26 TCPWM1 Group #0, Counter #26
72 PCLK_TCPWM1_CLOCKS27 TCPWM1 Group #0, Counter #27
73 PCLK_TCPWM1_CLOCKS28 TCPWM1 Group #0, Counter #28
74 PCLK_TCPWM1_CLOCKS29 TCPWM1 Group #0, Counter #29
75 PCLK_TCPWM1_CLOCKS30 TCPWM1 Group #0, Counter #30
76 PCLK_TCPWM1_CLOCKS31 TCPWM1 Group #0, Counter #31
77 PCLK_TCPWM1_CLOCKS32 TCPWM1 Group #0, Counter #32
78 PCLK_TCPWM1_CLOCKS33 TCPWM1 Group #0, Counter #33
79 PCLK_TCPWM1_CLOCKS34 TCPWM1 Group #0, Counter #34
80 PCLK_TCPWM1_CLOCKS35 TCPWM1 Group #0, Counter #35
81 PCLK_TCPWM1_CLOCKS36 TCPWM1 Group #0, Counter #36
82 PCLK_TCPWM1_CLOCKS37 TCPWM1 Group #0, Counter #37
83 PCLK_TCPWM1_CLOCKS38 TCPWM1 Group #0, Counter #38
84 PCLK_TCPWM1_CLOCKS39 TCPWM1 Group #0, Counter #39
85 PCLK_TCPWM1_CLOCKS40 TCPWM1 Group #0, Counter #40
86 PCLK_TCPWM1_CLOCKS41 TCPWM1 Group #0, Counter #41
87 PCLK_TCPWM1_CLOCKS42 TCPWM1 Group #0, Counter #42
88 PCLK_TCPWM1_CLOCKS43 TCPWM1 Group #0, Counter #43
89 PCLK_TCPWM1_CLOCKS44 TCPWM1 Group #0, Counter #44
90 PCLK_TCPWM1_CLOCKS45 TCPWM1 Group #0, Counter #45
91 PCLK_TCPWM1_CLOCKS46 TCPWM1 Group #0, Counter #46
92 PCLK_TCPWM1_CLOCKS47 TCPWM1 Group #0, Counter #47
93 PCLK_TCPWM1_CLOCKS48 TCPWM1 Group #0, Counter #48
94 PCLK_TCPWM1_CLOCKS49 TCPWM1 Group #0, Counter #49
95 PCLK_TCPWM1_CLOCKS50 TCPWM1 Group #0, Counter #50
96 PCLK_TCPWM1_CLOCKS51 TCPWM1 Group #0, Counter #51
97 PCLK_TCPWM1_CLOCKS52 TCPWM1 Group #0, Counter #52
98 PCLK_TCPWM1_CLOCKS53 TCPWM1 Group #0, Counter #53
99 PCLK_TCPWM1_CLOCKS54 TCPWM1 Group #0, Counter #54
100 PCLK_TCPWM1_CLOCKS55 TCPWM1 Group #0, Counter #55
101 PCLK_TCPWM1_CLOCKS56 TCPWM1 Group #0, Counter #56
102 PCLK_TCPWM1_CLOCKS57 TCPWM1 Group #0, Counter #57
103 PCLK_TCPWM1_CLOCKS58 TCPWM1 Group #0, Counter #58

Datasheet 84 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks

Table 21-1 Peripheral clock assignments (continued)

Output Destination Description
104 PCLK_TCPWM1_CLOCKS59 TCPWM1 Group #0, Counter #59
105 PCLK_TCPWM1_CLOCKS60 TCPWM1 Group #0, Counter #60
106 PCLK_TCPWM1_CLOCKS61 TCPWM1 Group #0, Counter #61
107 PCLK_TCPWM1_CLOCKS62 TCPWM1 Group #0, Counter #62
108 PCLK_TCPWM1_CLOCKS63 TCPWM1 Group #0, Counter #63
109 PCLK_TCPWM1_CLOCKS64 TCPWM1 Group #0, Counter #64
110 PCLK_TCPWM1_CLOCKS65 TCPWM1 Group #0, Counter #65
111 PCLK_TCPWM1_CLOCKS66 TCPWM1 Group #0, Counter #66
112 PCLK_TCPWM1_CLOCKS67 TCPWM1 Group #0, Counter #67
113 PCLK_TCPWM1_CLOCKS68 TCPWM1 Group #0, Counter #68
114 PCLK_TCPWM1_CLOCKS69 TCPWM1 Group #0, Counter #69
115 PCLK_TCPWM1_CLOCKS70 TCPWM1 Group #0, Counter #70
116 PCLK_TCPWM1_CLOCKS71 TCPWM1 Group #0, Counter #71
117 PCLK_TCPWM1_CLOCKS72 TCPWM1 Group #0, Counter #72
118 PCLK_TCPWM1_CLOCKS73 TCPWM1 Group #0, Counter #73
119 PCLK_TCPWM1_CLOCKS74 TCPWM1 Group #0, Counter #74
120 PCLK_TCPWM1_CLOCKS75 TCPWM1 Group #0, Counter #75
121 PCLK_TCPWM1_CLOCKS76 TCPWM1 Group #0, Counter #76
122 PCLK_TCPWM1_CLOCKS77 TCPWM1 Group #0, Counter #77
123 PCLK_TCPWM1_CLOCKS78 TCPWM1 Group #0, Counter #78
124 PCLK_TCPWM1_CLOCKS79 TCPWM1 Group #0, Counter #79
125 PCLK_TCPWM1_CLOCKS80 TCPWM1 Group #0, Counter #80
126 PCLK_TCPWM1_CLOCKS81 TCPWM1 Group #0, Counter #81
127 PCLK_TCPWM1_CLOCKS82 TCPWM1 Group #0, Counter #82
128 PCLK_TCPWM1_CLOCKS83 TCPWM1 Group #0, Counter #83
129 PCLK_TCPWM1_CLOCKS256 TCPWM1 Group #1, Counter #0
130 PCLK_TCPWM1_CLOCKS257 TCPWM1 Group #1, Counter #1
131 PCLK_TCPWM1_CLOCKS258 TCPWM1 Group #1, Counter #2
132 PCLK_TCPWM1_CLOCKS259 TCPWM1 Group #1, Counter #3
133 PCLK_TCPWM1_CLOCKS260 TCPWM1 Group #1, Counter #4
134 PCLK_TCPWM1_CLOCKS261 TCPWM1 Group #1, Counter #5
135 PCLK_TCPWM1_CLOCKS262 TCPWM1 Group #1, Counter #6
136 PCLK_TCPWM1_CLOCKS263 TCPWM1 Group #1, Counter #7
137 PCLK_TCPWM1_CLOCKS264 TCPWM1 Group #1, Counter #8
138 PCLK_TCPWM1_CLOCKS265 TCPWM1 Group #1, Counter #9
139 PCLK_TCPWM1_CLOCKS266 TCPWM1 Group #1, Counter #10
140 PCLK_TCPWM1_CLOCKS267 TCPWM1 Group #1, Counter #11
141 PCLK_TCPWM1_CLOCKS512 TCPWM1 Group #2, Counter #0
142 PCLK_TCPWM1_CLOCKS513 TCPWM1 Group #2, Counter #1
143 PCLK_TCPWM1_CLOCKS514 TCPWM1 Group #2, Counter #2
144 PCLK_TCPWM1_CLOCKS515 TCPWM1 Group #2, Counter #3

Datasheet 85 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral clocks

Table 21-1 Peripheral clock assignments (continued)

Output Destination Description
145 PCLK_TCPWM1_CLOCKS516 TCPWM1 Group #2, Counter #4
146 PCLK_TCPWM1_CLOCKS517 TCPWM1 Group #2, Counter #5
147 PCLK_TCPWM1_CLOCKS518 TCPWM1 Group #2, Counter #6
148 PCLK_TCPWM1_CLOCKS519 TCPWM1 Group #2, Counter #7
149 PCLK_TCPWM1_CLOCKS520 TCPWM1 Group #2, Counter #8
150 PCLK_TCPWM1_CLOCKS521 TCPWM1 Group #2, Counter #9
151 PCLK_TCPWM1_CLOCKS522 TCPWM1 Group #2, Counter #10
152 PCLK_TCPWM1_CLOCKS523 TCPWM1 Group #2, Counter #11
153 PCLK_TCPWM1_CLOCKS524 TCPWM1 Group #2, Counter #12

Datasheet 86 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Faults

22 Faults
Table 22-1 Fault assignments
Fault Source Description
CM0+ SMPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
0 CPUSS_MPU_VIO_0 DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31]: '0' MPU violation; '1': SMPU violation.
1 CPUSS_MPU_VIO_1 CRYPTO SMPU violation. See CPUSS_MPU_VIO_0 description.
2 CPUSS_MPU_VIO_2 P-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
3 CPUSS_MPU_VIO_3 P-DMA1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
4 CPUSS_MPU_VIO_4 M-DMA0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
5 CPUSS_MPU_VIO_5 SDHC MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
9 CPUSS_MPU_VIO_9 Ethernet0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
10 CPUSS_MPU_VIO_10 Ethernet1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
13 CPUSS_MPU_VIO_13 CM7_1 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
14 CPUSS_MPU_VIO_14 CM7_0 MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
15 CPUSS_MPU_VIO_15 Test Controller MPU/SMPU violation. See CPUSS_MPU_VIO_0 description.
Correctable ECC error in CM7_1 TCM memory
DATA0[23:2]: Violating address.
16 CPUSS_CM7_1_TCM_C_ECC DATA1[7:0]: Syndrome of code word (at address offset 0x0).
DATA1[31:30]: 0= ITCM, 2=D0TCM, 3=D1TCM
Non Correctable ECC error in CM7_1 TCM memory.
17 CPUSS_CM7_1_TCM_NC_ECC
See CPUSS_CM7_1_TCM_C_ECC description.
Correctable ECC error in CM7_0 Cache memories
18 CPUSS_CM7_0_CACHE_C_ECC DATA0[16:2]: location information: Tag/Data SRAM, Way, Index and line Offset, see CM7 UGRM
IEBR0/DEBR0 description for details.
DATA0[31]: 0=Instruction cache, 1= Data cache
Non Correctable ECC error in CM7_0 Cache memories.
19 CPUSS_CM7_0_CACHE_NC_ECC See CPUSS_CM7_0_CACHE_C_ECC description.
Correctable ECC error in CM7_1 Cache memories.
20 CPUSS_CM7_1_CACHE_C_ECC See CPUSS_CM7_0_CACHE_C_ECC description.
Non Correctable ECC error in CM7_1 Cache memories.
21 CPUSS_CM7_1_CACHE_NC_ECC See CPUSS_CM7_0_CACHE_C_ECC description.
P-DMA1 Peripheral Master Interface PPU violation.
25 PERI_MS_VIO_4 See PERI_MS_VIO_0 description.
Peripheral protection SRAM correctable ECC violation
26 PERI_PERI_C_ECC DATA0[10:0]: Violating address.
DATA1[7:0]: Syndrome of SRAM word.
27 PERI_PERI_NC_ECC Peripheral protection SRAM non-correctable ECC violation
CM0+ Peripheral Master Interface PPU violation
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
DATA1[3]: Privileged read.
28 PERI_MS_VIO_0 DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: master interface, PPU violation, “1': timeout detected, “2”: bus error, other:
undefined.
CM7_0 Peripheral Master Interface PPU violation.
29 PERI_MS_VIO_1 See PERI_MS_VIO_0 description.
CM7_1 Peripheral Master Interface PPU violation.
30 PERI_MS_VIO_2 See PERI_MS_VIO_0 description.

Datasheet 87 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Faults

Table 22-1 Fault assignments (continued)

Fault Source Description
P-DMA0 Peripheral Master Interface PPU_3 violation.
31 PERI_MS_VIO_3 See PERI_MS_VIO_0 description.
Peripheral Group #0 violation.
DATA0[31:0]: Violating address.
DATA1[0]: User read.
DATA1[1]: User write.
DATA1[2]: User execute.
32 PERI_GROUP_VIO_0 DATA1[3]: Privileged read.
DATA1[4]: Privileged write.
DATA1[5]: Privileged execute.
DATA1[6]: Non-secure.
DATA1[11:8]: Master identifier.
DATA1[15:12]: Protection context identifier.
DATA1[31:28]: “0”: decoder or peripheral bus error, other: undefined.
33 PERI_GROUP_VIO_1 Peripheral Group #1 violation. See PERI_GROUP_VIO_0 description.
34 PERI_GROUP_VIO_2 Peripheral Group #2 violation. See PERI_GROUP_VIO_0 description.
35 PERI_GROUP_VIO_3 Peripheral Group #3 violation. See PERI_GROUP_VIO_0 description.
36 PERI_GROUP_VIO_4 Peripheral Group #4 violation. See PERI_GROUP_VIO_0 description.
37 PERI_GROUP_VIO_5 Peripheral Group #5 violation. See PERI_GROUP_VIO_0 description.
38 PERI_GROUP_VIO_6 Peripheral Group #6 violation. See PERI_GROUP_VIO_0 description.
40 PERI_GROUP_VIO_8 Peripheral Group #8 violation. See PERI_GROUP_VIO_0 description.
41 PERI_GROUP_VIO_9 Peripheral Group #9 violation. See PERI_GROUP_VIO_0 description.
Flash controller main flash bus error
FAULT_DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit
48 CPUSS_FLASHC_MAIN_BUS_ERR
system address.
FAULT_DATA1[11:8]: Master identifier.
Flash controller main flash correctable ECC violation
DATA[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
49 CPUSS_FLASHC_MAIN_C_ECC DATA1[7:0]: Syndrome of 64-bit word (at address offset 0x00).
DATA1[15:8]: Syndrome of 64-bit word (at address offset 0x08).
DATA1[23:16]: Syndrome of 64-bit word (at address offset 0x10).
DATA1[31:24]: Syndrome of 64-bit word (at address offset 0x18).
Flash controller main flash non-correctable ECC violation.
50 CPUSS_FLASHC_MAIN_NC_ECC
See CPUSS_FLASHC_MAIN_C_ECC description.
Flash controller work-flash bus error.
51 CPUSS_FLASHC_WORK_BUS_ERR
See CPUSS_FLASHC_MAIN_BUS_ERR description.
Flash controller work flash correctable ECC violation.
52 CPUSS_FLASHC_WORK_C_ECC DATA0[26:0]: Violating address. Append 5'b00010 as most significant bits to derive 32-bit system
address.
DATA1[6:0]: Syndrome of 32-bit word.
Flash controller work-flash non-correctable ECC violation.
53 CPUSS_FLASHC_WORK_NC_ECC See CPUSS_FLASHC_WORK_C_ECC description.
Flash controller CM0+ cache correctable ECC violation.
DATA0[26:0]: Violating address.
54 CPUSS_FLASHC_CM0_CA_C_ECC DATA1[6:0]: Syndrome of 32-bit SRAM word (at address offset 0x0).
DATA1[14:8]: Syndrome of 32-bit SRAM word (at address offset 0x4).
DATA1[22:16]: Syndrome of 32-bit SRAM word (at address offset 0x8).
DATA1[30:24]: Syndrome of 32-bit SRAM word (at address offset 0xc).
Flash controller CM0+ cache non-correctable ECC violation.
55 CPUSS_FLASHC_CM0_CA_NC_ECC
See CPUSS_FLASHC_CM0_CA_C_ECC description.
CPU CM7_0 TCM memory correctable ECC violation.
56 CPUSS_CM7_0_TCM_C_ECC
See CPUSS_CM7_1_TCM_C_ECC description.
CPU CM7_0 TCM memory non-correctable ECC violation.
57 CPUSS_CM7_0_TCM_NC_ECC
See CPUSS_CM7_1_TCM_C_ECC description.
System memory controller 0 correctable ECC violation:
58 CPUSS_RAMC0_C_ECC DATA0[31:0]: Violating address.
DATA1[6:0]: Syndrome of 32-bit SRAM code word.

59 CPUSS_RAMC0_NC_ECC System memory controller 0 non-correctable ECC violation.

See CPUSS_RAMC0_C_ECC description.

60 CPUSS_RAMC1_C_ECC System memory controller 1 correctable ECC violation.

See CPUSS_RAMC0_C_ECC description.
System memory controller 1 non-correctable ECC violation.
61 CPUSS_RAMC1_NC_ECC See CPUSS_RAMC0_C_ECC description.

Datasheet 88 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Faults

Table 22-1 Fault assignments (continued)

Fault Source Description
System memory controller 2 correctable ECC violation.
62 CPUSS_RAMC2_C_ECC See CPUSS_RAMC0_C_ECC description.
System memory controller 2 non-correctable ECC violation.
63 CPUSS_RAMC2_NC_ECC See CPUSS_RAMC0_C_ECC description.
Crypto memory correctable ECC violation.
DATA0[31:0]: Violating address.
64 CPUSS_CRYPTO_C_ECC
DATA1[6:0]: Syndrome of Least Significant 32-bit SRAM.
DATA1[14:8]: Syndrome of Most Significant 32-bit SRAM.

65 CPUSS_CRYPTO_NC_ECC CRYPTO memory non-correctable ECC violation.

See CPUSS_CRYPTO_C_ECC description.
P-DMA0 memory correctable ECC violation:
DATA0[11:0]: Violating DW SRAM address
70 CPUSS_DW0_C_ECC
(word address, assuming byte addressable).
DATA1[6:0]: Syndrome of 32-bit SRAM code word.

71 CPUSS_DW0_NC_ECC P-DMA0 memory non-correctable ECC violation.

See CPUSS_DW0_C_ECC description.

72 CPUSS_DW1_C_ECC P-DMA1 memory correctable ECC violation.

See CPUSS_DW0_C_ECC description.

73 CPUSS_DW1_NC_ECC P-DMA1 memory non-correctable ECC violation.

See CPUSS_DW0_C_ECC description.
Flash code storage SRAM memory correctable ECC violation:
74 CPUSS_FM_SRAM_C_ECC DATA0[15:0]: Address location in the eCT Flash SRAM.
DATA1[6:0]: Syndrome of 32-bit SRAM word.
Flash code storage SRAM memory non-correctable ECC violation:
75 CPUSS_FM_SRAM_NC_ECC See CPUSS_FM_SRAMC_C_ECC description.
CAN0 message buffer correctable ECC violation:
DATA0[15:0]: Violating address.
80 CANFD_0_CAN_C_ECC DATA0[22:16]: ECC violating data[38:32] from MRAM.
DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA1[31:0]: ECC violating data[31:0] from MRAM.
CAN0 message buffer non-correctable ECC violation:
DATA0[15:0]: Violating address.
DATA0[22:16]: ECC violating data[38:32] from MRAM (not for Address Error).
81 CANFD_0_CAN_NC_ECC DATA0[27:24]: Master ID: 0-7 = CAN channel ID within mxttcanfd cluster, 8 = AHB I/F
DATA0[30]: Write access, only possible for Address Error
DATA0[31]: Address Error: a CAN channel did an MRAM access above MRAM_SIZE
DATA1[31:0]: ECC violating data[31:0] from MRAM (not for Address Error).

82 CANFD_1_CAN_C_ECC CAN1 message buffer correctable ECC violation.

See CANFD_0_CAN_C_ECC description.

83 CANFD_1_CAN_NC_ECC CAN1 message buffer non-correctable ECC violation.

See CANFD_0_CAN_NC_ECC description.
Consolidated fault output for clock supervisors. Multiple CSV can detect a violation at the same
time.
DATA0[15:0]: CLK_HF* root CSV violation flags.
90 SRSS_FAULT_CSV
DATA0[24]: CLK_REF CSV violation flag (reference clock for CLK_HF CSVs)
DATA0[25]: CLK_LF CSV violation flag
DATA0[26]: CLK_HVILO CSV violation flag
Consolidated fault output for supply supervisors. Multiple CSV can detect a violation at the same
time.
91 SRSS_FAULT_SSV DATA0[0]: BOD on VDDA
DATA[1]: OVD on VDDA
DATA[16]: LVD/HVD #1
DATA0[17]: LVD/HVD #2
Fault output for MCWDT0 (all sub-counters) Multiple counters can detect a violation at the same
time.
DATA0[0]: MCWDT sub counter 0 LOWER_LIMIT
92 SRSS_FAULT_MCWDT0 DATA0[1]: MCWDT sub counter 0 UPPER_LIMIT
DATA0[2]: MCWDT sub counter 1 LOWER_LIMIT
DATA0[3]: MCWDT sub counter 1 UPPER_LIMIT

93 SRSS_FAULT_MCWDT1 Fault output for MCWDT1 (all sub-counters).

See SRSS_FAULT_MCWDT0 description.

94 SRSS_FAULT_MCWDT2 Fault output for MCWDT2 (all sub-counters).

See SRSS_FAULT_MCWDT0 description.

Datasheet 89 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

23 Peripheral protection unit fixed structure pairs

Protection pair is a pair PPU structures, a master, and a slave structure. The master structure protects the slave
structure, and the slave structure protects resources such as peripheral registers, or the peripheral itself.
Table 23-1 PPU fixed structure pairs
Pair No. PPU Fixed Structure Pair Address Size Description
0 PERI_MS_PPU_FX_PERI_MAIN 0x40000200 0x00000040 Peripheral Interconnect main
1 PERI_MS_PPU_FX_PERI_SECURE 0x40002000 0x00000004 Peripheral interconnect secure
2 PERI_MS_PPU_FX_PERI_GR0_GROUP 0x40004010 0x00000004 Peripheral Group #0 main
3 PERI_MS_PPU_FX_PERI_GR1_GROUP 0x40004050 0x00000004 Peripheral Group #1 main
4 PERI_MS_PPU_FX_PERI_GR2_GROUP 0x40004090 0x00000004 Peripheral Group #2 main
5 PERI_MS_PPU_FX_PERI_GR3_GROUP 0x400040C0 0x00000020 Peripheral Group #3 main
6 PERI_MS_PPU_FX_PERI_GR4_GROUP 0x40004100 0x00000020 Peripheral Group #4 main
7 PERI_MS_PPU_FX_PERI_GR5_GROUP 0x40004140 0x00000020 Peripheral Group #5 main
8 PERI_MS_PPU_FX_PERI_GR6_GROUP 0x40004180 0x00000020 Peripheral Group #6 main
9 PERI_MS_PPU_FX_PERI_GR8_GROUP 0x40004200 0x00000020 Peripheral Group #8 main
10 PERI_MS_PPU_FX_PERI_GR9_GROUP 0x40004240 0x00000020 Peripheral Group #9 main
11 PERI_MS_PPU_FX_PERI_GR0_BOOT 0x40004020 0x00000004 Peripheral Group #0 boot
12 PERI_MS_PPU_FX_PERI_GR1_BOOT 0x40004060 0x00000004 Peripheral Group #1 boot
13 PERI_MS_PPU_FX_PERI_GR2_BOOT 0x400040A0 0x00000004 Peripheral Group #2 boot
14 PERI_MS_PPU_FX_PERI_GR3_BOOT 0x400040E0 0x00000004 Peripheral Group #3 boot
15 PERI_MS_PPU_FX_PERI_GR4_BOOT 0x40004120 0x00000004 Peripheral Group #4 boot
16 PERI_MS_PPU_FX_PERI_GR5_BOOT 0x40004160 0x00000004 Peripheral Group #5 boot
17 PERI_MS_PPU_FX_PERI_GR6_BOOT 0x400041A0 0x00000004 Peripheral Group #6 boot
18 PERI_MS_PPU_FX_PERI_GR8_BOOT 0x40004220 0x00000004 Peripheral Group #8 boot
19 PERI_MS_PPU_FX_PERI_GR9_BOOT 0x40004260 0x00000004 Peripheral Group #9 boot
20 PERI_MS_PPU_FX_PERI_TR 0x40008000 0x00008000 Peripheral trigger multiplexer
21 PERI_MS_PPU_FX_PERI_MS_BOOT 0x40030000 0x00001000 Peripheral master slave boot
22 PERI_MS_PPU_FX_PERI_PCLK_MAIN 0x40040000 0x00004000 Peripheral clock main
23 PERI_MS_PPU_FX_CRYPTO_MAIN 0x40100000 0x00000400 Crypto main
24 PERI_MS_PPU_FX_CRYPTO_CRYPTO 0x40101000 0x00000800 Crypto MMIO (Memory Mapped I/O)
25 PERI_MS_PPU_FX_CRYPTO_BOOT 0x40102000 0x00000100 Crypto boot
26 PERI_MS_PPU_FX_CRYPTO_KEY0 0x40102100 0x00000004 Crypto Key #0
27 PERI_MS_PPU_FX_CRYPTO_KEY1 0x40102120 0x00000004 Crypto Key #1
28 PERI_MS_PPU_FX_CRYPTO_BUF 0x40108000 0x00002000 Crypto buffer
29 PERI_MS_PPU_FX_CPUSS_CM7_0 0x40200000 0x00000400 CM7_0 CPU core
30 PERI_MS_PPU_FX_CPUSS_CM7_1 0x40200400 0x00000400 CM7_1 CPU core
31 PERI_MS_PPU_FX_CPUSS_CM0 0x40201000 0x00001000 CM0+ CPU core
32 PERI_MS_PPU_FX_CPUSS_BOOT[34] 0x40202000 0x00000200 CPUSS boot
33 PERI_MS_PPU_FX_CPUSS_CM0_INT 0x40208000 0x00001000 CPUSS CM0+ interrupts
34 PERI_MS_PPU_FX_CPUSS_CM7_0_INT 0x4020A000 0x00001000 CPUSS CM7_0 interrupts
35 PERI_MS_PPU_FX_CPUSS_CM7_1_INT 0x4020C000 0x00001000 CPUSS CM7_1 interrupts
36 PERI_MS_PPU_FX_FAULT_STRUCT0_MAIN 0x40210000 0x00000100 CPUSS Fault Structure #0 main
37 PERI_MS_PPU_FX_FAULT_STRUCT1_MAIN 0x40210100 0x00000100 CPUSS Fault Structure #1 main
38 PERI_MS_PPU_FX_FAULT_STRUCT2_MAIN 0x40210200 0x00000100 CPUSS Fault Structure #2 main
39 PERI_MS_PPU_FX_FAULT_STRUCT3_MAIN 0x40210300 0x00000100 CPUSS Fault Structure #3 main
40 PERI_MS_PPU_FX_IPC_STRUCT0_IPC 0x40220000 0x00000020 CPUSS IPC Structure #0

Datasheet 90 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
41 PERI_MS_PPU_FX_IPC_STRUCT1_IPC 0x40220020 0x00000020 CPUSS IPC Structure #1
42 PERI_MS_PPU_FX_IPC_STRUCT2_IPC 0x40220040 0x00000020 CPUSS IPC Structure #2
43 PERI_MS_PPU_FX_IPC_STRUCT3_IPC 0x40220060 0x00000020 CPUSS IPC Structure #3
44 PERI_MS_PPU_FX_IPC_STRUCT4_IPC 0x40220080 0x00000020 CPUSS IPC Structure #4
45 PERI_MS_PPU_FX_IPC_STRUCT5_IPC 0x402200A0 0x00000020 CPUSS IPC Structure #5
46 PERI_MS_PPU_FX_IPC_STRUCT6_IPC 0x402200C0 0x00000020 CPUSS IPC Structure #6
47 PERI_MS_PPU_FX_IPC_STRUCT7_IPC 0x402200E0 0x00000020 CPUSS IPC Structure #7
48 PERI_MS_PPU_FX_IPC_INTR_STRUCT0_INTR 0x40221000 0x00000010 CPUSS IPC Interrupt Structure #0
49 PERI_MS_PPU_FX_IPC_INTR_STRUCT1_INTR 0x40221020 0x00000010 CPUSS IPC Interrupt Structure #1
50 PERI_MS_PPU_FX_IPC_INTR_STRUCT2_INTR 0x40221040 0x00000010 CPUSS IPC Interrupt Structure #2
51 PERI_MS_PPU_FX_IPC_INTR_STRUCT3_INTR 0x40221060 0x00000010 CPUSS IPC Interrupt Structure #3
52 PERI_MS_PPU_FX_IPC_INTR_STRUCT4_INTR 0x40221080 0x00000010 CPUSS IPC Interrupt Structure #4
53 PERI_MS_PPU_FX_IPC_INTR_STRUCT5_INTR 0x402210A0 0x00000010 CPUSS IPC Interrupt Structure #5
54 PERI_MS_PPU_FX_IPC_INTR_STRUCT6_INTR 0x402210C0 0x00000010 CPUSS IPC Interrupt Structure #6
55 PERI_MS_PPU_FX_IPC_INTR_STRUCT7_INTR 0x402210E0 0x00000010 CPUSS IPC Interrupt Structure #7
56 PERI_MS_PPU_FX_PROT_SMPU_MAIN 0x40230000 0x00000040 Peripheral protection SMPU main
57 PERI_MS_PPU_FX_PROT_MPU0_MAIN 0x40234000 0x00000004 Peripheral protection MPU #0 main
58 PERI_MS_PPU_FX_PROT_MPU5_MAIN 0x40235400 0x00000400 Peripheral protection MPU #5 main
59 PERI_MS_PPU_FX_PROT_MPU9_MAIN 0x40236400 0x00000400 Peripheral protection MPU #9 main
60 PERI_MS_PPU_FX_PROT_MPU10_MAIN 0x40236800 0x00000400 Peripheral protection MPU #10 main
61 PERI_MS_PPU_FX_PROT_MPU13_MAIN 0x40237400 0x00000004 Peripheral protection MPU #13 main
62 PERI_MS_PPU_FX_PROT_MPU14_MAIN 0x40237800 0x00000004 Peripheral protection MPU #14 main
63 PERI_MS_PPU_FX_PROT_MPU15_MAIN 0x40237C00 0x00000400 Peripheral protection MPU #15 main
64 PERI_MS_PPU_FX_FLASHC_MAIN 0x40240000 0x00000008 Flash controller main
65 PERI_MS_PPU_FX_FLASHC_CMD 0x40240008 0x00000004 Flash controller command
66 PERI_MS_PPU_FX_FLASHC_DFT 0x40240200 0x00000100 Flash controller tests
67 PERI_MS_PPU_FX_FLASHC_CM0 0x40240400 0x00000080 Flash controller CM0+
68 PERI_MS_PPU_FX_FLASHC_CM7_0 0x402404E0 0x00000004 Flash controller CM7_0
69 PERI_MS_PPU_FX_FLASHC_CM7_1 0x40240560 0x00000004 Flash controller CM7_1
70 PERI_MS_PPU_FX_FLASHC_CRYPTO 0x40240580 0x00000004 Flash controller Crypto
71 PERI_MS_PPU_FX_FLASHC_DW0 0x40240600 0x00000004 Flash controller P-DMA0
72 PERI_MS_PPU_FX_FLASHC_DW1 0x40240680 0x00000004 Flash controller P-DMA1
73 PERI_MS_PPU_FX_FLASHC_DMAC 0x40240700 0x00000004 Flash controller M-DMA0
74 PERI_MS_PPU_FX_FLASHC_SLOW0 0x40240780 0x00000004 Flash External AHB-Lite Master 0
[34]
75 PERI_MS_PPU_FX_FLASHC_FlashMgmt 0x4024F000 0x00000080 Flash management
76 PERI_MS_PPU_FX_FLASHC_MainSafety 0x4024F400 0x00000008 Flash controller code-flash safety
77 PERI_MS_PPU_FX_FLASHC_WorkSafety 0x4024F500 0x00000004 Flash controller work-flash safety
78 PERI_MS_PPU_FX_SRSS_GENERAL 0x40260000 0x00000400 SRSS General
79 PERI_MS_PPU_FX_SRSS_MAIN 0x40261000 0x00001000 SRSS main
80 PERI_MS_PPU_FX_SRSS_SECURE 0x40262000 0x00002000 SRSS secure
81 PERI_MS_PPU_FX_MCWDT0_CONFIG 0x40268000 0x00000080 MCWDT #0 configuration
82 PERI_MS_PPU_FX_MCWDT1_CONFIG 0x40268100 0x00000080 MCWDT #1 configuration

Note
34.Fixed PPU is configured inside the Boot and user is not allowed to change the attributes of this PPU.

Datasheet 91 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
83 PERI_MS_PPU_FX_MCWDT2_CONFIG 0x40268200 0x00000080 MCWDT #2 configuration
84 PERI_MS_PPU_FX_MCWDT0_MAIN 0x40268080 0x00000040 MCWDT #0 main
85 PERI_MS_PPU_FX_MCWDT1_MAIN 0x40268180 0x00000040 MCWDT #1 main
86 PERI_MS_PPU_FX_MCWDT2_MAIN 0x40268280 0x00000040 MCWDT #2 main
87 PERI_MS_PPU_FX_WDT_CONFIG 0x4026C000 0x00000020 System WDT configuration
88 PERI_MS_PPU_FX_WDT_MAIN 0x4026C040 0x00000020 System WDT main
89 PERI_MS_PPU_FX_BACKUP_BACKUP 0x40270000 0x00010000 SRSS backup
90 PERI_MS_PPU_FX_DW0_DW 0x40280000 0x00000100 P-DMA0 main
91 PERI_MS_PPU_FX_DW1_DW 0x40290000 0x00000100 P-DMA1 main
92 PERI_MS_PPU_FX_DW0_DW_CRC 0x40280100 0x00000080 P-DMA0 CRC
93 PERI_MS_PPU_FX_DW1_DW_CRC 0x40290100 0x00000080 P-DMA1 CRC
94 PERI_MS_PPU_FX_DW0_CH_STRUCT0_CH 0x40288000 0x00000040 P-DMA0 Channel #0
95 PERI_MS_PPU_FX_DW0_CH_STRUCT1_CH 0x40288040 0x00000040 P-DMA0 Channel #1
96 PERI_MS_PPU_FX_DW0_CH_STRUCT2_CH 0x40288080 0x00000040 P-DMA0 Channel #2
97 PERI_MS_PPU_FX_DW0_CH_STRUCT3_CH 0x402880C0 0x00000040 P-DMA0 Channel #3
98 PERI_MS_PPU_FX_DW0_CH_STRUCT4_CH 0x40288100 0x00000040 P-DMA0 Channel #4
99 PERI_MS_PPU_FX_DW0_CH_STRUCT5_CH 0x40288140 0x00000040 P-DMA0 Channel #5
100 PERI_MS_PPU_FX_DW0_CH_STRUCT6_CH 0x40288180 0x00000040 P-DMA0 Channel #6
101 PERI_MS_PPU_FX_DW0_CH_STRUCT7_CH 0x402881C0 0x00000040 P-DMA0 Channel #7
102 PERI_MS_PPU_FX_DW0_CH_STRUCT8_CH 0x40288200 0x00000040 P-DMA0 Channel #8
103 PERI_MS_PPU_FX_DW0_CH_STRUCT9_CH 0x40288240 0x00000040 P-DMA0 Channel #9
104 PERI_MS_PPU_FX_DW0_CH_STRUCT10_CH 0x40288280 0x00000040 P-DMA0 Channel #10
105 PERI_MS_PPU_FX_DW0_CH_STRUCT11_CH 0x402882C0 0x00000040 P-DMA0 Channel #11
106 PERI_MS_PPU_FX_DW0_CH_STRUCT12_CH 0x40288300 0x00000040 P-DMA0 Channel #12
107 PERI_MS_PPU_FX_DW0_CH_STRUCT13_CH 0x40288340 0x00000040 P-DMA0 Channel #13
108 PERI_MS_PPU_FX_DW0_CH_STRUCT14_CH 0x40288380 0x00000040 P-DMA0 Channel #14
109 PERI_MS_PPU_FX_DW0_CH_STRUCT15_CH 0x402883C0 0x00000040 P-DMA0 Channel #15
110 PERI_MS_PPU_FX_DW0_CH_STRUCT16_CH 0x40288400 0x00000040 P-DMA0 Channel #16
111 PERI_MS_PPU_FX_DW0_CH_STRUCT17_CH 0x40288440 0x00000040 P-DMA0 Channel #17
112 PERI_MS_PPU_FX_DW0_CH_STRUCT18_CH 0x40288480 0x00000040 P-DMA0 Channel #18
113 PERI_MS_PPU_FX_DW0_CH_STRUCT19_CH 0x402884C0 0x00000040 P-DMA0 Channel #19
114 PERI_MS_PPU_FX_DW0_CH_STRUCT20_CH 0x40288500 0x00000040 P-DMA0 Channel #20
115 PERI_MS_PPU_FX_DW0_CH_STRUCT21_CH 0x40288540 0x00000040 P-DMA0 Channel #21
116 PERI_MS_PPU_FX_DW0_CH_STRUCT22_CH 0x40288580 0x00000040 P-DMA0 Channel #22
117 PERI_MS_PPU_FX_DW0_CH_STRUCT23_CH 0x402885C0 0x00000040 P-DMA0 Channel #23
118 PERI_MS_PPU_FX_DW0_CH_STRUCT24_CH 0x40288600 0x00000040 P-DMA0 Channel #24
119 PERI_MS_PPU_FX_DW0_CH_STRUCT25_CH 0x40288640 0x00000040 P-DMA0 Channel #25
120 PERI_MS_PPU_FX_DW0_CH_STRUCT26_CH 0x40288680 0x00000040 P-DMA0 Channel #26
121 PERI_MS_PPU_FX_DW0_CH_STRUCT27_CH 0x402886C0 0x00000040 P-DMA0 Channel #27
122 PERI_MS_PPU_FX_DW0_CH_STRUCT28_CH 0x40288700 0x00000040 P-DMA0 Channel #28
123 PERI_MS_PPU_FX_DW0_CH_STRUCT29_CH 0x40288740 0x00000040 P-DMA0 Channel #29
124 PERI_MS_PPU_FX_DW0_CH_STRUCT30_CH 0x40288780 0x00000040 P-DMA0 Channel #30
125 PERI_MS_PPU_FX_DW0_CH_STRUCT31_CH 0x402887C0 0x00000040 P-DMA0 Channel #31
126 PERI_MS_PPU_FX_DW0_CH_STRUCT32_CH 0x40288800 0x00000040 P-DMA0 Channel #32
127 PERI_MS_PPU_FX_DW0_CH_STRUCT33_CH 0x40288840 0x00000040 P-DMA0 Channel #33

Datasheet 92 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
128 PERI_MS_PPU_FX_DW0_CH_STRUCT34_CH 0x40288880 0x00000040 P-DMA0 Channel #34
129 PERI_MS_PPU_FX_DW0_CH_STRUCT35_CH 0x402888C0 0x00000040 P-DMA0 Channel #35
130 PERI_MS_PPU_FX_DW0_CH_STRUCT36_CH 0x40288900 0x00000040 P-DMA0 Channel #36
131 PERI_MS_PPU_FX_DW0_CH_STRUCT37_CH 0x40288940 0x00000040 P-DMA0 Channel #37
132 PERI_MS_PPU_FX_DW0_CH_STRUCT38_CH 0x40288980 0x00000040 P-DMA0 Channel #38
133 PERI_MS_PPU_FX_DW0_CH_STRUCT39_CH 0x402889C0 0x00000040 P-DMA0 Channel #39
134 PERI_MS_PPU_FX_DW0_CH_STRUCT40_CH 0x40288A00 0x00000040 P-DMA0 Channel #40
135 PERI_MS_PPU_FX_DW0_CH_STRUCT41_CH 0x40288A40 0x00000040 P-DMA0 Channel #41
136 PERI_MS_PPU_FX_DW0_CH_STRUCT42_CH 0x40288A80 0x00000040 P-DMA0 Channel #42
137 PERI_MS_PPU_FX_DW0_CH_STRUCT43_CH 0x40288AC0 0x00000040 P-DMA0 Channel #43
138 PERI_MS_PPU_FX_DW0_CH_STRUCT44_CH 0x40288B00 0x00000040 P-DMA0 Channel #44
139 PERI_MS_PPU_FX_DW0_CH_STRUCT45_CH 0x40288B40 0x00000040 P-DMA0 Channel #45
140 PERI_MS_PPU_FX_DW0_CH_STRUCT46_CH 0x40288B80 0x00000040 P-DMA0 Channel #46
141 PERI_MS_PPU_FX_DW0_CH_STRUCT47_CH 0x40288BC0 0x00000040 P-DMA0 Channel #47
142 PERI_MS_PPU_FX_DW0_CH_STRUCT48_CH 0x40288C00 0x00000040 P-DMA0 Channel #48
143 PERI_MS_PPU_FX_DW0_CH_STRUCT49_CH 0x40288C40 0x00000040 P-DMA0 Channel #49
144 PERI_MS_PPU_FX_DW0_CH_STRUCT50_CH 0x40288C80 0x00000040 P-DMA0 Channel #50
145 PERI_MS_PPU_FX_DW0_CH_STRUCT51_CH 0x40288CC0 0x00000040 P-DMA0 Channel #51
146 PERI_MS_PPU_FX_DW0_CH_STRUCT52_CH 0x40288D00 0x00000040 P-DMA0 Channel #52
147 PERI_MS_PPU_FX_DW0_CH_STRUCT53_CH 0x40288D40 0x00000040 P-DMA0 Channel #53
148 PERI_MS_PPU_FX_DW0_CH_STRUCT54_CH 0x40288D80 0x00000040 P-DMA0 Channel #54
149 PERI_MS_PPU_FX_DW0_CH_STRUCT55_CH 0x40288DC0 0x00000040 P-DMA0 Channel #55
150 PERI_MS_PPU_FX_DW0_CH_STRUCT56_CH 0x40288E00 0x00000040 P-DMA0 Channel #56
151 PERI_MS_PPU_FX_DW0_CH_STRUCT57_CH 0x40288E40 0x00000040 P-DMA0 Channel #57
152 PERI_MS_PPU_FX_DW0_CH_STRUCT58_CH 0x40288E80 0x00000040 P-DMA0 Channel #58
153 PERI_MS_PPU_FX_DW0_CH_STRUCT59_CH 0x40288EC0 0x00000040 P-DMA0 Channel #59
154 PERI_MS_PPU_FX_DW0_CH_STRUCT60_CH 0x40288F00 0x00000040 P-DMA0 Channel #60
155 PERI_MS_PPU_FX_DW0_CH_STRUCT61_CH 0x40288F40 0x00000040 P-DMA0 Channel #61
156 PERI_MS_PPU_FX_DW0_CH_STRUCT62_CH 0x40288F80 0x00000040 P-DMA0 Channel #62
157 PERI_MS_PPU_FX_DW0_CH_STRUCT63_CH 0x40288FC0 0x00000040 P-DMA0 Channel #63
158 PERI_MS_PPU_FX_DW0_CH_STRUCT64_CH 0x40289000 0x00000040 P-DMA0 Channel #64
159 PERI_MS_PPU_FX_DW0_CH_STRUCT65_CH 0x40289040 0x00000040 P-DMA0 Channel #65
160 PERI_MS_PPU_FX_DW0_CH_STRUCT66_CH 0x40289080 0x00000040 P-DMA0 Channel #66
161 PERI_MS_PPU_FX_DW0_CH_STRUCT67_CH 0x402890C0 0x00000040 P-DMA0 Channel #67
162 PERI_MS_PPU_FX_DW0_CH_STRUCT68_CH 0x40289100 0x00000040 P-DMA0 Channel #68
163 PERI_MS_PPU_FX_DW0_CH_STRUCT69_CH 0x40289140 0x00000040 P-DMA0 Channel #69
164 PERI_MS_PPU_FX_DW0_CH_STRUCT70_CH 0x40289180 0x00000040 P-DMA0 Channel #70
165 PERI_MS_PPU_FX_DW0_CH_STRUCT71_CH 0x402891C0 0x00000040 P-DMA0 Channel #71
166 PERI_MS_PPU_FX_DW0_CH_STRUCT72_CH 0x40289200 0x00000040 P-DMA0 Channel #72
167 PERI_MS_PPU_FX_DW0_CH_STRUCT73_CH 0x40289240 0x00000040 P-DMA0 Channel #73
168 PERI_MS_PPU_FX_DW0_CH_STRUCT74_CH 0x40289280 0x00000040 P-DMA0 Channel #74
169 PERI_MS_PPU_FX_DW0_CH_STRUCT75_CH 0x402892C0 0x00000040 P-DMA0 Channel #75
170 PERI_MS_PPU_FX_DW0_CH_STRUCT76_CH 0x40289300 0x00000040 P-DMA0 Channel #76
171 PERI_MS_PPU_FX_DW0_CH_STRUCT77_CH 0x40289340 0x00000040 P-DMA0 Channel #77
172 PERI_MS_PPU_FX_DW0_CH_STRUCT78_CH 0x40289380 0x00000040 P-DMA0 Channel #78

Datasheet 93 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
173 PERI_MS_PPU_FX_DW0_CH_STRUCT79_CH 0x402893C0 0x00000040 P-DMA0 Channel #79
174 PERI_MS_PPU_FX_DW0_CH_STRUCT80_CH 0x40289400 0x00000040 P-DMA0 Channel #80
175 PERI_MS_PPU_FX_DW0_CH_STRUCT81_CH 0x40289440 0x00000040 P-DMA0 Channel #81
176 PERI_MS_PPU_FX_DW0_CH_STRUCT82_CH 0x40289480 0x00000040 P-DMA0 Channel #82
177 PERI_MS_PPU_FX_DW0_CH_STRUCT83_CH 0x402894C0 0x00000040 P-DMA0 Channel #83
178 PERI_MS_PPU_FX_DW0_CH_STRUCT84_CH 0x40289500 0x00000040 P-DMA0 Channel #84
179 PERI_MS_PPU_FX_DW0_CH_STRUCT85_CH 0x40289540 0x00000040 P-DMA0 Channel #85
180 PERI_MS_PPU_FX_DW0_CH_STRUCT86_CH 0x40289580 0x00000040 P-DMA0 Channel #86
181 PERI_MS_PPU_FX_DW0_CH_STRUCT87_CH 0x402895C0 0x00000040 P-DMA0 Channel #87
182 PERI_MS_PPU_FX_DW0_CH_STRUCT88_CH 0x40289600 0x00000040 P-DMA0 Channel #88
183 PERI_MS_PPU_FX_DW0_CH_STRUCT89_CH 0x40289640 0x00000040 P-DMA0 Channel #89
184 PERI_MS_PPU_FX_DW0_CH_STRUCT90_CH 0x40289680 0x00000040 P-DMA0 Channel #90
185 PERI_MS_PPU_FX_DW0_CH_STRUCT91_CH 0x402896C0 0x00000040 P-DMA0 Channel #91
186 PERI_MS_PPU_FX_DW0_CH_STRUCT92_CH 0x40289700 0x00000040 P-DMA0 Channel #92
187 PERI_MS_PPU_FX_DW0_CH_STRUCT93_CH 0x40289740 0x00000040 P-DMA0 Channel #93
188 PERI_MS_PPU_FX_DW0_CH_STRUCT94_CH 0x40289780 0x00000040 P-DMA0 Channel #94
189 PERI_MS_PPU_FX_DW0_CH_STRUCT95_CH 0x402897C0 0x00000040 P-DMA0 Channel #95
190 PERI_MS_PPU_FX_DW0_CH_STRUCT96_CH 0x40289800 0x00000040 P-DMA0 Channel #96
191 PERI_MS_PPU_FX_DW0_CH_STRUCT97_CH 0x40289840 0x00000040 P-DMA0 Channel #97
192 PERI_MS_PPU_FX_DW0_CH_STRUCT98_CH 0x40289880 0x00000040 P-DMA0 Channel #98
193 PERI_MS_PPU_FX_DW0_CH_STRUCT99_CH 0x402898C0 0x00000040 P-DMA0 Channel #99
194 PERI_MS_PPU_FX_DW0_CH_STRUCT100_CH 0x40289900 0x00000040 P-DMA0 Channel #100
195 PERI_MS_PPU_FX_DW0_CH_STRUCT101_CH 0x40289940 0x00000040 P-DMA0 Channel #101
196 PERI_MS_PPU_FX_DW0_CH_STRUCT102_CH 0x40289980 0x00000040 P-DMA0 Channel #102
197 PERI_MS_PPU_FX_DW0_CH_STRUCT103_CH 0x402899C0 0x00000040 P-DMA0 Channel #103
198 PERI_MS_PPU_FX_DW0_CH_STRUCT104_CH 0x40289A00 0x00000040 P-DMA0 Channel #104
199 PERI_MS_PPU_FX_DW0_CH_STRUCT105_CH 0x40289A40 0x00000040 P-DMA0 Channel #105
200 PERI_MS_PPU_FX_DW0_CH_STRUCT106_CH 0x40289A80 0x00000040 P-DMA0 Channel #106
201 PERI_MS_PPU_FX_DW0_CH_STRUCT107_CH 0x40289AC0 0x00000040 P-DMA0 Channel #107
202 PERI_MS_PPU_FX_DW0_CH_STRUCT108_CH 0x40289B00 0x00000040 P-DMA0 Channel #108
203 PERI_MS_PPU_FX_DW0_CH_STRUCT109_CH 0x40289B40 0x00000040 P-DMA0 Channel #109
204 PERI_MS_PPU_FX_DW0_CH_STRUCT110_CH 0x40289B80 0x00000040 P-DMA0 Channel #110
205 PERI_MS_PPU_FX_DW0_CH_STRUCT111_CH 0x40289BC0 0x00000040 P-DMA0 Channel #111
206 PERI_MS_PPU_FX_DW0_CH_STRUCT112_CH 0x40289C00 0x00000040 P-DMA0 Channel #112
207 PERI_MS_PPU_FX_DW0_CH_STRUCT113_CH 0x40289C40 0x00000040 P-DMA0 Channel #113
208 PERI_MS_PPU_FX_DW0_CH_STRUCT114_CH 0x40289C80 0x00000040 P-DMA0 Channel #114
209 PERI_MS_PPU_FX_DW0_CH_STRUCT115_CH 0x40289CC0 0x00000040 P-DMA0 Channel #115
210 PERI_MS_PPU_FX_DW0_CH_STRUCT116_CH 0x40289D00 0x00000040 P-DMA0 Channel #116
211 PERI_MS_PPU_FX_DW0_CH_STRUCT117_CH 0x40289D40 0x00000040 P-DMA0 Channel #117
212 PERI_MS_PPU_FX_DW0_CH_STRUCT118_CH 0x40289D80 0x00000040 P-DMA0 Channel #118
213 PERI_MS_PPU_FX_DW0_CH_STRUCT119_CH 0x40289DC0 0x00000040 P-DMA0 Channel #119
214 PERI_MS_PPU_FX_DW0_CH_STRUCT120_CH 0x40289E00 0x00000040 P-DMA0 Channel #120
215 PERI_MS_PPU_FX_DW0_CH_STRUCT121_CH 0x40289E40 0x00000040 P-DMA0 Channel #121
216 PERI_MS_PPU_FX_DW0_CH_STRUCT122_CH 0x40289E80 0x00000040 P-DMA0 Channel #122
217 PERI_MS_PPU_FX_DW0_CH_STRUCT123_CH 0x40289EC0 0x00000040 P-DMA0 Channel #123

Datasheet 94 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
218 PERI_MS_PPU_FX_DW0_CH_STRUCT124_CH 0x40289F00 0x00000040 P-DMA0 Channel #124
219 PERI_MS_PPU_FX_DW0_CH_STRUCT125_CH 0x40289F40 0x00000040 P-DMA0 Channel #125
220 PERI_MS_PPU_FX_DW0_CH_STRUCT126_CH 0x40289F80 0x00000040 P-DMA0 Channel #126
221 PERI_MS_PPU_FX_DW0_CH_STRUCT127_CH 0x40289FC0 0x00000040 P-DMA0 Channel #127
222 PERI_MS_PPU_FX_DW0_CH_STRUCT128_CH 0x4028A000 0x00000040 P-DMA0 Channel #128
223 PERI_MS_PPU_FX_DW0_CH_STRUCT129_CH 0x4028A040 0x00000040 P-DMA0 Channel #129
224 PERI_MS_PPU_FX_DW0_CH_STRUCT130_CH 0x4028A080 0x00000040 P-DMA0 Channel #130
225 PERI_MS_PPU_FX_DW0_CH_STRUCT131_CH 0x4028A0C0 0x00000040 P-DMA0 Channel #131
226 PERI_MS_PPU_FX_DW0_CH_STRUCT132_CH 0x4028A100 0x00000040 P-DMA0 Channel #132
227 PERI_MS_PPU_FX_DW0_CH_STRUCT133_CH 0x4028A140 0x00000040 P-DMA0 Channel #133
228 PERI_MS_PPU_FX_DW0_CH_STRUCT134_CH 0x4028A180 0x00000040 P-DMA0 Channel #134
229 PERI_MS_PPU_FX_DW0_CH_STRUCT135_CH 0x4028A1C0 0x00000040 P-DMA0 Channel #135
230 PERI_MS_PPU_FX_DW0_CH_STRUCT136_CH 0x4028A200 0x00000040 P-DMA0 Channel #136
231 PERI_MS_PPU_FX_DW0_CH_STRUCT137_CH 0x4028A240 0x00000040 P-DMA0 Channel #137
232 PERI_MS_PPU_FX_DW0_CH_STRUCT138_CH 0x4028A280 0x00000040 P-DMA0 Channel #138
233 PERI_MS_PPU_FX_DW0_CH_STRUCT139_CH 0x4028A2C0 0x00000040 P-DMA0 Channel #139
234 PERI_MS_PPU_FX_DW0_CH_STRUCT140_CH 0x4028A300 0x00000040 P-DMA0 Channel #140
235 PERI_MS_PPU_FX_DW0_CH_STRUCT141_CH 0x4028A340 0x00000040 P-DMA0 Channel #141
236 PERI_MS_PPU_FX_DW0_CH_STRUCT142_CH 0x4028A380 0x00000040 P-DMA0 Channel #142
237 PERI_MS_PPU_FX_DW1_CH_STRUCT0_CH 0x40298000 0x00000040 P-DMA1 Channel #0
238 PERI_MS_PPU_FX_DW1_CH_STRUCT1_CH 0x40298040 0x00000040 P-DMA1 Channel #1
239 PERI_MS_PPU_FX_DW1_CH_STRUCT2_CH 0x40298080 0x00000040 P-DMA1 Channel #2
240 PERI_MS_PPU_FX_DW1_CH_STRUCT3_CH 0x402980C0 0x00000040 P-DMA1 Channel #3
241 PERI_MS_PPU_FX_DW1_CH_STRUCT4_CH 0x40298100 0x00000040 P-DMA1 Channel #4
242 PERI_MS_PPU_FX_DW1_CH_STRUCT5_CH 0x40298140 0x00000040 P-DMA1 Channel #5
243 PERI_MS_PPU_FX_DW1_CH_STRUCT6_CH 0x40298180 0x00000040 P-DMA1 Channel #6
244 PERI_MS_PPU_FX_DW1_CH_STRUCT7_CH 0x402981C0 0x00000040 P-DMA1 Channel #7
245 PERI_MS_PPU_FX_DW1_CH_STRUCT8_CH 0x40298200 0x00000040 P-DMA1 Channel #8
246 PERI_MS_PPU_FX_DW1_CH_STRUCT9_CH 0x40298240 0x00000040 P-DMA1 Channel #9
247 PERI_MS_PPU_FX_DW1_CH_STRUCT10_CH 0x40298280 0x00000040 P-DMA1 Channel #10
248 PERI_MS_PPU_FX_DW1_CH_STRUCT11_CH 0x402982C0 0x00000040 P-DMA1 Channel #11
249 PERI_MS_PPU_FX_DW1_CH_STRUCT12_CH 0x40298300 0x00000040 P-DMA1 Channel #12
250 PERI_MS_PPU_FX_DW1_CH_STRUCT13_CH 0x40298340 0x00000040 P-DMA1 Channel #13
251 PERI_MS_PPU_FX_DW1_CH_STRUCT14_CH 0x40298380 0x00000040 P-DMA1 Channel #14
252 PERI_MS_PPU_FX_DW1_CH_STRUCT15_CH 0x402983C0 0x00000040 P-DMA1 Channel #15
253 PERI_MS_PPU_FX_DW1_CH_STRUCT16_CH 0x40298400 0x00000040 P-DMA1 Channel #16
254 PERI_MS_PPU_FX_DW1_CH_STRUCT17_CH 0x40298440 0x00000040 P-DMA1 Channel #17
255 PERI_MS_PPU_FX_DW1_CH_STRUCT18_CH 0x40298480 0x00000040 P-DMA1 Channel #18
256 PERI_MS_PPU_FX_DW1_CH_STRUCT19_CH 0x402984C0 0x00000040 P-DMA1 Channel #19
257 PERI_MS_PPU_FX_DW1_CH_STRUCT20_CH 0x40298500 0x00000040 P-DMA1 Channel #20
258 PERI_MS_PPU_FX_DW1_CH_STRUCT21_CH 0x40298540 0x00000040 P-DMA1 Channel #21
259 PERI_MS_PPU_FX_DW1_CH_STRUCT22_CH 0x40298580 0x00000040 P-DMA1 Channel #22
260 PERI_MS_PPU_FX_DW1_CH_STRUCT23_CH 0x402985C0 0x00000040 P-DMA1 Channel #23
261 PERI_MS_PPU_FX_DW1_CH_STRUCT24_CH 0x40298600 0x00000040 P-DMA1 Channel #24
262 PERI_MS_PPU_FX_DW1_CH_STRUCT25_CH 0x40298640 0x00000040 P-DMA1 Channel #25

Datasheet 95 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
263 PERI_MS_PPU_FX_DW1_CH_STRUCT26_CH 0x40298680 0x00000040 P-DMA1 Channel #26
264 PERI_MS_PPU_FX_DW1_CH_STRUCT27_CH 0x402986C0 0x00000040 P-DMA1 Channel #27
265 PERI_MS_PPU_FX_DW1_CH_STRUCT28_CH 0x40298700 0x00000040 P-DMA1 Channel #28
266 PERI_MS_PPU_FX_DW1_CH_STRUCT29_CH 0x40298740 0x00000040 P-DMA1 Channel #29
267 PERI_MS_PPU_FX_DW1_CH_STRUCT30_CH 0x40298780 0x00000040 P-DMA1 Channel #30
268 PERI_MS_PPU_FX_DW1_CH_STRUCT31_CH 0x402987C0 0x00000040 P-DMA1 Channel #31
269 PERI_MS_PPU_FX_DW1_CH_STRUCT32_CH 0x40298800 0x00000040 P-DMA1 Channel #32
270 PERI_MS_PPU_FX_DW1_CH_STRUCT33_CH 0x40298840 0x00000040 P-DMA1 Channel #33
271 PERI_MS_PPU_FX_DW1_CH_STRUCT34_CH 0x40298880 0x00000040 P-DMA1 Channel #34
272 PERI_MS_PPU_FX_DW1_CH_STRUCT35_CH 0x402988C0 0x00000040 P-DMA1 Channel #35
273 PERI_MS_PPU_FX_DW1_CH_STRUCT36_CH 0x40298900 0x00000040 P-DMA1 Channel #36
274 PERI_MS_PPU_FX_DW1_CH_STRUCT37_CH 0x40298940 0x00000040 P-DMA1 Channel #37
275 PERI_MS_PPU_FX_DW1_CH_STRUCT38_CH 0x40298980 0x00000040 P-DMA1 Channel #38
276 PERI_MS_PPU_FX_DW1_CH_STRUCT39_CH 0x402989C0 0x00000040 P-DMA1 Channel #39
277 PERI_MS_PPU_FX_DW1_CH_STRUCT40_CH 0x40298A00 0x00000040 P-DMA1 Channel #40
278 PERI_MS_PPU_FX_DW1_CH_STRUCT41_CH 0x40298A40 0x00000040 P-DMA1 Channel #41
279 PERI_MS_PPU_FX_DW1_CH_STRUCT42_CH 0x40298A80 0x00000040 P-DMA1 Channel #42
280 PERI_MS_PPU_FX_DW1_CH_STRUCT43_CH 0x40298AC0 0x00000040 P-DMA1 Channel #43
281 PERI_MS_PPU_FX_DW1_CH_STRUCT44_CH 0x40298B00 0x00000040 P-DMA1 Channel #44
282 PERI_MS_PPU_FX_DW1_CH_STRUCT45_CH 0x40298B40 0x00000040 P-DMA1 Channel #45
283 PERI_MS_PPU_FX_DW1_CH_STRUCT46_CH 0x40298B80 0x00000040 P-DMA1 Channel #46
284 PERI_MS_PPU_FX_DW1_CH_STRUCT47_CH 0x40298BC0 0x00000040 P-DMA1 Channel #47
285 PERI_MS_PPU_FX_DW1_CH_STRUCT48_CH 0x40298C00 0x00000040 P-DMA1 Channel #48
286 PERI_MS_PPU_FX_DW1_CH_STRUCT49_CH 0x40298C40 0x00000040 P-DMA1 Channel #49
287 PERI_MS_PPU_FX_DW1_CH_STRUCT50_CH 0x40298C80 0x00000040 P-DMA1 Channel #50
288 PERI_MS_PPU_FX_DW1_CH_STRUCT51_CH 0x40298CC0 0x00000040 P-DMA1 Channel #51
289 PERI_MS_PPU_FX_DW1_CH_STRUCT52_CH 0x40298D00 0x00000040 P-DMA1 Channel #52
290 PERI_MS_PPU_FX_DW1_CH_STRUCT53_CH 0x40298D40 0x00000040 P-DMA1 Channel #53
291 PERI_MS_PPU_FX_DW1_CH_STRUCT54_CH 0x40298D80 0x00000040 P-DMA1 Channel #54
292 PERI_MS_PPU_FX_DW1_CH_STRUCT55_CH 0x40298DC0 0x00000040 P-DMA1 Channel #55
293 PERI_MS_PPU_FX_DW1_CH_STRUCT56_CH 0x40298E00 0x00000040 P-DMA1 Channel #56
294 PERI_MS_PPU_FX_DW1_CH_STRUCT57_CH 0x40298E40 0x00000040 P-DMA1 Channel #57
295 PERI_MS_PPU_FX_DW1_CH_STRUCT58_CH 0x40298E80 0x00000040 P-DMA1 Channel #58
296 PERI_MS_PPU_FX_DW1_CH_STRUCT59_CH 0x40298EC0 0x00000040 P-DMA1 Channel #59
297 PERI_MS_PPU_FX_DW1_CH_STRUCT60_CH 0x40298F00 0x00000040 P-DMA1 Channel #60
298 PERI_MS_PPU_FX_DW1_CH_STRUCT61_CH 0x40298F40 0x00000040 P-DMA1 Channel #61
299 PERI_MS_PPU_FX_DW1_CH_STRUCT62_CH 0x40298F80 0x00000040 P-DMA1 Channel #62
300 PERI_MS_PPU_FX_DW1_CH_STRUCT63_CH 0x40298FC0 0x00000040 P-DMA1 Channel #63
301 PERI_MS_PPU_FX_DW1_CH_STRUCT64_CH 0x40299000 0x00000040 P-DMA1 Channel #64
302 PERI_MS_PPU_FX_DMAC_TOP 0x402A0000 0x00000010 M-DMA0 main
303 PERI_MS_PPU_FX_DMAC_CH0_CH 0x402A1000 0x00000100 M-DMA0 Channel #0
304 PERI_MS_PPU_FX_DMAC_CH1_CH 0x402A1100 0x00000100 M-DMA0 Channel #1
305 PERI_MS_PPU_FX_DMAC_CH2_CH 0x402A1200 0x00000100 M-DMA0 Channel #2
306 PERI_MS_PPU_FX_DMAC_CH3_CH 0x402A1300 0x00000100 M-DMA0 Channel #3
307 PERI_MS_PPU_FX_DMAC_CH4_CH 0x402A1400 0x00000100 M-DMA0 Channel #4

Datasheet 96 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
308 PERI_MS_PPU_FX_DMAC_CH5_CH 0x402A1500 0x00000100 M-DMA0 Channel #5
309 PERI_MS_PPU_FX_DMAC_CH6_CH 0x402A1600 0x00000100 M-DMA0 Channel #6
310 PERI_MS_PPU_FX_DMAC_CH7_CH 0x402A1700 0x00000100 M-DMA0 Channel #7
311 PERI_MS_PPU_FX_EFUSE_CTL 0x402C0000 0x00000200 EFUSE control
312 PERI_MS_PPU_FX_EFUSE_DATA 0x402C0800 0x00000200 EFUSE data
313 PERI_MS_PPU_FX_BIST 0x402F0000 0x00001000 Built-in self test
314 PERI_MS_PPU_FX_HSIOM_PRT0_PRT 0x40300000 0x00000008 HSIOm Port #0
315 PERI_MS_PPU_FX_HSIOM_PRT1_PRT 0x40300010 0x00000008 HSIOm Port #1
316 PERI_MS_PPU_FX_HSIOM_PRT2_PRT 0x40300020 0x00000008 HSIOm Port #2
317 PERI_MS_PPU_FX_HSIOM_PRT3_PRT 0x40300030 0x00000008 HSIOm Port #3
318 PERI_MS_PPU_FX_HSIOM_PRT4_PRT 0x40300040 0x00000008 HSIOm Port #4
319 PERI_MS_PPU_FX_HSIOM_PRT5_PRT 0x40300050 0x00000008 HSIOm Port #5
320 PERI_MS_PPU_FX_HSIOM_PRT6_PRT 0x40300060 0x00000008 HSIOm Port #6
321 PERI_MS_PPU_FX_HSIOM_PRT7_PRT 0x40300070 0x00000008 HSIOm Port #7
322 PERI_MS_PPU_FX_HSIOM_PRT8_PRT 0x40300080 0x00000008 HSIOm Port #8
323 PERI_MS_PPU_FX_HSIOM_PRT9_PRT 0x40300090 0x00000008 HSIOm Port #9
324 PERI_MS_PPU_FX_HSIOM_PRT10_PRT 0x403000A0 0x00000008 HSIOm Port #10
325 PERI_MS_PPU_FX_HSIOM_PRT11_PRT 0x403000B0 0x00000008 HSIOm Port #11
326 PERI_MS_PPU_FX_HSIOM_PRT12_PRT 0x403000C0 0x00000008 HSIOm Port #12
327 PERI_MS_PPU_FX_HSIOM_PRT13_PRT 0x403000D0 0x00000008 HSIOm Port #13
328 PERI_MS_PPU_FX_HSIOM_PRT14_PRT 0x403000E0 0x00000008 HSIOm Port #14
329 PERI_MS_PPU_FX_HSIOM_PRT15_PRT 0x403000F0 0x00000008 HSIOm Port #15
330 PERI_MS_PPU_FX_HSIOM_PRT16_PRT 0x40300100 0x00000008 HSIOm Port #16
331 PERI_MS_PPU_FX_HSIOM_PRT17_PRT 0x40300110 0x00000008 HSIOm Port #17
332 PERI_MS_PPU_FX_HSIOM_PRT18_PRT 0x40300120 0x00000008 HSIOm Port #18
333 PERI_MS_PPU_FX_HSIOM_PRT19_PRT 0x40300130 0x00000008 HSIOm Port #19
334 PERI_MS_PPU_FX_HSIOM_PRT20_PRT 0x40300140 0x00000008 HSIOm Port #20
335 PERI_MS_PPU_FX_HSIOM_PRT21_PRT 0x40300150 0x00000008 HSIOm Port #21
336 PERI_MS_PPU_FX_HSIOM_PRT22_PRT 0x40300160 0x00000008 HSIOm Port #22
337 PERI_MS_PPU_FX_HSIOM_PRT23_PRT 0x40300170 0x00000008 HSIOm Port #23
338 PERI_MS_PPU_FX_HSIOM_PRT24_PRT 0x40300180 0x00000008 HSIOm Port #24
339 PERI_MS_PPU_FX_HSIOM_PRT25_PRT 0x40300190 0x00000008 HSIOm Port #25
340 PERI_MS_PPU_FX_HSIOM_PRT26_PRT 0x403001A0 0x00000008 HSIOm Port #26
341 PERI_MS_PPU_FX_HSIOM_PRT27_PRT 0x403001B0 0x00000008 HSIOm Port #27
342 PERI_MS_PPU_FX_HSIOM_PRT28_PRT 0x403001C0 0x00000008 HSIOm Port #28
343 PERI_MS_PPU_FX_HSIOM_PRT29_PRT 0x403001D0 0x00000008 HSIOm Port #29
344 PERI_MS_PPU_FX_HSIOM_PRT30_PRT 0x403001E0 0x00000008 HSIOm Port #30
345 PERI_MS_PPU_FX_HSIOM_PRT31_PRT 0x403001F0 0x00000008 HSIOm Port #31
346 PERI_MS_PPU_FX_HSIOM_PRT32_PRT 0x40300200 0x00000008 HSIOm Port #32
347 PERI_MS_PPU_FX_HSIOM_PRT33_PRT 0x40300210 0x00000008 HSIOm Port #33
348 PERI_MS_PPU_FX_HSIOM_PRT34_PRT 0x40300220 0x00000008 HSIOm Port #34
349 PERI_MS_PPU_FX_HSIOM_AMUX 0x40302000 0x00000010 HSIOm Analog multiplexer
350 PERI_MS_PPU_FX_HSIOM_MON 0x40302200 0x00000010 HSIOm monitor
351 PERI_MS_PPU_FX_HSIOM_ALTJTAG 0x40302240 0x00000004 HSIOm Alternate JTAG
352 PERI_MS_PPU_FX_GPIO_PRT0_PRT 0x40310000 0x00000040 GPIO_ENH Port #0

Datasheet 97 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
353 PERI_MS_PPU_FX_GPIO_PRT1_PRT 0x40310080 0x00000040 GPIO_STD Port #1
354 PERI_MS_PPU_FX_GPIO_PRT2_PRT 0x40310100 0x00000040 GPIO_STD Port #2
355 PERI_MS_PPU_FX_GPIO_PRT3_PRT 0x40310180 0x00000040 GPIO_STD Port #3
356 PERI_MS_PPU_FX_GPIO_PRT4_PRT 0x40310200 0x00000040 GPIO_STD Port #4
357 PERI_MS_PPU_FX_GPIO_PRT5_PRT 0x40310280 0x00000040 GPIO_STD Port #5
358 PERI_MS_PPU_FX_GPIO_PRT6_PRT 0x40310300 0x00000040 GPIO_STD Port #6
359 PERI_MS_PPU_FX_GPIO_PRT7_PRT 0x40310380 0x00000040 GPIO_STD Port #7
360 PERI_MS_PPU_FX_GPIO_PRT8_PRT 0x40310400 0x00000040 GPIO_STD Port #8
361 PERI_MS_PPU_FX_GPIO_PRT9_PRT 0x40310480 0x00000040 GPIO_STD Port #9
362 PERI_MS_PPU_FX_GPIO_PRT10_PRT 0x40310500 0x00000040 GPIO_STD Port #10
363 PERI_MS_PPU_FX_GPIO_PRT11_PRT 0x40310580 0x00000040 GPIO_STD Port #11
364 PERI_MS_PPU_FX_GPIO_PRT12_PRT 0x40310600 0x00000040 GPIO_STD Port #12
365 PERI_MS_PPU_FX_GPIO_PRT13_PRT 0x40310680 0x00000040 GPIO_STD Port #13
366 PERI_MS_PPU_FX_GPIO_PRT14_PRT 0x40310700 0x00000040 GPIO_STD Port #14
367 PERI_MS_PPU_FX_GPIO_PRT15_PRT 0x40310780 0x00000040 GPIO_STD Port #15
368 PERI_MS_PPU_FX_GPIO_PRT16_PRT 0x40310800 0x00000040 GPIO_STD Port #16
369 PERI_MS_PPU_FX_GPIO_PRT17_PRT 0x40310880 0x00000040 GPIO_STD Port #17
370 PERI_MS_PPU_FX_GPIO_PRT18_PRT 0x40310900 0x00000040 GPIO_STD Port #18
371 PERI_MS_PPU_FX_GPIO_PRT19_PRT 0x40310980 0x00000040 GPIO_STD Port #19
372 PERI_MS_PPU_FX_GPIO_PRT20_PRT 0x40310A00 0x00000040 GPIO_STD Port #20
373 PERI_MS_PPU_FX_GPIO_PRT21_PRT 0x40310A80 0x00000040 GPIO_STD Port #21
374 PERI_MS_PPU_FX_GPIO_PRT22_PRT 0x40310B00 0x00000040 GPIO_STD Port #22
375 PERI_MS_PPU_FX_GPIO_PRT23_PRT 0x40310B80 0x00000040 GPIO_STD Port #23
376 PERI_MS_PPU_FX_GPIO_PRT24_PRT 0x40310C00 0x00000040 HSIO_STD Port #24
377 PERI_MS_PPU_FX_GPIO_PRT25_PRT 0x40310C80 0x00000040 HSIO_STD Port #25
378 PERI_MS_PPU_FX_GPIO_PRT26_PRT 0x40310D00 0x00000040 HSIO_STD Port #26
379 PERI_MS_PPU_FX_GPIO_PRT27_PRT 0x40310D80 0x00000040 HSIO_STD Port #27
380 PERI_MS_PPU_FX_GPIO_PRT28_PRT 0x40310E00 0x00000040 GPIO_STD Port #28
381 PERI_MS_PPU_FX_GPIO_PRT29_PRT 0x40310E80 0x00000040 GPIO_STD Port #29
382 PERI_MS_PPU_FX_GPIO_PRT30_PRT 0x40310F00 0x00000040 GPIO_STD Port #30
383 PERI_MS_PPU_FX_GPIO_PRT31_PRT 0x40310F80 0x00000040 GPIO_STD Port #31
384 PERI_MS_PPU_FX_GPIO_PRT32_PRT 0x40311000 0x00000040 GPIO_STD Port #32
385 PERI_MS_PPU_FX_GPIO_PRT33_PRT 0x40311080 0x00000040 HSIO_STD Port #33
386 PERI_MS_PPU_FX_GPIO_PRT34_PRT 0x40311100 0x00000040 HSIO_STD Port #34
387 PERI_MS_PPU_FX_GPIO_PRT0_CFG 0x40310040 0x00000020 GPIO_ENH Port #0 configuration
388 PERI_MS_PPU_FX_GPIO_PRT1_CFG 0x403100C0 0x00000020 GPIO_STD Port #1 configuration
389 PERI_MS_PPU_FX_GPIO_PRT2_CFG 0x40310140 0x00000020 GPIO_STD Port #2 configuration
390 PERI_MS_PPU_FX_GPIO_PRT3_CFG 0x403101C0 0x00000020 GPIO_STD Port #3 configuration
391 PERI_MS_PPU_FX_GPIO_PRT4_CFG 0x40310240 0x00000020 GPIO_STD Port #4 configuration
392 PERI_MS_PPU_FX_GPIO_PRT5_CFG 0x403102C0 0x00000020 GPIO_STD Port #5 configuration
393 PERI_MS_PPU_FX_GPIO_PRT6_CFG 0x40310340 0x00000020 GPIO_STD Port #6 configuration
394 PERI_MS_PPU_FX_GPIO_PRT7_CFG 0x403103C0 0x00000020 GPIO_STD Port #7 configuration
395 PERI_MS_PPU_FX_GPIO_PRT8_CFG 0x40310440 0x00000020 GPIO_STD Port #8 configuration
396 PERI_MS_PPU_FX_GPIO_PRT9_CFG 0x403104C0 0x00000020 GPIO_STD Port #9 configuration
397 PERI_MS_PPU_FX_GPIO_PRT10_CFG 0x40310540 0x00000020 GPIO_STD Port #10 configuration

Datasheet 98 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
398 PERI_MS_PPU_FX_GPIO_PRT11_CFG 0x403105C0 0x00000020 GPIO_STD Port #11 configuration
399 PERI_MS_PPU_FX_GPIO_PRT12_CFG 0x40310640 0x00000020 GPIO_STD Port #12 configuration
400 PERI_MS_PPU_FX_GPIO_PRT13_CFG 0x403106C0 0x00000020 GPIO_STD Port #13 configuration
401 PERI_MS_PPU_FX_GPIO_PRT14_CFG 0x40310740 0x00000020 GPIO_STD Port #14 configuration
402 PERI_MS_PPU_FX_GPIO_PRT15_CFG 0x403107C0 0x00000020 GPIO_STD Port #15 configuration
403 PERI_MS_PPU_FX_GPIO_PRT16_CFG 0x40310840 0x00000020 GPIO_STD Port #16 configuration
404 PERI_MS_PPU_FX_GPIO_PRT17_CFG 0x403108C0 0x00000020 GPIO_STD Port #17 configuration
405 PERI_MS_PPU_FX_GPIO_PRT18_CFG 0x40310940 0x00000020 GPIO_STD Port #18 configuration
406 PERI_MS_PPU_FX_GPIO_PRT19_CFG 0x403109C0 0x00000020 GPIO_STD Port #19 configuration
407 PERI_MS_PPU_FX_GPIO_PRT20_CFG 0x40310A40 0x00000020 GPIO_STD Port #20 configuration
408 PERI_MS_PPU_FX_GPIO_PRT21_CFG 0x40310AC0 0x00000020 GPIO_STD Port #21 configuration
409 PERI_MS_PPU_FX_GPIO_PRT22_CFG 0x40310B40 0x00000020 GPIO_STD Port #22 configuration
410 PERI_MS_PPU_FX_GPIO_PRT23_CFG 0x40310BC0 0x00000020 GPIO_STD Port #23 configuration
411 PERI_MS_PPU_FX_GPIO_PRT24_CFG 0x40310C40 0x00000020 HSIO_STD Port #24 configuration
412 PERI_MS_PPU_FX_GPIO_PRT25_CFG 0x40310CC0 0x00000020 HSIO_STD Port #25 configuration
413 PERI_MS_PPU_FX_GPIO_PRT26_CFG 0x40310D40 0x00000020 HSIO_STD Port #26 configuration
414 PERI_MS_PPU_FX_GPIO_PRT27_CFG 0x40310DC0 0x00000020 HSIO_STD Port #27 configuration
415 PERI_MS_PPU_FX_GPIO_PRT28_CFG 0x40310E40 0x00000020 GPIO_STD Port #28 configuration
416 PERI_MS_PPU_FX_GPIO_PRT29_CFG 0x40310EC0 0x00000020 GPIO_STD Port #29 configuration
417 PERI_MS_PPU_FX_GPIO_PRT30_CFG 0x40310F40 0x00000020 GPIO_STD Port #30 configuration
418 PERI_MS_PPU_FX_GPIO_PRT31_CFG 0x40310FC0 0x00000020 GPIO_STD Port #31 configuration
419 PERI_MS_PPU_FX_GPIO_PRT32_CFG 0x40311040 0x00000020 GPIO_STD Port #32 configuration
420 PERI_MS_PPU_FX_GPIO_PRT33_CFG 0x403110C0 0x00000020 HSIO_STD Port #33 configuration
421 PERI_MS_PPU_FX_GPIO_PRT34_CFG 0x40311140 0x00000020 HSIO_STD Port #34 configuration
422 PERI_MS_PPU_FX_GPIO_GPIO 0x40314000 0x00000040 GPIO main
423 PERI_MS_PPU_FX_GPIO_TEST 0x40315000 0x00000008 GPIO test
424 PERI_MS_PPU_FX_SMARTIO_PRT12_PRT 0x40320C00 0x00000100 SMART I/O #12
425 PERI_MS_PPU_FX_SMARTIO_PRT13_PRT 0x40320D00 0x00000100 SMART I/O #13
426 PERI_MS_PPU_FX_SMARTIO_PRT14_PRT 0x40320E00 0x00000100 SMART I/O #14
427 PERI_MS_PPU_FX_SMARTIO_PRT15_PRT 0x40320F00 0x00000100 SMART I/O #15
428 PERI_MS_PPU_FX_SMARTIO_PRT17_PRT 0x40321100 0x00000100 SMART I/O #17
429 PERI_MS_PPU_FX_TCPWM0_GRP0_CNT0_CNT 0x40380000 0x00000080 TCPWM0 Group #0, Counter #0
430 PERI_MS_PPU_FX_TCPWM0_GRP0_CNT1_CNT 0x40380080 0x00000080 TCPWM0 Group #0, Counter #1
431 PERI_MS_PPU_FX_TCPWM0_GRP0_CNT2_CNT 0x40380100 0x00000080 TCPWM0 Group #0, Counter #2
432 PERI_MS_PPU_FX_TCPWM0_GRP1_CNT0_CNT 0x40388000 0x00000080 TCPWM0 Group #1, Counter #0
433 PERI_MS_PPU_FX_TCPWM0_GRP1_CNT1_CNT 0x40388080 0x00000080 TCPWM0 Group #1, Counter #1
434 PERI_MS_PPU_FX_TCPWM0_GRP1_CNT2_CNT 0x40388100 0x00000080 TCPWM0 Group #1, Counter #2
435 PERI_MS_PPU_FX_TCPWM0_GRP2_CNT0_CNT 0x40390000 0x00000080 TCPWM0 Group #2, Counter #0
436 PERI_MS_PPU_FX_TCPWM0_GRP2_CNT1_CNT 0x40390080 0x00000080 TCPWM0 Group #2, Counter #1
437 PERI_MS_PPU_FX_TCPWM0_GRP2_CNT2_CNT 0x40390100 0x00000080 TCPWM0 Group #2, Counter #2
438 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT0_CNT 0x40580000 0x00000080 TCPWM1 Group #0, Counter #0
439 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT1_CNT 0x40580080 0x00000080 TCPWM1 Group #0, Counter #1
440 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT2_CNT 0x40580100 0x00000080 TCPWM1 Group #0, Counter #2
441 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT3_CNT 0x40580180 0x00000080 TCPWM1 Group #0, Counter #3
442 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT4_CNT 0x40580200 0x00000080 TCPWM1 Group #0, Counter #4

Datasheet 99 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
443 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT5_CNT 0x40580280 0x00000080 TCPWM1 Group #0, Counter #5
444 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT6_CNT 0x40580300 0x00000080 TCPWM1 Group #0, Counter #6
445 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT7_CNT 0x40580380 0x00000080 TCPWM1 Group #0, Counter #7
446 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT8_CNT 0x40580400 0x00000080 TCPWM1 Group #0, Counter #8
447 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT9_CNT 0x40580480 0x00000080 TCPWM1 Group #0, Counter #9
448 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT10_CNT 0x40580500 0x00000080 TCPWM1 Group #0, Counter #10
449 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT11_CNT 0x40580580 0x00000080 TCPWM1 Group #0, Counter #11
450 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT12_CNT 0x40580600 0x00000080 TCPWM1 Group #0, Counter #12
451 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT13_CNT 0x40580680 0x00000080 TCPWM1 Group #0, Counter #13
452 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT14_CNT 0x40580700 0x00000080 TCPWM1 Group #0, Counter #14
453 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT15_CNT 0x40580780 0x00000080 TCPWM1 Group #0, Counter #15
454 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT16_CNT 0x40580800 0x00000080 TCPWM1 Group #0, Counter #16
455 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT17_CNT 0x40580880 0x00000080 TCPWM1 Group #0, Counter #17
456 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT18_CNT 0x40580900 0x00000080 TCPWM1 Group #0, Counter #18
457 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT19_CNT 0x40580980 0x00000080 TCPWM1 Group #0, Counter #19
458 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT20_CNT 0x40580A00 0x00000080 TCPWM1 Group #0, Counter #20
459 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT21_CNT 0x40580A80 0x00000080 TCPWM1 Group #0, Counter #21
460 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT22_CNT 0x40580B00 0x00000080 TCPWM1 Group #0, Counter #22
461 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT23_CNT 0x40580B80 0x00000080 TCPWM1 Group #0, Counter #23
462 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT24_CNT 0x40580C00 0x00000080 TCPWM1 Group #0, Counter #24
463 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT25_CNT 0x40580C80 0x00000080 TCPWM1 Group #0, Counter #25
464 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT26_CNT 0x40580D00 0x00000080 TCPWM1 Group #0, Counter #26
465 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT27_CNT 0x40580D80 0x00000080 TCPWM1 Group #0, Counter #27
466 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT28_CNT 0x40580E00 0x00000080 TCPWM1 Group #0, Counter #28
467 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT29_CNT 0x40580E80 0x00000080 TCPWM1 Group #0, Counter #29
468 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT30_CNT 0x40580F00 0x00000080 TCPWM1 Group #0, Counter #30
469 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT31_CNT 0x40580F80 0x00000080 TCPWM1 Group #0, Counter #31
470 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT32_CNT 0x40581000 0x00000080 TCPWM1 Group #0, Counter #32
471 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT33_CNT 0x40581080 0x00000080 TCPWM1 Group #0, Counter #33
472 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT34_CNT 0x40581100 0x00000080 TCPWM1 Group #0, Counter #34
473 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT35_CNT 0x40581180 0x00000080 TCPWM1 Group #0, Counter #35
474 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT36_CNT 0x40581200 0x00000080 TCPWM1 Group #0, Counter #36
475 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT37_CNT 0x40581280 0x00000080 TCPWM1 Group #0, Counter #37
476 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT38_CNT 0x40581300 0x00000080 TCPWM1 Group #0, Counter #38
477 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT39_CNT 0x40581380 0x00000080 TCPWM1 Group #0, Counter #39
478 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT40_CNT 0x40581400 0x00000080 TCPWM1 Group #0, Counter #40
479 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT41_CNT 0x40581480 0x00000080 TCPWM1 Group #0, Counter #41
480 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT42_CNT 0x40581500 0x00000080 TCPWM1 Group #0, Counter #42
481 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT43_CNT 0x40581580 0x00000080 TCPWM1 Group #0, Counter #43
482 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT44_CNT 0x40581600 0x00000080 TCPWM1 Group #0, Counter #44
483 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT45_CNT 0x40581680 0x00000080 TCPWM1 Group #0, Counter #45
484 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT46_CNT 0x40581700 0x00000080 TCPWM1 Group #0, Counter #46
485 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT47_CNT 0x40581780 0x00000080 TCPWM1 Group #0, Counter #47
486 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT48_CNT 0x40581800 0x00000080 TCPWM1 Group #0, Counter #48
487 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT49_CNT 0x40581880 0x00000080 TCPWM1 Group #0, Counter #49

Datasheet 100 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
488 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT50_CNT 0x40581900 0x00000080 TCPWM1 Group #0, Counter #50
489 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT51_CNT 0x40581980 0x00000080 TCPWM1 Group #0, Counter #51
490 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT52_CNT 0x40581A00 0x00000080 TCPWM1 Group #0, Counter #52
491 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT53_CNT 0x40581A80 0x00000080 TCPWM1 Group #0, Counter #53
492 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT54_CNT 0x40581B00 0x00000080 TCPWM1 Group #0, Counter #54
493 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT55_CNT 0x40581B80 0x00000080 TCPWM1 Group #0, Counter #55
494 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT56_CNT 0x40581C00 0x00000080 TCPWM1 Group #0, Counter #56
495 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT57_CNT 0x40581C80 0x00000080 TCPWM1 Group #0, Counter #57
496 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT58_CNT 0x40581D00 0x00000080 TCPWM1 Group #0, Counter #58
497 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT59_CNT 0x40581D80 0x00000080 TCPWM1 Group #0, Counter #59
498 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT60_CNT 0x40581E00 0x00000080 TCPWM1 Group #0, Counter #60
499 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT61_CNT 0x40581E80 0x00000080 TCPWM1 Group #0, Counter #61
500 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT62_CNT 0x40581F00 0x00000080 TCPWM1 Group #0, Counter #62
501 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT63_CNT 0x40581F80 0x00000080 TCPWM1 Group #0, Counter #63
502 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT64_CNT 0x40582000 0x00000080 TCPWM1 Group #0, Counter #64
503 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT65_CNT 0x40582080 0x00000080 TCPWM1 Group #0, Counter #65
504 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT66_CNT 0x40582100 0x00000080 TCPWM1 Group #0, Counter #66
505 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT67_CNT 0x40582180 0x00000080 TCPWM1 Group #0, Counter #67
506 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT68_CNT 0x40582200 0x00000080 TCPWM1 Group #0, Counter #68
507 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT69_CNT 0x40582280 0x00000080 TCPWM1 Group #0, Counter #69
508 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT70_CNT 0x40582300 0x00000080 TCPWM1 Group #0, Counter #70
509 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT71_CNT 0x40582380 0x00000080 TCPWM1 Group #0, Counter #71
510 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT72_CNT 0x40582400 0x00000080 TCPWM1 Group #0, Counter #72
511 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT73_CNT 0x40582480 0x00000080 TCPWM1 Group #0, Counter #73
512 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT74_CNT 0x40582500 0x00000080 TCPWM1 Group #0, Counter #74
513 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT75_CNT 0x40582580 0x00000080 TCPWM1 Group #0, Counter #75
514 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT76_CNT 0x40582600 0x00000080 TCPWM1 Group #0, Counter #76
515 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT77_CNT 0x40582680 0x00000080 TCPWM1 Group #0, Counter #77
516 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT78_CNT 0x40582700 0x00000080 TCPWM1 Group #0, Counter #78
517 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT79_CNT 0x40582780 0x00000080 TCPWM1 Group #0, Counter #79
518 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT80_CNT 0x40582800 0x00000080 TCPWM1 Group #0, Counter #80
519 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT81_CNT 0x40582880 0x00000080 TCPWM1 Group #0, Counter #81
520 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT82_CNT 0x40582900 0x00000080 TCPWM1 Group #0, Counter #82
521 PERI_MS_PPU_FX_TCPWM1_GRP0_CNT83_CNT 0x40582980 0x00000080 TCPWM1 Group #0, Counter #83
522 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT0_CNT 0x40588000 0x00000080 TCPWM1 Group #1, Counter #0
523 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT1_CNT 0x40588080 0x00000080 TCPWM1 Group #1, Counter #1
524 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT2_CNT 0x40588100 0x00000080 TCPWM1 Group #1, Counter #2
525 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT3_CNT 0x40588180 0x00000080 TCPWM1 Group #1, Counter #3
526 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT4_CNT 0x40588200 0x00000080 TCPWM1 Group #1, Counter #4
527 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT5_CNT 0x40588280 0x00000080 TCPWM1 Group #1, Counter #5
528 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT6_CNT 0x40588300 0x00000080 TCPWM1 Group #1, Counter #6
529 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT7_CNT 0x40588380 0x00000080 TCPWM1 Group #1, Counter #7
530 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT8_CNT 0x40588400 0x00000080 TCPWM1 Group #1, Counter #8
531 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT9_CNT 0x40588480 0x00000080 TCPWM1 Group #1, Counter #9
532 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT10_CNT 0x40588500 0x00000080 TCPWM1 Group #1, Counter #10

Datasheet 101 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
533 PERI_MS_PPU_FX_TCPWM1_GRP1_CNT11_CNT 0x40588580 0x00000080 TCPWM1 Group #1, Counter #11
534 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT0_CNT 0x40590000 0x00000080 TCPWM1 Group #2, Counter #0
535 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT1_CNT 0x40590080 0x00000080 TCPWM1 Group #2, Counter #1
536 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT2_CNT 0x40590100 0x00000080 TCPWM1 Group #2, Counter #2
537 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT3_CNT 0x40590180 0x00000080 TCPWM1 Group #2, Counter #3
538 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT4_CNT 0x40590200 0x00000080 TCPWM1 Group #2, Counter #4
539 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT5_CNT 0x40590280 0x00000080 TCPWM1 Group #2, Counter #5
540 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT6_CNT 0x40590300 0x00000080 TCPWM1 Group #2, Counter #6
541 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT7_CNT 0x40590380 0x00000080 TCPWM1 Group #2, Counter #7
542 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT8_CNT 0x40590400 0x00000080 TCPWM1 Group #2, Counter #8
543 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT9_CNT 0x40590480 0x00000080 TCPWM1 Group #2, Counter #9
544 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT10_CNT 0x40590500 0x00000080 TCPWM1 Group #2, Counter #10
545 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT11_CNT 0x40590580 0x00000080 TCPWM1 Group #2, Counter #11
546 PERI_MS_PPU_FX_TCPWM1_GRP2_CNT12_CNT 0x40590600 0x00000080 TCPWM1 Group #2, Counter #12
547 PERI_MS_PPU_FX_EVTGEN0 0x403F0000 0x00001000 Event generator #0
548 PERI_MS_PPU_FX_SMIF0 0x40420000 0x00010000 Serial Memory Interface #0
549 PERI_MS_PPU_FX_SDHC0 0x40460000 0x00010000 Secure Digital High Capacity #0
550 PERI_MS_PPU_FX_ETH0 0x40480000 0x00010000 Ethernet0
551 PERI_MS_PPU_FX_ETH1 0x40490000 0x00010000 Ethernet1
552 PERI_MS_PPU_FX_LIN0_MAIN 0x40500000 0x00000008 LIN0, main
553 PERI_MS_PPU_FX_LIN0_CH0_CH 0x40508000 0x00000100 LIN0, Channel #0
554 PERI_MS_PPU_FX_LIN0_CH1_CH 0x40508100 0x00000100 LIN0, Channel #1
555 PERI_MS_PPU_FX_LIN0_CH2_CH 0x40508200 0x00000100 LIN0, Channel #2
556 PERI_MS_PPU_FX_LIN0_CH3_CH 0x40508300 0x00000100 LIN0, Channel #3
557 PERI_MS_PPU_FX_LIN0_CH4_CH 0x40508400 0x00000100 LIN0, Channel #4
558 PERI_MS_PPU_FX_LIN0_CH5_CH 0x40508500 0x00000100 LIN0, Channel #5
559 PERI_MS_PPU_FX_LIN0_CH6_CH 0x40508600 0x00000100 LIN0, Channel #6
560 PERI_MS_PPU_FX_LIN0_CH7_CH 0x40508700 0x00000100 LIN0, Channel #7
561 PERI_MS_PPU_FX_LIN0_CH8_CH 0x40508800 0x00000100 LIN0, Channel #8
562 PERI_MS_PPU_FX_LIN0_CH9_CH 0x40508900 0x00000100 LIN0, Channel #9
563 PERI_MS_PPU_FX_LIN0_CH10_CH 0x40508A00 0x00000100 LIN0, Channel #10
564 PERI_MS_PPU_FX_LIN0_CH11_CH 0x40508B00 0x00000100 LIN0, Channel #11
565 PERI_MS_PPU_FX_LIN0_CH12_CH 0x40508C00 0x00000100 LIN0, Channel #12
566 PERI_MS_PPU_FX_LIN0_CH13_CH 0x40508D00 0x00000100 LIN0, Channel #13
567 PERI_MS_PPU_FX_LIN0_CH14_CH 0x40508E00 0x00000100 LIN0, Channel #14
568 PERI_MS_PPU_FX_LIN0_CH15_CH 0x40508F00 0x00000100 LIN0, Channel #15
569 PERI_MS_PPU_FX_LIN0_CH16_CH 0x40509000 0x00000100 LIN0, Channel #16
570 PERI_MS_PPU_FX_LIN0_CH17_CH 0x40509100 0x00000100 LIN0, Channel #17
571 PERI_MS_PPU_FX_LIN0_CH18_CH 0x40509200 0x00000100 LIN0, Channel #18
572 PERI_MS_PPU_FX_LIN0_CH19_CH 0x40509300 0x00000100 LIN0, Channel #19
573 PERI_MS_PPU_FX_CANFD0_CH0_CH 0x40520000 0x00000200 CAN0, Channel #0
574 PERI_MS_PPU_FX_CANFD0_CH1_CH 0x40520200 0x00000200 CAN0, Channel #1
575 PERI_MS_PPU_FX_CANFD0_CH2_CH 0x40520400 0x00000200 CAN0, Channel #2
576 PERI_MS_PPU_FX_CANFD0_CH3_CH 0x40520600 0x00000200 CAN0, Channel #3
577 PERI_MS_PPU_FX_CANFD0_CH4_CH 0x40520800 0x00000200 CAN0, Channel #4

Datasheet 102 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
578 PERI_MS_PPU_FX_CANFD1_CH0_CH 0x40540000 0x00000200 CAN1, Channel #0
579 PERI_MS_PPU_FX_CANFD1_CH1_CH 0x40540200 0x00000200 CAN1, Channel #1
580 PERI_MS_PPU_FX_CANFD1_CH2_CH 0x40540400 0x00000200 CAN1, Channel #2
581 PERI_MS_PPU_FX_CANFD1_CH3_CH 0x40540600 0x00000200 CAN1, Channel #3
582 PERI_MS_PPU_FX_CANFD1_CH4_CH 0x40540800 0x00000200 CAN1, Channel #4
583 PERI_MS_PPU_FX_CANFD0_MAIN 0x40521000 0x00000100 CAN0 main
584 PERI_MS_PPU_FX_CANFD1_MAIN 0x40541000 0x00000100 CAN1 main
585 PERI_MS_PPU_FX_CANFD0_BUF 0x40530000 0x00010000 CAN0 buffer
586 PERI_MS_PPU_FX_CANFD1_BUF 0x40550000 0x00010000 CAN1 buffer
587 PERI_MS_PPU_FX_FLEXRAY0 0x40560000 0x00001000 FlexRay Interface #0
588 PERI_MS_PPU_FX_SCB0 0x40600000 0x00010000 SCB0
589 PERI_MS_PPU_FX_SCB1 0x40610000 0x00010000 SCB1
590 PERI_MS_PPU_FX_SCB2 0x40620000 0x00010000 SCB2
591 PERI_MS_PPU_FX_SCB3 0x40630000 0x00010000 SCB3
592 PERI_MS_PPU_FX_SCB4 0x40640000 0x00010000 SCB4
593 PERI_MS_PPU_FX_SCB5 0x40650000 0x00010000 SCB5
594 PERI_MS_PPU_FX_SCB6 0x40660000 0x00010000 SCB6
595 PERI_MS_PPU_FX_SCB7 0x40670000 0x00010000 SCB7
596 PERI_MS_PPU_FX_SCB8 0x40680000 0x00010000 SCB8
597 PERI_MS_PPU_FX_SCB9 0x40690000 0x00010000 SCB9
598 PERI_MS_PPU_FX_SCB10 0x406A0000 0x00010000 SCB10
599 PERI_MS_PPU_FX_I2S0 0x40800000 0x00001000 AUDIOSS I2S0
600 PERI_MS_PPU_FX_I2S1 0x40801000 0x00001000 AUDIOSS I2S1
601 PERI_MS_PPU_FX_I2S2 0x40802000 0x00001000 AUDIOSS I2S2
602 PERI_MS_PPU_FX_PASS0_SAR0_SAR 0x40900000 0x00000400 PASS SAR0
603 PERI_MS_PPU_FX_PASS0_SAR1_SAR 0x40901000 0x00000400 PASS SAR1
604 PERI_MS_PPU_FX_PASS0_SAR2_SAR 0x40902000 0x00000400 PASS SAR2
605 PERI_MS_PPU_FX_PASS0_SAR0_CH0_CH 0x40900800 0x00000040 SAR0, Channel #0
606 PERI_MS_PPU_FX_PASS0_SAR0_CH1_CH 0x40900840 0x00000040 SAR0, Channel #1
607 PERI_MS_PPU_FX_PASS0_SAR0_CH2_CH 0x40900880 0x00000040 SAR0, Channel #2
608 PERI_MS_PPU_FX_PASS0_SAR0_CH3_CH 0x409008C0 0x00000040 SAR0, Channel #3
609 PERI_MS_PPU_FX_PASS0_SAR0_CH4_CH 0x40900900 0x00000040 SAR0, Channel #4
610 PERI_MS_PPU_FX_PASS0_SAR0_CH5_CH 0x40900940 0x00000040 SAR0, Channel #5
611 PERI_MS_PPU_FX_PASS0_SAR0_CH6_CH 0x40900980 0x00000040 SAR0, Channel #6
612 PERI_MS_PPU_FX_PASS0_SAR0_CH7_CH 0x409009C0 0x00000040 SAR0, Channel #7
613 PERI_MS_PPU_FX_PASS0_SAR0_CH8_CH 0x40900A00 0x00000040 SAR0, Channel #8
614 PERI_MS_PPU_FX_PASS0_SAR0_CH9_CH 0x40900A40 0x00000040 SAR0, Channel #9
615 PERI_MS_PPU_FX_PASS0_SAR0_CH10_CH 0x40900A80 0x00000040 SAR0, Channel #10
616 PERI_MS_PPU_FX_PASS0_SAR0_CH11_CH 0x40900AC0 0x00000040 SAR0, Channel #11
617 PERI_MS_PPU_FX_PASS0_SAR0_CH12_CH 0x40900B00 0x00000040 SAR0, Channel #12
618 PERI_MS_PPU_FX_PASS0_SAR0_CH13_CH 0x40900B40 0x00000040 SAR0, Channel #13
619 PERI_MS_PPU_FX_PASS0_SAR0_CH14_CH 0x40900B80 0x00000040 SAR0, Channel #14
620 PERI_MS_PPU_FX_PASS0_SAR0_CH15_CH 0x40900BC0 0x00000040 SAR0, Channel #15
621 PERI_MS_PPU_FX_PASS0_SAR0_CH16_CH 0x40900C00 0x00000040 SAR0, Channel #16
622 PERI_MS_PPU_FX_PASS0_SAR0_CH17_CH 0x40900C40 0x00000040 SAR0, Channel #17

Datasheet 103 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
623 PERI_MS_PPU_FX_PASS0_SAR0_CH18_CH 0x40900C80 0x00000040 SAR0, Channel #18
624 PERI_MS_PPU_FX_PASS0_SAR0_CH19_CH 0x40900CC0 0x00000040 SAR0, Channel #19
625 PERI_MS_PPU_FX_PASS0_SAR0_CH20_CH 0x40900D00 0x00000040 SAR0, Channel #20
626 PERI_MS_PPU_FX_PASS0_SAR0_CH21_CH 0x40900D40 0x00000040 SAR0, Channel #21
627 PERI_MS_PPU_FX_PASS0_SAR0_CH22_CH 0x40900D80 0x00000040 SAR0, Channel #22
628 PERI_MS_PPU_FX_PASS0_SAR0_CH23_CH 0x40900DC0 0x00000040 SAR0, Channel #23
629 PERI_MS_PPU_FX_PASS0_SAR0_CH24_CH 0x40900E00 0x00000040 SAR0, Channel #24
630 PERI_MS_PPU_FX_PASS0_SAR0_CH25_CH 0x40900E40 0x00000040 SAR0, Channel #25
631 PERI_MS_PPU_FX_PASS0_SAR0_CH26_CH 0x40900E80 0x00000040 SAR0, Channel #26
632 PERI_MS_PPU_FX_PASS0_SAR0_CH27_CH 0x40900EC0 0x00000040 SAR0, Channel #27
633 PERI_MS_PPU_FX_PASS0_SAR0_CH28_CH 0x40900F00 0x00000040 SAR0, Channel #28
634 PERI_MS_PPU_FX_PASS0_SAR0_CH29_CH 0x40900F40 0x00000040 SAR0, Channel #29
635 PERI_MS_PPU_FX_PASS0_SAR0_CH30_CH 0x40900F80 0x00000040 SAR0, Channel #30
636 PERI_MS_PPU_FX_PASS0_SAR0_CH31_CH 0x40900FC0 0x00000040 SAR0, Channel #31
637 PERI_MS_PPU_FX_PASS0_SAR1_CH0_CH 0x40901800 0x00000040 SAR1, Channel #0
638 PERI_MS_PPU_FX_PASS0_SAR1_CH1_CH 0x40901840 0x00000040 SAR1, Channel #1
639 PERI_MS_PPU_FX_PASS0_SAR1_CH2_CH 0x40901880 0x00000040 SAR1, Channel #2
640 PERI_MS_PPU_FX_PASS0_SAR1_CH3_CH 0x409018C0 0x00000040 SAR1, Channel #3
641 PERI_MS_PPU_FX_PASS0_SAR1_CH4_CH 0x40901900 0x00000040 SAR1, Channel #4
642 PERI_MS_PPU_FX_PASS0_SAR1_CH5_CH 0x40901940 0x00000040 SAR1, Channel #5
643 PERI_MS_PPU_FX_PASS0_SAR1_CH6_CH 0x40901980 0x00000040 SAR1, Channel #6
644 PERI_MS_PPU_FX_PASS0_SAR1_CH7_CH 0x409019C0 0x00000040 SAR1, Channel #7
645 PERI_MS_PPU_FX_PASS0_SAR1_CH8_CH 0x40901A00 0x00000040 SAR1, Channel #8
646 PERI_MS_PPU_FX_PASS0_SAR1_CH9_CH 0x40901A40 0x00000040 SAR1, Channel #9
647 PERI_MS_PPU_FX_PASS0_SAR1_CH10_CH 0x40901A80 0x00000040 SAR1, Channel #10
648 PERI_MS_PPU_FX_PASS0_SAR1_CH11_CH 0x40901AC0 0x00000040 SAR1, Channel #11
649 PERI_MS_PPU_FX_PASS0_SAR1_CH12_CH 0x40901B00 0x00000040 SAR1, Channel #12
650 PERI_MS_PPU_FX_PASS0_SAR1_CH13_CH 0x40901B40 0x00000040 SAR1, Channel #13
651 PERI_MS_PPU_FX_PASS0_SAR1_CH14_CH 0x40901B80 0x00000040 SAR1, Channel #14
652 PERI_MS_PPU_FX_PASS0_SAR1_CH15_CH 0x40901BC0 0x00000040 SAR1, Channel #15
653 PERI_MS_PPU_FX_PASS0_SAR1_CH16_CH 0x40901C00 0x00000040 SAR1, Channel #16
654 PERI_MS_PPU_FX_PASS0_SAR1_CH17_CH 0x40901C40 0x00000040 SAR1, Channel #17
655 PERI_MS_PPU_FX_PASS0_SAR1_CH18_CH 0x40901C80 0x00000040 SAR1, Channel #18
656 PERI_MS_PPU_FX_PASS0_SAR1_CH19_CH 0x40901CC0 0x00000040 SAR1, Channel #19
657 PERI_MS_PPU_FX_PASS0_SAR1_CH20_CH 0x40901D00 0x00000040 SAR1, Channel #20
658 PERI_MS_PPU_FX_PASS0_SAR1_CH21_CH 0x40901D40 0x00000040 SAR1, Channel #21
659 PERI_MS_PPU_FX_PASS0_SAR1_CH22_CH 0x40901D80 0x00000040 SAR1, Channel #22
660 PERI_MS_PPU_FX_PASS0_SAR1_CH23_CH 0x40901DC0 0x00000040 SAR1, Channel #23
661 PERI_MS_PPU_FX_PASS0_SAR1_CH24_CH 0x40901E00 0x00000040 SAR1, Channel #24
662 PERI_MS_PPU_FX_PASS0_SAR1_CH25_CH 0x40901E40 0x00000040 SAR1, Channel #25
663 PERI_MS_PPU_FX_PASS0_SAR1_CH26_CH 0x40901E80 0x00000040 SAR1, Channel #26
664 PERI_MS_PPU_FX_PASS0_SAR1_CH27_CH 0x40901EC0 0x00000040 SAR1, Channel #27
665 PERI_MS_PPU_FX_PASS0_SAR1_CH28_CH 0x40901F00 0x00000040 SAR1, Channel #28
666 PERI_MS_PPU_FX_PASS0_SAR1_CH29_CH 0x40901F40 0x00000040 SAR1, Channel #29
667 PERI_MS_PPU_FX_PASS0_SAR1_CH30_CH 0x40901F80 0x00000040 SAR1, Channel #30

Datasheet 104 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Peripheral protection unit fixed structure pairs

Table 23-1 PPU fixed structure pairs (continued)

Pair No. PPU Fixed Structure Pair Address Size Description
668 PERI_MS_PPU_FX_PASS0_SAR1_CH31_CH 0x40901FC0 0x00000040 SAR1, Channel #31
669 PERI_MS_PPU_FX_PASS0_SAR2_CH0_CH 0x40902800 0x00000040 SAR2, Channel #0
670 PERI_MS_PPU_FX_PASS0_SAR2_CH1_CH 0x40902840 0x00000040 SAR2, Channel #1
671 PERI_MS_PPU_FX_PASS0_SAR2_CH2_CH 0x40902880 0x00000040 SAR2, Channel #2
672 PERI_MS_PPU_FX_PASS0_SAR2_CH3_CH 0x409028C0 0x00000040 SAR2, Channel #3
673 PERI_MS_PPU_FX_PASS0_SAR2_CH4_CH 0x40902900 0x00000040 SAR2, Channel #4
674 PERI_MS_PPU_FX_PASS0_SAR2_CH5_CH 0x40902940 0x00000040 SAR2, Channel #5
675 PERI_MS_PPU_FX_PASS0_SAR2_CH6_CH 0x40902980 0x00000040 SAR2, Channel #6
676 PERI_MS_PPU_FX_PASS0_SAR2_CH7_CH 0x409029C0 0x00000040 SAR2, Channel #7
677 PERI_MS_PPU_FX_PASS0_SAR2_CH8_CH 0x40902A00 0x00000040 SAR2, Channel #8
678 PERI_MS_PPU_FX_PASS0_SAR2_CH9_CH 0x40902A40 0x00000040 SAR2, Channel #9
679 PERI_MS_PPU_FX_PASS0_SAR2_CH10_CH 0x40902A80 0x00000040 SAR2, Channel #10
680 PERI_MS_PPU_FX_PASS0_SAR2_CH11_CH 0x40902AC0 0x00000040 SAR2, Channel #11
681 PERI_MS_PPU_FX_PASS0_SAR2_CH12_CH 0x40902B00 0x00000040 SAR2, Channel #12
682 PERI_MS_PPU_FX_PASS0_SAR2_CH13_CH 0x40902B40 0x00000040 SAR2, Channel #13
683 PERI_MS_PPU_FX_PASS0_SAR2_CH14_CH 0x40902B80 0x00000040 SAR2, Channel #14
684 PERI_MS_PPU_FX_PASS0_SAR2_CH15_CH 0x40902BC0 0x00000040 SAR2, Channel #15
685 PERI_MS_PPU_FX_PASS0_SAR2_CH16_CH 0x40902C00 0x00000040 SAR2, Channel #16
686 PERI_MS_PPU_FX_PASS0_SAR2_CH17_CH 0x40902C40 0x00000040 SAR2, Channel #17
687 PERI_MS_PPU_FX_PASS0_SAR2_CH18_CH 0x40902C80 0x00000040 SAR2, Channel #18
688 PERI_MS_PPU_FX_PASS0_SAR2_CH19_CH 0x40902CC0 0x00000040 SAR2, Channel #19
689 PERI_MS_PPU_FX_PASS0_SAR2_CH20_CH 0x40902D00 0x00000040 SAR2, Channel #20
690 PERI_MS_PPU_FX_PASS0_SAR2_CH21_CH 0x40902D40 0x00000040 SAR2, Channel #21
691 PERI_MS_PPU_FX_PASS0_SAR2_CH22_CH 0x40902D80 0x00000040 SAR2, Channel #22
692 PERI_MS_PPU_FX_PASS0_SAR2_CH23_CH 0x40902DC0 0x00000040 SAR2, Channel #23
693 PERI_MS_PPU_FX_PASS0_SAR2_CH24_CH 0x40902E00 0x00000040 SAR2, Channel #24
694 PERI_MS_PPU_FX_PASS0_SAR2_CH25_CH 0x40902E40 0x00000040 SAR2, Channel #25
695 PERI_MS_PPU_FX_PASS0_SAR2_CH26_CH 0x40902E80 0x00000040 SAR2, Channel #26
696 PERI_MS_PPU_FX_PASS0_SAR2_CH27_CH 0x40902EC0 0x00000040 SAR2, Channel #27
697 PERI_MS_PPU_FX_PASS0_SAR2_CH28_CH 0x40902F00 0x00000040 SAR2, Channel #28
698 PERI_MS_PPU_FX_PASS0_SAR2_CH29_CH 0x40902F40 0x00000040 SAR2, Channel #29
699 PERI_MS_PPU_FX_PASS0_SAR2_CH30_CH 0x40902F80 0x00000040 SAR2, Channel #30
700 PERI_MS_PPU_FX_PASS0_SAR2_CH31_CH 0x40902FC0 0x00000040 SAR2, Channel #31
701 PERI_MS_PPU_FX_PASS0_TOP 0x409F0000 0x00001000 PASS0 SAR main

Datasheet 105 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Bus masters

24 Bus masters
The Arbiter (part of flash controller) performs priority-based arbitration based on the master identifier. Each bus
master has a dedicated 4-bit master identifier. This master identifier is used for bus arbitration and IPC function-
ality.
Table 24-1 Bus masters for access and protection control
ID No. Master ID Description
0 CPUSS_MS_ID_CM0 Master ID for CM0+
1 CPUSS_MS_ID_CRYPTO Master ID for Crypto
2 CPUSS_MS_ID_DW0 Master ID for P-DMA0
3 CPUSS_MS_ID_DW1 Master ID for P-DMA1
4 CPUSS_MS_ID_DMAC Master ID for M-DMA0
5 CPUSS_MS_ID_SLOW0 Master ID for External AHB-Lite Master 0 (SDHC)
9 CPUSS_MS_ID_FAST0 Master ID for External AXI Master 0 (ETH0)
10 CPUSS_MS_ID_FAST1 Master ID for External AXI Master 1 (ETH1)
13 CPUSS_MS_ID_CM7_1 Master ID for CM7_1
14 CPUSS_MS_ID_CM7_0 Master ID for CM7_0
15 CPUSS_MS_ID_TC Master ID for DAP Tap Controller

Datasheet 106 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Miscellaneous configuration

25 Miscellaneous configuration
Table 25-1 Miscellaneous configuration for CYT4BF devices
Sl. No. Configuration Number/Instances Description

0 SRSS_NUM_CLKPATH 7 Number of clock paths. One for each of FLL, PLL, Direct and CSV

1 SRSS_NUM_HFROOT 8 Number of CLK_HFs present

2 PERI_PC_NR 8 Number of protection contexts

3 PERI_PERI_PCLK_PCLK_GROUP_NR 2 Number of asynchronous PCLK groups

4 PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_8_VECT 4 Group 0, Number of divide-by-8 clock dividers

5 PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_16_VECT 3 Group 0, Number of divide-by-16 clock dividers

6 PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_DIV_24_5_VECT 1 Group 0, Number of divide-by-24.5 clock dividers

7 PERI_PERI_PCLK_PCLK_GROUP_NR0_GR_CLOCK_VECT 15 Group 0, Number of programmable clocks [1, 256]

8 PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_8_VECT 19 Group 1, Number of divide-by-8 clock dividers

9 PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_16_VECT 20 Group 1, Number of divide-by-16 clock dividers

10 PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_DIV_24_5_VECT 21 Group 1, Number of divide-by-24.5 clock dividers

11 PERI_PERI_PCLK_PCLK_GROUP_NR1_GR_CLOCK_VECT 154 Group 1, Number of programmable clocks [1, 256]

12 CPUSS_CM0P_MPU_NR 8 Number of MPU regions in CM0+

CM7_0 Floating point unit configuration.
0 - No FPU
13 CPUSS_CM7_0_FPU_LVL 2 1 - Single precision FPU
2 - Single and Double precision FPU

14 CPUSS_CM7_0_MPU_NR 16 Number of MPU regions in CM7_0

15 CPUSS_CM7_0_ICACHE_SIZE 16 CM7_0 Instruction cache (ICACHE) size in KB

16 CPUSS_CM7_0_DCACHE_SIZE 16 CM7_0 Data cache size (DCACHE) in KB

17 CPUSS_CM7_0_ITCM_SIZE 16 CM7_0 Instruction TCM (ITCM) size in KB

18 CPUSS_CM7_0_DTCM_SIZE 16 CM7_0 Data TCM (DTCM) size in KB

CM7_1 Floating point unit configuration.
0 - No FPU
19 CPUSS_CM7_1_FPU_LVL 2 1 - Single precision FPU
2 - Single and Double precision FPU

20 CPUSS_CM7_1_MPU_NR 16 Number of MPU regions in CM7_1

21 CPUSS_CM7_1_ICACHE_SIZE 16 CM7_1 Instruction cache (ICACHE) size in KB

22 CPUSS_CM7_1_DCACHE_SIZE 16 CM7_1 Data cache size (DCACHE) in KB

23 CPUSS_CM7_1_ITCM_SIZE 16 CM7_1 Instruction TCM (ITCM) size in KB

24 CPUSS_CM7_1_DTCM_SIZE 16 CM7_1 Data TCM (DTCM) size in KB

25 CPUSS_DW0_CH_NR 143 Number of P-DMA0 channels

26 CPUSS_DW1_CH_NR 65 Number of P-DMA1 channels

27 CPUSS_DMAC_CH_NR 8 Number of M-DMA0 controller channels

Number of 32-bit words in the IP internal memory buffer (to allow for
28 CPUSS_CRYPTO_BUFF_SIZE 2048 a 256-B, 512-B, 1-KB, 2-KB, 4-KB, 8-KB, 16-KB, and 32-KB memory
buffer)

29 CPUSS_FAULT_FAULT_NR 4 Number of fault structures

Number of IPC structures
0 - Reserved for CM0+ access
1 - Reserved for CM7_0 access
30 CPUSS_IPC_IPC_NR 8 2 - Reserved for CM7_1 access
3 - Reserved for DAP access
Remaining for user purposes

31 CPUSS_PROT_SMPU_STRUCT_NR 16 Number of SMPU protection structures

Number of EZ memory bytes. This memory is used in EZ mode,
32 SCBx_EZ_DATA_NR 256 CMD_RESP mode and FIFO mode.
Note: Only SCB0 supports CMD_RESP mode

33 TCPWM0_TR_ONE_CNT_NR 3 Number of input triggers per counter, routed to one counter

Number of input triggers routed to all counters, based on the pin
34 TCPWM0_TR_ALL_CNT_NR 12 package

35 TCPWM0_GRP_NR 3 Number of TCPWM0 counter groups

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Miscellaneous configuration

Table 25-1 Miscellaneous configuration for CYT4BF devices (continued)

Sl. No. Configuration Number/Instances Description

36 TCPWM0_GRP_NR0_GRP_GRP_CNT_NR 3 Number of counters per TCPWM0 Group #0

Counter width in number of bits per TCPWM0
37 TCPWM0_GRP_NR0_CNT_GRP_CNT_WIDTH 16 Group #0

38 TCPWM0_GRP_NR1_GRP_GRP_CNT_NR 3 Number of counters per TCPWM0 Group #1

Counter width in number of bits per TCPWM0
39 TCPWM0_GRP_NR1_CNT_GRP_CNT_WIDTH 16 Group #1

40 TCPWM0_GRP_NR2_GRP_GRP_CNT_NR 3 Number of counters per TCPWM0 Group #2

Counter width in number of bits per TCPWM0
41 TCPWM0_GRP_NR2_CNT_GRP_CNT_WIDTH 32 Group #2

42 TCPWM1_GRP_NR 3 Number of TCPWM1 counter groups

43 TCPWM1_GRP_NR0_GRP_GRP_CNT_NR 84 Number of counters per TCPWM1 Group #0

Counter width in number of bits per TCPWM1
44 TCPWM1_GRP_NR0_CNT_GRP_CNT_WIDTH 16 Group #0

45 TCPWM1_GRP_NR1_GRP_GRP_CNT_NR 12 Number of counters per TCPWM1 Group #1

Counter width in number of bits per TCPWM1
46 TCPWM1_GRP_NR1_CNT_GRP_CNT_WIDTH 16 Group #1

47 TCPWM1_GRP_NR2_GRP_GRP_CNT_NR 13 Number of counters per TCPWM1 Group #2

48 TCPWM1_GRP_NR2_CNT_GRP_CNT_WIDTH 32 Counter width in number of bits per TCPWM1 Group #2

49 CANFD0_MRAM_SIZE / CANFD1_MRAM_SIZE 40 Message RAM size in KB shared by all the channels

50 EVTGEN_COMP_STRUCT_NR 16 Number of Event Generator comparator structures

Datasheet 108 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Development support

26 Development support
CYT4BF has a rich set of documentation, programming tools, and online resources to assist during the devel-
opment process. Visit www.infineon.com to find out more.

26.1 Documentation
A suite of documentation supports CYT4BF to ensure that you can find answers to your questions quickly. This
section contains a list of some of the key documents.

26.1.1 Software User Guide

A step-by-step guide for using the sample driver library along with third-party IDEs such as IAR EWARM and GHS
Multi.

26.1.2 Technical Reference Manual

The Technical Reference Manual (TRM) contains all the technical detail needed to use a CYT4BF device, including
a complete description of all registers. The TRM is available in the documentation section at www.infineon.com.

26.2 Tools
CYT4BF is supported on third-party development tool ecosystems such as IAR and GHS. CYT4BF is also supported
by Cypress programming utilities for programming, erasing, or reading using Cypress’ MiniProg4 or Segger J-link.
More details are available in the documentation section at www.infineon.com.

Datasheet 109 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27 Electrical specifications
27.1 Absolute maximum ratings
Use of this device under conditions outside the Min and Max limits listed in Table 27-1 may cause permanent
damage to the device. Exposure to conditions within the limits of Table 27-1 but beyond those of normal
operation for extended periods of time may affect device reliability. The maximum storage temperature is 150 °C
in compliance with JEDEC Standard JESD22-A103, High Temperature Storage Life. When operated under condi-
tions within the limits of Table 27-1 but beyond those of normal operation, the device may not operate to speci-
fication.

Power considerations
The average chip-junction temperature, TJ, in °C, may be calculated using Equation 1:

T J = T A +  P D   JA 
Equation. 1
Where:
TA is the ambient temperature in °C.
θJA is the package junction-to-ambient thermal resistance, in °C/W.
PD is the sum of PINT and PIO (PD = PINT + PIO).
PINT is the chip internal power. (PINT = VDDD × IDD + VDDA × IA)
PIO represents the power dissipation on input and output pins; user determined.
For most applications, PIO < PINT and may be neglected.
On the other hand, PIO may be significant if the device is configured to continuously drive external modules
and/or memories.

WARNING:

• The recommended operating conditions are required to ensure the normal operation of the semiconductor
device. All of the device's electrical characteristics are guaranteed when the device is operated under these
conditions.
• Operation under any conditions other than those mentioned in the respective “Details/Conditions” may
adversely affect reliability of the device and can result in device failure.
• No guarantee is made with respect to any use, operating conditions, or combinations not represented in this
datasheet. If you want to operate the device under any condition other than those listed herein, contact the
sales representatives.

Datasheet 110 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-1 Absolute maximum ratings

Details/
Spec ID Parameter Description Min Typ Max Units
Conditions
For ports 0, 1, 2, 3, 4, 5, 16, 17,
SID10 VDDD_ABS VDDD power supply voltage[35] VSSD – 0.3 – VSSD + 6.0 V 18, 19, 20, 21, 22, 23, 28, 29, 30,
31
SID10B VDDIO_1_ABS VDDIO_1 power supply voltage[35] VSSD – 0.3 – VSSD + 6.0 V For ports 6, 7, 8, 9, 32
[35]
SID10C VDDIO_2_ABS VDDIO_2 power supply voltage VSSD – 0.3 – VSSD + 6.0 V For ports 10, 11, 12, 13, 14, 15
SID10D VDDIO_3_ABS VDDIO_3 power supply voltage[35] VSSIO_3 – 0.3 – VSSIO_3 + 4.0 V For ports 24, 25
SID10E VDDIO_4_ABS VDDIO_4 power supply voltage[35] VSSIO_4 – 0.3 – VSSIO_4 + 4.0 V For ports 26, 27, 33, 34
[35]
SID11 VDDA_ABS VDDA analog power supply voltage VSSA – 0.3 – VSSA + 6.0 V VDDIO_2 = VDDA
[35] VREFH 
SID12 VREFH_ABS Analog reference voltage, HIGH VSSA – 0.3 – VSSA + 6.0 V
(VDDA + 0.3 V)
SID12A VREFL_ABS Analog reference voltage, LOW[35] VSSA – 0.3 – VSSA + 0.3 V
SID13 VCCD_ABS VCCD Power supply voltage[35] VSSD – 0.3 – VSSD + 1.21 V
For ports 0, 1, 2, 3, 4, 5, 16, 17,
SID15A VI0_ABS Input voltage[35] VSSD – 0.5 – VDDD + 0.5 V 18, 19, 20, 21, 22, 23, 28, 29, 30,
31
SID15B VI1_ABS Input voltage[35] VSSD – 0.5 – VDDIO_1 + 0.5 V For ports 6, 7, 8, 9, 32
SID15C VI2_ABS Input voltage[35] VSSD – 0.5 – VDDIO_2 + 0.5 V For ports 10, 11, 12, 13, 14, 15
[35]
SID15D VI3_ABS Input voltage VSSIO_3 – 0.5 – VDDIO_3 + 0.5 V For ports 24, 25
SID15E VI4_ABS Input voltage[35] VSSIO_4 – 0.5 – VDDIO_4 + 0.5 V For ports 26, 27, 33, 34
For EXT_PS_CTL0 in external
SID15F VI5_ABS Input voltage[35] VSSD – 0.5 – VDDD + 0.5 V PMIC/transistor mode,
EXT_PS_CTL1 in external
transistor mode.
SID16 VIA_ABS Analog input voltage[35] VSSA – 0.3 – VDDA + 0.3 V
For ports 0, 1, 2, 3, 4, 5, 16, 17,
SID17A VO0_ABS Output voltage[35] VSSD – 0.3 – VDDD + 0.3 V 18, 19, 20, 21, 22, 23, 28, 29, 30,
31
SID17B VO1_ABS Output voltage[35] VSSD – 0.3 – VDDIO_1 + 0.3 V For ports 6, 7, 8, 9, 32
SID17C VO2_ABS Output voltage[35] VSSD – 0.3 – VDDIO_2 + 0.3 V For ports 10, 11, 12, 13, 14, 15
[35]
SID17D VO3_ABS Output voltage VSSIO_3 – 0.3 – VDDIO_3 + 0.3 V For ports 24, 25
SID17E VO5_ABS Output voltage[35] VSSIO_4 – 0.3 – VDDIO_4 + 0.3 V For ports 26, 27, 33, 34
For EXT_PS_CTL1/2 in
SID17F VO4_ABS Output voltage[35] VSSD – 0.3 – VDDD + 0.3 V external PMIC mode,
DRV_VOUT in external
transistor mode
SID18 |ICLAMP_ABS| Maximum clamp current[36, 37, 38] –5 – 5 mA
Maximum positive clamp current per
ICLAMP_SUP- I/O supply pin. Limit applies to I/O +B injected DC current is not
SID18A – – 10 mA
PLY_POS_ABS supply pin closest to the B+ injected allowed for Ports 11 and 21.
current[40]
Maximum negative clamp current per
ICLAMP_SUP- I/O ground pin. Limit applies to I/O +B injected DC current is not
SID18B – – 10 mA
PLY_NEG_ABS supply pin closest to the B+ injected allowed for Ports 11 and 21.
current.[40]
Maximum positive clamp current per
ICLAMP_TO-
SID18C I/O supply, if not limited by the per – – 50 mA
TAL_POS_ABS supply pin (based on SID18A).

Notes
35.These parameters are based on the condition that VSSD = VSSA = VSSIO_3 = VSSIO_4 = 0.0 V.
36.A current-limiting resistor must be provided such that the current at the I/O pin does not exceed rated values at any time, including
during power transients. Refer to Figure 27-1 for more information on the recommended circuit.
37.VDDD and VDDIO must be sufficiently loaded or protected to prevent them from being pulled out of the recommended operating range
by the clamp current.
38.When the conditions of [36], [37] and SID18A/B/C/D are met, |ICLAMP_ABS| supersedes VIA_ABS and VI_ABS.
39.The definition of “closer” depends on the package. In TEQFP packaging, “closest” is determined by counting pins. For example, in a
176-TEQFP package, P17.4 (pin 120) is closer to the VDDD on pin 110 than on pin 132. Ports 11 and 21 should not be used for injection
currents. The impact of injection currents is only defined for GPIO_STD/GPIO_ENH type I/Os. In BGA packaging, the following IO port
groups are treated as having separate supply pins: Ports 0, 1, 2, 22, 23, and 28; Ports 3, 4, 5, 29, 30, and 31; Ports 6, 7, 8, 9, and 32;
Ports 10, 12, 13, 14, 15, 26, and 27; Ports 16 and 17; Ports 18, 19, and 20.

Datasheet 111 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-1 Absolute maximum ratings (continued)

Details/
Spec ID Parameter Description Min Typ Max Units
Conditions
Maximum negative clamp current per
ICLAMP_TO-
SID18D I/O ground, if not limited by the per – – 50 mA
TAL_NEG_ABS supply pin (based on SID18B).
GPIO_STD, configured for
SID20A IOL1A_ABS LOW-level maximum output current[40] – – 6 mA drive_sel<1:0>= 0b0X
GPIO_STD, configured for
SID20B IOL1B_ABS LOW-level maximum output current[40] – – 2 mA drive_sel<1:0>= 0b10
GPIO_STD, configured for
SID20C IOL1C_ABS LOW-level maximum output current[40] – – 1 mA drive_sel<1:0>= 0b11
GPIO_ENH, configured for
SID21A IOL2A_ABS LOW-level maximum output current[40] – – 6 mA drive_sel<1:0>= 0b0X
GPIO_ENH, configured for
SID21B IOL2B_ABS LOW-level maximum output current[40] – – 2 mA drive_sel<1:0>= 0b10
GPIO_ENH, configured for
SID21C IOL2C_ABS LOW-level maximum output current[40] – – 1 mA drive_sel<1:0>= 0b11
HSIO, configured for
SID22A IOL3A_ABS LOW-level maximum output current[40] – – 10 mA drive_sel<1:0>= 0b00
HSIO, configured for
SID22B IOL3B_ABS LOW-level maximum output current[40] – – 2 mA drive_sel<1:0>= 0b01
HSIO, configured for
SID22C IOL3C_ABS LOW-level maximum output current[40] – – 1 mA drive_sel<1:0>= 0b10
HSIO, configured for
SID22D IOL3D_ABS LOW-level maximum output current[40] – – 0.5 mA drive_sel<1:0>= 0b11
For pin EXT_PS_CTL1 in
external PMIC mode and
SID23A IOL4A_ABS Sink maximum current[40] – – 4 mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode
For pin EXT_PS_CTL1 in
external PMIC mode and
SID23B IOL4B_ABS Sink average current[41] – – 1 mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode
For pin DRV_VOUT in external
SID23C IOL4C_ABS Sink maximum current[40] – – 25 mA
transistor mode
SID26A ∑IOL_ABS_GPIO LOW-level total output current[44] – – 50 mA
SID26B ∑IOL_ABS_HSIO LOW-level total output current[43] – – 85 mA
GPIO_STD, configured for
SID27A IOH1A_ABS HIGH-level maximum output current[40] – – –5 mA
drive_sel<1:0>= 0b0X
GPIO_STD, configured for
SID27B IOH1B_ABS HIGH-level maximum output current[40] – – –2 mA
drive_sel<1:0>= 0b10
GPIO_STD, configured for
SID27C IOH1C_ABS HIGH-level maximum output current[40] – – –1 mA
drive_sel<1:0>= 0b11
GPIO_ENH, configured for
SID28A IOH2A_ABS HIGH-level maximum output current[40] – – –5 mA
drive_sel<1:0>= 0b0X
GPIO_ENH, configured for
SID28B IOH2B_ABS HIGH-level maximum output current[40] – – –2 mA
drive_sel<1:0>= 0b10
GPIO_ENH, configured for
SID28C IOH2C_ABS HIGH-level maximum output current[40] – – –1 mA
drive_sel<1:0>= 0b11
HSIO, configured for
SID29A IOH3A_ABS HIGH-level maximum output current[40] – – –10 mA
drive_sel<1:0>= 0b00
HSIO, configured for
SID29B IOH3B_ABS HIGH-level maximum output current[40] – – –2 mA
drive_sel<1:0>= 0b01
HSIO, configured for
SID29C IOH3C_ABS HIGH-level maximum output current[40] – – –1 mA
drive_sel<1:0>= 0b10
HSIO, configured for
SID29D IOH3D_ABS HIGH-level maximum output current[40] – – –0.5 mA
drive_sel<1:0>= 0b11
Notes
40. The maximum output current is the peak current flowing through any one I/O.
41. The average output current is defined as the value of the average current flowing through any one of the corresponding pins for a 10 ms period. The
average value is the operation current × the operation ratio. The operation current period over the average current spec should be less than 100 ns.
42. The total output current is the maximum current flowing through all GPIO_STD and GPIO_ENH I/Os.
43. The total output current is the maximum current flowing through all HSIO_STD I/Os.

Datasheet 112 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-1 Absolute maximum ratings (continued)

Details/
Spec ID Parameter Description Min Typ Max Units
Conditions
For pin EXT_PS_CTL1 in
external PMIC mode and
SID30A IOH4A_ABS Source maximum current[40] – – –4 mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode.
For pin DRV_VOUT in external
SID30B IOH4B_ABS Source maximum current[40] – – –25 mA
transistor mode.
For pin EXT_PS_CTL1 in
external PMIC mode and
SID30C IOH4C_ABS Source average current[41] – – –1 mA internal regulator mode and
pin EXT_PS_CTL2 in external
PMIC mode.
For pin DRV_VOUT in external
SID30D IOH4D_ABS Source average current[41] – – –12 mA
transistor mode.
[44]
SID33A ∑IOH_ABS_GPIO HIGH-level total output current – – –50 mA
SID33B ∑IOH_ABS_HSIO HIGH-level total output current[43] – – –85 mA
SID33D PIO Total output power dissipation[44] – – 307 mW
Power dissipation for external
SID34 PD – – 1000 mW TJ should not exceed 150 °C
PMIC/transistor mode
Power dissipation for internal regulator
SID34A PD – – 2000 mW TJ should not exceed 150 °C
mode
SID35 TA Ambient temperature –40 – 105 °C For S-grade devices
SID36 TA Ambient temperature –40 – 125 °C For E-grade devices
SID37 TSTG Storage temperature –55 – 150 °C
SID38 TJ Operating Junction temperature –40 – 150 °C
SID39A VESD_HBM Electrostatic discharge human body 2000 – – V
model
SID39B1 VESD_CDM1 Electrostatic discharge charged device 750 – – V
model for corner pins
SID39B2 VESD_CDM2 Electrostatic discharge charged device 500 – – V
model for all other pins
SID39C ILU The maximum pin current the device –100 – 100 mA
can tolerate before triggering a latch-up

VDDD or VDDIO

Current
Protection limiting
Diode resistor

+B input
Protection
Diode

VSS

Figure 27-1 Example of a recommended circuit[45]

WARNING:
Semiconductor devices may be permanently damaged by application of stress (including, without limitation, voltage, current, or
temperature) in excess of absolute maximum ratings. Do not exceed any of these ratings.
Notes
44.The total output power dissipation is the maximum power dissipation flowing through all I/Os. PIO = (VDDD,VDDIO_1,VDDIO_2) ×
(|∑IOH_ABS_GPIO| + |∑IOL_ABS_GPIO|) + (VDDIO_3, VDDIO_4) × (|∑IOH_ABS_HSIO| + |∑IOL_ABS_HSIO|)
45.+B is the positive battery voltage around 45 V.

Datasheet 113 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.2 Device-level specifications

Table 27-2 Recommended operating conditions
Spec ID Parameter Description Min Typ Max Units Details/Conditions
VDDD, VDDA,
SID40 VDDIO_1, Power supply voltage[46] 2.7[47] – 5.5[48] V
VDDIO_2,
Power supply voltage for
SID40A VDDIO_1_EFP eFuse programming[49] 3 – 5.5 V

SID40B VDDIO_3, Power supply voltage 2.7 – 3.6 V

VDDIO_4
External VCCD power
supply range when
SID40C VCCD External VCCD power supply 1.10 1.15 1.20 V
externally supplying
VCCD
SID41 CS1 Smoothing capacitor[50, 51] 6.79 – 22 µF

VCCD VREF_L

CS1 VSSD VSSA

Single-point connection
between analog and
digital grounds

Figure 27-2 Smoothing capacitor

Smoothing capacitor should be placed as close as possible to the VCCD pin.

Notes
46.VDDD, VDDIO_1, VDDIO_2, VDDIO_3, VDDIO_4, and VDDA do not have any sequencing limitation and can establish in any order. These supplies (except
VDDA and VDDIO_2) are independent in voltage level. See 12-Bit SAR ADC DC Specifications when using ADC units.
47.3.0 V ±10% is supported with a lower BOD setting option for VDDD and VDDA. This setting provides robust protection for internal timing but
BOD reset occurs at a voltage below the specified operating conditions. A higher BOD setting option is available (consistent with down to
3.0 V) and guarantees that all operating conditions are met.
48.5.0 V ±10% is supported with a higher OVD setting option for VDDD and VDDA. This setting provides robust protection for internal and interface
timing, but OVD reset occurs at a voltage above the specified operating conditions. A lower OVD setting option is available (consistent with
up to 5.0 V) and guarantees that all operating conditions are met. Voltage overshoot to a higher OVD setting range for VDDD and VDDA is
permissible, provided the duration is less than 2 hours cumulated. Note that during overshoot voltage condition electrical parameters are
not guaranteed.
49.eFuse programming must be executed with the part in a “quiet” state, with minimal activity (preferably only JTAG or a single LIN/CAN channel
on VDDD domain, no activity on VDDIO_1).
50.Smoothing capacitor, CS1 is required per chip (not per VCCD pin). The VCCD pins must be connected together to ensure a low-impedance
connection (see the requirement in Figure 27-2).
51.Capacitors used for power supply decoupling or filtering are operated under a continuous DC-bias. Many capacitors used with DC power
across them provide less than their target capacitance, and their capacitance is not constant across their working voltage range. When
selecting capacitors for use with this device, ensure that the selected components provide the required capacitance under the specific
operating conditions of temperature and voltage used in your design. While the temperature coefficient is normally found within a part’s
catalog (such as, X7R, C0G, Y5V), the matching voltage coefficient may only be available on the component datasheet or direct from the
manufacturer. Use of components that do not provide the required capacitance under the actual operating conditions may cause the device
to operate to less than datasheet specifications.

Datasheet 114 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.3 DC specifications
Table 27-3 DC specifications, CPU current, and transition time specifications
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Active/Sleep mode
CM0+ and CM7_0 clocked at 8 MHz
with IMO.
CM7_1 powered off.
VDDD current in internal All peripherals are disabled. No IO
regulator mode, LPACTIVE toggling. CPUs CM7_0 and CM0+
IDD_VDDD_CM0 mode
SID49C1 – 10 17 mA executing Dhrystone from flash
7_8_1 (CM0+ and CM7_0 at 8 MHz, all with cache enabled.
peripherals are disabled) Typ: TA = 25 °C, VDDD = 5.0 V,
process typ (TT)
Max: TA = 25 °C, VDDD = 5.5 V,
process worst (FF)
CM0+ and CM7_0 clocked at 8 MHz
with IMO.
CM7_1 powered off.
All peripherals are enabled. No IO
toggling.
VDDD current in internal M-DMA transferring data from
regulator mode, LPACTIVE code + work flash, P-DMA chains
IDD_VDDD_CM0
SID49C mode – 12 226 mA with maximum trigger activity.
7_8 (CM0+ and CM7_0 at 8 MHz, all CPUs CM7_0 and CM0+ executing
peripherals are enabled) Dhrystone from flash with cache
enabled.
Typ: TA = 25 °C, VDDD = 5.0 V,
process typ (TT)
Max: TA = 105 °C, VDDD = 5.5 V,
process worst (FF)
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
CM7_1 powered off.
VCCD current in external M-DMA transferring data from
PMIC/transistor mode, Active code + work flash, P-DMA chains
IDD1_VC-
SID49E1 mode (CM7_0 at – 155 431 mA with maximum trigger activity.
CD_CM7_350 350 MHz, CM0+ at 100 MHz, all CPUs CM7_0 and CM0+ executing
peripherals are enabled) Dhrystone from flash with cache
enabled.
Typ: TA = 25 °C, VCCD = 1.15 V,
process typ (TT)
Max: TA = 125 °C, VCCD = 1.20 V,
process worst (FF)

Datasheet 115 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-3 DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter Description Min Typ Max Units Details/Conditions
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
CM7_1 powered off.
VDDD current in external M-DMA transferring data from
PMIC/transistor mode, Active code + work flash, P-DMA chains
IDD1_-
SID49E2 mode (CM7_0 at – 7 9 mA with maximum trigger activity.
VDDD_CM7_350 350 MHz, CM0+ at 100 MHz, all
CPUs CM7_0 and CM0+ executing
peripherals are enabled) Dhrystone from flash with cache
enabled.
Typ: TA = 25 °C, VDDD = 5.0 V,
process typ (TT)
Max: TA = 125 °C, VDDD = 5.5 V,
process worst (FF)
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
M-DMA transferring data from
VCCD current in external code + work flash, P-DMA chains
PMIC/transistor mode, Active with maximum trigger activity.
SID50A1 IDD1_VCCD_F mode (CM7 CPUs at 350 MHz, – 209 543 mA
CM0+ at 100 MHz, all periph- CM7 CPUs and CM0+ executing
erals are enabled) Dhrystone from flash with cache
enabled.
Typ: TA = 25 °C, VCCD = 1.15 V,
process typ (TT)
Max: TA = 125 °C, VCCD = 1.20 V,
process worst (FF)
PLL enabled at 350 MHz with ECO
reference.
All peripherals are enabled. No IO
toggling.
M-DMA transferring data from
VDDD current in external code + work flash, P-DMA chains
PMIC/transistor mode, Active with maximum trigger activity.
SID50A2 IDD1_VDDD_F mode (CM7 CPUs at 350 MHz, – 7 9.3 mA
CM0+ at 100 MHz, all periph- CM7 CPUs and CM0+ executing
erals are enabled) Dhrystone from flash with cache
enabled.
Typ: TA = 25 °C, VDDD = 5.0 V,
process typ (TT)
Max: TA = 125 °C, VDDD = 5.5 V,
process worst (FF)
IMO clocked at 8 MHz.
All peripherals, PLL, FLL,
peripheral clocks, interrupts, CSV,
VDDD current in internal DMA are disabled. No IO toggling.
SID53A IDD2_8_VDDD regulator mode. CM7_1=OFF, – 7 218 mA
Other CPUs in Sleep. Typ: TA = 25 °C, VDDD = 5.0 V,
process typ (TT)
Max: TA = 105 °C, VDDD = 5.5 V,
process worst (FF)

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-3 DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter Description Min Typ Max Units Details/Conditions
TA = 25 °C, 64-KB SRAM retention,
Event generator operates with
ILO0 in DeepSleep and LP Active,
Smart I/O operates with ILO0,
CM0+, CM7_0: Retained,
CM7_1: OFF.
Typ: VDDD = 5.0 V,
process typ (TT)
Max: VDDD = 5.5 V,
process worst (FF)
This average current is achieved
under the following conditions.
1. MCU repetitively goes from
DeepSleep to LP Active with a
Average current for cyclic
wake-up operation. This is the period of 32 ms.
average current for the 2. One of the I/Os is toggled using
SID58A IDD_CWU2 specified LPACTIVE mode and – 60 198 µA Smart I/O to activate an external
DeepSleep mode (RTC, WDT, sensor connected to an analog
and Event Generator input of A/D in DeepSleep
operating).
3. After 200 µs delay, the CM7_0
wakes up by Event generator
trigger to LP Active mode with IMO
and A/D conversion is triggered by
software.
4. Group A/D conversion is
performed on 5 channels with the
sampling time of 1 µs each.
5. Once the group A/D conversion
is finished, and the results fit in the
window of the range comparator,
the I/O is toggled back by software
to de-activate the sensor and the
CM7_0 goes back to DeepSleep.
DeepSleep mode
DeepSleep Mode (RTC, WDT, and
event generator operating, all
other peripherals are off except for
retention registers),
64-KB SRAM retention, ILO0
SID64A IDD_DS64A operation
– 50 176 µA CM0+, CM7_0: Retained
TA = 25 °C
Typ: VDDD = 5.0 V, process typ (TT)
Max: VDDD = 5.5 V,
process worst (FF)
DeepSleep Mode steady state at TA
= 125 °C (RTC, WDT, and event
generator operating, all other
peripherals are off except for
64 KB SRAM retention, ILO0 retention registers),
SID64C IDD_DS64C operation
– 1.4 5.5 mA CM0+, CM7_0: Retained
Typ: VDDD = 5.0 V, process worst
(TT)
Max: VDDD = 5.5 V, process worst
(FF)

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-3 DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Hibernate mode
ILO0/WDT operating. All other
peripherals, and all CPUs are off.
SID66 IDD_HIB1 Hibernate Mode – 8 – µA TA = 25 °C, VDDD = 5.0 V,
Process typ (TT)
ILO0/WDT operating. All other
peripherals, and all CPUs are off.
SID66A IDD_HIB2 Hibernate Mode – – 180 µA TA = 125 °C, VDDD = 5.5 V,
Process worst (FF)
Power mode transition times
When the IMO is already running and
Power down time from Active all HFCLK roots are at least 8 MHz.
SID69 tACT_DS to DeepSleep
– – 2.8 µs HFCLK roots that are slower than
this will require additional time to
turn off.

DeepSleep to Active transition When using the 8-MHz IMO.

SID67 tDS_ACT – – 10[52] µs Measured from wakeup interrupt
time (IMO clock) during DeepSleep until wakeup.
When using the 8-MHz IMO.
DeepSleep to Active transition Measured from wakeup interrupt
SID67C tDS_ACT1 time (IMO clock, flash – – 26[52] µs
during DeepSleep until flash
execution) execution.
When using the FLL to generate
96 MHz from the 8-MHz IMO.
DeepSleep to Active transition
SID67A tDS_ACT_FLL time (FLL clock) – – 15[52] µs Measured from wakeup interrupt
during DeepSleep until the FLL
locks.
When using the FLL to generate
DeepSleep to Active transition 96 MHz from the 8-MHz IMO.
SID67D tDS_ACT_FLL1 time (FLL clock, flash – – 26[52] µs Measured from wakeup interrupt
execution) during DeepSleep until flash
execution.
When using the PLL to generate
96 MHz from the 8-MHz IMO.
DeepSleep to Active transition
SID67B tDS_ACT_PLL – – 60[52] µs Measured from wakeup interrupt
time (PLL clock) during DeepSleep until the PLL
locks.
Release time from HV reset
(POR, BOD, OVD, OCD, WDT,
Without boot runtime, guaranteed
SID68 tHVR_ACT Hibernate wakeup, or XRES_L) – – 265 µs
by design
release until CM0+ begins
executing ROM boot
Release time from LV reset
(Fault, Internal system reset,
Without boot runtime.
SID68A tLVR_ACT MCWDT, or CSV) during – – 10 µs
Guaranteed by design
Active/Sleep until CM0+ begins
executing ROM boot
Release time from LV reset
(Fault, or MCWDT) during Without boot runtime.
SID68B tLVR_DS DeepSleep until CM0+ begins – – 15 µs
Guaranteed by design
executing ROM boot

Note
52.At cold temperature –5 °C to –40 °C, the DeepSleep to Active transition time can be higher than the max time indicated by as much
as 20 µs.

Datasheet 118 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-3 DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter Description Min Typ Max Units Details/Conditions
ROM boot startup time or Guaranteed by Design, CM0+
SID80A tRB_N wakeup time from hibernate in – – 1640 µs clocked at 100 MHz (Flash boot
NORMAL protection state version 3.1.0.554 and later)
ROM boot startup time or Guaranteed by Design, CM0+
SID80B tRB_S wakeup time from hibernate in – – 2330 µs clocked at 100 MHz (Flash boot
SECURE protection state version 3.1.0.554 and later)
Guaranteed by Design,
Flash boot startup time or
TOC2_FLAGS=0x2CF, CM0+
wakeup time from hibernate in
SID81A tFB NORMAL/SECURE protection
– – 80 µs clocked at 100 MHz (Flash boot
version 3.1.0.554 and later),
state
Listen window = 0 ms
SID81B tFB_A Flash boot with app – – 5000 µs Guaranteed by Design,
authentication time in TOC2_FLAGS=0x24F, CM0+
NORMAL/SECURE protection clocked at 100 MHz (Flash boot
state version 3.1.0.554 and later),
Listen window = 0 ms, Public key
exponent e = 0x010001, App size is
64 KB with the last 256 bytes being
a digital signature in
RSASSA-PKCS1-v1.5
Valid for RSA-2048.
ROM boot startup time or Guaranteed by design, CM0+
SID80A_2 tRB_N_2 wakeup time from hibernate in – – 2640 µs clocked at 50 MHz (Flash boot
NORMAL protection state version earlier than 3.1.0.554)
ROM boot startup time or Guaranteed by design, CM0+
SID80B_2 tRB_S_2 wakeup time from hibernate in – – 3890 µs clocked at 50 MHz (Flash boot
SECURE protection state version earlier than 3.1.0.554)
Guaranteed by design,
Flash boot startup time or TOC2_FLAGS=0x2CF, CM0+
wakeup time from hibernate in
SID81A_2 tFB_2 NORMAL/SECURE protection
– – 200 µs clocked at 50 MHz (Flash boot
version earlier than 3.1.0.554),
state Listen window = 0 ms
SID81B_2 tFB_A_2 Flash boot with app – – 10000 µs Guaranteed by design,
authentication time in TOC2_FLAGS=0x24F, CM0+
NORMAL/SECURE protection clocked at 50 MHz (Flash boot
state version earlier than 3.1.0.554),
Listen window = 0 ms, Public key
exponent e = 0x010001, App size is
64 KB with the last 256 bytes being
a digital signature in
RSASSA-PKCS1-v1.5
Valid for RSA-2048.
Regulator specifications
Core supply voltage (transient
SID600 VCCD 1.05 1.1 1.15 V
range)
Core supply voltage (static
SID600A VCCD_S 1.075 1.1 1.125 V Guaranteed by design
range, no load)
Regulator operating current in
SID601 IDDD_ACT Active/Sleep mode
– 900 1500 µA Guaranteed by design

Regulator operating current in

SID602 IDDD_DPSLP – 1.5 20 µA Guaranteed by design
DeepSleep mode
Average VDDD current until Cs1
SID603 IRUSH In-rush current – – 850 mA (connected to VCCD pin) is charged
after Active regulator is turned on
Internal regulator output
SID604 IILDOUT – – 300 mA
current for operation

Datasheet 119 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-3 DC specifications, CPU current, and transition time specifications (continued)
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Spec ID Parameter Description Min Typ Max Units Details/Conditions
High current regulator output
SID605 IHCROUT – – 600 mA Using an external pass transistor
current for operation
Output voltage LOW level for
SID606 VOL_HCR external PMIC enable output – – 0.5 V IOL = 1 mA
(EXT_PS_CTL1)
Output voltage HIGH level for
VDDD –
SID606A VOH_HCR external PMIC enable output
0.5
– – V IOH = –1 mA
(EXT_PS_CTL1)
Input voltage HIGH threshold
0.7 ×
SID607 VIH_HCR for external PMIC power OK
VDDD – – V
input (EXT_PS_CTL0)
Input voltage LOW threshold
0.3 ×
SID607A VIL_HCR for external PMIC power OK – – V
VDDD
input (EXT_PS_CTL0)
Hysteresis for external PMIC 0.05 ×
SID607B VHYS_HCR – – V
power OK input (EXT_PS_CTL0) VDDD
DRV_VOUT pin output current See Architecture TRM for external
SID608 IDRV_VOUT to external NPN base current – – 9 mA NPN transistor selection

27.4 Reset specifications

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.

Table 27-4 XRES_L reset

Spec ID Parameter Description Min Typ Max Units Details/Conditions
XRES_L DC specifications
MAX: TA = 125 °C,
VDDD = 5.5 V,
SID73 IIDD_XRES IDD when XRES_L asserted – – 2.5 mA V
CCD = 1.15 V,
process worst (FF)
Input voltage HIGH
SID74 VIH 0.7 × VDDD – – V CMOS Input
threshold
Input voltage LOW
SID75 VIL – – 0.3 × VDDD V CMOS Input
threshold
SID76 RPULLUP Pull-up resistor 7 – 20 kΩ
SID77 CIN Input capacitance – – 5 pF
SID78 VHYSXRES Input voltage hysteresis 0.05 × VDDD – – V
XRES_L AC specifications
Without boot
SID70 tXRES_ACT XRES_L deasserted to – – 265 µs runtime, guaranteed
Active transition time
by design
SID71 tXRES_PW XRES_L pulse width 5 – – µs
SID72 tXRES_FT Pulse suppression width 100 – – ns

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

HV/LV reset release

System clock

System reset release

MODES RESET ACTIVE

1 2 3 4

1: SID68/68A/68B: Time from HV/LV reset release until CM0+ begins executing ROM boot
2: SID80A/80B: ROM boot code operation
3: SID81A/81B: Flash boot code operation
4: User code operation

Figure 27-3 Reset sequence

Datasheet 121 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.5 I/O
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-5 I/O specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
GPIO_STD Specifications for ports P1 through P23, P28 to P32
IOL = 6 mA
drive_sel<1:0> = 0b0X,
SID650 VOL1_GPIO_STD Output voltage LOW level – – 0.6 V
4.5 V ≤ VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
IOL = 5 mA
drive_sel<1:0> = 0b0X,
SID650C VOL1C_GPIO_STD Output voltage LOW level – – 0.4 V 4.5 V ≤ VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
IOL = 2 mA
drive_sel<1:0> = 0b0X,
SID651 VOL2_GPIO_STD Output voltage LOW level – – 0.4 V
2.7 V ≤ VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
IOL = 1 mA
drive_sel<1:0> = 0b10,
SID652 VOL3_GPIO_STD Output voltage LOW level – – 0.4 V
2.7 V ≤ VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
IOL = 2 mA
drive_sel<1:0> = 0b10,
SID652C VOL3C_GPIO_STD Output voltage LOW level – – 0.4 V 4.5 V ≤ VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
IOL = 0.5 mA
drive_sel<1:0> = 0b11,
SID653 VOL4_GPIO_STD Output voltage LOW level – – 0.4 V
2.7 V ≤ VDDD or VDDIO_1 or
VDDIO_2 < 4.5 V
IOL = 1 mA
drive_sel<1:0> = 0b11,
SID653C VOL4C_GPIO_STD Output voltage LOW level – – 0.4 V
4.5 V ≤ VDDD or VDDIO_1 or
VDDIO_2 ≤ 5.5 V
(VDDD, IOH = –2 mA
VDDIO_1, or drive_sel<1:0> = 0b0X,
SID654 VOH1_GPIO_STD Output voltage HIGH level – – V
VDDIO_2) – 2.7 V ≤ VDDD or VDDIO_1 or
0.5 VDDIO_2 < 4.5 V
(VDDD, IOH = –5 mA
SID655 VOH2_GPIO_STD Output voltage HIGH level VDDIO_1, or – – V drive_sel<1:0> = 0b0X,
VDDIO_2) – 4.5 V ≤ VDDD or VDDIO_1 or
0.5 VDDIO_2 ≤ 5.5 V
(VDDD, IOH = –1 mA
VDDIO_1, or drive_sel<1:0> = 0b10,
SID656 VOH3_GPIO_STD Output voltage HIGH level – – V
VDDIO_2) – 2.7 V ≤ (VDDD, VDDIO_1, or
0.5 VDDIO_2) < 4.5 V
(VDDD, IOH = –2 mA
VDDIO_1, or drive_sel<1:0> = 0b10,
SID656C VOH3C_GPIO_STD Output voltage HIGH level – – V
VDDIO_2) – 4.5 V ≤ (VDDD, VDDIO_1, or
0.5 VDDIO_2) ≤ 5.5 V
(VDDD, IOH = –0.5 mA
SID657 VOH4_GPIO_STD Output voltage HIGH level VDDIO_1, or – – V drive_sel<1:0> = 0b11,
VDDIO_2) – 2.7 V ≤ (VDDD, VDDIO_1, or
0.5 VDDIO_2) < 4.5 V
(VDDD, IOH = –1 mA
VDDIO_1, or drive_sel<1:0> = 0b11,
SID657C VOH4C_GPIO_STD Output voltage HIGH level – – V
VDDIO_2) – 4.5 V ≤ (VDDD, VDDIO_1, or
0.5 VDDIO_2) ≤ 5.5 V
SID658 RPD_GPIO_STD Pull-down resistance 25 50 100 kΩ
SID659 RPU_GPIO_STD Pull-up resistance 25 50 100 kΩ
0.7 × (VDDD,
SID660 VIH_CMOS_GPIO_STD Input voltage HIGH threshold V
in CMOS mode DDIO_1, or – – V
VDDIO_2)
Input voltage HIGH threshold
SID661 VIH_TTL_GPIO_STD in TTL mode 2.0 – – V

0.8 × (VDDD,
Input voltage HIGH threshold
SID662 VIH_AUTO_GPIO_STD VDDIO_1, or – – V
in AUTO mode VDDIO_2)

Datasheet 122 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-5 I/O specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
0.3 ×
Input voltage LOW threshold (VDDD,
SID663 VIL_CMOS_GPIO_STD – – V
in CMOS mode VDDIO_1, or
VDDIO_2)
Input voltage LOW threshold
SID664 VIL_TTL_GPIO_STD – – 0.8 V
in TTL mode
0.5 ×
Input voltage LOW threshold (VDDD,
SID665 VIL_AUTO_GPIO_STD – – V
in AUTO mode VDDIO_1, or
VDDIO_2)
0.05 × (VDDD,
SID666 VHYST_CMOS_GPIO_STD Hysteresis in CMOS mode VDDIO_1, or – – V
VDDIO_2)
0.05 × (VDDD,
SID668 VHYST_AUTO_GPIO_STD Hysteresis in AUTO mode VDDIO_1, or – – V
VDDIO_2)
SID669 Cin_GPIO_STD Input pin capacitance – – 5 pF For 10 MHz and 100 MHz
For GPIO_STD except P21.0,
P21.1, P21.2, P21.3, P21.4, P22.1,
P22.2, P22.3, P23.3, P23.4.
VDDIO_1 = VDDIO_2 = VDDD = VDDA =
SID670 IIL_GPIO_STD Input leakage current –250 0.02 250 nA 5.5 V,
VSSD < VI < VDDD, VDDIO_1, VDDIO_2
–40 °C  TA  125 °C
Typ: TA = 25 °C, VDDIO_1 = VDDIO_2 =
VDDD = VDDA = 5.0 V
Only for P21.0, P21.1, P21.2,
P21.3, P21.4, P22.1, P22.2, P22.3,
P23.3, P23.4.
VDDIO_1 = VDDIO_2 = VDDD = VDDA =
SID670C IIL_GPIO_STD_B Input leakage current –700 0.02 700 nA 5.5 V,
VSSD < VI < VDDD, VDDIO_1, VDDIO_2
–40 °C  TA  125 °C
Typ: TA = 25 °C, VDDIO_1 = VDDIO_2 =
VDDD = VDDA = 5.0 V

SID671 tR or tF (fast)_20_0_GPI- Rise time or fall time (10% to 1 – 10 ns 20-pF load, drive_sel<1:0> = 0b00
O_STD 90% of VDDIO)
tR or tF (fast)_50_0_GPI- Rise time or fall time (10% to
SID672 1 – 20 ns 50-pF load, drive_sel<1:0> = 0b00
O_STD 90% of VDDIO)
tR or tF (fast)_20_1_GPI- Rise time or fall time (10% to
SID673 1 – 20 ns 20-pF load, drive_sel<1:0> = 0b01
O_STD 90% of VDDIO)

SID674 tR or tF (fast)_10_2_GPI- Rise time or fall time (10% to 1 – 20 ns 10-pF load, drive_sel<1:0> = 0b10
O_STD 90% of VDDIO)
tR or tF (fast)_6_3_GPI- Rise time or fall time (10% to
SID675 1 – 20 ns 6-pF load, drive_sel<1:0> = 0b11
O_STD 90% of VDDIO)
10-pF to 400-pF load, RPU = 767 Ω,
Fall time (30% to 70% of
SID676 tF (fast)_100_GPIO_STD 0.35 – 250 ns drive_sel<1:0>= 0b00,
VDDIO)
Freq = 100 kHz
10-pF to 400-pF load, RPU = 350 Ω,
Fall time (30% to 70% of
SID677 tF (fast)_400_GPIO_STD 0.35 – 250 ns drive_sel<1:0>= 0b00,
VDDIO)
Freq = 400 kHz
SID678 fIN_GPIO_STD Input frequency – – 100 MHz
20-pF load,
drive_sel<1:0>= 00,
SID679 fOUT_GPIO_STD0H Output frequency – – 50 MHz
4.5 V ≤ VDDD or VDDIO_1 or VDDIO_2
≤ 5.5 V
20-pF load,
drive_sel<1:0>= 00,
SID680 fOUT_GPIO_STD0L Output frequency – – 32 MHz
2.7 V ≤ VDDD or VDDIO_1 or VDDIO_2
< 4.5 V

Datasheet 123 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-5 I/O specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
20-pF load,
drive_sel<1:0>= 01,
SID681 fOUT_GPIO_STD1H Output frequency – – 25 MHz
4.5 V ≤ VDDD or VDDIO_1 or VDDIO_2
≤ 5.5 V
20-pF load,
drive_sel<1:0>= 01,
SID682 fOUT_GPIO_STD1L Output frequency – – 15 MHz
2.7 V ≤ VDDD or VDDIO_1 or VDDIO_2
< 4.5 V
10-pF load,
drive_sel<1:0>= 10,
SID683 fOUT_GPIO_STD2H Output frequency – – 25 MHz
4.5 V ≤ VDDD or VDDIO_1 or VDDIO_2
≤ 5.5 V
10-pF load,
drive_sel<1:0>= 10,
SID684 fOUT_GPIO_STD2L Output frequency – – 15 MHz
2.7 V ≤ VDDD or VDDIO_1 or VDDIO_2
< 4.5 V
6-pF load,
drive_sel<1:0>= 11,
SID685 fOUT_GPIO_STD3H Output frequency – – 15 MHz
4.5 V ≤ VDDD or VDDIO_1 or VDDIO_2
≤ 5.5 V
6-pF load,
drive_sel<1:0>= 11,
SID686 fOUT_GPIO_STD3L Output frequency – – 10 MHz
2.7 V ≤ VDDD or VDDIO_1 or VDDIO_2
< 4.5 V
GPIO_ENH Specifications for P0
IOL = 6 mA
SID650A VOL1_GPIO_ENH Output voltage LOW level – – 0.6 V drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD ≤ 5.5 V
IOL = 5 mA
SID650D VOL1D_GPIO_ENH Output voltage LOW level – – 0.4 V drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD ≤ 5.5 V
IOL = 2 mA
SID651A VOL2_GPIO_ENH Output voltage LOW level – – 0.4 V drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD < 4.5 V
IOL = 1 mA
SID652A VOL3_GPIO_ENH Output voltage LOW level – – 0.4 V drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD < 4.5 V
IOL = 2 mA
SID652D VOL3D_GPIO_ENH Output voltage LOW level – – 0.4 V drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
IOL = 0.5 mA
SID653A VOL4_GPIO_ENH Output voltage LOW level – – 0.4 V drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD < 4.5 V
IOL = 1 mA
SID653D VOL4D_GPIO_ENH Output voltage LOW level – – 0.4 V drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
IOH = –2 mA
SID654A VOH1_GPIO_ENH Output voltage HIGH level VDDD – 0.5 – – V drive_sel<1:0> = 0b0X,
2.7 V ≤ VDDD < 4.5 V
IOH = –5 mA
SID655A VOH2_GPIO_ENH Output voltage HIGH level VDDD – 0.5 – – V drive_sel<1:0> = 0b0X,
4.5 V ≤ VDDD ≤ 5.5 V
IOH = –1 mA
SID656A VOH3_GPIO_ENH Output voltage HIGH level VDDD – 0.5 – – V drive_sel<1:0> = 0b10,
2.7 V ≤ VDDD < 4.5 V
IOH = –2 mA
SID656D VOH3D_GPIO_ENH Output voltage HIGH level VDDD – 0.5 – – V drive_sel<1:0> = 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
IOH = –0.5 mA
SID657A VOH4_GPIO_ENH Output voltage HIGH level VDDD – 0.5 – – V drive_sel<1:0> = 0b11,
2.7 V ≤ VDDD < 4.5 V

Datasheet 124 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-5 I/O specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
IOH = –1 mA
SID657D VOH4D_GPIO_ENH Output voltage HIGH level VDDD – 0.5 – – V drive_sel<1:0> = 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
SID658A RPD_GPIO_ENH Pull-down resistance 25 50 100 kΩ
SID659A RPU_GPIO_ENH Pull-up resistance 25 50 100 kΩ
Input voltage HIGH threshold
SID660A VIH_CMOS_GPIO_ENH 0.7 × VDDD – – V
in CMOS mode
Input voltage HIGH threshold
SID661A VIH_TTL_GPIO_ENH 2.0 – – V
in TTL mode
Input voltage HIGH threshold
SID662A VIH_AUTO_GPIO_ENH in AUTO mode 0.8 × VDDD – – V

Input voltage LOW threshold

SID663A VIL_CMOS_GPIO_ENH – – 0.3 × VDDD V
in CMOS mode
Input voltage LOW threshold
SID664A VIL_TTL_GPIO_ENH – – 0.8 V
in TTL mode
Input voltage LOW threshold
SID665A VIL_AUTO_GPIO_ENH in AUTO mode – – 0.5 × VDDD V

SID666A VHYST_CMOS_GPIO_ENH Hysteresis in CMOS mode 0.05 × VDDD – – V

SID668A VHYST_AUTO_GPIO_ENH Hysteresis in AUTO mode 0.05 × VDDD – – V
SID669A Cin_GPIO_ENH Input pin capacitance – – 5 pF For 10 MHz and 100 MHz
VDDD = VDDA = 5.5 V,
VSSD < VI < VDDD
SID670A IIL_GPIO_ENH Input leakage current –350 0.055 350 nA –40 °C  TA  125 °C
Typ: TA = 25 °C,
VDDD = VDDA = 5.0 V
tR or tF (fast)_20_0_GPI- Rise time or fall time (10% to 20-pF load, drive_sel<1:0> = 0b00,
SID671A 1 – 10 ns
O_ENH 90% of VDDIO) slow = 0
tR or tF (fast)_50_0_GPI- Rise time or fall time (10% to 50-pF load, drive_sel<1:0> = 0b00,
SID672A 1 – 20 ns
O_ENH 90% of VDDIO) slow = 0
tR or tF (fast)_20_1_GPI- Rise time or fall time (10% to 20-pF load, drive_sel<1:0> = 0b01,
SID673A 1 – 20 ns
O_ENH 90% of VDDIO) slow = 0
tR or tF (fast)_10_2_GPI- Rise time or fall time (10% to 10-pF load, drive_sel<1:0> = 0b10,
SID674A 1 – 20 ns
O_ENH 90% of VDDIO) slow = 0
tR or tF (fast)_6_3_GPI- Rise time or fall time (10% to 6-pF load, drive_sel<1:0> = 0b11,
SID675A 1 – 20 ns
O_ENH 90% of VDDIO) slow = 0
10-pF to 400-pF load,
Fall time (30% to 70% of 20 × (VDDD /
SID676A tF_I2C (slow)_GPIO_ENH – 250 ns drive_sel<1:0> = 0b00,
VDDIO) 5.5)
slow = 1, minimum RPU = 400 Ω
20-pF load, drive_sel<1:0> = 0b00,
tR or tF (slow)_20_GPI- Rise time or fall time (10% to 20 × (VDDD /
SID677A – 160 ns slow = 1,
O_ENH 90% of VDDIO) 5.5)
output frequency = 1 MHz
400-pF load, drive_sel<1:0> =
tR or tF (slow)_400_GPI- Rise time or fall time (10% to 20 × (VDDD /
SID678A 90% of VDDIO) 5.5) – 250 ns 0b00, slow = 1,
O_ENH
output frequency = 400 kHz
SID679A fIN_GPIO_ENH Input frequency – – 100 MHz
20-pF load,
SID680A fOUT_GPIO_ENH0H Output frequency – – 50 MHz drive_sel<1:0>= 0b00,
4.5 V ≤ VDDD ≤ 5.5 V
20-pF load,
SID681A fOUT_GPIO_ENH0L Output frequency – – 32 MHz drive_sel<1:0>= 0b00,
2.7 V ≤ VDDD < 4.5 V
20-pF load,
SID682A fOUT_GPIO_ENH1H Output frequency – – 25 MHz drive_sel<1:0>= 0b01,
4.5 V ≤ VDDD ≤ 5.5 V
20-pF load,
SID683A fOUT_GPIO_ENH1L Output frequency – – 15 MHz drive_sel<1:0>= 0b01,
2.7 V ≤ VDDD < 4.5 V

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Electrical specifications

Table 27-5 I/O specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
10-pF load,
SID684A fOUT_GPIO_ENH2H Output frequency – – 25 MHz drive_sel<1:0>= 0b10,
4.5 V ≤ VDDD ≤ 5.5 V
10-pF load,
SID685A fOUT_GPIO_ENH2L Output frequency – – 15 MHz drive_sel<1:0>= 0b10,
2.7 V ≤ VDDD < 4.5 V
6-pF load,
SID686A fOUT_GPIO_ENH3H Output frequency – – 15 MHz drive_sel<1:0>= 0b11,
4.5 V ≤ VDDD ≤ 5.5 V
6-pF load,
SID687A fOUT_GPIO_ENH3L Output frequency – – 10 MHz drive_sel<1:0>= 0b11,
2.7 V ≤ VDDD < 4.5 V
HSIO Specifications for ports P24 through P27, P33, P34
IOL = 4 mA,
SID650B VOL_GMII Output LOW voltage – – 0.6 V
drive_sel<1:0> = 0b00
IOL = 0.1 mA,
SID651B VOL_HB_HSSPI Output LOW voltage – – 0.2 V
drive_sel<1:0> = 0b00
0.125 × IOL = 0.1 mA,
SID652B VOL_eMMC Output LOW voltage – – V
VDDIO_3/4 drive_sel<1:0> = 0b00
0.125 × IOL = 2 mA,
SID653B VOL_SD Output LOW voltage – – VDDIO_3/4 V
drive_sel<1:0> = 0b00
IOL = 10 mA,
SID654B VOL1 Output LOW voltage – – 0.4 V drive_sel<1:0> = 0b00,
VDDIO_3/4 = 2.7 V
IOL = 2 mA,
SID655B VOL2 Output LOW voltage – – 0.4 V drive_sel<1:0> = 0b01,
VDDIO_3/4 = 2.7 V
IOL = 1 mA,
SID656B VOL3 Output LOW voltage – – 0.4 V drive_sel<1:0> = 0b10,
VDDIO_3/4 = 2.7 V
IOL = 0.5 mA,
SID656E VOL4 Output LOW voltage – – 0.4 V drive_sel<1:0> = 0b11,
VDDIO_3/4 = 2.7 V
VDDIO_3/4 – IOH = –4 mA
SID657B VOH_GMII Output HIGH voltage – – V
0.6 drive_sel<1:0> = 0b00
VDDIO_3/4 – IOH = –0.1 mA
SID658B VOH_HB_HSSPI Output HIGH voltage – – V
0.2 drive_sel<1:0> = 0b00
VDDIO_3/4 – IOH = –0.1 mA
SID659B VOH_eMMC Output HIGH voltage (0.25 × – – V
VDDIO_3/4) drive_sel<1:0> = 0b00
VDDIO_3/4 – IOH = –2 mA
SID660B VOH_SD Output HIGH voltage (0.25 × – – V
VDDIO_3/4) drive_sel<1:0> = 0b00
IOH = –10 mA
VDDIO_3/4 –
SID661B VOH1 Output HIGH voltage – – V drive_sel<1:0> = 0b00,
0.5
VDDIO_3/4 = 2.7 V
IOH = –2 mA
VDDIO_3/4 –
SID662B VOH2 Output HIGH voltage – – V drive_sel<1:0> = 0b01,
0.5
VDDIO_3/4 = 2.7 V
IOH = –1 mA
SID663B VOH3 Output HIGH voltage VDDIO_3/4 – – – V drive_sel<1:0> = 0b10,
0.5
VDDIO_3/4 = 2.7 V
IOH = –0.5 mA
VDDIO_3/4 –
SID663E VOH3 Output HIGH voltage – – V drive_sel<1:0> = 0b11,
0.5
VDDIO_3/4 = 2.7 V
SID664B RPD Pull-down resistance 25 50 100 kΩ
SID665B RPU Pull-up resistance 25 50 100 kΩ

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-5 I/O specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Input HIGH voltage for
SID666B VIH_CMOS HyperBus and HSSPI in 0.7 × – – V vtrip_sel<1:0> = 0b00
VDDIO_3/4
CMOS mode
Input HIGH voltage for RGMII 0.8 ×
SID667B VIH_RGMII in CMOS mode VDDIO_3/4 – – V vtrip_sel<1:0> = 0b00

Input Voltage HIGH

SID668E VIH_TTL 2 – – V vtrip_sel<1:0> = 0b01
threshold for TTL mode
Input HIGH voltage for GMII
SID668B VIH_GMII 1.7 – – V vtrip_sel<1:0> = 0b11
mode
Input HIGH voltage for SD 0.625 ×
SID669B VIH_SD_eMMC and eMMC in CMOS mode VDDIO_3/4 – – V vtrip_sel<1:0> = 0b00

Input Voltage HIGH 0.8 ×

SID669E VIH_AUTO – – V vtrip_sel<1:0> = 0b10
threshold in AUTO mode VDDIO_3/4
Input LOW voltage for
0.3 ×
SID670B VIL_CMOS HYPERBUS™ and HSSPI in – – V vtrip_sel<1:0> = 0b00
VDDIO_3/4
CMOS mode
Input LOW voltage for RGMII 0.2 ×
SID671B VIL_RGMII – – V vtrip_sel<1:0> = 0b00
in CMOS mode VDDIO_3/4
Input Voltage LOW threshold
SID672E VIL_TTL for TTL mode – – 0.8 V vtrip_sel<1:0> = 0b01

Input LOW voltage for GMII

SID672B VIL_GMII – – 0.9 V vtrip_sel<1:0> = 0b11
mode
Input LOW voltage for SD and 0.25 ×
SID673B VIL_SD_eMMC – – V vtrip_sel<1:0> = 0b00
eMMC in CMOS mode VDDIO_3/4
Input Voltage LOW threshold 0.5 ×
SID673E VIL_AUTO – – V vtrip_sel<1:0> = 0b10
in AUTO mode VDDIO_3/4
0.05 ×
SID674B VHYST_CMOS Hysteresis in CMOS mode – – V vtrip_sel<1:0> = 0b00
VDDIO_3/4

SID674F VHYST_AUTO Hysteresis in AUTO mode 0.05 × – – V vtrip_sel<1:0> = 0b10

VDDIO_3
SID675B CIN Input pin capacitance – – 5 pF For 10 MHz and 100 MHz
VDDIO_3/4 = 3.6 V,
VSSIO_3/4 < VI < VDDIO_3/4
SID676B IIL Input leakage current –450 1.02 450 nA –40 °C  TA  125 °C
Typ: TA = 25 °C,
VDDIO_3/4 = 3.3 V
SID677B fIN_GMII Input frequency – – 125 MHz
SID678B fIN_RGMII Input frequency – – 125 MHz
SID679B fIN_HB_HSSPI Input frequency – – 100 MHz
SID680B fIN_eMMC Input frequency – – 52 MHz
SID681B fIN_SD Input frequency – – 50 MHz
SID682B fOUT_GMII_RGMII Output frequency – – 125 MHz
SID683B fOUT_HB_HSSPI Output frequency – – 100 MHz
SID684B fOUT_eMMC Output frequency – – 52 MHz
SID685B fOUT_SD Output frequency – – 50 MHz
GPIO Input Specifications
Analog glitch filter (pulse
SID98 tFT – – 50[53] ns One filter per port
suppression width)
Minimum pulse width for
SID99 tINT 160 – t– ns
GPIO interrupt

Note
53.If a longer pulse suppression width is necessary, use Smart I/O.

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Based on Arm® Cortex®-M7 dual
Electrical specifications

27.6 Analog peripherals

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.

27.6.1 SAR ADC

0xFFF

Actual conversion
characteristics
1.5 LSb
0xFFE

1 LSb (N - 1) + 0.5 LSb

0xFFD
Digital output

VN T

0x003

Actual conversion
characteristics
0x002

Ideal
characteristics
0x001

0.5 LSb

VREFL Analog input VREFH

Total error of digital output N = ( V NT {1 LSb × (N – 1) + 0.5 LSb} ) / 1 LSb [LSb]

[V]
1 LSb (Ideal value) = (VREFH – VREFL) / 4096

N: A/D converter digital output value

VZT (Ideal value): V REFL + 0.5 LSb [V]
VFST (Ideal value): VREFH – 1.5 LSb [V]
VNT: Voltage at which the digital output changes from N – 1 to N

Figure 27-4 ADC characteristics and error descriptions

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-6 12-Bit SAR ADC DC specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID100 A_RES SAR ADC – – 12 bits
resolution
SID101 A_VINS Input voltage VREFL – VREFH V
range
SID102A A_VDDA[54] VDDA voltage 2.7 – 5.5 V
range
ADC performance
VREFH voltage degrades when high
SID102 A_VREFH 2.7 – VDDA V
range reference is higher than
supply (VDDA)
ADC performance
VREFL voltage degrades when low
SID103 A_VREFL range VSSA – VSSA V reference is lower than
ground
SID103A Vband_gap Internal band gap 0.882 0.9 0.918 V
reference voltage
Ratio of current
collected on a pin
CLAMP_COUPLING_RA- to the positive
SID19A TIO_POS current injected – – 0.1 %
into a neighboring
pin
Ratio of current
collected on a pin
CLAMP_COUPLING_RA- to the negative
SID19B – – 1.2 %
TIO_NEG current injected
into a neighboring
pin
Internal pin
resistance to
SID19C RCLAMP_INTERNAL – – 50 Ω
current collection
point

27.6.2 Calculating the impact of neighboring pins

The three ADC specifications based on SID19A, SID19B, and SID19C, can be used to calculate the pin leakage and
resulting ADC offset caused by injection current using the below formula:

ILEAK = IINJECTED × CLAMP_COUPLING_RATIO

VERROR = ILEAK × (RCLAMP_INTERNAL + RSOURCE)
Code Error = VERROR × 212 / VREF

Where:
IINJECTED is the injected current in mA.
ILEAK is the calculated leakage current in mA.
VERROR is the voltage error calculated due to leakage currents in V.
VREF is the ADC reference voltage in V.

Note
54.VDDD must be greater than 0.8 × VDDA when ADC[2] is enabled. VDDIO_1 must be greater than 0.8 × VDDA when ADC[0] is enabled.

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Electrical specifications

Integral linearity error Differential linearity error

0xFFF
Ideal
characteristics
Actual conversion
0xFFE N+1
characteristics

VFST Actual conversion

0xFFD (1 LSb [N - 1] + VZT) (Measured value) characteristics

Digital output
N
Digital output

VN T
(Measured value)
0x004

0x003 Actual conversion N-1

characteristics V(N + 1 )T
(Measured value)
VN T
0x002
(Measured value)
Ideal
characteristics
0x001 N -2 Actual conversion
characteristics
VZT
(Measured value)

VREFL Analog input VREFH VREFL Analog input VREFH

Integral linearity error of digital output N = (VNT – {1 LSb × (N – 1) + VZT}) / 1 LSb [LSb]

Differential linearity error of digital output N = (V(N + 1)T – VNT – 1 LSb ) / 1 LSb [LSb]

1 LSb = (VFST – VZT ) / 4094 [V]

VZT: Voltage for which digital output changes from 0x000 to 0x001
VFST: Voltage for which digital output changes from 0xFFE to 0xFFF.

Figure 27-5 Integral and differential linearity errors

EXTERNAL CIRCUIT INTERNAL EQUIVALENT CIRCUIT

VD DIO
Channel selection MUX and ADC

REX T RVIN

CVIN

CEX T CIN

ESD Protection

REX T: Source impedance

CEX T: On-PCB capacitance
CIN: I/O pad or Input capacitance
RVIN : ADC equivalent input resistance
CVIN : ADC equivalent input capacitance
K: Constant for sampling accuracy, K = ln(abs(4096/LSbSA MPL E ))

Sampling Time (tSA MPL E ) requirement is shown in the following equation

tSA MPL E > K x { CVIN x ( RVIN + REX T ) + ( CIN + CEX T ) x (REX T) } [seconds]

K = value of 9.0 is recommended to get ±0.5 LSb sampling accuracy at 12-bit (LSbSA MPL E = ±0.5)

Figure 27-6 ADC equivalent circuit for analog input

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-7 SAR ADC AC specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
SID104 VZT Zero transition voltage –20 – 20 mV before offset
adjustment
VDDA = 2.7 V to 5.5 V,
Full-scale transition –40 °C ≤ TA ≤ 125 °C
SID105 VFST voltage –20 – 20 mV before offset
adjustment
SID114 fADC_4P5 ADC operating frequency 2 – 26.67 MHz 4.5 V ≤ VDDA ≤ 5.5 V
SID114A fADC_2P7 ADC operating frequency 2 – 13.34 MHz 2.7 V ≤ VDDA ≤ 4.5 V
Analog input sample
time for channels of own 4.5 V ≤ VDDA ≤ 5.5 V,
SID113 tS_4P5 SARMUX 412 – – ns guaranteed by design
(4.5 V ≤ VDDA)
Analog input sample
SID113A tS_2P7 time for channels of own 600 – – ns 2.7 V ≤ VDDA ≤ 4.5 V,
SARMUX guaranteed by design
(2.7 V ≤ VDDA)
Analog input sample
time when input is from 4.5 V ≤ VDDA ≤ 5.5 V,
SID113B tS_DR_4P5 2 – – µs
diagnostic reference (4.5 guaranteed by design
V ≤ VDDA)
Analog input sample
time when input is from 2.7 V ≤ VDDA ≤ 4.5 V,
SID113C tS_DR_2P7 diagnostic reference (2.7 2.5 – – µs guaranteed by design
V ≤ VDDA)
SID113D tS_TS Analog input sample 7 – – µs 2.7 V  VDDA  5.5 V
time for temperature Guaranteed by design
sensor
SID113E tS_4P5_A Analog input sample time 824 4.5 V ≤ VDDA ≤ 5.5 V
for channels of another When ADC0 borrows the
SARMUXn (n=1,2) – – ns SARMUX of another ADC,
guaranteed by design
SID113F tS_2P7_A Analog input sample time 1648 2.7V ≤ VDDA < 4.5 V
for channels of another – – ns When ADC0 borrows the
SARMUXn (n=1,2) SARMUX of another ADC,
guaranteed by design
ADC max throughput 4.5 V ≤ VDDA ≤ 5.5 V,
SID106 tST_4P5 (samples per second) – – 1 Msps 80 MHz / 3 = 26.67 MHz,
when using the SARMUX 11 sampling cycles,
of own ADC 15 conversion cycles
ADC max throughput 2.7 V ≤ VDDA < 4.5 V
(samples per second) 80 MHz / 6 = 13.3 MHz,
SID106A tST_2P7 – – 0.5 Msps
when using the SARMUX 11 sampling cycles,
of own ADC 15 conversion cycles
ADC0 max throughput
(samples per second) 4.5 V ≤ VDDA ≤ 5.5 V,
SID106B tST_4P5_A when borrowing the – – 0.5 Msps 80 MHz/6 = 13.3 MHz,
SARMUXn of another ADC 11 sampling cycles,
(n=1,2) 15 conversion cycles

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-7 SAR ADC AC specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
ADC0 max throughput 2.7V ≤ VDDA < 4.5 V,
(samples per second) 80 MHz / 12 = 6.67 MHz, 11
SID106C tST_2P7_A when borrowing the – – 0.25 Msps sampling cycles,
SARMUXn of another ADC 15 conversion cycles
(n=1,2)

SID107 CVIN ADC input sampling – – 4.8 pF Guaranteed by design

capacitance
Input path ON resistance
SID108 RVIN1 (4.5 V to 5.5 V) – – 9.4 kΩ Guaranteed by design
Input path ON resistance
SID108A RVIN2 (2.7 V to 4.5 V) – – 13.9 kΩ Guaranteed by design
Diagnostic path ON resis-
SID108B RDREF1 tance (4.5 V to 5.5 V) – – 40 kΩ Guaranteed by design
Diagnostic path ON resis-
SID108C RDREF2 tance (2.7 V to 4.5 V) – – 50 kΩ Guaranteed by design
Diagnostic reference
SID119 ACC_RLAD resistor ladder accuracy –4 – 4 %
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
SID109 A_TE Total error –5 – 5 LSb –40 °C ≤ TA ≤ 125 °C
Total Error after offset
and gain adjustment at
12-bit resolution mode
VDDA = VREFH = 2.7 V to
5.5 V, VREFL = VSSA
–40 °C ≤ TA ≤ 125 °C
SID109A A_TEB Total error –12 – 12 LSb Total error before offset
and gain adjustment at
12 bit resolution mode
SID110 A_INL Integral nonlinearity –2.5 – 2.5 LSb VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
SID111 A_DNL Differential nonlinearity –0.99 – 1.9 LSb VDDA = 2.7 V to 5.5 V,
–40 °C ≤ TA ≤ 125 °C
Channel to channel VDDA = 2.7 V to 5.5 V,
SID112 A_CE variation (for channels –1 – 1 LSb
connected to same ADC) –40 °C ≤ TA ≤ 125 °C
Analog input leakage When input pad is
SID115 IAIC current –350 70 350 nA selected for conversion
Diagnostic reference
SID116 IDIAGREF current – – 70 µA
Analog power supply
SID117 IVDDA current while ADC is – 360 550 µA Per enabled ADC
operating
Analog power supply
SID117A IVDDA_DS current while ADC is not – 1 21 µA Per enabled ADC
operating
Analog reference voltage
SID118 IVREF current while ADC is – 360 550 µA Per enabled ADC
operating
Analog reference voltage
SID118A IVREF_LEAK current while ADC is not – 1.8 5 µA Per enabled ADC
operating

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Based on Arm® Cortex®-M7 dual
Electrical specifications

27.6.3 Temperature sensor

Table 27-8 Temperature sensor specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID201 TSENSACC2 Temperature sensor –5 – 5 °C –40 °C ≤ TJ ≤ 150 °C
accuracy 2 This spec is valid when using
ADC[0] (VDDIO_1), ADC[1] (VDDIO_2)
or ADC[2] (VDDD) with the
following conditions:
a. 3.0 V ≤ VDDD, VDDIO_1 or
VDDIO_2 = VDDA = VREFH ≤ 3.6 V
or
b. 4.5 V ≤ VDDD, VDDIO_1 or
VDDIO_2 = VDDA = VREFH ≤ 5.5 V
SID201A TSENSACC3 Temperature sensor –10 – 10 °C –40 °C ≤ TJ ≤ 150 °C
accuracy 3 This spec is valid when using
ADC[0] (VDDIO_1) or ADC[2] (VDDD)
with the following condition:
2.7 V ≤ VDDD or VDDIO_1 ≤ 5.5 V and
2.7 V ≤ VDDA = VREFH ≤ 5.5 V and
0.8 × VDDA < VDDD or VDDIO_1

27.6.4 Voltage divider accuracy

Table 27-9 Voltage divider accuracy
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Uncorrected monitor
voltage divider accuracy Any HV supply pad
SID202 VMONDIV (measured by ADC), –20 2 20 % within 2.7 V–5.5 V
compared to ideal operating range
supply/2

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Based on Arm® Cortex®-M7 dual
Electrical specifications

27.7 AC specifications
Unless otherwise noted, the timings are defined with the guidelines mentioned in the Figure 27-7.

Definition of rise / fall times

VDDD or VDDIO_x
80 % 80 %

20 % 20 %
VSSD or VSSD_x or VSSIO_x
tR tF

Time Reference Point Definition

VDDD or VDDIO_x

0.5 x VDDD or VDDIO_x Timing Reference Points

VSSD or VSSD_x or VSSIO_x

Figure 27-7 AC timings specifications

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Based on Arm® Cortex®-M7 dual
Electrical specifications

27.8 Digital peripherals

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-10 Timer/counter/PWM (TCPWM) specifications
Spec Unit
ID Parameter Description Min Typ Max s Details/Conditions
SID120 fC TCPWM operating frequency – – 100 MHz fC = peripheral clock
Trigger Events can be
Stop, Start, Reload,
SID121 tPWMENEXT Input trigger pulse width for all 2 / fC – – ns Count, Capture, or Kill
trigger events depending on which
mode of operation is
selected.
Minimum possible
width of Overflow,
Underflow, and
SID122 tPWMEXT Output trigger pulse widths 2 / fC – – ns Counter = Compare
(CC) value trigger
outputs
Minimum time
SID123 tCRES Resolution of counter 1 / fC – – ns between successive
counts
Minimum pulse width
SID124 tPWMRES PWM resolution 1 / fC – – ns of PWM output
Minimum pulse width
SID125 tQRES Quadrature inputs resolution 2 / fC – – ns between Quadrature
phase inputs.

TCPWM Timing Diagrams

Input Signal VIH

1 1
VIL

Output Signal VOH

2 2
VOL

1: tPWMENEXT, tQRES
2: tPWMEXT

Figure 27-8 TCPWM timing diagrams

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-11 Serial communication block (SCB) specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID129 fSCB SCB operating frequency – – 100 MHz
2
I C interface-Standard-mode
SID130 fSCL SCL clock frequency – – 100 kHz
SID131 tHD;STA Hold time, START condition 4000 – – ns
SID132 tLOW Low period of SCL 4700 – – ns
SID133 tHIGH High period of SCL 4000 – – ns

SID134 tSU;STA Setup time for a repeated 4700 – – ns

START
SID135 tHD;DAT Data hold time, for receiver 0 – – ns
SID136 tSU;DAT Data setup time 250 – – ns
SID138 tF Fall time of SCL and SDA – – 300 ns Input and output
SID139 tSU;STO Setup time for STOP 4000 – – ns

SID140 tBUF Bus-free time between START 4700 – – ns

and STOP
SID141 CB Capacitive load for each bus line – – 400 pF

SID142 tVD;DAT Time for data signal from SCL – – 3450 ns

LOW to SDA output
SID143 tVD;ACK Data valid acknowledge time – – 3450 ns

SID144 VOL LOW level output voltage 0 – 0.4 V Open-drain at 3 mA

sink current
SID145 IOL LOW level output current 3 – – mA VOL = 0.4 V
2
I C interface-Fast-mode
SID150 fSCL_F SCL clock frequency – – 400 kHz
SID151 tHD;STA_F Hold time, START condition 600 – – ns
SID152 tLOW_F Low period of SCL 1300 – – ns
SID153 tHIGH_F High period of SCL 600 – – ns
Setup time for a repeated
SID154 tSU;STA_F 600 – – ns
START
SID155 tHD;DAT_F Data hold time, for receiver 0 – – ns
SID156 tSU;DAT_F Data setup time 100 – – ns
20 × Input and output,
SID158 tF_F Fall time of SCL and SDA (VDDD / – 300 ns GPIO_ENH: slow
5.5) mode, 400 pF load
Input and output
GPIO_STD:
drive_sel<1:0>= 0b00
SID158A tFA_F Fall time of SCL and SDA 0.35 – 300 ns MIN: 10 pF load,
RPU = 35.41 kΩ
Max: 400 pF load,
RPU = 350 Ω
SID159 tSU;STO_F Setup time for STOP 600 – – ns Input and output
Bus free time between START
SID160 tBUF_F and STOP 1300 – – ns

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Electrical specifications

Table 27-11 Serial communication block (SCB) specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID161 CB_F Capacitive load for each bus line – – 400 pF
Time for data signal from SCL
SID162 tVD;DAT_F LOW to SDA output – – 900 ns

SID163 tVD;ACK_F Data valid acknowledge time – – 900 ns

Pulse width of spikes that must
SID164 tSP_F be suppressed by the input filter – – 50 ns

Open-drain at 3 mA
SID165 VOL_F LOW level output voltage 0 – 0.4 V sink current
SID166 IOL_F LOW level output current 3 – – mA VOL = 0.4 V

SID167 IOL2_F LOW level output current 6 – – mA VOL = 0.6 V[55]

I2C interface-Fast-Plus mode
SID170 fSCL_FP SCL clock frequency – – 1 MHz
SID171 tHD;STA_FP Hold time, START condition 260 – – ns
SID172 tLOW_FP Low period of SCL 500 – – ns
SID173 tHIGH_FP High period of SCL 260 – – ns
Setup time for a repeated
SID174 tSU;STA_FP 260 – – ns
START
SID175 tHD;DAT_FP Data hold time, for receiver 0 – – ns
SID176 tSU;DAT_FP Data setup time 50 – – ns
20 × Input and output
SID178 tF_FP Fall time of SCL and SDA (VDDD / – 160 ns 20-pF load
5.5) GPIO_ENH: slow mode
SID179 tSU;STO_FP Setup time for STOP 260 – – ns Input and output
Bus free time between START
SID180 tBUF_FP 500 – – ns
and STOP
SID181 CB_FP Capacitive load for each bus line – – 20 pF
Time for data signal from SCL
SID182 tVD;DAT_FP – – 450 ns
LOW to SDA output
SID183 tVD;ACK_FP Data valid acknowledge time – – 450 ns
Pulse width of spikes that must
SID184 tSP_FP – – 50 ns
be suppressed by the input filter
Open-drain at 3 mA
SID186 VOL_FP LOW level output voltage 0 – 0.4 V sink current
SID187 IOL_FP LOW level output current 3[56] – – mA VOL = 0.4 V[56]
SPI Interface Master (Full-clock mode: LATE_MISO_SAMPLE = 1) [Conditions: drive_sel<1:0>= 0x]
Do not use half-clock
mode:
SID190 fSPI SPI operating frequency – – 12.5 MHz
LATE_MISO_SAMPLE =
0

Notes
55.In order to drive full bus load at 400 kHz, 6 mA IOL is required at 0.6 V VOL.
56.In order to drive full bus load at 1 MHz, 20 mA IOL is required at 0.4 V VOL. However, this device does not support it.

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-11 Serial communication block (SCB) specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID191 tDMO SPI Master: MOSI valid after – – 15 ns

SCLK driving edge
SPI Master: MISO valid before
SID192 tDSI 40 – – ns
SCLK capturing edge
SPI Master: Previous MOSI data
SID193 tHMO hold time 0 – – ns

Only for
SID193A tHMOA SPI Master: Previous MOSI data –3.5 – – ns SCB4_MOSI/P0.3 and
hold time
SCB4_CLK/P1.0
0.5 ×
SID194 tW_SCLK_H_L SPI SCLK pulse width HIGH or 0.4 × (1 / (1 / 0.6 × (1 / ns
LOW fSPI) fSPI)
fSPI)
SPI Master: MISO hold time after
SID196 tDHI SCLK capturing edge 0 – – ns

SID198 tEN_SETUP SSEL valid, before the first SCK 0.5 × – – ns Min is half clock period
capturing edge (1/fSPI)
SSEL hold, after the last SCK 0.5 ×
SID199 tEN_SHOLD – – ns Min is half clock period
capturing edge (1/fSPI)
SID195 CSPIM_MS SPI capacitive load – – 10 pF
SPI interface slave (internally clocked) [Conditions: drive_sel<1:0>= 0x]
SID205 fSPI_INT SPI operating frequency – – 10 MHz
SPI Slave: MOSI Valid before
SID206 tDMI_INT Sclock capturing edge 5 – – ns

SPI Slave: MISO Valid after

SID207 tDSO_INT Sclock driving edge, in the – – 62 ns
internal-clocked mode

SID208 tHSP SPI Slave: Previous MISO data 3 – – ns

hold time
tEN_SET- SPI Slave: SSEL valid to first SCK
SID209 33 – – ns
UP_INT valid edge
SPI Slave Select active (LOW)
SID210 tEN_HOLD_INT from last SCLK hold 33 – – ns

tEN_SET- SPI Slave: from SSEL valid, to

SID211 SCK falling edge before the first 20 – – ns
UP_PRE data bit
SPI Slave: from SCK falling edge
SID212 tEN_HOLD_PRE before the first data bit, to SSEL 20 – – ns
invalid
SPI Slave: from SSEL valid, to
SID213 tEN_SETUP_CO SCK falling edge in the first data 20 – – ns
bit
SPI Slave: from SCK falling edge
SID214 tEN_HOLD_CO in the first data bit, to SSEL 20 – – ns
invalid
SID215 tW_DIS_INT SPI Slave Select inactive time 40 – – ns
SID216 tW_SCLKH_INT SPI SCLK pulse width HIGH 20 – – ns
SID217 tW_SCLKL_INT SPI SCLK pulse width LOW 20 – – ns

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-11 Serial communication block (SCB) specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID218 tSIH_INT SPI MOSI hold from SCLK 12 – – ns
SID219 CSPIS_INT SPI Capacitive Load – – 10 pF
SPI interface slave (externally clocked) [Conditions: drive_sel<1:0>= 0x]
SID220 fSPI_EXT SPI operating frequency – – 12.5 MHz
SPI Slave: MOSI Valid before
SID221 tDMI_EXT 5 – – ns
Sclock capturing edge
SPI Slave: MISO Valid after
SID222 tDSO_EXT Sclock driving edge, in the – – 32 ns
external-clocked mode
SPI Slave: Previous MISO data
SID223 tHSO_EXT hold time 3 – – ns

SID224 tEN_SET- SPI Slave: SSEL valid to first SCK 40 – – ns

UP_EXT valid edge
SPI Slave Select active (LOW)
SID225 tEN_HOLD_EXT 40 – – ns
from last SCLK hold
SID226 tW_DIS_EXT SPI Slave Select inactive time 80 – – ns
SID227 tW_SCLKH_EXT SPI SCLK pulse width HIGH 34 – – ns
SID228 tW_SCLKL_EXT SPI SCLK pulse width LOW 34 – – ns
SID229 tSIH_EXT SPI MOSI hold from SCLK 20 – – ns
SID230 CSPIS_EXT SPI Capacitive Load – – 10 pF

SID231 tVSS_EXT SPI Slave: MISO valid after SSEL – – 33 ns

falling edge (CPHA = 0)
UART interface
SID240 fBPS Data rate – – 10 Mbps

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Based on Arm® Cortex®-M7 dual
Electrical specifications

8 9 7
70% 70% 70% 70%
SDA
30% 30% 30% 30%

6 12
8 9 4
70% 70% 70% 70% 70%
SCL
30% 30% 30% 30% 30% 30% 30%
2
1 3

START condition

11
70% 70% 70% 70%
SDA
30% 30% 30%

14 10
13

70% 70% 70%

SCL
30%

5 2 9th clock

Repeated START STOP condition START condition

condition

1: SCL clock period = 1/fSCL

2: Hold time, START condition = tHD;STA
3: LOW period of SCL = tLOW
4: HIGH period of SCL = tHIGH
5: Setup time for a repeated START = tSU;STA
6: Data hold time, for receiver = tHD;DAT
7: Data setup time = tSU;DAT
8: Fall time of SCL and SDA = tF
9: Rise time of SCL and SDA = tR
10: Setup time for STOP = tSU;STO
11: Bus-free time between START and STOP = tBUF
12: Time for data signal from SCL LOW to SDA output = tVD;DAT
13: Data valid acknowledge time = tVD;ACK
14: Pulse width of spikes that must be suppressed by the input filter = tSP

Figure 27-9 I2C timing diagrams

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Based on Arm® Cortex®-M7 dual
Electrical specifications

SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)

CPHA=0

SSEL

2 1 3

SCLK
(CPOL=0) 4 4

SCLK
(CPOL=1)

5 6

MISO
(input)

7 8

MOSI
(output)

1: SCLK period = 1 / fSPI

2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tDHI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)

Figure 27-10 SPI master timing diagrams with LOW clock phase

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Based on Arm® Cortex®-M7 dual
Electrical specifications

SPI Master Timing Diagrams (LATE_MISO_SAMPLE=1)

CPHA=1

SSEL

2 3
1

SCLK
(CPOL=0) 4 4

SCLK
(CPOL=1)

5 6

MISO
(input)

7 8

MOSI
(output)

1: SCLK period = 1 / fSPI

2: Enable lead time (setup) = tEN_SETUP = Depends on SPI_CTRL.SSEL_SETUP_DEL (Refer to the Register TRM)
3: Enable trail time (hold) = tEN_HOLD = Depends on SPI_CTRL.SSEL_HOLD_DEL (Refer to the Register TRM)
4: SCLK high or low time = tW_SCLK_H_L
5: Input data setup time = tDSI
6: Input data hold time = tHDI
7: Output data valid after SCLK driving edge = tDMO
8: Output data hold time = tHMO
9: SSEL high pulse width = Depends on SPI_CTRL.SSEL_INTER_FRAME_DEL (Refer to the Register TRM)

Figure 27-11 SPI master timing diagrams with HIGH clock phase

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

SPI Slave Timing Diagrams

CPHA=0

10

SSEL

2 1 3

SCLK
(CPOL=0) 4 4

SCLK
(CPOL=1)

8 7 9

MISO
(output)

5 6

MOSI
(input)

1: SCLK period = 1 / fSPI_EXT

2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data valid after SSEL falling edge (CPHA=0) = tVSS_EXT
9: output data hold time = tHSO
10: SSEL high pulse width = tDIS_EXT

Figure 27-12 SPI slave timing diagrams with LOW clock phase

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

SPI slave Timing Diagrams

CPHA=1

SSEL

2 3
1

SCLK
(CPOL=0) 4

SCLK
(CPOL=1)

7 8

MISO
(output)

5 6

MOSI
(input)

1: SCLK period = 1 / fSPI_EXT

2: enable lead time (setup) = tEN_SETUP_EXT
3: enable trail time (hold) = tEN_HOLD_EXT
4: SCLK high or low time = tw_SCLKH_EXT = tw_SCLKL_EXT
5: input data setup time = tDMI_EXT
6: input data hold time = tSIH_EXT
7: output data valid after SCLK driving edge = tDSO_EXT
8: output data hold time = tHSO
9: SSEL high pulse width = tDIS_EXT

Figure 27-13 SPI slave timing diagrams with HIGH clock phase

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-12 CAN FD specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID630 fHCLK System clock frequency – – 100 MHz fCCLK ≤ fHCLK,,
guaranteed by design
SID631 fCCLK CAN clock frequency – – 100 MHz fCCLK ≤ fHCLK,,
guaranteed by design

Table 27-13 LIN specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID249 fLIN Internal clock frequency to the – – 100 MHz
LIN block
SID250 BR_NOM Bit rate on the LIN bus 1 – 20 kbps Guaranteed by design
Bit rate on the LIN bus (not in
SID250A BR_REF standard LIN specification) for 1 – 115.2 kbps Guaranteed by design
re-flashing in LIN slave mode

Datasheet 145 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.9 Memory
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-14 Flash DC specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID260A VPE Erase and program voltage 2.7 – 5.5 V

Table 27-15 Flash AC specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Zero wait access to
Maximum flash memory code-flash memory up to
SID257 fFO – – 100 MHz 100 MHz
operation frequency Zero wait access with cache
hit up to 350 MHz
Maximum time from erase
SID254 tERS_SUS suspend command till erase – – 37.5 µs
is indeed suspend
Minimum time allowed from
SID255 tERS_RES_SUS erase resume to erase 250 – – µs Guaranteed by design
suspend
10 + At 100 MHz, N ≥ 4 and
SID258 tBC_WF Blank check time for N-bytes – – 0.3 × multiple of 4, excludes
µs
of work-flash
N system overhead time
SID259 tSECTORE- Sector erase time – 45 90 ms Includes internal
RASE1 (code-flash: 32 KB) preprogramming time
tSECTORE- Sector erase time Includes internal
SID260 (code-flash: 8 KB) – 15 30 ms preprogramming time
RASE2
tSECTORE- Sector erase time Includes internal
SID261 – 80 160 ms
RASE3 (work-flash, 2 KB) preprogramming time
SID262 tSECTORE- Sector erase time – 5 15 ms Includes internal
RASE4 (work-flash, 128 B) preprogramming time
64-bit write time Excludes system overhead
SID263 tWRITE1 (code-flash) – 30 60 µs time
256-bit write time Excludes system overhead
SID264 tWRITE2 – 40 70 µs
(code-flash) time
SID265 tWRITE3 4096-bit write time – 320 1200 µs Excludes system overhead
(code-flash)[57] time
32-bit write time Excludes system overhead
SID266 tWRITE4 (work-flash) – 30 60 µs time
Code-flash retention. T (power on and off) ≤ 85 °C
SID267 tFRET1 20 – – years A
1000 program/erase cycles average
Work-flash retention. TA (power on and off) ≤ 85 °C
SID268 tFRET3 125,000 program/erase 20 – – years
cycles average
Work-flash retention.
TA (power on and off) ≤ 85 °C
SID269 tFRET4 250,000 program/erase 10 – – years average
cycles

Note
57.The code-flash includes a 'Write Buffer' of 4096-bit. If the application software writes this buffer multiple times, to get the overall write
time multiply one sector write time with the corresponding factor (say for factor 64, example, 64 x 512 B = 32 KB [one sector]).

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-15 Flash AC specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Typ: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
(TT)
Program operating VCCD
SID612 ICC_ACT2 current (code or work-flash) – 7 58 mA Max: TA = 125 °C,
VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
Erase operating VCCD current (TT)
SID613 ICC_ACT3 – 7 52 mA Max: TA = 125 °C,
(code- or work-flash) VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
Program operating VDDD (TT)
SID612A ICC_ACT2A – 8 10 mA Max: TA = 125 °C,
current (code or work-flash) VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design
Typ: TA = 25 °C, VDDD = 5.0 V,
VCCD = 1.15 V, process typ
Erase operating VDDD current (TT)
SID613A ICC_ACT3A – 8 16 mA Max: TA = 125 °C,
(code- or work-flash) VDDD = 5.5 V, VCCD = 1.2 V,
process worst (FF)
Guaranteed by design

Datasheet 147 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.10 System resources

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-16 System resources

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
Power-on reset specifications
VDDD rising voltage to de assert Guaranteed by
SID270 VPOR_D 1.5 – 2.35 V
POR design
SID276 VPOR_A VDDD falling voltage to assert 1.45 – 2.1 V
POR
SID271 VPOR_H Level detection hysteresis 20 – 300 mV
Delay between VDDD rising
Guaranteed by
SID272 tDLY_POR through 2.3 V and internal – – 3 µs design
deassertion of POR
SID273 tPOFF VDDD Power off time 100 – – µs VDDD < 1.45 V
VDDD power ramp rate with This ramp
SID274 POR_RR1 robust BOD (BOD operation is – – 100 mV/µs supports robust
guaranteed) BOD
This ramp does
VDDD power ramp rate without not support
SID275 POR_RR2 – – 1000 mV/µs robust BOD
robust BOD tPOFF must be
satisfied.
High-voltage BOD (HV BOD) specifications
HV BOD 2.7 V rising detection
SID500 VTR_2P7_R point for VDDD and VDDA 2.474 2.55 2.627 V
(default)
HV BOD 2.7 V falling detection
SID501 VTR_2P7_F point for VDDD and VDDA 2.449 2.525 2.601 V
(default)
HV BOD 3.0 V rising detection
SID502 VTR_3P0_R 2.765 2.85 2.936 V
point for VDDD and VDDA
HV BOD 3.0 V falling detection
SID503 VTR_3P0_F 2.74 2.825 2.91 V
point for VDDD and VDDA
Power ramp rate: VDDD and
SID505 HVBOD_RR_A – – 100 mV/µs
VDDA (Active)
Power ramp rate: VDDD and
SID506 HVBOD_RR_DS – – 10 mV/µs
VDDA (DeepSleep)
Active mode delay between
VDDD falling/rising through Guaranteed by
SID507 tDLY_ACT_HVBOD VTR_2P7_F/R or VTR_3P0_F/R and – – 0.5 µs
an internal HV BOD signal design
transitioning
Active mode delay between
VDDA falling/rising through Guaranteed by
SID507A tDLY_ACT_HVBOD VTR_2P7_F/R or VTR_3P0_F/R and – – 1 µs
internal HV BOD signal transi- design
tioning

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-16 System resources (continued)

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
DeepSleep mode delay
between VDDD/VDDA
falling/rising through Guaranteed by
SID507B tDLY_DS_HVBOD – – 4 µs
VTR_2P7_F/R or VTR_3P0_F/R and design
an internal HV BOD signal
transitioning
Response time of HV BOD,
VDDD/VDDA supply. (For Guaranteed by
SID508 tRES_HVBOD falling-then-rising supply at 100 – – ns
max ramp rate; threshold is design
VTR_2P7_F or VTR_3P0_F)
Low-voltage BOD (LV BOD) specifications
LV BOD rising detection point
SID510 VTR_R_LVBOD for VCCD 0.917 0.945 0.973 V
LV BOD falling detection point
SID511 VTR_F_LVBOD for VCCD 0.892 0.920 0.948 V
Active delay between VCCD
falling/rising through Guaranteed by
SID515 tDLY_ACT_LVBOD – – 1 µs
VTR_R/F_LVBOD and an internal design
LV BOD signal transitioning
DeepSleep mode delay
between VCCD falling/rising
SID515A tDLY_DS_LVBOD through VTR_R/F_LVBOD and an – – 12 µs Guaranteed by
design
internal LV BOD signal transi-
tioning
Response time of LV BOD (for
falling-then-rising supply at Guaranteed by
SID516 tRES_LVBOD max ramp rate; threshold is 100 – – ns design
VTR_F_LVBOD)
Low-voltage detector (LVD) DC specifications
LVD 2.8 V falling detection point Typ – Typ +
SID520 VTR_2P8_F for VDDD 4% 2800 4% mV
LVD 2.9 V falling detection point Typ – Typ +
SID521 VTR_2P9_F for VDDD 4% 2900 4% mV
LVD 3.0 V falling detection point Typ – Typ +
SID522 VTR_3P0_F for VDDD 4% 3000 4% mV
LVD 3.1 V falling detection point Typ – Typ +
SID523 VTR_3P1_F for VDDD 4% 3100 4% mV
LVD 3.2 V falling detection point Typ – Typ +
SID524 VTR_3P2_F for VDDD 4% 3200 4% mV
LVD 3.3 V falling detection point Typ – Typ +
SID525 VTR_3P3_F for VDDD 4% 3300 4% mV
LVD 3.4 V falling detection point Typ – Typ +
SID526 VTR_3P4_F for VDDD 4% 3400 4% mV
LVD 3.5 V falling detection point Typ – Typ +
SID527 VTR_3P5_F for VDDD 4% 3500 4% mV
LVD 3.6 V falling detection point Typ – Typ +
SID528 VTR_3P6_F 3600 mV
for VDDD 4% 4%
LVD 3.7 V falling detection point Typ – Typ +
SID529 VTR_3P7_F 3700 mV
for VDDD 4% 4%

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-16 System resources (continued)

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
SID530 VTR_3P8_F LVD 3.8 V falling detection point Typ – 3800 Typ + mV
for VDDD 4% 4%
SID531 VTR_3P9_F LVD 3.9 V falling detection point Typ – 3900 Typ + mV
for VDDD 4% 4%
SID532 VTR_4P0_F LVD 4.0 V falling detection point Typ – 4000 Typ + mV
for VDDD 4% 4%
LVD 4.1 V falling detection point Typ – Typ +
SID533 VTR_4P1_F for VDDD 4% 4100 4% mV
LVD 4.2 V falling detection point Typ – Typ +
SID534 VTR_4P2_F for VDDD 4% 4200 4% mV
LVD 4.3 V falling detection point Typ – Typ +
SID535 VTR_4P3_F for VDDD 4% 4300 4% mV
LVD 4.4 V falling detection point Typ – Typ +
SID536 VTR_4P4_F for VDDD 4% 4400 4% mV
LVD 4.5 V falling detection point Typ – Typ +
SID537 VTR_4P5_F for VDDD 4% 4500 4% mV
LVD 4.6 V falling detection point Typ – Typ +
SID538 VTR_4P6_F for VDDD 4% 4600 4% mV
LVD 4.7 V falling detection point Typ – Typ +
SID539 VTR_4P7_F for VDDD 4% 4700 4% mV
LVD 4.8 V falling detection point Typ – Typ +
SID540 VTR_4P8_F for VDDD 4% 4800 4% mV
LVD 4.9 V falling detection point Typ – Typ +
SID541 VTR_4P9_F for VDDD 4% 4900 4% mV
LVD 5.0 V falling detection point Typ – Typ +
SID542 VTR_5P0_F for VDDD 4% 5000 4% mV
LVD 5.1 V falling detection point Typ – Typ +
SID543 VTR_5P1_F for VDDD 4% 5100 4% mV
LVD 5.2 V falling detection point Typ – Typ +
SID544 VTR_5P2_F for VDDD 4% 5200 4% mV
LVD 5.3 V falling detection point Typ – Typ +
SID545 VTR_5P3_F for VDDD 4% 5300 4% mV
LVD 2.8 V rising detection point Typ – Typ + Same as
SID546 VTR_2P8_R for VDDD 4% 2825 4% mV VTR_2P8_F + 25 mV
LVD 2.9 V rising detection point Typ – Typ + Same as
SID547 VTR_2P9_R for VDDD 4% 2925 4% mV VTR_2P9_F + 25 mV
LVD 3.0 V rising detection point Typ – Typ + Same as
SID548 VTR_3P0_R for VDDD 4% 3025 4% mV VTR_3P0_F + 25 mV
LVD 3.1 V rising detection point Typ – Typ + Same as
SID549 VTR_3P1_R for VDDD 4% 3125 4% mV VTR_3P1_F + 25 mV
LVD 3.2 V rising detection point Typ – Typ + Same as
SID550 VTR_3P2_R for VDDD 4% 3225 4% mV VTR_3P2_F + 25 mV
LVD 3.3 V rising detection point Typ – Typ + Same as
SID551 VTR_3P3_R for VDDD 4% 3325 4% mV VTR_3P3_F + 25 mV
LVD 3.4 V rising detection point Typ – Typ + Same as
SID552 VTR_3P4_R 3425 mV
for VDDD 4% 4% VTR_3P4_F + 25 mV
LVD 3.5 V rising detection point Typ – Typ + Same as
SID553 VTR_3P5_R 3525 mV
for VDDD 4% 4% VTR_3P5_F + 25 mV

Datasheet 150 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-16 System resources (continued)

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
SID554 VTR_3P6_R LVD 3.6 V rising detection point Typ – 3625 Typ + mV Same as
for VDDD 4% 4% VTR_3P6_F + 25 mV
SID555 VTR_3P7_R LVD 3.7 V rising detection point Typ – 3725 Typ + mV Same as
for VDDD 4% 4% VTR_3P7_F + 25 mV
SID556 VTR_3P8_R LVD 3.8 V rising detection point Typ – 3825 Typ + mV Same as
for VDDD 4% 4% VTR_3P8_F + 25 mV
LVD 3.9 V rising detection point Typ – Typ + Same as
SID557 VTR_3P9_R for VDDD 4% 3925 4% mV VTR_3P9_F + 25 mV
LVD 4.0 V rising detection point Typ – Typ + Same as
SID558 VTR_4P0_R for VDDD 4% 4025 4% mV VTR_4P0_F + 25 mV
LVD 4.1 V rising detection point Typ – Typ + Same as
SID559 VTR_4P1_R for VDDD 4% 4125 4% mV VTR_4P1_F + 25 mV
LVD 4.2 V rising detection point Typ – Typ + Same as
SID560 VTR_4P2_R for VDDD 4% 4225 4% mV VTR_4P2_F + 25 mV
LVD 4.3 V rising detection point Typ – Typ + Same as
SID561 VTR_4P3_R for VDDD 4% 4325 4% mV VTR_4P3_F + 25 mV
LVD 4.4 V rising detection point Typ – Typ + Same as
SID562 VTR_4P4_R for VDDD 4% 4425 4% mV VTR_4P4_F + 25 mV
LVD 4.5 V rising detection point Typ – Typ + Same as
SID563 VTR_4P5_R for VDDD 4% 4525 4% mV VTR_4P5_F + 25 mV
LVD 4.6 V rising detection point Typ – Typ + Same as
SID564 VTR_4P6_R for VDDD 4% 4625 4% mV VTR_4P6_F + 25 mV
LVD 4.7 V rising detection point Typ – Typ + Same as
SID565 VTR_4P7_R for VDDD 4% 4725 4% mV VTR_4P7_F + 25 mV
LVD 4.8 V rising detection point Typ – Typ + Same as
SID566 VTR_4P8_R for VDDD 4% 4825 4% mV VTR_4P8_F + 25 mV
LVD 4.9 V rising detection point Typ – Typ + Same as
SID567 VTR_4P9_R for VDDD 4% 4925 4% mV VTR_4P9_F + 25 mV
LVD 5.0 V rising detection point Typ – Typ + Same as
SID568 VTR_5P0_R for VDDD 4% 5025 4% mV VTR_5P0_F + 25 mV
LVD 5.1 V rising detection point Typ – Typ + Same as
SID569 VTR_5P1_R for VDDD 4% 5125 4% mV VTR_5P1_F + 25 mV
LVD 5.2 V rising detection point Typ – Typ + Same as
SID570 VTR_5P2_R for VDDD 4% 5225 4% mV VTR_5P2_F + 25 mV
LVD 5.3 V rising detection point Typ – Typ + Same as
SID571 VTR_5P3_R for VDDD 4% 5325 4% mV VTR_5P3_F + 25 mV
SID573 LVD_RR_A Power ramp rate: VDDD (Active) – – 100 mV/µs
SID574 LVD_RR_DS Power ramp rate: VDDD – – 10 mV/µs
(DeepSleep)
Active mode delay between
VDDD falling/rising through LVD
SID575 tDLY_ACT_LVD rising/falling point and an – – 1 µs Guaranteed by
design
internal LVD signal
transitioning

Datasheet 151 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-16 System resources (continued)

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
DeepSleep mode delay
between VDDD falling/rising
SID575A tDLY_DS_LVD through LVD rising/falling point – – 4 µs Guaranteed by
design
and an internal LVD signal
transitioning
Response time of LVD, VDDD
supply. (For falling-then-rising Guaranteed by
SID576 tRES_LVD 100 – – ns
supply at max ramp rate; design
threshold is LVD falling point)
High-voltage OVD specifications
HV OVD 5.0-V rising detection
SID580 VTR_5P0_R 5.049 5.205 5.361 V
point for VDDD and VDDA
HV OVD 5.0-V falling detection
SID581 VTR_5P0_F 5.025 5.18 5.335 V
point for VDDD and VDDA
HV OVD 5.5-V rising detection
SID582 VTR_5P5_R point for VDDD and VDDA 5.548 5.72 5.892 V
(default)
HV OVD 5.5-V falling detection
SID583 VTR_5P5_F point for VDDD and VDDA 5.524 5.695 5.866 V
(default)
Power ramp rate: VDDD and
SID585 HVOVD_RR_A V – – 100 mV/µs
DDA (Active)
Power ramp rate: VDDD and
SID586 HVOVD_RR_DS V – – 10 mV/µs
DDA (DeepSleep)
Active mode delay between
VDDD falling/rising through
Guaranteed by
SID587 tDLY_ACT_HVOVD VTR_5P0_F/R or VTR_5P5_F/R and – – 1 µs design
an internal HV OVD signal
transitioning
Active mode delay between
VDDA falling/rising through
tDLY_ACT_H- Guaranteed by
SID587A VTR_5P0_F/R or VTR_5P5_F/R and – – 1.5 µs design
VOVD_A
an internal HV OVD signal
transitioning
DeepSleep mode delay
between VDDD/VDDA
falling/rising through Guaranteed by
SID587B tDLY_DS_HVOVD V – – 4 µs
TR_5P0_F/R or VTR_5P5_F/R and design
an internal HV OVD signal
transitioning
Response time of HV OVD (for
SID588 tRES_HVOVD rising-then-falling supply at 100 – – ns Guaranteed by
max ramp rate; threshold is design
VTR_5P0_R or VTR_5P5_R)
Low-voltage OVD specifications
SID590 VTR_R_LVOVD LV OVD rising detection point 1.261 1.3 1.339 V
for VCCD
LV OVD falling detection point
SID591 VTR_F_LVOVD for VCCD 1.237 1.275 1.313 V

Datasheet 152 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-16 System resources (continued)

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
Active mode delay between
V falling/rising through Guaranteed by
SID595 tDLY_ACT_LVOVD V CCD – – 1 µs
TR_F/R_LVOVD and an internal LV design
OVD signal transitioning
DeepSleep mode delay
between VCCD falling/rising Guaranteed by
SID595A tDLY_DS_LVOVD through VTR_F/R_LVOVD and an – – 12 µs
design
internal LV OVD signal transi-
tioning
Response time of LV OVD. (For
rising-then-falling supply at Guaranteed by
SID596 tRES_LVOVD max ramp rate; threshold is 100 – – ns design
VTR_R_LVOVD)
Over-current detection (OCD) specifications
Over current detection range Guaranteed by
SID598A IOCD_LDO for internal Active regulator 312 – 630 mA design
Over current detection range
SID598B IOCD_EXT for external transistor mode 675 – 825 mA
Over current detection range
SID599 IOCD_DPSLP for internal DeepSleep 18 – 72 mA
regulator

VDDD
CPU and CPU and
Peripherals Regulators I/O Peripherals Regulators I/O
6.0 V
Reset
High-Z
By HV OVD
HV OVD rising trip
(Default: 5.548 V to
5.892 V)

Normal Normal
Enable
Reset Operation Operation
By
XRES_L
Disable High-Z
HV BOD rising trip
(Default: 2.474 V to
2.627 V) Reset
By HV BOD
POR rising trip
(1.5 V to 2.35 V)
Reset
High-Z
By POR
CMOS threshold
Disable
(0.7 V)
OFF OFF
-0.3 V

VDDD

XRES_L LOW Level HIGH Level

Figure 27-14 Device operations supply range

Datasheet 153 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

2.3 V

VDDD

tDLY_POR

Internal reset by POR

VDDD

tPOFF
1.45 V

Figure 27-15 POR specifications

Datasheet 154 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

VDDD, VDDA

VTR_2P7_R or VTR_3P0_R

VTR_2P7_F or VTR_3P0_F

Internal HV BOD signal

tDLY_ACT/DS_HVBOD
tDLY_ACT/DS_HVBOD

VDDD, VDDA

tRES_HVBOD
VTR_2P7_F or VTR_3P0_F

Figure 27-16 High-voltage BOD specifications

Datasheet 155 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

VCCD

VTR_R_LVBOD
VTR_F_LVBOD

Internal LV BOD signal

tDLY_ACT/DS_LVBOD tDLY_ACT/DS_LVBOD

VCCD

tRES_LVBOD
VTR_F_LVBOD

Figure 27-17 Low-voltage BOD specifications

Datasheet 156 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

VTR_5P0_R or VTR_5P5_R
VTR_5P0_F or VTR_5P5_F

VDDD/VDDA

Internal HV OVD signal

tDLY_ACT/DS_HVOVD
tDLY_ACT/DS_HVOVD

VTR_5P0_R or VTR_5P5_R
tRES_HVOVD

VDDD/VDDA

Figure 27-18 High-voltage OVD specifications

Datasheet 157 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

VTR_R_LVOVD

VTR_F_LVOVD

VCCD

Internal LV OVD signal

tDLY_ACT/DS_LVOVD

tDLY_ACT/DS_LVOVD

VTR_R_LVOVD
tRES_LVOVD

VCCD

Figure 27-19 Low-voltage OVD specifications

Datasheet 158 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

VDDD

LVD rising detection point

LVD falling detection point

Internal LVD signal

tDLY_ACT/DS_LVD
tDLY_ACT/DS_LVD

VDDD

tRES_LVD
LVD falling detection point

Figure 27-20 LVD specifications

Datasheet 159 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.10.1 SWD interface

Table 27-17 SWD interface specifications [Conditions: drive_sel<1:0>= 00]
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID300 fSWDCLK SWD clock input frequency – – 10 MHz 2.7 V ≤ VDDD ≤ 5.5 V
SID301 tSWDI_SETUP SWDI setup time 0.25 × T – – ns T = 1 / fSWDCLK
SID302 tSWDI_HOLD SWDI hold time 0.25 × T – – ns T = 1 / fSWDCLK
SID303 tSWDO_VALID SWDO valid time – – 0.5 × T ns T = 1 / fSWDCLK
SID304 tSWDO_HOLD SWDO hold time 1 – – ns T = 1 / fSWDCLK

Table 27-18 JTAG AC specifications [Conditions: drive_sel<1:0>= 00]

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID620 tJCKH TCK HIGH time 30 – – ns 30-pF load
SID621 tJCKL TCK LOW time 30 – – ns 30-pF load
SID622 tJCP TCK clock period 66.7 – – ns 30-pF load
SID623 tJSU TDI/TMS setup time 12 – – ns 30-pF load
SID624 tJH TDI/TMS hold time 12 – – ns 30-pF load
SID625 tJZX TDO High-Z to active – – 30 ns 30-pF load
SID626 tJXZ TDO active to High-Z – – 30 ns 30-pF load
SID627 tJCO TDO clock to output – – 30 ns 30-pF load

tJC KH tJC KL tJC P

TCK

tJH
tJS U
TDI/TMS

tJC O tJX Z
tJZX
TDO

Figure 27-21 JTAG specifications

Datasheet 160 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-19 Trace specifications [Conditions: drive_sel<1:0>= 00]

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID1412A CTRACE Trace Capacitive Load – – 30 pF
Trace clock cycle
SID1412 tTRACE_CYC Trace clock period 40 – – ns
time for 25 MHz
Clock low pulse
SID1413 tTRACE_CLKL Trace clock LOW pulse width 2 – – ns
width
SID1414 tTRACE_CLKH Trace clock HIGH pulse width 2 – – ns Clock high pulse
width
SID1415A tTRACE_SETUP Trace data setup time 3 – – ns Trace data setup
time
SID1416A tTRACE_HOLD Trace data hold time 2 – – ns Trace data hold time

Datasheet 161 002-21617 Rev. *M

2024-01-25
 27.11 Clock specifications

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Electrical specifications
All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.

Table 27-20 Root and intermediate clocks[58]

Maximum permitted clock frequency setting (MHz)[59]
Max permitted
Clock clock frequency Source PLL/FLL Clock source: ECO[60] PLL/FLL Clock source: IMO[61] Description
(MHz)[59]
Integer SSCG Fractional Integer SSCG Fractional
PLL200#0 200 NA NA 190 NA NA
200
FLL 100 NA NA 96 NA NA
CLK_HF0 Root clock for CPUSS, PERI
PLL200#0 100 NA NA 98 NA NA
100
FLL 100 NA NA 96 NA NA
PLL400#0 350 340 344 333 326 330
CLK_HF1 350 CM7 CPU Core#0, CM7 CPU Core#1 clock
FLL 100 NA NA 96 NA NA
PLL200#1 100 NA NA 98 NA NA
CLK_HF2 100 Peripheral clock root other than CLK_PERI
FLL 100 NA NA 96 NA NA
PLL200#0 100 NA NA 98 NA NA
CLK_HF3 100 Event generator (CLK_REF), clock output on EXT_CLK pins (when used as output)
162

FLL 100 NA NA 96 NA NA
PLL400#1 125 122 122 119 117 117
CLK_HF4 125 Ethernet Channel#0, Ethernet Channel#1 internal clock
FLL 100 NA NA 96 NA NA
PLL400#1 196.608 193 196.608 189 185 187 I2S channel#0, I2S channel#1, I2S channel#2 interface clock, Ethernet Channel#0 TSU,
CLK_HF5 196.608
FLL 100 NA NA 96 NA NA Ethernet Channel#1 TSU

PLL200#0 200 NA NA 190 NA NA

CLK_HF6 200 Root clock for SDHC, SMIF interface clock
FLL 100 NA NA 96 NA NA
CLK_HF7 8 ILO NA NA NA NA NA NA CSV
PLL400#0 350 340 344 333 326 330
CLK_FAST_0 350 Generated by clock gating CLK_HF1, CM7 CPU Core#0, intermediate clock
FLL 100 NA NA 96 NA NA
PLL400#0 350 340 344 333 326 330
CLK_FAST_1 350 Generated by clock gating CLK_HF1, CM7 CPU Core#1, intermediate clock
FLL 100 NA NA 96 NA NA
002-21617 Rev. *M

Notes
58. Intermediate clocks that are not listed have the same limitations as that of their parent clock.
59. Maximum clock frequency after the corresponding clock source (PLL/FLL + dividers). All internal tolerances and affects are covered by these frequencies.
2024-01-25

60. For ECO: up to ±150 ppm uncertainty of the external clock source are tolerated by design.
61. The IMO operation frequency tolerance is included. When DeepSleep mode isn't used, maximum permitted clock frequency setting of clock source IMO case is equal to clock source ECO case.
62. CLOCK_SLOW and CLK_HF0 are related by integer frequency ratio (that is, 1:1, 1:2, 1:3, and so on).
 Table 27-20 Root and intermediate clocks[58] (continued)

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Electrical specifications
Maximum permitted clock frequency setting (MHz)[59]
Max permitted
Clock clock frequency Source PLL/FLL Clock source: ECO[60] PLL/FLL Clock source: IMO[61] Description
(MHz)[59]
Integer SSCG Fractional Integer SSCG Fractional
PLL200#0 200 NA NA 190 NA NA
200
FLL 100 NA NA 96 NA NA
CLK_MEM Generated by clock gating CLK_HF0, intermediate clock for SMIF, Flash, Ethernet
PLL200#0 100 NA NA 98 NA NA
100
FLL 100 NA NA 96 NA NA
PLL200#0 100 NA NA 98 NA NA Generated by clock gating CLK_MEM, intermediate clock for CM0+, P-DMA, M-DMA,
CLK_SLOW 100
FLL 100 NA NA 96 NA NA Crypto, SMIF, SDHC

PLL200#0 100 NA NA 98 NA NA Generated by clock gating CLK_HF0, intermediate clock for IOSS, TCPWM0, CPU trace,
CLK_PERI 100 SMIF
FLL 100 NA NA 96 NA NA
163
002-21617 Rev. *M
2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-21 Relation between CLK_HF0 and CLK_SLOW (Example)[62]

CLK_HF0 (MHz) CLK_SLOW (MHz)
200 100
180 90
160 80
120 60
100 100
80 80

Table 27-22 PLL400 operation modes

PLL400 operation mode Spread spectrum clock generation Fractional

(SSCG)
Integer OFF OFF
SSCG ON OFF
Fractional OFF ON

Table 27-23 IMO AC specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID310 fIMOTOL IMO operating frequency 7.68 8 8.32 MHz
Start-up time to 90%
SID311 tSTARTIMO IMO start-up time – – 7.5 µs of final frequency
SID312 IIMO_ACT IMO current – 13.5 22 µA

Datasheet 164 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-24 ILO AC specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID320 fILOTRIM ILO operating frequency 30.47424 32.768 35.06176 kHz
Start-up time to 90%
SID321 tSTARTILO ILO start-up time – 8 12 µs of final frequency
SID323 IILO ILO current – 500 2800 nA

Table 27-25 ECO specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID330 fECO Crystal frequency range 8 – 33.34 MHz
SID332 RFDBK Feedback resistor value. 100 – 400 kΩ Guaranteed by design
Min: RTRIM = 3; Max: RTRIM =
0 with 100-kΩ step size on
RTRIM
Maximum operation
SID333 IECO3 ECO current at TJ = 150 °C – – 2000 µA current with a 33-MHz
crystal, 18-pF load
Time from set
CLK_ECO_-
CONFIG.ECO_EN to 1
SID334 tSTART_8M 8-MHz ECO start-up time[63] – – 10 ms until
CLK_ECO_STATUS.ECO
_READY is set to 1 (See
Clock Timing Diagrams)
Time from set
CLK_ECO_-
CONFIG.ECO_EN to 1
SID335 tSTART_33M 33-MHz ECO start-up time[63] – – 1 ms until
CLK_ECO_STATUS.ECO
_READY is set to 1 (See
Clock Timing Diagrams)

MCU VDDD

ITrim

Rf
RTrim ECO_IN: External crystal oscillator input pin
ECO_IN ECO_OUT: External crystal oscillator output pin
C1, C2: Load Capacitors
C1 C3* GT rim
C3*, C4*: Stray Capacitance of the PCB
VSSD
ECO

VSSD
C2 C4*
ECO_OUT
Rd Rd
0R FTrim

Figure 27-22 ECO connection scheme[64]

Notes
63.Mainly depends on the external crystal.
64.Refer to the family-specific Architecture TRM for more information on crystal requirements (002-24401, TRAVEO™ T2G Automotive
MCU body controller high architecture technical reference manual).

Datasheet 165 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-26 PLL specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
PLL (without SSCG and fractional divider) Specifications for 200 MHz
Time from stable
reference clock until PLL
SID340 tPLL200_LOCK Time to achieve PLL lock – – 35 µs frequency is within 0.1%
of final value and lock
indicator is set
SID341 fPLL_OUT Output frequency from PLL 11 – 200 MHz
block
For 125 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
SID342 PLL_LJIT1 Long term jitter –0.25 – 0.25 ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 500 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
SID343 PLL_LJIT2 Long term jitter –0.5 – 0.5 ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 1000 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
SID344 PLL_LJIT3 Long term jitter –0.5 – 0.5 ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
For 10000 ns
Guaranteed by design
fPLL_VCO: 320 MHz or 400
SID345A1 PLL_LJIT5 Long term jitter –0.75 – 0.75 ns MHz
fPLL_OUT: 40 MHz to 200 MHz
fPLL_PFD: 8 MHz
fPLL_IN: ECO
SID346 fPLL_IN PLL input frequency 3.988 – 33.34 MHz
PLL operating current
SID347 IPLL_200M (fOUT = 200 MHz) – 0.87 1.85 mA fOUT = 200 MHz
SID348C fPLL_VCO VCO frequency 170 – 400 MHz
SID349C fPLL_PFD PFD frequency 3.988 – 8 MHz
PLL (with SSCG and fractional divider) specifications for 400 MHz
Time from stable
reference clock until PLL
SID340A tPLL400_LOCK Time to achieve PLL lock – – 50 µs frequency is within 0.1%
of final value and lock
indicator is set
Programmed output
SID341A fOUT 25 – 350 MHz Integer mode
frequency from PLL Block
Programmed output
SID341B fOUT 25 – 340 MHz SSCG mode
frequency from PLL Block

Datasheet 166 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-26 PLL specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID343A SPREAD_D Spread spectrum 0.5 – 3 % Downspread only,
modulation depth triangle modulation
SID343B fSPREAD_MR Spread spectrum – – 32 kHz Selected by modulation
modulation rate divider from fPFD
For 125 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
SID342D1 PLL400_LJIT1 Long term jitter –0.25 – 0.25 ns (Integer mode)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
For 500 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
SID343D1 PLL400_LJIT2 Long term jitter –0.5 – 0.5 ns (Integer mode)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
For 1000 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
SID344D1 PLL400_LJIT3 Long term jitter –1 – 1 ns (Integer mode)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
For 10000 ns
Guaranteed by design
fVCO: 800 MHz or 700 MHz
SID345E1 PLL400_LJIT5 Long term jitter –1.5 – 1.5 ns (Integer mode)
fIN: ECO
fPFD: 4 MHz
fOUT: 100 MHz to 350 MHz
SID345A fVCO VCO frequency 400 – 800 MHz
SID346A fIN PLL input frequency 3.988 – 33.34 MHz
SID347A IPLL_400M PLL operating current – 1.4 2.2 mA fOUT = 400 MHz
(fOUT = 400 MHz)
SID348A fPFD_S PFD Frequency 3.988 – 20 MHz Integer/SSCG mode
(fIN / Reference divider)
SID349A fPFD_F PFD Frequency 8 – 20 MHz Fractional operation
(fIN / Reference divider)
fPFD = 8 MHz,
fVCO = 400 MHz,
Output frequency from PLL f = 100MHz,
SID341C fOUT_400_8S1 93 – 105 MHz OUT
Block (SSCG mode) Modulation frequency:
fPFD / 512,
Modulation depth: 3%
fPFD = 8 MHz,
fVCO = 400 MHz,
SID342C tPLL_C- Cycle to cycle jitter –710 – 710 ps fOUT = 100MHz,
JIT400_8S1 (SSCG mode) Modulation frequency:
fPFD / 512,
Modulation depth: 3%

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Electrical specifications

Table 27-26 PLL specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
fPFD = 8 MHz,
fVCO = 400 MHz,
Output frequency from PLL fOUT = 100MHz,
SID341D fOUT_400_8S2 Block (SSCG mode) 93 – 105 MHz Modulation frequency:
fPFD / 256,
Modulation depth: 3%
fPFD = 8 MHz,
fVCO = 400 MHz,
SID342D tPLL_C- Cycle to cycle jitter –710 – 710 ps fOUT = 100MHz,
JIT400_8S2 (SSCG mode) Modulation frequency:
fPFD / 256,
Modulation depth: 3%

Table 27-27 FLL specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
Wakeup with < 10 °C
temperature change
while in DeepSleep.
fFLL_IN = 8 MHz,
fFLL_OUT = 100 MHz,
SID350 tFLL_WAKE FLL wake up time – – 5 µs Time from stable
reference clock until
FLL frequency is
within 5% of final
value
Output frequency from FLL Output range of FLL
SID351 fFLL_OUT 24 – 100 MHz
block divided-by-2 output
This is added to the
SID352 FLL_CJIT FLL frequency accuracy –1 – 1 %
error of the source
SID353 fFLL_IN Input frequency 0.25 – 80 MHz
Reference clock: IMO,
CCO frequency:
SID354 IFLL FLL operating current – 250 360 µA 200 MHz, FLL
frequency: 100 MHz,
guaranteed by design

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-28 WCO specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
SID360 fWCO Crystal frequency – 32.768 – kHz Maximum drive level:
0.5 µW
SID361 WCO_DC WCO duty cycle 10 – 90 %
For Grade-S devices
Time from set
CTL.WCO_EN to 1
SID362 tSTART_WCO WCO start up time[65] – – 1000 ms until
STATUS.WCO_OK is
set to 1. (See Clock
Timing Diagrams)
SID362E tSTART_WCOE WCO start-up time[65] – – 1400 ms For Grade-E devices
Time from set
CTL.WCO_EN to 1
until
STATUS.WCO_OK is
set to 1. (See Clock
Timing Diagrams)
SID363 IWCO WCO current – 1.4 – µA

VDDD

MCU

Rf
WCO_IN: Watch crystal oscillator input pin
WCO_IN WCO_OUT: Watch crystal oscillator output pin
C1, C2: Load Capacitors
C1 C3* C3*, C4*: Stray Capacitance of the PCB
WCO

VSSD
VSSD
C2 C4*
WCO_OUT
Rd
0R

Figure 27-23 WCO connection scheme[66]

Notes
65.Mainly depends on the external crystal.
66.Refer to the family-specific Architecture TRM for more information on crystal requirements (002-24401, TRAVEO™ T2G Automotive
MCU body controller high architecture technical reference manual).

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-29 External clock input specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
For EXT_CLK pin (all
External clock input input level settings:
SID366 fEXT frequency 0.25 – 80 MHz CMOS, TTL,
Automotive)
SID367 EXT_DC External clock duty cycle 45 – 55 %

Table 27-30 MCWDT timeout specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
When using the ILO
(32.768 kHz + 7%) and
SID410 tMCWDT1 Minimum MCWDT timeout 57 – – µs
16-bit MCWDT counter
Guaranteed by design
When using the ILO
(32.768 kHz – 7%) and
SID411 tMCWDT2 Maximum MCWDT timeout – – 2.15 s 16-bit MCWDT counter
Guaranteed by design

Table 27-31 WDT timeout specifications

Spec ID Parameter Description Min Typ Max Units Details/Conditions
When using the ILO
(32.768 kHz + 7%) and
SID412 tWDT1 Minimum WDT timeout 57 – – µs
32-bit WDT counter,
guaranteed by design
When using the ILO
(32.768 kHz – 7%) and
SID413 tWDT2 Maximum WDT timeout – – 39.15 h 32-bit WDT counter,
guaranteed by design
When using the ILO
and 32-bit WDT
SID414 tWDT3 Default WDT timeout – 1000 – ms counter at 0x8000
(default value),
guaranteed by design

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Based on Arm® Cortex®-M7 dual
Electrical specifications

27.12 Clock timing diagrams

ECO: 8 MHz
PLL: 160 MHz
FLL: 100 MHz

Active
CLK_ECO_CONFIG.ECO_EN
8 MHz

ECO_OUT

CLK_ECO_STATUS.ECO_READY

10 ms

CLK_PLL_CONFIG.ENABLE

CLK_PLL_STATUS.LOCKED

35 µs 160 MHz

PLL_OUTPUT

CLK_FLL_CONFIG.FLL_ENABLE

CCO is already up-and-running

CLK_FLL_STATUS.LOCKED

5 µs 100 MHz

FLL_OUTPUT

Figure 27-24 ECO to PLL or FLL diagram

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Based on Arm® Cortex®-M7 dual
Electrical specifications

WCO: 32.768 kHz

FLL: 100 MHz

Active
CTL.WCO_EN
32.768 kHz

WCO_OUT

STATUS.WCO_OK

1000 ms

CLK_FLL_CONFIG.FLL_ENABLE
CCO is already up-and-running

CLK_FLL_STATUS.LOCKED

5 µs 100 MHz

FLL_OUTPUT

Figure 27-25 WCO to FLL diagram

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.13 Ethernet specifications

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-32 Ethernet specifications [Conditions: drive_sel<1:0>= 00]
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Ethernet general specifications
SID368 fSYS System clock max frequency – – 100 MHz Guaranteed by design
SID369 fAXI AXI clock max frequency – – 200 MHz Guaranteed by design
SID370 VETH Ethernet MAC IO supply voltage 3.0 – 3.6 V For VDDD or VDDIO_4
For MDIO all signals
SID364A CL_MD Load capacitance – – 25 pF between MAC and
PHY using
GPIO_STD/HSIO_STD
For MII and RMII all
signals between MAC
SID364A1 CL_MH Load capacitance – – 25 pF
and PHY using
HSIO_STD
For MII and RMII all
signals between MAC
SID364A2 CL_MG Load capacitance – – 15 pF and PHY using
GPIO_STD
For GMII and RGMII all
SID364B CL_GH Load capacitance – – 10 pF signals between MAC
and PHY using
HSIO_STD
20% to 80%, For MII,
SID365A tRF Rise / fall time (For input pins) – – 2 ns RMII, and MDIO using
GPIO_STD/HSIO_STD
Rise / fall time (For input and 20% to 80%, For GMII
SID365B tRF_G – – 1 ns
output pins) using HSIO_STD
Rise / fall time (For input and 20% to 80%, For RGMII
SID365B1 tRF_GM – – 0.75 ns
output pins) using HSIO_STD
Ethernet MII specifications for GPIO_STD/HSIO_STD
–
SID375 fTXRX_CLK MII TX/RX_CLK clock frequency 100pp 25 100pp MHz
at 100 Mbps m
m
DUTY_TX-
SID376 TX/RX clock duty cycle 35 – 65 %
RX_CLK
MII Transmit data (TX_CTL, TXD,
SID372 tSKEWT 0.5 – 25 ns
TX_ER) valid after TX_CLK
MII Receive data setup to
SID373 tSUR 10 – – ns
RX_CLK rising edge
MII Receive data hold to RX_CLK
SID374 tHOLDR 10 – – ns
rising edge
Ethernet RMII Specifications for GPIO_STD/HSIO_STD
–
SID375A fREF_CLK RMII reference clock frequency 50pp 50 50pp MHz External clock
(input) m
m
SID376A DUTY_REF_ Duty cycle of reference clock 35 – 65 %
CLK (input)
SID377 tSU RX_CTL, RXD[1:0], RX_ER data 4 – – ns
setup to REF_CLK rising edge

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-32 Ethernet specifications [Conditions: drive_sel<1:0>= 00] (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
RX_CTL, RXD[1:0], RX_ER, data
SID378 tHOLD 2 – – ns
hold from REF_CLK rising edge
TX_CTL, TXD[1:0], data output
SID393 tTXOUT 2 – 14.6 ns For GPIO_STD
delay from REF_CLK rising edge
TX_CTL, TXD[1:0], data output
SID393A tTXOUT_A 2 – 14 ns For HSIO_STD
delay from REF_CLK rising edge
Ethernet GMII Specifications for HSIO_STD
SID379 fP_REFCLK REF_CLK clock frequency – 125 – MHz
–
SID380 fP_RXCLK RX_CLK clock frequency 50pp 125 50pp MHz
m
m
SID380A tP_RXCLK RX_CLK clock period 7.5 – 8.5 ns
SID380B tP_HL_RXCLK RX_CLK clock time HIGH/LOW 2.5 – – ns
TX(GTX)_CLK frequency – 100pp
SID389 fP_TXCLK 100pp 125 MHz
(External/Internal mode) m m
TX(GTX)_CLK clock period
SID389A tP_TXCLK (External/Internal mode) 7.5 – 8.5 ns
TX(GTX)_CLK clock time
SID389B tP_HL_TXCLK HIGH/LOW (External/Internal 2.5 – – ns
mode)
TX_CTL, TXD, TX_ER Setup to
SID381 tSETUPT 2.5 – – ns
TX(GTX)_CLK rising edge
TX_CTL, TXD, TX_ER hold from
SID382 tHOLDT 0.5 – – ns
TX(GTX)_CLK rising edge
RX_CTL, RXD, RX_ER setup to
SID383 tSETUPR 2 – – ns
RX_CLK rising edge
RX_CTL, RXD, RX_ER hold from
SID384 tHOLDR 0 – – ns
RX_CLK rising edge
Ethernet RGMII Specifications for HSIO_STD
SID385 fCYC REF_CLK clock frequency – 125 – MHz
TX(TXC)_CLK (External mode) – 50pp
SID385_1 fP_TXCRXC and RX(RXC)_CLK clock 50pp 125 MHz
frequency m m
TX(TXC)_CLK (External
SID385B tP_TXCRXC mode)/RX(RXC)_CLK clock 7.2 8 8.8 ns
period
DUTY_TXC Duty for TX(TXC)_CLK (External
SID386B 45 – 55 %
RXC mode)/RX(RXC)_CLK clock
SID387 tSKEWT Data to clock output skew –0.5 – 0.5 ns
SID388 tSKEWR Data to clock input skew 1 – 2.6 ns
Ethernet MDIO Specifications for GPIO_STD/HSIO_STD
SID395 tMDCYC MDC clock cycle 400 – – ns
The minimum HIGH and LOW
SID395A tHL_MDCYC 160 – – ns
times for MDC
MDIO input setup time to MDC
SID396 tMDIS 100 – – ns
rising edge

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-32 Ethernet specifications [Conditions: drive_sel<1:0>= 00] (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions
MDIO input hold time to MDC
SID397 tMDIH 0 – – ns
rising edge
MDIO output skew from MDC
SID398 tMDIO 10 – 390 ns
rising edge

RX_CLK 2.0 V

0.8 V

2 3

RXD, RX_CTL,
RX_ER 2.0 V

0.8 V

2.0 V
TX_CLK
0.8 V
4

2.0 V
TXD, TX_CTL,
TX_ER 0.8 V

1: RX_CLK or TX_CLK cycle = 1/fTXRX_CLK

2: MII receive data setup time to RX_CLK rising edge = tSUR
3: MII receive data hold time to RX_CLK rising edge = tHOLDR
4: MII transmit data valid after TX_CLK rising edge = tSKEWT

Figure 27-26 MII timing diagram

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Based on Arm® Cortex®-M7 dual
Electrical specifications

MDC 2.0 V

0.8 V

2 3

MDIO
2.0 V

0.8 V

2.0 V
MDC
0.8 V
4

2.0 V
MDIO
0.8 V

1: MDC clock cycle = tMDCCYC

2: MDIO input setup time to MDC rising edge = tMDIS
3: MDIO input hold time tp MDC rising edge = tMDIH
4: MDIO output skew from MDC rising edge = tMDIO

Figure 27-27 MDIO timing diagram

REF_CLK
1.4 V

2 3

RXD, RX_CTL, 2.0 V

RX_ER
0.8 V

2.0 V
TXD, TX_CTL
0.8 V

1: RMII reference clock cycle = 1/fREF_CLK

2: Data setup to REF_CLK rising edge = tSU
3: Data hold from REF_CLK rising edge = tHOLD
4: Data output delay from REF_CLK_rising edge = tTXOUT

Figure 27-28 RMII timing diagram

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

TX_CLK or 1.9 V
RX_CLK
0.7 V

2 3

TXD, TX_CTL,
TX_ER or RXD, 1.9 V
RX_CTL,
RX_ER 0.7 V

1: TX_CLK or RX_CLK cycle = tP_TXCLK = tP_RXCLK

2: Data setup to TX_CLK or RX_CLK rising edge = tSETUPT or tSETUPR
3: Data hold from TX_CLK or RX_CLK rising edge = tHOLDT or tHOLDR

Figure 27-29 GMII timing diagram

1
100 %
RX_CLK,
TX_CLK 50 %
0%

TX_CTL, 100 %
RX_CTL, TXD,
RXD 50 %
0%
2 2
2 2

1: TX_CLK and RX_CLK clock cycle = 1/fCYC

2: Data to clock output skew = tSKEWT

Figure 27-30 RGMII Tx timing diagram

1
100 %
RX_CLK,
TX_CLK 50 %
0%

TX_CTL, 100 %
RX_CTL, TXD,
RXD 50 %
0%
2 2 2 2

1: TX_CLK and RX_CLK clock cycle = 1/fCYC

2: Data to clock input skew = tSKEWR

Figure 27-31 RGMII Rx timing diagram

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.13.1 Minimum bus frequency requirements

The following table details the required minimum operating frequencies for all possible Ethernet configurations
and MAC speeds. Ethernet module uses AXI interface for DMA access.

Table 27-33 Minimum AXI frequency for MAC speeds

DMA bus width MAC rate Minimum AXI frequency
64 1 Gbps 65 MHz
64 100 Mbps 10 MHz
64 10 Mbps 10 MHz

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.14 SDHC specifications

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-34 SDHC specifications
Spec ID Parameter Description Min Typ Max Units Details/Conditions
SDHC and eMMC specifications (the source clock must be divided by 2 or more in DDR modes)
SID801 VSDHC SDHC IO supply voltage 2.7 – 3.6 V For VDDIO_1 or VDDIO_3
drive_sel<1:0>= 0b00
SID802 IODS I/O drive select 8 – 8 mA for all modes
SID803 tIT Input transition time 0.7 – 3 ns
SD: DS timing specifications for GPIO_STD/HSIO_STD
SID810 fLP Interface clock period – – 25 MHz 40-ns period
SID812 CD I/O loading at DATA/CMD pins – – 40 pF
SID813 CC I/O loading at CLK pins – – 40 pF
Output setup time of CMD/DAT
SID814 tOS 5.5 – – ns
prior to CLK
Output hold time of CMD/DAT
SID815 tOH after CLK 5.5 – – ns

SID816 tIS_LP Input setup time of CMD/DAT 24 – – ns Clock period - Output

prior to CLK delay
Input hold time of CMD/DAT
SID818 tIH 0 – – ns
after CLK
SD: HS timing specifications for HSIO_STD
SID820 fLP_SD_HS Interface clock period – – 50 MHz 20-ns period
SID822 CD_SD_HS I/O loading at DATA/CMD pins – – 40 pF
SID823 CC_SD_HS I/O loading at CLK pins – – 40 pF
Output setup time of CMD/DAT
SID824 tOS_SD_HS 6.5 – – ns
prior to CLK
Output hold time of CMD/DAT
SID825 tOH_SD_HS after CLK 2.5 – – ns

SID826 tIS_LP_SD_HS Input setup time of CMD/DAT 4 – – ns Clock period less

prior to CLK output delay
Input hold time of CMD/DAT
SID828 tIH_SD_HS 2.5 – – ns
after CLK
eMMC: BWC timing specifications for GPIO_STD/HSIO_STD
fLP_eM-
SID870 Interface clock period – – 26 MHz 38.4-ns period
MC_BWC
CD_eM-
SID872 I/O loading at DATA/CMD pins – – 30 pF
MC_BWC

SID873 CC_eM- I/O loading at CLK pins – – 30 pF

MC_BWC
tOS_eM- Output setup time of CMD/DAT
SID874 3.5 – – ns
MC_BWC prior to CLK
tOH_eM- Output hold time of CMD/DAT
SID875 3.5 – – ns
MC_BWC after CLK

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-34 SDHC specifications (continued)

Spec ID Parameter Description Min Typ Max Units Details/Conditions

SID876 tIS_LP_eM- Input setup time of CMD/DAT 9.7 – – ns Clock period less
MC_BWC prior to CLK output delay
tIH_eM- Input hold time of CMD/DAT
SID878 8.3 – – ns
MC_BWC after CLK
eMMC: SDR timing specifications for HSIO_STD
fLP_eM-
SID880 Interface clock period – – 52 MHz 19.2-ns period
MC_SDR
CD_eM-
SID882 I/O loading at DATA/CMD pins – – 30 pF
MC_SDR
CC_eM-
SID883 I/O loading at CLK pins – – 30 pF
MC_SDR

SID884 tOS_eM- Output setup time of CMD/DAT 3.5 – – ns

MC_SDR prior to CLK
tOH_eM- Output hold time of CMD/DAT
SID885 3.5 – – ns
MC_SDR after CLK
tIS_LP_eM- Input setup time of CMD/DAT Clock period less
SID886 prior to CLK 3.5 – – ns output delay
MC_SDR

SID888 tIH_eM- Input hold time of CMD/DAT 2.5 – – ns

MC_SDR after CLK
eMMC: DDR timing specifications for HSIO_STD

SID890 fLP_eM- Interface clock period – – 52 MHz 19.2-ns period

MC_DDR
DUTY_-
SID892 CLK_eM- Duty cycle of output CLK 45 – 55 %
MC_DDR
CD_eM-
SID893 I/O loading at DATA/CMD pins – – 20 pF
MC_DDR
CC_eM-
SID894 I/O loading at CLK pins – – 20 pF
MC_DDR

SID895 tOS_eM- Output setup time of CMD/DAT 2.6 – – ns

MC_DDR prior to CLK
tOH_eM- Output hold time of CMD/DAT
SID896 2.6 – – ns
MC_DDR after CLK
tIS_LP_eM- Input setup time of CMD/DAT Clock period less
SID897 prior to CLK 2.4 – – ns output delay
MC_DDR

SID899 tIH_eM- Input hold time of CMD/DAT 1.5 – – ns

MC_DDR after CLK

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Input Timing for SD: DS

1 VDDIO_1
or VDDIO_3
CLK 0.5 x VDDIO_1
or VDDIO_3
VSSD or VSSIO_3

2 3

CMD/DAT 0.5 x VDDIO_1

Invalid Valid
or VDDIO_3

1: Clock period = 1/fLP

2: Input setup time = tIS_LP
3: Input hold time = tIH

Figure 27-32 SD default speed input timing

Output Timing for SD: DS

VDDIO_1 1
or
VDDIO_3
CLK 0.5 x VDDIO_1
or VDDIO_3
VSSD or VSSIO_3

2 3

CMD/DAT 0.5 x VDDIO_1

Invalid Valid Invalid
or VDDIO_3

1: Clock period = 1/fLP

2: Output setup time = tOS
3: Output hold time = tOH

Figure 27-33 SD default speed output timing

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Input Timing for SD: HS and eMMC: BWC/SDR

1 VDDIO_1
or VDDIO_3
CLK 0.5 x VDDIO_1
or VDDIO_3
VSSD or VSSIO_3

2 3

CMD/DAT 0.5 x VDDIO_1

Invalid Valid
or VDDIO_3

1: Clock period = 1/fLP_SD_HS or 1/fLP_eMMC_BWC or 1/fLP_eMMC_SDR

2: Input setup time = tIS_LP_SD_HS or tIS_LP_eMMC_BWC or tIS_LP_eMMC_SDR
3: Input hold time = tIH_SD_HS or tIH_eMMC_BWC or tIH_eMMC_SDR

Figure 27-34 SD high-speed and eMMC BWC/SDR input timing

Output Timing for SD: HS and eMMC: BWC/SDR

VDDIO_1 1
or
VDDIO_3
CLK 0.5 x VDDIO_1
or VDDIO_3
VSSD or VSSIO_3

2 3

CMD/DAT 0.5 x VDDIO_1

Invalid Valid Invalid
or VDDIO_3

1: Clock period = 1/fLP_SD_HS or 1/fLP_eMMC_BWC or 1/fLP_eMMC_SDR

2: Output setup time = tOS_SD_HS or tOS_eMMC_BWC or tOS_eMMC_SDR
3: Output hold time = tOH_SD_HS or tOH_eMMC_BWC or tOH_eMMC_SDR

Figure 27-35 SD high-speed and eMMC BWC/SDR output timing

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Based on Arm® Cortex®-M7 dual
Electrical specifications

Input Timing for eMMC: DDR

1
VDDIO_3

CLK 0.5 x VDDIO_3

VSSIO_3
2 3 2 3

CMD/DAT Valid Valid 0.5 x VDDIO_3

1: Clock period = 1/fLP_eMMC_DDR

2: Input setup time = tIS_LP_eMMC_DDR
3: Input hold time = tIH_eMMC_DDR

Figure 27-36 eMMC DDR input timing

Output Timing for eMMC: DDR

1
VDDIO_3

CLK 0.5 x VDDIO_3

VSSIO_3
2 3 2 3

CMD/DAT Valid Valid 0.5 x VDDIO_3

1: Clock period = 1/fLP_eMMC_DDR

2: Output setup time = tOS_LP_eMMC_DDR
3: Output hold time = tOH_eMMC_DDR

Figure 27-37 eMMC DDR output timing

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Based on Arm® Cortex®-M7 dual
Electrical specifications

27.15 FlexRay specifications

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-35 FlexRay specification
Spec ID Parameter Description Min Typ Max Units Details/Conditions
Guaranteed by design,
SID465 fCLK_S System clock (clk_sys) frequency – – 80 MHz
Reference clock: ECO
FlexRay clock (clk_peri) Guaranteed by design,
SID466 fCLK_P frequency
– – 80 MHz
Reference clock: ECO
FlexRay I/O supply voltage
SID470 VFR 3.0 – 5.5 V drive_sel<1:0> = 0b00
(VDDIO_2)
TxEN output characteristics
SID450 tCCTxENRISE25 Rise time of TxEN signal at CC – – 9 ns 20% to 80%, 25-pF load
SID451 tCCTxENFALL25 Fall time of TxEN signal at CC – – 9 ns 20% to 80%, 25-pF load
Sum of delay between TP1_FF
20% to 80%, 25-pF load,
SID452 tCCTxEN01 and TP1_CC and delays derived – – 25 ns
from TP1_FFi, rising edge TxEN guaranteed by design

Sum of delay between TP1_FF

20% to 80%, 25-pF load,
SID453 tCCTxEN10 and TP1_CC and delays derived – – 25 ns
guaranteed by design
from TP1_FFi, falling edge TxEN
SID468 CTXEN I/O loading at TxEN pin – – 25 pF
TxD output characteristics
Asymmetry of sending CC 25-pF load, guaranteed
SID454 tCCTxASYM (= tCCDTxD 50% – 100 ns) –2.45 – 2.45 ns by design
SID455 tCCTxDRF25 Sum of rise and fall time – – 9 ns 20% to 80%, 25-pF load
SID455A tCCTxDR15 Rise time of TxD signal – – 2.5 ns 30% to 70%, 15-pF load
SID455B tCCTxDF15 Fall time of TxD signal – – 2.5 ns 30% to 70%, 15-pF load
Sum of delay between clock to Q 20% to 80%, 25-pF load,
SID456 tCCTxD01 of the last FF and the final output – – 25 ns guaranteed by design
buffer, rising edge TxD
Sum of delay between clock to Q
20% to 80%, 25-pF load,
SID457 tCCTxD10 of the last FF and the final output – – 25 ns
guaranteed by design
buffer, falling edge TxD
SID469 CTXD I/O loading at TxD pin – – 25 pF
RxD input characteristics
SID458 CCCRxD Input capacitance on RxD pin – – 10 pF
Threshold for detecting logical 0.35 × 0.70 ×
SID459 VCCLogic_1 – V
HIGH VDDIO_2 VDDIO_2
Threshold for detecting logical 0.30 × 0.65 ×
SID460 VCCLogic_0 LOW VDDIO_2 – V
VDDIO_2
Sum of delay from actual input to
SID461 tCCRxD01 the D input of the first FF, rising – – 10 ns Guaranteed by design
edge RxD
Sum of delay from actual input to
SID462 tCCRxD10 the D input of the first FF, falling – – 10 ns Guaranteed by design
edge RxD
Receiver asymmetry

Acceptance of asymmetry at For all data rates

SID463 tCCRxASYMAC15 receiving CC with 15-pF load –31.5 – 44 ns including clock deviation
of ±500 ppm
For all data rates
tCCRxASYMAC25 Acceptance
of asymmetry at
SID464 receiving CC with 25-pF load –30.5 – 43 ns including clock deviation
of ±500 ppm

Datasheet 184 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.16 Audio subsystem specifications

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-36 Audio subsystem specifications
Details/
Spec ID Parameter Description Min Typ Max Units Conditions

SID770 fAUDIO Audio subsystem frequency Guaranteed by

– – 200 MHz
design
Audio subsystem I/O supply
SID772 VAUDIO 3.0 – 3.6 V For VDDIO_2
voltage
drive_sel<1:0>=
SID773 VOL_A Output voltage LOW level – – 0.4 V 0b0X, Pull-up,
pull-down: off
drive_sel<1:0>=
SID774 VOH_A Output voltage HIGH level VDDIO_2 – 0.5 – – V 0b0X, Pull-up,
pull-down: off
Input voltage HIGH
SID775 VIH_CMOS_A 0.7 × VDDIO_2 – – V
threshold in CMOS mode
Input voltage LOW
SID776 VIL_CMOS_A – – 0.3 × VDDIO_2 V
threshold in CMOS mode
I2S/TDM word clock frequency
SID796 fWS_I2S WS clock rate in I2S mode Guaranteed by
8 – 192 kHz
design

SID797 fWS_TDM WS clock rate in TDM mode Guaranteed by

– – 96 kHz
design

SID798 Word Length of I2S word Guaranteed by

8 – 32 bit
design
I2S/TDM Master mode
Except TDM 96 kHz
mode, TX/RX_WS
Delay Time of TX/RX_WS output and
Output Transition from TX/RX_SCK output
SID740 tD_WS –8 – 9 ns
Falling Edge of TX/RX_SCK with
Output drive_sel<1:0> = 0b
01, guaranteed by
design
TDM 96 kHz mode,
TX/RX_WS output
with
Delay Time of TX/RX_WS drive_sel<1:0> =
output Transition from 0b01 and
SID740A tD_WS_TDM96A –8 – 11 ns
Falling Edge of TX/RX_SCK TX/RX_SCK output
output with
drive_sel<1:0> =
0b00, guaranteed
by design

Datasheet 185 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-36 Audio subsystem specifications (continued)

Details/
Spec ID Parameter Description Min Typ Max Units Conditions
TX_SDO and
TX_SCK output
Delay Time of TX_SDO with
SID741 tD_SDO Transition from Falling Edge drive_sel<1:0> =
–8 – 8 ns
of TX_SCK Output 0b01 for except
TDM 96 kHz mode,
guaranteed by
design
TX_SDO with
drive_sel<1:0> =
0b01 and TX_SCK
Delay time of TX_SDO output with
SID741A tD_SDO_TDM96 Transition from Falling Edge –8 – 8 ns drive_sel<1:0> =
of TX_SCK Output 0b00 for TDM
96 kHz mode,
guaranteed by
design

RX_SDI setup time to the RX_SCK output

following rising edge of with
SID742 tS_SDI 11 – – ns drive_sel<1:0> =
RX_SCK output
(RX_CTL.B_CLOCK_INV = 0) 0b00, guaranteed
by design
RX_SDI hold time to the RX_SCK output
rising edge of RX_SCK with
SID743 tH_SDI tMCLK_SOC – 0.9 – – ns drive_sel<1:0> =
output
(RX_CTL.B_CLOCK_INV = 0) 0b00, guaranteed
by design

RX_SDI setup time to the RX_SCK output

following falling edge of with
SID744 tS_SDI1 11 – – ns drive_sel<1:0> =
RX_SCK output
(RX_CTL.B_CLOCK_INV = 1) 0b00, guaranteed
by design

RX_SDI hold time to the RX_SCK output

falling edge of RX_SCK with
SID745 tH_SDI1 tMCLK_SOC –
output 0.9 – – ns drive_sel<1:0> =
(RX_CTL.B_CLOCK_INV = 1) 0b00, guaranteed
by design
TX/RX_SCK output bit clock Guaranteed by
SID746 tSCKCY 45 – 55 %
duty cycle design
Internal Fractional
SID748 fMCLK_SOC MCLK input clock frequency 1.024 – 196.608 MHz PLL, guaranteed by
design
SID748A fMCLK_SOC_E MCLK input clock frequency 1.024 – 98.304 MHz External clock
SID749 tMCLK_SOC MCLK input clock period Guaranteed by
5.086 – 976.563 ns
design
MCLK Input clock jitter Guaranteed by
SID750 tJITTER –200 – 200 ps
tolerance design

Datasheet 186 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-36 Audio subsystem specifications (continued)

Details/
Spec ID Parameter Description Min Typ Max Units Conditions
MCLK output with
MCLK output clock drive_sel<1:0> =
SID748B fMCLK 1.024 – 25 MHz
frequency 0b00, Guaranteed
by design
MCLK output with
MCLK output clock drive_sel<1:0> =
SID748C fMCLK1 1.024 – 15 MHz
frequency 0b01, Guaranteed
by design

SID749B fMCLK_DT MCLK output clock duty Guaranteed by

45 – 55 %
design
I2S/TDM Slave mode
TX/RX_WS input alignment
clock setup time to the Guaranteed by
SID751 tS_WS 5 – – ns
following rising edge of design
TX/RX_SCK input
TX/RX_WS input alignment
SID752 tH_WS clock hold time to the rising tMCLK_SOC + 5.0 Guaranteed by
– – ns
edge of TX/RX_SCK Input design
Delay time of TX_SDO TX_SDO with
transition from falling edge drive_sel<1:0>=
SID753 tD_SDO –tMCLK_SOC + 5.0 – tMCLK_SOC + 15 ns
of TX_SCK input 0b00, guaranteed
(TX_CTL.B_CLOCK_INV = 0) by design
Delay time of TX_SDO TX_SDO with
transition from rising edge drive_sel<1:0>=
SID754 tD_SDO1 –tMCLK_SOC + 5.0 – tMCLK_SOC + 15 ns
of TX_SCK input 0b00, guaranteed
(TX_CTL.B_CLOCK_INV = 1) by design
RX_SDI setup time to the
SID755 tS_SDI following rising edge of Guaranteed by
5 – – ns
RX_SCK input design
RX_SDI hold time to the Guaranteed by
SID756 tH_SDI
rising edge of RX_SCK input tMCLK_SOC + 5.0 – – ns
design
TX/RX_SCK input bit clock Guaranteed by
SID757 tSCKCY 45 – 55 %
duty cycle design

Datasheet 187 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

I2S/TDM Master Mode: Output Delay Timing

VDDIO_2
TX/RX_SCK
or TX_SCK 0.5 x VDDIO_2
output
VSSD

VDDIO_2
TX/RX_WS
or TX_SDO 0.5 x VDDIO_2
output
VSSD

1: Delay time = tD_WS or tD_WS_TDM96A or tD_SDO or tD_SDO_TDM96

Figure 27-38 Master output delay

I2S/TDM Master Mode: Setup Timing

(RX_CTL.B_CLOCK_INV = 0)

VDDIO_2
RX_SCK
0.5 x VDDIO_2
output
VSSD

1 2

VDDIO_2
RX_SDI
input 0.5 x VDDIO_2

VSSD

1: Setup time = tS_SDI

2: Hold time = tH_SDI

Figure 27-39 Master setup without clock inversion

Datasheet 188 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

I2S/TDM Master Mode: Setup Timing

(RX_CTL.B_CLOCK_INV = 1)

VDDIO_2
RX_SCK
0.5 x VDDIO_2
output
VSSD

1 2

VDDIO_2
RX_SDI
input 0.5 x VDDIO_2

VSSD

1: Setup time = tS_SDI1

2: Hold time = tH_SDI1

Figure 27-40 Master setup with clock inversion

I2S/TDM Slave Mode: Output Delay Timing

VDDIO_2

TX_SCK input 0.5 x VDDIO_2

(TX_CTL.B_CLOCK_INV = 0)
VSSD

VDDIO_2
TX_SCK input
(TX_CTL.B_CLOCK_INV = 1) 0.5 x VDDIO_2

VSSD

VDDIO_2

TX_SDO output 0.5 x VDDIO_2

VSSD

1: Delay time = t D_SDO or tD_SDO1

Figure 27-41 Slave output delay

Datasheet 189 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

I2S/TDM Slave Mode: Setup Timing

VDDIO_2
TX/RX_SCK
or RX_SCK 0.5 x VDDIO_2
input
VSSD

1 2

VDDIO_2
TX/RX_WS
or RX_SDI 0.5 x VDDIO_2
input
VSSD

1: Setup time = tS_WS or tS_SDI

2: Hold time = tH_WS or tH_SDI

Figure 27-42 Slave setup

Datasheet 190 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

27.17 Serial memory interface specifications

All specifications are valid for –40 °C  TA  125 °C and for 2.7 V to 5.5 V except where noted.
Table 27-37 SMIF specifications [Conditions: drive_sel<1:0>= 00]

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
SMIF DC specification
SID785 VSMIF SMIF I/O supply voltage 2.7 – 3.6 V For VDDIO_1 or VDDIO_3
SMIF HSSPI(SDR) specification for HSIO_STD
SID760 CL_SDR_HSIO Load capacitance – – 30 pF
Guaranteed by
SID761 SR_SDR_HSIO Input rise and fall slew rates 1.5 – – V/ns
design
SID762 fCK_SDR_HSIO Clock frequency - – 100 MHz
SID763 tCK_SDR_HSIO Clock period 1 / fCK_SDR_HSIO – – ns
SID764 DCK_SDR_HSIO Clock duty 45 – 55 %
SID765 CSR_SDR_HSIO Clock rise and fall slew rates 1.5 – – V/ns
SID766 tCS_SDR_HSIO Chip select HIGH time 10 – – ns
SID767 tCSS_SDR_HSIO Chip select active setup time 3 – – ns
SID768 tCSH_SDR_HSIO Chip select active hold time 5 – – ns
For other
frequencies:
tSU = tSU_min + 0.45 ×
(tCK - tCK_min)
Data setup time tSU_min = value at min
SID769 tSU_SDR_HSIO 1.5 – – ns
(fCK = 100 MHz) of SID769
tCK_min = value at min
of SID763
tCK = actual clock
period
For other
frequencies:
tHD = tHD_min + 0.45 ×
(tCK - tCK_min)
Data hold time tHD_min = value at
SID780 tHD_SDR_HSIO 2 – – ns
(fCK = 100 MHz) min of SID780
tCK_min = value at min
of SID763
tCK = actual clock
period
Clock LOW to input data
SID781 tV_SDR_HSIO 1.5 – 7.65 ns
valid
SID782 tHO_SDR_HSIO Input hold time 2 – – ns
Guaranteed by
SID783 tDIS_SDR_HSIO Input disable time 0 – 7.5 ns
design
tIO_SKEW_S- Data skew (first data bit to Guaranteed by
SID784 – – 0.6 ns
DR_HSIO last data bit) design
SMIF HSSPI(SDR) Specification for GPIO_STD
SID760A CL_SDR_GPIO Load capacitance – – 30 pF

Datasheet 191 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-37 SMIF specifications (continued)[Conditions: drive_sel<1:0>= 00]

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
Guaranteed by
SID761A SR_SDR_GPIO Input rise and fall slew rates 1 – – V/ns
design
SID762A fCK_SDR_GPIO Clock frequency – – 32 MHz
SID763A tCK_SDR_GPIO Clock period 1 / fCK_SDR_GPIO – – ns
DCK_S-
SID764A Clock duty 45 – 55 %
DR_GPIO
SID765A CSR_SDR_GPIO Clock rise and fall slew rates 1 – – V/ns
SID766A tCS_SDR_GPIO Chip select HIGH time 30 – – ns
SID767A tCSS_SDR_GPIO Chip select active setup time 9 – – ns
SID768A tCSH_SDR_GPIO Chip select active hold time 15 – – ns
SID769A tSU_SDR_GPIO Data setup time 4.5 – – ns
SID780A tHD_SDR_GPIO Data hold time 6 – – ns
Clock LOW to input data
SID781A tV_SDR_GPIO 4.5 – 9 ns
valid
SID782A tHO_SDR_GPIO Input hold time 2 – – ns
Guaranteed by
SID783A tDIS_SDR_GPIO Input disable time 0 – 22.5 ns
design
tIO_SKEW_S- Data skew (first data bit to Guaranteed by
SID784A – – 1.8 ns
DR_GPIO last data bit) design
SMIF HSSPI(DDR) specification for HSIO_STD
SID760B CL_DDR_HSIO Load capacitance – – 15 pF
Guaranteed by
SID761B SR_DDR_HSIO Input rise and fall slew rates 1.5 – - V/ns
design
SID762B2 fCK_DDR_HSIO Clock frequency - – 90 MHz
SID763B tCK_DDR_HSIO Clock period 1 / fCK_DDR_HSIO – – ns
DCK_D-
SID764B Clock duty 45 – 55 %
DR_HSIO
CSR_D-
SID765B Clock rise and fall slew rates 1.5 – – V/ns
DR_HSIO
SID766B tCS_DDR_HSIO Chip select HIGH time 10 – – ns
SID767B tCSS_DDR_HSIO Chip select active setup time 4 – – ns
SID768B tCSH_DDR_HSIO Chip select active hold time 4 – – ns
For other
frequencies:
tSU = tSU_min + 0.225 ×
(tCK - tCK_min)
Data setup time tSU_min = value at min
SID769B tSU_DDR_HSIO 2 – – ns
(fCK = 90 MHz) of SID769B
tCK_min = value at min
of SID763B
tCK = actual clock
period

Datasheet 192 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-37 SMIF specifications (continued)[Conditions: drive_sel<1:0>= 00]

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
For other
frequencies:
tHD = tHD_min + 0.225
× (tCK - tCK_min)
Data hold time tHD_min = value at
SID780B tHD_DDR_HSIO 1.2 – – ns
(fCK = 90 MHz) min of SID780B
tCK_min = value at min
of SID763B
tCK = actual clock
period
Clock LOW to input data
SID781B tV_DDR_HSIO 0 – 6.5 ns
valid
SID782B tHO_DDR_HSIO Input hold time 1 – – ns
Guaranteed by
SID783B tDIS_DDR_HSIO Input disable time – – 7.5 ns
design
tIO_SKEW_D- Data skew (first data bit to Guaranteed by
SID784B – – 0.6 ns
DR_HSIO last data bit) design
SMIF HSSPI(DDR) specification for GPIO_STD
SID760C CL_DDR_GPIO Load capacitance – – 15 pF
Guaranteed by
SID761C SR_DDR_GPIO Input rise and fall slew rates 1 – – V/ns
design
SID762C fCK_DDR_GPIO Clock frequency – – 32 MHz
SID763C tCK_DDR_GPIO Clock period 1 / fCK_DDR_GPIO – - ns
DCK_D-
SID764C Clock duty 45 – 55 %
DR_GPIO
CSR_D-
SID765C Clock rise and fall slew rates 1 – – V/ns
DR_GPIO
SID766C tCS_DDR_GPIO Chip select HIGH time 30 – – ns
SID767C tCSS_DDR_GPIO Chip select active setup time 5 – – ns
SID768C tCSH_DDR_GPIO Chip select active hold time 4 – – ns
SID769C tSU_DDR_GPIO Data setup time 5 – – ns
SID780C tHD_DDR_GPIO Data hold time 4.5 – – ns
Clock LOW to input data
SID781C tV_DDR_GPIO 0 – 9 ns
valid
SID782C tHO_DDR_GPIO Input hold time 3 – – ns
Guaranteed by
SID783C tDIS_DDR_GPIO Input disable time – – 22.5 ns
design
tIO_SKEW_D-
Data skew (first data bit to Guaranteed by
SID784C – – 1.8 ns
DR_GPIO last data bit) design
SMIF HYPERBUS™ specification for HSIO_STD
SID788 CL_HB_HSIO Load capacitance – – 20 pF
For all signals,
SID786 SRI_HB_HSIO Input rise and fall slew rates 1 – – V/ns guaranteed by
design

Datasheet 193 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-37 SMIF specifications (continued)[Conditions: drive_sel<1:0>= 00]

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
Output rise and fall slew
SID787 SRO_HB_HSIO 1 – – V/ns For all signals
rates
Clock characteristics
SID700 fCK_HB_HSIO Clock frequency – – 100 MHz
1 / fCK_H-
SID701 tCK_HB_HSIO Clock period – – ns
B_HSIO
SID702 DCK_HB_HSIO Clock duty 45 – 55 %
AC parameters
Chip select HIGH between Guaranteed by
SID706 tCSHI_HB_HSIO 10 – – ns
transactions design
Chip select setup to next CK
SID708 tCSS_HB_HSIO 3 – – ns
rising edge
SID709 tDSV_HB_HSIO Data strobe valid – – 12 ns
SID710 tOSU_HB_HSIO DQ output setup 1 – – ns
SID711 tOH_HB_HSIO DQ output hold 1 – – ns
SID715 tCKD_HB_HSIO CK transition to DQ valid 1 – 5.5 ns
SID718 tCKDS_HB_HSIO CK transition to RWDS valid 1 – 5.5 ns
RWDS transition to input DQ
SID719 tDSS_HB_HSIO –0.8 – 0.8 ns
valid
Input DQ invalid to RWDS
SID720 tDSH_HB_HSIO –0.8 – 0.8 ns
transition
Chip select hold after CK
SID721 tCSH_HB_HSIO 0 – - ns
falling edge
SMIF HYPERBUS™ specification for GPIO_STD
SID785A CL_HB_GPIO Load capacitance – – 20 pF
For all signals,
SID786A SRI_HB_GPIO Input rise and fall slew rates 0.45 – – V/ns guaranteed by
design
Output rise and fall slew
SID787A SRO_HB_GPIO 0.45 – – V/ns For all signals
rates
Clock characteristics
SID700A fCK_HB_GPIO Clock frequency - – 32 MHz
1 / fCK_H-
SID701A tCK_HB_GPIO Clock period – – ns
B_GPIO
SID702A DCK_HB_GPIO Clock duty 45 – 55 %
AC parameters
Chip select HIGH between Guaranteed by
SID706A tCSHI_HB_GPIO 30 – – ns
transactions design
Chip select setup to next CK
SID708A tCSS_HB_GPIO 9 – – ns
rising edge
Guaranteed by
SID709A tDSV_HB_GPIO Data strobe valid – – 36 ns
design
SID710A tOSU_HB_GPIO DQ output setup 3 – – ns
SID711A tOH_HB_GPIO DQ output hold 3 – – ns

Datasheet 194 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Table 27-37 SMIF specifications (continued)[Conditions: drive_sel<1:0>= 00]

Spec ID Parameter Description Min Typ Max Units Details/

Conditions
SID715A tCKD_HB_GPIO CK transition to DQ valid 3 – 16.5 ns
SID718A tCKDS_HB_GPIO CK transition to RWDS valid 3 – 16.5 ns
RWDS transition to input DQ
SID719A tDSS_HB_GPIO –2.4 – 2.4 ns
valid
Input DQ invalid to RWDS
SID720A tDSH_HB_GPIO –2.4 – 2.4 ns
transition
Chip select hold after CK
SID721A tCSH_HB_GPIO 0 – – ns
falling edge

VDDIO_1 tCK
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tSU tHD

Data 0.5 x VDDIO_1

Timing Reference Level
or VDDIO_3

Figure 27-43 SDR write timing reference level

VDDIO_1 tCK
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tV tHO

Data Timing Reference Level 0.5 x VDDIO_1

or VDDIO_3

Figure 27-44 SDR read timing reference level

tCK VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tSU tHD tSU tHD

Data 0.5 x VDDIO_1

Timing Reference Level
or VDDIO_3

Datasheet 195 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

Figure 27-45 DDR write timing reference level

tCK
VDDIO_1
or
VDDIO_3
CK
VSSD
tHO or
tV tHO VSSIO_3

Timing 0.5 x VDDIO_1

Data or VDDIO_3
Reference Level

Figure 27-46 DDR read timing reference level

CK

1 6

Chip
select
2 3
4 5 8

Data MSB OUT LSB OUT MSB IN LSB IN

Write Timing Read Timing

1: Chip select active setup time = tCSS

2: Data setup time = tSU
3: Data hold time = tHD
4: Clock LOW to input data valid = tV
5: Input data hold time = tHO
6: Chip select active hold time = tCSH
7: Chip select HIGH time = tCS
8: Input disable time = tDIS

Figure 27-47 SDR write and read timing diagram

CK

7
1
Chip
select
2 3 2 3 4 5 5 8

Data MSB OUT LSB OUT MSB IN LSB IN

Write Timing Read Timing

1: Chip select active setup time = tCSS

2: Data setup time = tSU
3: Data hold time = tHD
4: Clock LOW to input data valid = tV
5: Input data hold time = tHO
6: Chip select active hold time = tCSH
7: Chip select HIGH time = tCS
8: Input disable time = tDIS

Figure 27-48 DDR write and read timing diagram

Datasheet 196 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Electrical specifications

tCK VDDIO_1
or
VDDIO_3
CK
VSSD
or
VSSIO_3
tIS tIH tIS tIH

Data 0.5 x VDDIO_1

Timing Reference Level
or VDDIO_3

Figure 27-49 HYPERBUS™ timing reference level

9
Chip
select
10
1

CK

2 5

RWDS
3 4 3 4

DQ[7:0]
(output)
Command Address Host drives DQ[7:0] and RWDS
6
DQ[7:0]
(input)
7 8
Memory drives DQ[7:0] and RWDS

1: Chip select setup to next CK rising edge = tCSS

2: Data strobe valid = tDSV
3: DQ output setup = tOSU
4: DQ output hold = tOH
5: CK transition to RWDS valid = tCKDS
6: CK transition to DQ valid = tCKD
7: RWDS transition to input DQ valid = tDSS
8: Input DQ invalid to RWDS transition = tDSH
9: Chip select hold after CK falling edge = tCSH
10: Chip select HIGH between transactions = tCSHI

Figure 27-50 HYPERBUS™ timing diagram

Datasheet 197 002-21617 Rev. *M

2024-01-25
 28 Ordering information

Based on Arm® Cortex®-M7 dual

TRAVEO™ T2G 32-bit Automotive MCU
Datasheet

Ordering information
The CYT4BF microcontroller part numbers and features are listed in Table 28-1. The Arm® TAP JTAG ID is 0x6BA0 0477.

Table 28-1 CYT4BF ordering information

Temperature Grade
Ordering Code[67]

Work-flash (KB)
Code-flash (KB)

JTAG ID Code
Device Code

SD/eMMC
Channels

Channels

Channels

Channels
RAM (KB)

Ethernet
Package

FlexRay
Cores
CM7

ADC

SCB

LIN
CYT4BF8CES CYT4BF8CEDQ0AESGS 176-TEQFP 2 8384[68] 256[69] 1024 81 10 17 1 0 1 S[70] 0x2E5D3069[74]
CYT4BF8CEE CYT4BF8CEDQ0AEEGS 176-TEQFP 2 8384 256 1024 81 10 17 1 0 1 E[71] 0x2E5D3069
[73]
CYT4BF8CDS CYT4BF8CDDQ0AESGS 176-TEQFP 2 8384 256 1024 81 10 17 1 1 1 S 0x2E5D7069
CYT4BF8CDE[72] CYT4BF8CDDQ0AEEGS 176-TEQFP 2 8384 256 1024 81 10 17 1 1 1 E 0x2E5D7069
CYT4BFBCJS CYT4BFBCJDQ0BZSGS 272-BGA 2 8384 256 1024 96 11 20 2 0 1 S 0x2E5EB069
CYT4BFBCJE CYT4BFBCJDQ0BZEGS 272-BGA 2 8384 256 1024 96 11 20 2 0 1 E 0x2E5EB069
CYT4BFBCHS CYT4BFBCHDQ0BZSGS 272-BGA 2 8384 256 1024 96 11 20 2 1 1 S 0x2E5EF069
198

CYT4BFBCHE[72] CYT4BFBCHDQ0BZEGS 272-BGA 2 8384 256 1024 96 11 20 2 1 1 E 0x2E5EF069

CYT4BFCCJS CYT4BFCCJDQ0BZSGS 320-BGA 2 8384 256 1024 96 11 20 2 0 1 S 0x2E5FB069
CYT4BFCCJE CYT4BFCCJDQ0BZEGS 320-BGA 2 8384 256 1024 96 11 20 2 0 1 E 0x2E5FB069
CYT4BFCCHS CYT4BFCCHDQ0BZSGS 320-BGA 2 8384 256 1024 96 11 20 2 1 1 S 0x2E5FF069
[72]
CYT4BFCCHE CYT4BFCCHDQ0BZEGS 320-BGA 2 8384 256 1024 96 11 20 2 1 1 E 0x2E5FF069

Notes
67.Supported shipment types are “Tray” (default) and “Tape and Reel”. Add the character ‘T’ at the end to get the ordering code for “Tape and Reel” shipment type.
002-21617 Rev. *M

68.Code-flash size 8384 KB = 32 KB × 254 (Large Sectors) + 8 KB × 32 (Small Sectors)

69.Work-flash size 256 KB = 2 KB × 96 (Large Sectors) + 128 B × 512 (Small Sectors)
70.S-grade Temperature (–40 °C to 105 °C).
2024-01-25

71.E-grade Temperature (–40 °C to 125 °C).

72.These parts are available as engineering samples.
73.One interface of FlexRay supports two channels (ch A and ch B).
74.JTAG ID CODE bits 12 through 27, represents the Silicon ID of the device.
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Ordering information

28.1 Part number nomenclature

Table 28-2 Device code nomenclature
Field Description Value Meaning
CY Cypress prefix CY
T Category T TRAVEO™
2 Family name 4 TRAVEO™ T2G (Core M7 dual)
B Application B Body
D Code-flash/Work-flash/SRAM F 8384 KB / 256 KB / 1024 KB
quantity
8 176-TEQFP
P Packages B 272-BGA
C 320-BGA
H Hardware option C eSHE – on, HSM – on, RSA-2048
E Ethernet - 1 ch, FlexRay - 0, eMMC - 1
D Ethernet - 1 ch, FlexRay - 2, eMMC - 1
I Marketing option
J Ethernet - 2 ch, FlexRay - 0, eMMC - 1
H Ethernet - 2 ch, FlexRay - 2, eMMC - 1
S S-grade (–40 °C to 105 °C)
C Temperature grade
E E-grade (–40 °C to 125 °C)

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Ordering information

Table 28-3 Ordering code nomenclature

Field Description Value Meaning
CY Cypress prefix CY
T Category T TRAVEO™
2 Family name 4 TRAVEO™ T2G (Core M7 dual)
B Application B Body
D Code-flash/Work-flash/SRAM F 8384 KB / 256 KB / 1024 KB
quantity
8 176-TEQFP
P Packages B 272-BGA
C 320-BGA
H Hardware option C eSHE – on, HSM – on, RSA-2048
E Ethernet - 1 ch, FlexRay - 0, eMMC - 1
D Ethernet - 1 ch, FlexRay - 2, eMMC - 1
I Marketing option
J Ethernet - 2 ch, FlexRay - 0, eMMC - 1
H Ethernet - 2 ch, FlexRay - 2, eMMC - 1
A First revision
B Second revision
R Revision
C Third revision
D Fourth revision
F Fab Location Q UMC (Fab 12i) Singapore
X Reserved 0 Reserved
AE TEQFP
K Package code
BZ BGA
S S-grade (–40 °C to 105 °C)
C Temperature grade
E E-grade (–40 °C to 125 °C)
ES Engineering samples
Q Quality grade
GS Standard grade of automotive
Blank Tray shipment
S Shipment type
T Tape and reel shipment

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Packaging

29 Packaging
CYT4BF microcontroller is offered in the packages listed in the Table 29-1.
Table 29-1 Package information
Package Dimensions[75] Contact/Lead pitch Coefficient of thermal expansion[80] I/O Pins
[76] [77]
a1 = 8.4 ppm/°C, a2 = 29.4
176-TEQFP 24 × 24 × 1.70 mm (max) 0.5-mm 148
ppm/°C
a1[76] = 11.9 ppm/°C, a2[77] = 34.3
272-BGA 16 × 16 × 1.70 mm (max) 0.8-mm 220
ppm/°C
a1[76] = 11.9 ppm/°C, a2[77] = 34.5
320-BGA 17 × 17 × 1.70 mm (max) 0.8-mm ppm/°C 240

Table 29-2 Package characteristics

Parameter Description Conditions Min Typ Max Units
Operating ambient
TA S-grade –40 – 105 °C
temperature
Operating ambient
TA temperature E-grade –40 – 125 °C

TJ Operating junction – – – 150 °C

temperature
176-TEQFP – – 16.4 °C/W
Package thermal resistance,
RθJA junction to ambient θJA[78, 79]
272-BGA – – 22.4 °C/W
320-BGA – – 21.8 °C/W
176-TEQFP – – 11.96 °C/W
Package thermal resistance,
RθJB junction to board θJB
272-BGA – – 13.5 °C/W
320-BGA – – 13.6 °C/W
176-TEQFP – – 7.5 °C/W
Package thermal resistance,
RθJC junction to case θJC 272-BGA – – 8.9 °C/W
320-BGA – – 6.5 °C/W

Table 29-3 Solder reflow peak temperature, package moisture sensitivity level (MSL), IPC/JEDEC
J-STD-2
Maximum peak temperature Maximum time at peak temperature
Package MSL
(°C) (seconds)
176-TEQFP 260 30 3
272-BGA 260 30 3
320-BGA 260 30 3

Notes
75.The dimensions (column 2) are valid for room temperature.
76.a1 = CTE (Coefficient of Thermal Expansion) value below Tg (ppm/°C) (Tg is glass transition temperature which is 131°C).
77.a2 = CTE value above Tg (ppm/°C).
78.Maximum value °C/Watt shown is for TA = 125 °C.
79.Board condition complies to JESD51-7(4 Layers).
80.The numbers are estimated values based simulation only and are based on a single bill of material combination per package type.

Datasheet 201 002-21617 Rev. *M

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Packaging

002-25324 **

Figure 29-1 Package outline – 176-TEQFP

Datasheet 202 002-21617 Rev. *M

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Packaging

002-24865 *A

Figure 29-2 Package outline – 272-BGA

Datasheet 203 002-21617 Rev. *M

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Packaging

002-23091 *A

Figure 29-3 Package outline – 320-BGA

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Appendix

30 Appendix
30.1 Bootloading or end-of-line programming
• Triggered at device startup, if a trigger condition is applied
• Either CAN or LIN communication may be used
• Bootloader polls for the communication on CAN or LIN at the separate time frames, until the overall 300-second
timeout is reached
• If a bootloader command is received on either communication interface, the polling stops and bootloader starts
using this interface

10 ms 10 ms 150 ms

CAN, CAN, LIN, CAN,

Bootloader
100 Kbps 500 Kbps 20 Kbps 100 Kbps ….
Stopped
Polling Polling Polling Polling

Overall bootloading time, if no communication ( 300 s)

Figure 30-1 Bootloading sequence

Table 30-1 CAN interface details

Sl. No. CAN interface Configuration
1 CAN mode Classic CAN
2 CAN instance CAN0, Channel#1
3 CAN TX P0.2 / CAN0_1_TX
4 CAN RX P0.3 / CAN0_1_RX
5 CAN transceiver NSTB / EN (Low) P23.3 (optional)
6 CAN transceiver EN / EN (High) P2.1 (optional)
7 CAN RX Message ID 0x1A1
8 CAN TX Message ID 0x1B1
9 Baud 100 or 500 kbps alternating

VSS

CAN
TRAVEOTM T2G MCU Transceiver

EN (Low) NSTB

EN (High) EN

TX TX

RX RX

Figure 30-2 MCU to CAN transceiver connections

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Appendix

Table 30-2 LIN interface details

Sl. No. LIN interface Configuration
1 LIN type LIN0, Channel#1
2 LIN mode Slave
3 LIN checksum type Classic
4 LIN TX P0.1 / LIN1_TX
5 LIN RX P0.0 / LIN1_RX
6 LIN EN / EN (High) P2.1 (optional)
7 LIN EN (Low) P23.3 (optional)
8 LIN TX PID 0x46
9 LIN RX PID 0x45
10 Baud 20 or 115.2 kbps
11 Break field length 11
12 Break delimiter length 1 bit

VDDD / VDDIO

LIN
TRAVEOTM T2G MCU
Transceiver

EN (Low)
EN
EN (High)

TX TX

RX RX

Figure 30-3 MCU to LIN transceiver connections

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Appendix

30.2 External IP revisions

Table 30-3 IP revisions
Module IP Revision Vendor
FlexRay mxflexray Release - Revision 1.0.3, CREL - 103 9 02 06, E-Ray Spec - Bosch
v1.2.7, Protocol Spec - v2.1
SDHC mxsdhc version 1.70a Synopsys
CANFD mxttcanfd M_TTCAN IP revision: Rev.3.2.3 Bosch
Arm® Cortex®-M0+ armcm0p Cortex®-M0+-r0p1 Arm®
Arm® Cortex®-M7 armcm7 Cortex®-M7-r1p2 Arm®
Arm® Coresight armcoresighttk CoreSight-SoC-TM100-r3p2 Arm®
Ethernet mxeth GEM_GXL r1p09 Cadence

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Acronyms

31 Acronyms
Table 31-1 Acronyms used in the document
Acronym Description Acronym Description
A/D Analog to Digital PLL Phase Locked Loop
ABS Absolute POR Power-on reset
ADC Analog to Digital converter PPU Peripheral protection unit
AES Advanced encryption standard PRNG Pseudo-random number generator
AHB AMBA (advanced microcontroller bus PSoC Programmable system on chip
architecture) high-performance bus, Arm®
data transfer bus
Arm® Advanced RISC machine, a CPU architecture PWM Pulse-width modulation
ASIL Automotive safety integrity level MCU Microcontroller Unit
BOD Brown-out detection MCWDT Multi-counter watchdog timer
CAN FD Controller Area Network with Flexible Data M-DMA Memory-Direct Memory Access
rate
CMOS Complementary metal-oxide-semiconductor MISO Master-in slave-out
CPU Central Processing Unit MMIO Memory mapped I/O
CRC Cyclic redundancy check, an error-checking MOSI Master-out slave-in
protocol
CSV Clock supervisor MPU Memory protection unit
CTI Cross Trigger Interface NVIC Nested vectored interrupt
controller
DES Data encryption standard RAM Random access memory
ECC Error correcting code RISC Reduced-instruction-set
computing
ECO External crystal oscillator ROM Read only memory
ETM Embedded Trace Macrocell RTC Real-time clock
FLL Frequency Locked Loop SAR Successive approximation register
FPU Floating point unit SCB Serial communication block
GHS Green hills tool chain with IDE SCL I2C serial clock
GPIO General purpose input/output SDA I2C serial data
HSM Hardware security module SHA Secure hash algorithm
I/O Input/output SHE Secure hardware extension
I2C Inter-Integrated Circuit, a communications SMPU Shared memory protection unit
protocol
I2S Inter-Integrated Circuit Sound SPI Serial peripheral interface, a
communications protocol
ILO Internal low-speed oscillator SRAM Static random access memory
IMO Internal main oscillator SWD Single wire debug
IPC Inter-processor communication TCM Tightly Coupled Memory
IrDA Infrared interface TCPWM Timer/Counter Pulse-width
modulator
IRQ Interrupt request TTL Transistor-transistor logic
JTAG Joint test action group TRNG True random number generator

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Acronyms

Table 31-1 Acronyms used in the document

Acronym Description Acronym Description
LIN Local Interconnect Network, a communica- UART Universal Asynchronous Trans-
tions protocol mitter Receiver, a communications
protocol
LVD Low voltage detection WCO Watch crystal oscillator
OTA Over-the-air programming WDT Watchdog timer reset
OTP One-time programmable XIP eXecute In Place
OVD Over voltage detection XTAL Crystal
PASS Programmable Analog Subsystem
P-DMA Peripheral-Direct Memory Access

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Architecture block diagram

32 Errata
This section describes the errata for the CYT4BF product family. Details include trigger conditions, scope of
impact, available workaround, and silicon revision applicability. Contact your local Cypress Sales Representative
if you have further questions.
Part numbers affected

Part numbers
All CYT4BF parts

CYT4BF qualification status

Production samples
CYT4BF errata summary
The following table defines the errata applicability to available CYT4BF family devices.
Items Errata ID CYT4BF Silicon Rev. Fix status
[1] CAN FD RX FIFO top pointer feature does not function 96 No silicon fix planned.
as expected Use workaround.
[2] CAN FD debug message handling state machine is not 97 No silicon fix planned.
reset to Idle state when CANFD_CH_CCCR.INIT is set Use workaround.
[3] Limitation of the memory hole in SCB register space 124 No silicon fix planned.
Use workaround.
[4] Limitation of the memory hole in Ethernet (ETH) 128 No silicon fix planned.
register space Use workaround.
[5] CAN FD controller message order inversion when No silicon fix planned.
transmitting from dedicated Tx Buffers configured with 147 Use workaround.
same Message ID
[6] CAN FD incomplete description of Dedicated Tx No silicon fix planned.
Buffers and Tx Queue related to transmission from 167 Use workaround. TRM
multiple buffers configured with the same Message ID was updated.
[7] Misleading status is returned for Flash and eFuse No silicon fix planned.
system calls, if there are pending NC ECC faults in SRAM 175 TRM was updated.
controller #0
CYT4BF8CEDQ0AESGS No silicon fix planned.
[8] WDT reset causes loss of SRAM retention 176
CYT4BF8CEDQ0AEEGS TRM was updated.
[9] RMII TX output maximum delay spec change for CYT4BF8CDDQ0AESGS No silicon fix planned.
177 CYT4BF8CDDQ0AEEGS
GPIO_STD
CYT4BFBCJDQ0BZSGS
[10] Crypto ECC errors may be set after boot with appli- CYT4BFBCJDQ0BZEGS No silicon fix planned.
185 D
cation authentication CYT4BFBCHDQ0BZSGS TRM was updated.
CYT4BFBCHDQ0BZEGS
[11]Incomplete erase of Code Flash cells could happen CYT4BFCCJDQ0BZSGS Fixed to update the Flash
Erase Suspend / Erase Resume is used along with Erase 198 CYT4BFCCJDQ0BZEGS settings from date code
Sector operation in Non-Blocking mode CYT4BFCCHDQ0BZSGS 312xxxxx.
[12]Limitation for keeping the port state from peripheral CYT4BFCCHDQ0BZEGS No silicon fix planned.
199
IP after wakeup from DeepSleep TRM was updated.
[13] A part of the PWR_CTL2.BGREF_LPMODE description 201 No silicon fix planned.
is lacked in the existing register TRM TRM was updated.
[14]Limitation of clock configuration before entering 202 No silicon fix planned.
DeepSleep mode TRM was updated.
[15] Several data retention information in the Register 203 No silicon fix planned.
TRM are incorrect TRM was updated.
[16] SCBx_INTR_TX.UNDERFLOW bit may be set uninten- 204 No silicon fix planned.
tionally TRM was updated.
[17] Hardfault may occur when calling the SROM APIs No silicon fix planned.
listed below while executingw EraseSector or 206 TRM will be updated.
ProgramRow in non-blocking mode
[18] CAN FD sporadic data corruption (payload) in case No silicon fix planned.
acceptance filtering does not finish before reception of 209 Use workaround.
data R3 (DB7..DB4) is complete
[19] Description for PASS SARx to TCPWMx direct connect No silicon fix planned.
212
triggers one-to-one is incorrect in datasheet Use workaround.

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Architecture block diagram

1. CAN FD RX FIFO top pointer feature does not function as expected

Problem Definition RX FIFO top pointer function calculates the address for received messages in Message RAM by hardware. This address
should restart from the start address after reading all messages of RX FIFO n size (n: 0 or 1). However, the address does
not restart from the start address when RX FIFO n size is set to 1(CANFD_CH_RXFnC.FnS = 0x01). This results in CPU/DMA
reading messages from the wrong address in Message RAM.
Parameters Affected NA
Trigger Condition(s) The RX FIFO top pointer function is used when RX FIFO n size is set to 1 element (CANFD_CH_RXFnC.FnS = 0x01).
Scope of Impact Received message cannot be correctly read by using the RX FIFO top pointer function, when RX FIFO n size is set to 1
element.
Workaround Any of the following can be used as a workaround:
1) Set RX FIFO n size to 2 or more when using the RX FIFO top pointer function.
2) Do not use the RX FIFO top pointer function when RX FIFO n size is set to 1 element. Instead of the RX FIFO top pointer,
read received messages from the Message RAM directly.
Fix Status No silicon fix planned. Use workaround.

2. CAN FD debug message handling state machine is not reset to Idle state when CANFD_CH_CCCR.INIT is set
Problem Definition If either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module enters BusOff state, the debug
message handling state machine stays in its current state instead of being reset to Idle state. Configuring the bit
CANFD_CH_CCCR.CCE does not change CANFD_CH_RXF1S.DMS.
Parameters Affected NA
Trigger Condition(s) Either of the CANFD_CH_CCCR.INIT bits is set by the Host or when the M_TTCAN module enters BusOff state.
Scope of Impact The errata is limited to the use case when the debug on CAN functionality is active. Normal operation of the CAN module
is not affected, in which case the debug message handling state machine always remains in Idle state. In the described
use case, the debug message handling state machine is stopped and remains in the current state signaled by the
CANFD_CH_RXF1S.DMS bit. In case CANFD_CH_RXF1S.DMS is set to 0b11, the DMA request remains active.
Bosch classifies this as a non-critical error with low severity, there is no fix for the IP. Bosch recommends the workaround
listed here.
Workaround In case the debug message handling state machine has stopped while CANFD_CH_RXF1S.DMS is 0b01 or 0b10, it can be
reset to Idle state by hardware reset or by reception of debug messages after CANFD_CH_CCCR.INIT is reset to zero.
Fix Status No silicon fix planned. Use workaround.

3. Limitation of the memory hole in SCB register space

Problem Definition The memory hole [offset address: 0x1000 to 0xFFFF] inside SCB register space is not aligned to the below defined spec.
The offset address bits [15:12] are ignored and treated as 4’b0000, so write/read access to offset address [0x1000 to
0xFFFF], will actually happen to [0x0000 to 0x0FFF].
- Access to address gaps in memory mapped space: writes are ignored and any read returns a zero.
Parameters Affected NA
Trigger Condition(s) Access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space.
Scope of Impact The memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space is not aligned to other IP registers.
Workaround Do not access to the memory hole [offset address: 0x1000 to 0xFFFF] in SCB register space.
Fix Status No silicon fix planned.

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Architecture block diagram

4. Limitation of the memory hole in Ethernet (ETH) register space

Problem Definition The memory hole [offset address: 0x2000 to 0xFFFF] in ETH register space has the below mentioned original spec.
However, when accessing address gaps within [0x1000 to 0x1FFF], the offset address bits [15:13] are ignored and treated
as 3’b000, so write/read access to offset address [0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to 0x7FFF, 0x9000 to
0x9FFF, 0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF], will actually happen to [0x1000 to 0x1FFF].
- Access to address gaps within [0x0000 to 0x0FFF]: writes are ignored and any read returns a zero.
- Access to address gaps within [0x1000 to 0x1FFF]: returns AHB ERROR.
Parameters Affected NA
Trigger Condition(s) Access to the memory hole [offset address: 0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to 0x7FFF, 0x9000 to 0x9FFF,
0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF] in ETH register space.
Scope of Impact Write/read access to offset address [0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to 0x7FFF, 0x9000 to 0x9FFF, 0xB000 to
0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF], will actually happen to [0x1000 to 0x1FFF].
Workaround Do not access the memory hole [offset address: 0x3000 to 0x3FFF, 0x5000 to 0x5FFF, 0x7000 to 0x7FFF, 0x9000 to 0x9FFF,
0xB000 to 0xBFFF, 0xD000 to 0xDFFF, 0xF000 to 0xFFFF] in ETH register space.
Fix Status No silicon fix planned.

5. CAN FD controller message order inversion when transmitting from dedicated Tx Buffers configured with same Message ID
Problem Definition Configuration:
Several Tx buffers are configured with same Message ID. Transmission of these Tx buffers is requested sequentially with
a delay between the individual Tx requests.

Expected behavior:
When multiple Tx buffers that are configured with the same Message ID have pending Tx requests, they shall be trans-
mitted in ascending order of their Tx buffer numbers. The Tx buffer with lowest buffer number and pending Tx request
is transmitted first.

Observed behavior:
It may happen, depending on the delay between the individual Tx requests, that if multiple Tx buffers are configured
with the same Message ID, the Tx buffers are not transmitted in order of the Tx buffer number (lowest number first).
Parameters Affected NA
Trigger Condition(s) When multiple Tx buffers configured with the same Message ID have pending Tx requests.
Scope of Impact In the case described, it is possible that Tx buffers configured with the same Message ID and pending Tx request are not
transmitted with lowest Tx buffer number first (message order inversion).
Workaround Any of the following:
1) First, write the group of Tx message with the same Message ID to the Message RAM and then afterwards request
transmission of all these messages concurrently by a single write access to CANFDx_CHy_TXBAR. Before requesting a
group of Tx messages with this Message ID ensure that no message with this Message ID has a pending Tx request.
2) Use the Tx FIFO instead of dedicated Tx buffers for the transmission of several messages with the same Message ID in
a specific order.

Applications not able to use workaround #1 or #2 can implement a counter within the data section of their messages
sent with same ID in order to allow the recipients to determine the correct sending sequence.
Fix Status No silicon fix planned. Use workaround.

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Errata

6. CAN FD incomplete description of Dedicated Tx Buffers and Tx Queue related to transmission from multiple buffers configured with the same
Message ID
Problem Definition The following are the updated description in Sections "Dedicated Tx Buffers" and "Tx Queue" of the Architecture TRM
related to the transmission from multiple buffers configured with the same Message ID.

Dedicated Tx buffers
- TRM Statement: If multiple Tx buffers are configured with the same Message ID, the Tx buffer with the lowest buffer
number is transmitted first.
- Enhancement: These Tx buffers shall be requested in ascending order with lowest buffer number first. Alternatively all
Tx buffers configured with the same Message ID can be requested simultaneously by a single write access to CANFDx-
_CHy_TXBAR.

Tx queue
- TRM statement: If multiple queue buffers are configured with the same Message ID, the queue buffer with the lowest
buffer number is transmitted first.
- Replacement: If multiple Tx queue buffers are configured with the same Message ID, the transmission order depends
on numbers of the buffers where the messages were stored for transmission. As these buffer numbers depend on the
then current states of the PUT Index, a prediction of the transmission order is not possible.

- TRM statement: An Add Request cyclically increments the Put Index to the next free Tx Buffer.
- Replacement: The PUT Index always points to that free buffer of the Tx Queue with the lowest number.
Parameters Affected NA
Trigger Condition(s) Using multiple dedicated Tx buffers or Tx queue buffers configured with the same Message ID.
Scope of Impact If the dedicated Tx buffers with the same Message ID are not requested in ascending order or at the same time, or if there
are multiple Tx queue buffers with the same Message ID, it cannot be guaranteed, that these messages are transmitted
in ascending order with lowest buffer number first.
Workaround In case a defined order of transmission is required the Tx FIFO shall be used for transmission of messages with the same
Message ID. Alternatively dedicated Tx buffers with the same Message ID shall be requested in ascending order with
lowest buffer number first or by a single write access to CANFDx_CHy_TXBAR. Alternatively a single Tx Buffer can be used
to transmit those messages one after the other.
Fix Status No silicon fix planned. Use workaround. TRM was updated.

7. Misleading status is returned for Flash and eFuse system calls, if there are pending NC ECC faults in SRAM controller #0
Problem Definition Flash and eFuse system calls will return misleading status of 0xF0000005 (“Page is write protected”) even for
non-protected row, or 0xF0000002 (“Invalid eFuse address”) for valid eFuse address in case of pending NC ECC faults in
SRAM controller #0.
Parameters Affected Return status of Flash and eFuse system calls.
Trigger Condition(s) NC ECC fault(s) pending in SRAM controller #0 and SWPUs are populated in the design.
Scope of Impact Flash and eFuse system calls will not work until the NC ECC fault(s) pending in SRAM controller #0 is/are properly
handled.
Workaround If the NC ECC fault(s) are not due to HW malfunction (i.e. if the faults are due to usage of non-initialized SRAM or improper
SRAM initialization), then clearing of these pending faults will resolve the issue.
Fix Status No silicon fix planned. TRM was updated.

8. WDT reset causes loss of SRAM retention

Problem Definition Architecture TRM Table on “Reset Cause Distribution” shows that, the WDT reset can retain SRAM if there is an orderly
shutdown of the SRAM only during a warning interrupt. However, this is wrong. WDT reset causes loss of SRAM retention.
Parameters Affected NA
Trigger Condition(s) WDT reset
Scope of Impact WDT reset causes loss of SRAM retention.
Workaround None
Fix Status No silicon fix planned. TRM was updated.

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Errata

9. RMII TX output maximum delay spec change for GPIO_STD

Problem Definition RMII TX output maximum delay specification has been changed from 14 ns to 14.6 ns for GPIO_STD. The HSIO_STD spec
of 14 ns is unchanged.
Parameters Affected SID393
Trigger Condition(s) Using GPIO_STD as RMII
Scope of Impact This spec change will cause the PCB delay budget between MCU and PHY to be cut down to 1.4 ns from 2 ns.
[PCB delay budget = REF_CLK period (e.g. 20 ns) – SID393 (14.6 ns) – PHY RXD setup (e.g. 4 ns)]
Workaround None
Fix Status No silicon fix planned.

10.Crypto ECC errors may be set after boot with application authentication
Problem Definition Due to the improper initialization of the Crypto memory buffer, Crypto ECC errors may be set after boot with application
authentication.
Parameters Affected N/A
Trigger Condition(s) Boot device with application authentication.
Scope of Impact Crypto ECC errors may be set after boot with application authentication.
Workaround Clear or ignore Crypto ECC errors which generated during boot with application authentication.
Fix Status No silicon fix planned. TRM was updated.

11.Incomplete erase of Code Flash cells could happen Erase Suspend / Erase Resume is used along with Erase Sector operation in Non-Blocking
mode
Problem Definition Code Flash memory can be erased in “Non-Blocking” mode; a Non-Blocking mode supported option allows users to
suspend an ongoing erase sector operation. When an ongoing erase operation is interrupted using “Erase Suspend” and
“Erase Resume”, Flash cells may not have been erased completely, even after the erase operation complete is indicated
by FLASHC_STATUS register. Only Code Flash is impacted by this issue, Work Flash and Supervisory Flash (SFlash) are
not impacted.
Parameters Affected N/A
Trigger Condition(s) Using EraseSector System Call in Non-Blocking mode for CM0+ to erase Code Flash and the ongoing erase operation is
interrupted using EraseSuspend and EraseResume System calls.
Scope of Impact When Code Flash sectors are erased in Non-Blocking mode and the ongoing erase operation is interrupted by Erase
Suspend / Erase Resume, it cannot be guaranteed that the Code Flash cells are fully erased. Any read on the Code Flash
area after the erase is complete or read on the programmed data after ProgramRow is complete can trigger ECC errors.
Workaround Use any of the following:
1) Use Non-Blocking mode for EraseSector, but do not interrupt the erase operation using Erase Suspend / Erase Resume.
2) If a Code Flash sector erase operation is interrupted using Erase Suspend / Erase Resume, then erase the same sector
again without Erase Suspend / Erase Resume before reading the sector or programming the sector.
Fix Status Fixed to update the Flash settings from date code 312xxxxx.

Datasheet 214 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata

12.Limitation for keeping the port state from peripheral IP after wakeup from DeepSleep
Problem Definition The port state is not retained when the port selects peripheral IP (except for LIN or CAN FD) and MCU wakes up from
DeepSleep.
Parameters Affected N/A
Trigger Condition(s) The port selects peripherals (except for LIN or CAN-FD) and MCU wakes up from DeepSleep.
Scope of Impact Unexpected port output change might affect user system.
Workaround If the port selects peripherals (except for LIN or CAN FD), and the port output value need to be maintained after wakeup
from DeepSleep, set HSIOM_PRTx_PORT_SEL.IOy_SEL = 0 (GPIO) before DeepSleep and set the required output value
in GPIO configuration registers. After wakeup, change HSIOM_PRTx_PORT_SEL.IOy_SEL back to the peripheral module
as needed.
Fix Status No silicon fix planned. TRM was updated.

13.A part of the PWR_CTL2.BGREF_LPMODE description is lacked in the existing register TRM
Problem Definition The following is missing from the PWR_CTL2.BGREF_LPMODE description in the existing register TRM.
This register will not set unless CLK_ILO0_CONFIG.ILO0_ENABLE = 1. When changing back to continuous operation, keep
ILO0 enabled for at least 5 ILO0 cycles after clearing this bit to allow for internal synchronization.
Parameters Affected N/A
Trigger Condition(s) Using the PWR_CTL2.BGREF_LPMODE
Scope of Impact PWR_CTL2.BGREF_LPMODE may not be set or cleared.
Workaround Use the PWR_CTL2.BGREF_LPMODE according to the following description. This register will not set unless CLK_ILO0_-
CONFIG.ILO0_ENABLE==1. When changing back to continuous operation, keep ILO0 enabled for at least 5 ILO0 cycles
after clearing this bit to allow for internal synchronization.
Fix Status No silicon fix planned. TRM was updated.

14.Limitation of clock configuration before entering DeepSleep mode

Problem Definition DeepSleep should not be entered while any FLL/PLL is enabled and uses ECO as its reference clock. Since the unstable
ECO clock after wakeup is outside the allowed reference clock limits for FLL/PLL, there is possibility of failing the
DeepSleep wakeup.
Parameters Affected N/A
Trigger Condition(s) DeepSleep transition while any FLL/PLL is enabled and using ECO as its reference clock.
Scope of Impact There is a possibility of DeepSleep wakeup failing.
Workaround If any FLL/PLL is operating with the ECO as its reference clock, change the clock to either ECO direct or IMO direct or IMO
with FLL/PLL before entering DeepSleep.
Fix Status No silicon fix planned. TRM was updated.

15.Several data retention information in the Register TRM are incorrect

Problem Definition The following registers are described as ‘Retained’ in the Register TRM while it is not guaranteed that the value before
entering DeepSleep mode is still readable from the register:
- SARADC: PASSx_SARy_CHz_RESULT
- SRSS: PWR_LVD_STATUS
- SRSS: PWR_LVD_STATUS2
- SRSS: CLK_CAL_CNT1
- SRSS: CLK_CAL_CNT2
- SRSS: CLK_FLL_STATUS
- SRSS: WDT_INTR
- SRSS: WDT_INTR_MASKED
- SRSS: CLK_PLL400Mx_STATUS"
Parameters Affected N/A

Datasheet 215 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata

Trigger Condition(s) Use of the related function and wakeup from DeepSleep mode.
Scope of Impact The values before entering DeepSleep are not retained.
Workaround For PASSx_SARy_CHz_RESULT, any of following can be used as a workaround:
1) Store the conversion values at another memory location before entering DeepSleep mode
2) Restart the conversion after wakeup from DeepSleep mode
For the other registers: Rewrite the register value or read the status flags again after wakeup.
Fix Status No silicon fix planned. TRM was updated.

16.SCBx_INTR_TX.UNDERFLOW bit may be set unintentionally

Problem Definition There is a possibility of setting the SCBx_INTR_TX.UNDERFLOW bit even if the FIFO is not empty.
Parameters Affected N/A
Trigger Condition(s) Using the TX FIFO for SCB when the AHB-Lite interface clock (CLK_GR6) frequency of the AHB bus is greater than 3x the
SCB functionality clock (PCLK_SCBx_CLOCK).
Scope of Impact SCBx_INTR_TX.UNDERFLOW bit may be set unintentionally.
Workaround Ignore the SCBx_INTR_TX.UNDERFLOW bit if the FIFO is not empty.
Fix Status No silicon fix planned. TRM was updated.

17.Hardfault may occur when calling the SROM APIs listed below while executingw EraseSector or ProgramRow in non-blocking mode
Problem Definition The following SROM APIs read data from bank#0 (or bank#1 if dual bank mode with mapping B is used) in SFlash. While
doing that, the check for active non-blocking erase or program of bank#0 (or bank#1 if dual bank mode with mapping B
is used) is not performed. Therefore, reading bank#0 (or bank#1 if dual bank mode with mapping B is used) while there
is an active erase/program operation triggers a bus error, which can result in a hardfault occurrence based on FLASH-
C_FLASH_CTL register settings.
Affected SROM APIs:
- ReadSWPU
- WriteSWPU
- GenerateHash
- Checksum*
- ComputeBasicHash*
- CheckFactoryHash
- ProgramWorkFlash**
- SwitchOverRegulators
- LoadRegulatorsTrims
*: Do not call it to calculate on the bank where programming/erasing is in progress.
**: Do not use it during non-blocking operation.
Parameters Affected N/A
Trigger Condition(s) Calling the affected SROM APIs while executing EraseSector or ProgramRow in non-blocking mode on bank#0 (or
bank#1 if dual bank mode with mapping B is used).
Scope of Impact The affected SROM APIs cannot be used while executing EraseSector or ProgramRow in non-blocking mode on bank#0
(or bank#1 if dual bank mode with mapping B is used).
Workaround Do not use the affected SROM APIs while executing EraseSector or ProgramRow in non-blocking mode on bank#0 (or
bank#1 if dual bank mode with mapping B is used).
Fix Status No silicon fix planned. TRM will be updated.
Impact on Infineon software S-LLD, HSM-Perf-Lib: While executing EraseSector or ProgramRow in non-blocking mode on bank#0 (or bank#1 if dual
bank mode with mapping B is used), users must not do any of following:
a) call CySldProt_GetSwpuFlashStructCfg
b) call CySldProt_VerifySecureDomainFlashWriteProtection if CySldProt_SwpuFlashStructGroupConfigu-
rations is non-empty

Datasheet 216 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Architecture block diagram

18.CAN FD sporadic data corruption (payload) in case acceptance filtering does not finish before reception of data R3 (DB7..DB4) is
complete
Problem Definition During frame reception the Rx Handler accesses the external Message RAM for acceptance filtering (read accesses)
and for storing of the accepted messages (write accesses).
The time needed for acceptance filtering and for storing of a received message depends on
• The Host clock frequency
• The worst-case latency of the read and write accesses to the external Message RAM
• The number of configured filter elements
• The workload of the transmit message (Tx) handler in parallel to the receive message (Rx) handler

Received data bytes (DB0..DBm) from the CAN Core are buffered in the cache of the Rx Handler before they are written
to the Message RAM (in words of 4 byte). Data words inside the Message RAM are numbered from R2 to Rn (n ≤ 17).

Figure 1 Rx Buffer and FIFO Element

Under the following conditions, a received message has corrupted data while the received message is signaled as
valid to the host.
1) The data length code (DLC) of the received Message is greater than 4 (DLC > 4)
2) The storage of Ri of a received message into the Message RAM (after acceptance filtering is done) has not completed
before R(i+1) is transferred from the CAN Core into the cache of the Rx Handler (where 2 ≤ i ≤ 5).
3) While condition 1) and 2) apply, a concurrent read of data word Ri from the cache and write of data word R(i+1)
into the cache of the Rx handler happens.

The data will be corrupted in a way, that in the Message RAM R(i+1) has the same content as Ri.

Despite the corrupted data, the M_TTCAN signals the storage of a valid frame in the Message RAM:
• Rx FIFO: FIFO put index RXFnS.FnPI is updated.
• Dedicated Rx Buffer: New Data flag NDATn.NDxx is set.
• Interrupt flag IR.MRAF is not set.

The issue may occur in the FD Frame Format as well as in the Classic Frame Format.

Figure 2 shows how the available time for acceptance filtering and storage is reduced.

Original available time for acceptance filtering and storage of

R2 (DB3_DB0)

Figure 2 CAN Frame with DLC>4

Datasheet 217 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Architecture block diagram

18.CAN FD sporadic data corruption (payload) in case acceptance filtering does not finish before reception of data R3 (DB7..DB4) is
complete

Table 1 TRAVEO™ T2G: Minimum host clock frequency for CAN FD when DLC = 5
Number of Number of Arbitration bit rate = 0.5 Mbps Arbitration bit rate = 1 Mbps
configured active active CAN Data bit Data bit Data bit Data bit Data bit Data bit Data bit rate Data bit rate
filter element channels in an rate = 0.5 rate = 1 rate = 2 rate = 4 rate = 1 rate = 2 = 4 Mbps = 5 Mbps
11-bit IDs / 29-bit instance Mbps Mbps Mbps Mbps Mbps Mbps
IDs 1,2
32 / 16 2 3.9 MHz 7.1 MHz 13.1 MHz 22.8 MHz 7.7 MHz 14.1 MHz 26.1 MHz 31.5 MHz
3 5.4 MHz 9.9 MHz 18.3 MHz 31.8 MHz 10.7 MHz 19.7 MHz 36.5 MHz 44.0 MHz
4 6.9 MHz 12.7 MHz 23.5 MHz 40.8 MHz 13.8 MHz 25.3 MHz 46.9 MHz 56.5 MHz
5 8.4 MHz 15.5 MHz 28.6 MHz 49.9 MHz 16.8 MHz 30.9 MHz 57.2 MHz 69.0 MHz
64 / 32 2 7.4 MHz 13.5 MHz 24.9 MHz 43.4 MHz 14.7 MHz 26.9 MHz 49.8 MHz 60.0 MHz
3 10.3 MHz 18.8 MHz 34.9 MHz 60.7 MHz 20.5 MHz 37.6 MHz 69.7 MHz 84.0 MHz
4 13.2 MHz 24.2 MHz 44.8 MHz 78.0 MHz 26.3 MHz 48.4 MHz 89.5 MHz 107.9 MHz3
5 16.1 MHz 29.6 MHz 54.7 MHz 95.3 MHz 32.1 MHz 59.1 MHz 109.4 MHz3 131.8 MHz3
96 / 48 2 10. 8 MHz 19.9 MHz 36.8 MHz 64.0 MHz 21.6 MHz 39.7 MHz 73.5 MHz 88.6 MHz
3 15.1 MHz 27.8 MHz 51.5 MHz 89.6 MHz 30.2 MHz 55.6 MHz 102.9 MHz3 124.0 MHz3
4 19.4 MHz 35.7 MHz 66.1 MHz 115.1 MHz3 38.8 MHz 71.4 MHz 132.2 MHz3 159.3 MHz3
5 23.7 MHz 43.6 MHz 80.8 MHz 140.7 MHz3 47.4 MHz 87.2 MHz 161.5 MHz3 194.7 MHz3
128 / 64 2 14.3 MHz 26.3 MHz 48.6 MHz 84.7 MHz 28.4 MHz 52.5 MHz 97.2 MHz 117.2 MHz3
3 20.0 MHz 36.8 MHz 68.0 MHz 118.5 MHz3 40.0 MHz 73.5 MHz 136.0 MHz3 164.0 MHz3
4 25.7 MHz 47.2 MHz 87.5 MHz 152.3 MHz3 51.4 MHz 94.4 MHz 174.9 MHz3 210.8 MHz3
5 31.4 MHz 57.7 MHz 106.9 MHz3 186.1 MHz3 62.7 MHz 115.4 MHz3 213.7 MHz3 257.5 MHz3

1.M_TTCAN always starts at filter element #0 and proceeds through the filter list to find a matching element. Accep-
tance filtering stops at the first matching element and the following filter elements are not evaluated for this
message. Therefore, the sequence of configured filter elements has a significant impact on the performance of the
filtering process.
2.Acceptance filtering search for 11-bit IDs and 29-bit IDs filter element runs separately; only one configured filter
setting should be considered. Searching for one 29-bit filter element requires approximately double cycles for one
11-bit filter element.
3.Frequency is not reachable since the maximum host clock frequency for M_TTCAN in TRAVEO™ T2G is 100 MHz.
Parameters Affected N/A
Trigger Condition(s) Under the following conditions a received message has corrupted data while the received message is signaled as
valid to the host:
1) The data length code (DLC) of the received message is greater than 4 (DLC > 4)
2) The storage of Ri of a received message into the Message RAM (after acceptance filtering is done) has not completed
before R(i+1) is transferred from the CAN Core into the cache of the Rx Handler (where 2 ≤ i ≤ 5).
3) While condition 1) and 2) apply, a concurrent read of data word Ri from the cache and write of data word R(i+1)
into the cache of the Rx handler happens.
Scope of Impact The erratum is limited to the case when the Host clock frequency used in the actual device is below the limit shown
in Table 1.
Corrupted data is written to the Rx FIFO element from the respective dedicated Rx Buffer.
The received frame is nevertheless signaled as valid.

Datasheet 218 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Architecture block diagram

18.CAN FD sporadic data corruption (payload) in case acceptance filtering does not finish before reception of data R3 (DB7..DB4) is
complete
Workaround Check whether the minimum Host clock frequency (shown in Table 1) is below the Host clock frequency used in the
actual device.
If yes, there is no problem with the selected configuration.
If no, use one of the following two workarounds.

1) Try a different configuration by changing the following parameters until the actual Host clock frequency
(CLK_GR5) is above the minimum host frequency shown in Table 1:
• Increase the CLK_GR5 frequency in the actual device
• Reduce the CAN-FD data bit rate
• Reduce the number of configured filter elements
• Reduce the number of active CAN channels in an instance

Also, use DLC ≥ 8 instead of DLCs 5, 6, and 7 in the CAN environment/system, as they place higher demands on the
minimum Host clock frequency (the worst case is DLC = 5) or restrict your CAN environment/system to DLC 4.

Note: While changing the actual host clock frequency, CLK_GR5 must always be equal to or higher than PCLK_-
CANFD[x]_CLOCK_CAN[y] for all configurations.

2) Due to condition 3) listed in “Trigger Conditions”, the issue occurs only sporadically. Use an end-to-end (E2E)
protection (for example, checksum or CRC covering the data field) and add it to all messages in the CAN system, to
detect data corruption in the received frames.
Fix Status No silicon fix planned. Use workaround.
Impact on Infineon Impact: Limitation
software Related modules: CAN, MCU
Comment: The user must evaluate the impact of the erratum for each CAN instance separately. A CAN instance
is the entirety of CanControllers with the same CanControllerInstance value.
1) For the number of active CAN nodes: Use the maximum number of CanController configurations of a CAN
instance that can be active (Autosar controller state STARTED or SLEEP) at a time.
2) For the host clock frequency: In McuPeriGroupSettings, locate the setting with McuPeriGroup =
MCU_PERI_GROUP5_MMIO5 and take the value from McuPeriGroupClockFrequency.
4) For the number of configured active filter element 11-bit IDs / 29-bit IDs: Use the corresponding values from
the "Message RAM (…) linking table" in the generated Can_PBcfg.h file. Note that each CanController has its
separate table. Take the maximum values.
5) For the arbitration bit rate: Use the maximum CanControllerBaudRate value of all the CanControllers.
6) For the data bit rate: Use the maximum CanControllerFdBaudRate value of all the CanControllers if
configured. Otherwise use CanControllerBaudRate.

19.Description for PASS SARx to TCPWMx direct connect triggers one-to-one is incorrect in datasheet
Problem Definition The existing datasheet shows the incorrect TCPWM input trigger selection (TR_IN_SEL) value,'trig=2', in the description
for PASS SARx to TCPWMx direct connect triggers one-to-one. The correct value to calculate is '4' as shown in the archi-
tecture TRM chapter 25 descriptions and table 25-2.
Parameters Affected N/A
Trigger Condition(s) Using the triggers one-to-one for PASS SARx to TCPWMx direct connect
Scope of Impact The triggers one-to-one for PASS SARx to TCPWMx direct connect cannot work if TCPWM's input trigger selection is not
correct.
Workaround Use '4' as TCPWM's input trigger selection (TR_IN_SEL) value for PASS SARx to TCPWMx direct connect
Fix Status No silicon fix planned. Datasheet was updated.
Impact on Infineon software Impact: No
Related modules: PWM
Comment: MCAL PWM module does not support one-to-one triggers.

Datasheet 219 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Revision history

Revision histor y
Document Date of release Description of changes
version
** 2018-02-23 New datasheet
Updated Features and Features list.
Updated Blocks and functionality.
Updated Functional description.
Updated CYT4BF address map, Flash base address map, and Peripheral I/O map.
Added CYT4BF clock diagram.
Added Pin assignment
*A 2018-05-04 Updated Electrical specifications.
Added the following timing diagrams in Electrical specifications:
Reset, TCPWM, SCB (I2C, SPI), Crystal Connection Scheme, SAR ADC, System Resources, and JTAG.
Added Interrupts and wake-up assignments, Peripheral clock assignments, Trigger multiplexer,
Triggers group inputs, Triggers group outputs, Triggers one-to-one, and Faults.
Added Peripheral I/O map
Added Packaging.
Updated Features and Features list.
Updated Blocks and functionality.
Updated Pin assignment.
*B 2018-07-27 Updated Electrical specifications.
Added Timing Diagrams for Ethernet, SMIF
Updated SCB Diagrams
Added Ordering information.
Updated Features list and Peripheral I/O map.
Updated Functional description.
Updated Pin assignment and Package pin list and alternate functions.
*C 2018-09-28 Updated Trigger multiplexer, Core interrupt types, and Peripheral clock assignments.
Added General P-DMA descriptions and Clock Dividers.
Updated CYT4BF clock diagram.
Updated Electrical specifications.
Updated Design Review.
Updated Features list and Peripheral I/O map.
Updated Functional description.
*D 2019-01-16 Updated Pin assignment for 176-TEQFP package
Updated Electrical specifications.
Updated Design and Expert Reviews.
Updated Features list, CYT4BF address map, Peripheral I/O map.
Updated Pin assignment, Alternate function pin assignments.
Updated Trigger Group tables.
Updated Peripheral clocks and Peripheral protection unit fixed structure pairs.
Updated Bus masters and Miscellaneous configuration.
*E 2019-06-06
Updated Electrical specifications.
Updated and SPI Diagrams.
Updated Table 27-20.
Updated Ordering information and Packaging.
Updated Appendix.
Updated TCPWM Channels and Programmable Analog in Features.
Updated Ethernet MAC, TCPWM, SAR ADC, Audio I2S, and Debug Trace in Features list.
Updated TCPWM channels in Architecture block diagram.
Updated DeepSleep, PLL and FLL, TCPWM, and External Memory Interface sections in Functional
description.
Updated SRAM details in CYT4BF address map.
Added eFUSE and updated PERI Programmable PPU in Peripheral I/O map.
*F 2019-11-15
Added VSSD_2 in Power pin assignments.
Updated PASS interrupts in Interrupts and wake-up assignments.
Added Note 40 in Peripheral protection unit fixed structure pairs.
Changed MiniProg3 to MiniProg4 in Development support.
Updated , ADC Calculation of impact of neighboring pins, Clock Specifications, and SMIF Diagrams in
Electrical specifications.
Updated Ordering information and Packaging.
Updated Functional description.
Updated Power pin assignments.
Updated Pin mux descriptions.
Updated Fault assignments.
*G 2020-05-04 Updated ECO spec from 3.988 MHz to 8 MHz.
Updated Electrical specifications.
Updated Ordering information.
Added Errata.

Datasheet 220 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Errata

Document
version Date of release Description of changes

Updated Features.
Updated Features list.
Updated Regulators.
Updated Clock system.
Updated Peripheral I/O map.
Updated Power pin assignments.
Updated Pin mux descriptions.
*H 2020-09-23 Updated DC specifications.
Updated Ethernet specifications.
Updated Packaging.
Updated Appendix.
Updated Electrical specifications.

Please refer to Revision history change logRev. *M electrical spec updates for the detailed list of
changes for this revision.
Removed Preliminary status.
Updated Features.
Updated Clock system.
Updated Power modes.
Updated Audio interface.
Updated I/Os.
Updated Pin assignment.
Updated High-speed I/O matrix connections.
*I 2021-10-27 Updated Alternate function pin assignments.
Updated Interrupts and wake-up assignments.
Updated Faults.
Updated Electrical specifications.
Updated Part number nomenclature.
Added Errata

Please refer to Rev. *M electrical spec updatesRevision history change log for the detailed list of
changes for this revision.
Updated System resources.
*J 2022-02-18 Updated Serial memory interface specifications.
Updated Errata.
Updated External memory interface.
Updated Alternate function pin assignments.
*K 2022-10-10 Updated Electrical specifications.
Added note in Packaging.
Updated Errata.
Updated Features list.
Updated Blocks and functionality.
Updated Peripherals, and Peripheral I/O map.
Updated Package pin list and alternate functions and Power pin assignments.
*L 2023-07-12
Updated Pin mux descriptions.
Updated Electrical specifications.
Added note in Packaging.
Updated Errata.
Updated Ethernet MAC.
Updated CYT3BB/4BB CPU start-up sequence.
*M 2024-01-25 Updated Triggers one-to-one.
Updated figures in Serial memory interface specifications.
Updated Errata.

Datasheet 221 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Revision history change log

Revision histor y change log

Rev. *M section updates
Reason for
Section Change Description Current Spec New Spec change
3.3.8. Ethernet MAC Updated description CYT3BB/4BB supports half/full-duplex data CYT3BB/4BB supports full-duplex data Correction
transport transport
8. CYT3BB/4BB CPU Updated CLK_HFx ii. Sets clocks for CM7_0 (CLK_HF1) and ii. Sets clocks for CM7_0 (CLK_HF1) and CM7_1 Correction
start-up sequence CM7_1 (CLK_HF2) (CLK_HF1)
20. Triggers MUX Group 6: PASS SARx to Description: Description: Correction
one-to-one TCPWM1 direct connect SAR0 ch#0, range violation to TCPWM1 SAR0 ch#0, range violation to TCPWM1 Group
Input: 0 Group #1 Counter #00 trig=2 #1 Counter #00 trig=4
: : :
Input 71 SAR2 ch#7, range violation to TCPWM1 SAR2 ch#7, range violation to TCPWM1 Group
Group #0 Counter #51 trig=2 #0 Counter #51 trig=4
27.17 Serial memory Figure 27-43 Figure of "Figure 27-12 SDR write timing Figure of "Figure 27-43 SDR write timing Correction
interface specifica- reference level" reference level"
tions
27.17 Serial memory Figure 27-44 Figure of "Figure 27-13 SDR read timing Figure of "Figure 27-44 SDR read timing Correction
interface specifica- reference level" reference level"
tions
27.17 Serial memory Figure 27-45 Figure of "Figure 27-14 DDR write timing Figure of "Figure 27-45 DDR write timing Correction
interface specifica- reference level" reference level"
tions
27.17 Serial memory Figure 26-46 Figure of "Figure 27-15 SDR read timing Figure of "Figure 27-46 SDR read timing Correction
interface specifica- reference level" reference level"
tions
27.17 Serial memory Figure 27-47 Figure of "Figure 27-16 SDR read timing Figure of "Figure 27-47 SDR read timing Correction
interface specifica- reference level" reference level"
tions 4: Clock LOW output valid = tV 4: Clock LOW to input data valid = tV
27.17 Serial memory Figure 27-48 Figure of "Figure 27-17 SDR read timing Figure of "Figure 27-48 SDR read timing Correction
interface specifica- reference level" reference level"
tions 4: Clock LOW output valid = tV 4: Clock LOW to input data valid = tV
none Write Timing
none Read Timing
31. Errata CYT4BF errata summary [17] Items: Items: Updated errata
Items: Hardfault may occur when calling Hardfault may occur when calling the SROM
Fix Status: ReadSWPU or WriteSWPU while executing APIs listed below while executing EraseSector
EraseSector or ProgramRow in non-blocking or ProgramRow in non-blocking mode
mode
Fix Status:
Fix Status: No silicon fix planned. TRM will be updated.
No silicon fix planned. TRM was updated.
31. Errata CYT4BF errata summary [19] none Items: Added errata
Items: Description for PASS SARx to TCPWMx direct
Errata ID: connect triggers one-to-one is incorrect in
Fix Status: datasheet
Errata ID: 212

Fix Status:
No silicon fix planned. Datasheet will be
updated.

Datasheet 222 002-21617 Rev. *M

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TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Revision history change log

Reason for
Section Change Description Current Spec New Spec change
31. Errata 17.Hardfault may occur when Problem Definition: Problem Definition: Updated errata
calling the SROM APIs listed below ReadSWPU or WriteSWPU read data from The following SROM APIs read data from
while executing EraseSector or bank#0 (or bank#1 if dual bank mode with bank#0 (or bank#1 if dual bank mode with
ProgramRow in non-blocking mapping B is used) in SFlash. While doing mapping B is used) in SFlash. While doing that,
mode that, the check for active non-blocking erase the check for active non-blocking erase or
Problem Definition: or program of bank#0 (or bank#1 if dual program of bank#0 (or bank#1 if dual bank
Trigger Condition(s): bank mode with mapping B is used) is not mode with mapping B is used) is not
Scope of Impact: performed. Therefore, reading bank#0 (or performed. Therefore, reading bank#0 (or
Workaround: bank#1 if dual bank mode with mapping B is bank#1 if dual bank mode with mapping B is
Fix Status: used) while there is an active erase/program used) while there is an active erase/program
operation will trigger a bus error, which can operation triggers a bus error, which can result
result in a hardfault occurrence based on in a hardfault occurrence based on FLASHC_
FLASHC_FLASH_CTL register settings. FLASH_CTL register settings.

Trigger Condition(s): Affected SROM APIs:

Calling ReadSWPU or WriteSWPU while - ReadSWPU
executing EraseSector or ProgramRow in - WriteSWPU
non-blocking mode on bank#0 (or bank#1 if - GenerateHash
dual bank mode with mapping B is used). - Checksum*
- ComputeBasicHash*
Scope of Impact: - CheckFactoryHash
ReadSWPU or WriteSWPU cannot be used - ProgramWorkFlash**
while executing EraseSector or ProgramRow - SwitchOverRegulators
in non-blocking mode - LoadRegulatorsTrims
on bank#0 (or bank#1 if dual bank mode *: Do not call it to calculate on the bank where
with mapping B is used). programming/erasing is in progress.
**: Do not use it during non-blocking
operation.

Trigger Condition(s):
Calling the affected SROM APIs while executing
EraseSector or ProgramRow in non-blocking
mode on bank#0 (or bank#1 if dual bank mode
with mapping B is used).

Scope of Impact:
The affected SROM APIs cannot be used while
executing EraseSector or ProgramRow in
non-blocking mode
on bank#0 (or bank#1 if dual bank mode with
mapping B is used).
Workaround: Workaround:
Do not use ReadSWPU or WriteSWPU while Do not use the affected SROM APIs while
executing EraseSector or ProgramRow in executing EraseSector or ProgramRow in
non-blocking mode non-blocking mode on
on bank#0 (or bank#1 if dual bank mode bank#0 (or bank#1 if dual bank mode with
with mapping B is used). mapping B is used).

Fix Status: Fix Status:

No silicon fix planned. TRM was updated. No silicon fix planned. TRM will be updated.
31. Errata 19.Description for PASS SARx to none Added "19.Description for PASS SARx to Added errata
TCPWMx direct connect triggers TCPWMx direct connect triggers one-to-one is
one-to-one is incorrect in incorrect in datasheet"
datasheet

Datasheet 223 002-21617 Rev. *M

2024-01-25
TRAVEO™ T2G 32-bit Automotive MCU
Based on Arm® Cortex®-M7 dual
Revision history change log

Rev. *M electrical spec updates

Spec ID Description Changed Item Current Spec New Spec Reason for Change
SID69 Power down time Max Max: 2.5 μs Max: 2.8 μs Updated spec
from Active to
DeepSleep

SID194 SPI Master: MISO valid Min Min: - Min: 0.4 X (1 / fSPI) ns Updated spec
before SCLK capturing Typ Typ: 0.4 X (1 / fSPI) ns Typ: 0.5 X (1 / fSPI) ns
edge Max Max: - Max: 0.6 X (1 / fSPI) ns

SID769 Data setup time Description Description: Data setup time Description: Data setup time (fCK = 100 MHz) Updated condition
(fCK = 100 MHz) Details/Conditions Details/Conditions: none Details/Conditions: For other frequencies: tSU =
tSU_min + 0.45 ×
(tCK - tCK_min)
tSU_min = value at min of SID769
tCK_min = value at min of SID763
tCK = actual clock period

SID769B Data setup time (fCK = Description Description: Data setup time Description: Data setup time (fCK = 90 MHz) Updated condition
90 MHz) Details/Conditions Details/Conditions: none Details/Conditions: For other frequencies: tSU =
tSU_min + 0.225 ×
(tCK - tCK_min)
tSU_min = value at min of SID769B
tCK_min = value at min of SID763B
tCK = actual clock period

SID780 Data hold time (fCK = Description Description: Data hold time Description: Data hold time (fCK = 100 MHz) Updated condition
100 MHz) Details/Conditions Details/Conditions: none Details/Conditions: For other frequencies: tHD =
tHD_min + 0.45 ×
(tCK - tCK_min)
tHD_min = value at min of SID780
tCK_min = value at min of SID763
tCK = actual clock period

SID780B Data hold time (fCK = Description Description: Data hold time Description: Data hold time (fCK = 90 MHz) Updated condition
90 MHz) Details/Conditions Details/Conditions: none Details/Conditions: For other frequencies:
tHD = tHD_min + 0.225 × (tCK - tCK_min)
tHD_min = value at min of SID780B
tCK_min = value at min of SID763B
tCK = actual clock period

SID781 Clock LOW to input Description Description: Clock LOW output valid Description: Clock LOW to input data valid Updated description
data valid
SID781A Clock LOW to input Description Description: Clock LOW output valid Description: Clock LOW to input data valid Updated description
data valid
SID781B Clock LOW to input Descriptiong Description: Clock LOW output valid Description: Clock LOW to input data valid Updated description
data valid
SID781C Clock LOW to input Description Description: Clock LOW output valid Description: Clock LOW to input data valid Updated description
data valid
SID812 I/O loading at Min Min: 40 pF Min: - Updated condition
DATA/CMD pins
SID813 I/O loading at CLK pins Min Min: 40 pF Min: - Updated condition
SID822 I/O loading at Min Min: 40 pF Min: - Updated condition
DATA/CMD pins
SID823 I/O loading at CLK pins Min Min: 40 pF Min: - Updated condition
SID872 I/O loading at Min Min: 30 pF Min: - Updated condition
DATA/CMD pins
SID873 I/O loading at CLK pins Min Min: 30 pF Min: - Updated condition
SID882 I/O loading at Min Min: 30 pF Min: - Updated condition
DATA/CMD pins
SID883 I/O loading at CLK pins Min Min: 30 pF Min: - Updated condition
SID893 I/O loading at Min Min: 20 pF Min: - Updated condition
DATA/CMD pins
SID894 I/O loading at CLK pins Min Min: 20 pF Min: - Updated condition

Datasheet 224 002-21617 Rev. *M

2024-01-25
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