LIST OF EXPERIMENTS

1.Verification of Boolean theorems using logic gates.

2.Implementation of code converters.
3.Implementation of 4-bit binary adder/subtractor circuits.
4.
6.Implementation of functions using Multiplexers.
7.Implementation of the synchronous counters
8.Implementation of a Universal Shift register
Design and implementation of combinational circuits using gates for arbitrary functions
Implementation of BCD adder, encoder and decoder circuits
9. Simulator based study of Computer Architecture
 INDEX

Staff
Ex.No. Date Title Marks
Sign.

1a STUDY OF LOGIC GATES

VERIFICATION OF BOOLEAN
1b THEOREMS USING DIGITAL
LOGIC GATES

2 DESIGN AND IMPLEMENTATION

OF COMBINATIONAL CIRCUITS
USING GATES FOR ARBITRARY
FUNCTIONS

3 IMPLEMENTATION OF CODE
CONVERTERS
IMPLEMENTATION OF 4 BIT
4 BINARY ADDER/SUBTRACTOR
CIRCUITS ADDER AND
SUBTRACTOR
IMPLEMENTATION OF
5
BCD ADDER,ENCODER
AND DECODER
CIRCUITS
IMPLEMENTATION OF FUNCTIONS
6 USING MULTIPLEXERS

IMPLEMENTATION
7
OF SYNCHRONOUS
COUNTERS

8 IMPLEMENTATION OF UNIVERSAL
SHIFT REGISTER
SIMULATOR BASED STUDY
9
OF COMPUTER
ARCHITECTURE
Ex.No.-1a STUDY OF LOGIC GATES

AIM:
To study about logic gates and verify their truth tables.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. NAND GATE 2 I/P IC 7400 1
5. NOR GATE IC 7402 1
6. X-OR GATE IC 7486 1
7. NAND GATE 3 I/P IC 7410 1
8. IC TRAINER KIT - 1
9. PATCH CORD - 14

THEORY:
Circuit that takes the logical decision and the process are called logic gates.
Each gate has one or more input and only one output.
OR, AND and NOT are basic gates. NAND, NOR and X-OR are known as
universal gates. Basic gates form these gates.

AND GATE:
The AND gate performs a logical multiplication commonly known as AND
function. The output is high when both the inputs are high. The output is low level
when any one of the inputs is low.

OR GATE:
The OR gate performs a logical addition commonly known as OR function.
The output is high when any one of the inputs is high. The output is low level when
both the inputs are low.

NOT GATE:
The NOT gate is called an inverter. The output is high when the input is low.
The output is low when the input is high.

AND GATE:
The NAND gate is a contraction of AND-NOT. The output is high when both
inputs are low and any one of the input is low .The output is low level when both
inputs are high.

NOR GATE:
The NOR gate is a contraction of OR-NOT. The output is high when both
inputs are low. The output is low when one or both inputs are high.
X- OR GATE:
The output is high when any one of the inputs is high. The output is
low when both the inputs are low and both the inputs are high.

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

AND GATE

SYMBOL PIN DIAGRAM

OR GATE
 NOT GATE

SYMBOL PIN DIAGRAM

EX-OR GATE

SYMBOL PIN DIAGRAM

 2-INPUT NAND GATE

SYMBOL PIN DIAGRAM

3-INPUT NAND GATE

 NOR GATE

RESULT:

The logic gates are studied and its truth tables are verified.
Ex.No.-1b VERIFICATION OF BOOLEAN
THEOREMS USING DIGITAL LOGIC GATES

AIM:

To verify the Boolean Theorems using logic gates.

APPARATUS REQUIRED:

SL. NO. COMPONENT SPECIFICATION QTY.

1. AND GATE IC 7408 1
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
4. IC TRAINER KIT - 1
As per
5. CONNECTING WIRES - required

THEORY:

BASIC BOOLEAN LAWS

1. Commutative Law
The binary operator OR, AND is said to be commutative if,
1. A+B = B+A
2. A.B=B.A

2. Associative Law
The binary operator OR, AND is said to be associative if,
1. A+(B+C) = (A+B)+C
2. A.(B.C) = (A.B).C

3. Distributive Law
The binary operator OR, AND is said to be distributive if,
1. A+(B.C) = (A+B).(A+C)
2. A.(B+C) = (A.B)+(A.C)

4. Absorption Law
1. A+AB = A
2. A+AB = A+B

5. Involution (or) Double complement Law

1. A = A

6. Idempotent Law
1. A+A = A
2. A.A = A
7. Complementary Law
1. A+A' = 1
2. A.A' = 0

8. De Morgan’s Theorem
1. The complement of the sum is equal to the sum of the product of the
individual complements.
A+B = A.B
2. The complement of the product is equal to the sum of the individual complements.
A.B = A+B
Demorgan’s Theorem
a) Proof of equation (1):
Construct the two circuits corresponding to the functions A’. B’and (A+B)’
respectively. Show that for all combinations of A and B, the two circuits give
identical results. Connect these circuits and verify their operations.
b) Proof of equation (2)
Construct two circuits corresponding to the functions A’+B’and (A.B)’ A.B,
respectively. Show that, for all combinations of A and B, the two circuits give
identical results. Connect these circuits and verify their operations.
We will also use the following set of postulates:
P1: Boolean algebra is closed under the AND, OR, and NOT operations.
P2: The identity element with respect to • is one and + is zero. There is no
identity element with respect to logical NOT.
P3: The • and + operators are commutative.
P4: • and + are distributive with respect to one another. That is,
A • (B + C) = (A • B) + (A • C) and A + (B • C) = (A + B) • (A + C).
P5: For every value A there exists a value A’ such that A•A’ = 0 and A+A’ = 1.
This value is the logical complement (or NOT) of A.
P6: • and + are both associative. That is, (A•B)•C = A•(B•C) and (A+B)+C = A+(B+C).
You can prove all other theorems in boolean algebra using these postulates.

PROCEDURE:

1. Obtain the required IC along with the Digital trainer kit.

2. Connect zero volts to GND pin and +5 volts to Vcc .
3. Apply the inputs to the respective input pins.
4. Verify the output with the truth table.

RESULT:
Thus the above stated Boolean laws are verified.

13
Ex.No.-2 IMPLEMENTATION OF CODE CONVERTOR

AIM:

To design and implement 4-bit

(i) Binary to gray code converter
(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

APPARATUS REQUIRED:
SL.NO. COMPONENT SPECIFICATION QTY.
1. X-OR GATE IC 7486 1
2. AND GATE IC 7408 1
3. OR GATE IC 7432 1
4. NOT GATE IC 7404 1
5. IC TRAINER KIT - 1
6. PATCH CORDS - 35

THEORY:

The availability of large variety of codes for the same discrete elements of
information results in the use of different codes by different systems. A conversion circuit
must be inserted between the two systems if each uses different codes for same
information. Thus, code converter is a circuit that makes the two systems compatible even
though each uses different binary code.

The bit combination assigned to binary code to gray code. Since each code uses
four bits to represent a decimal digit. There are four inputs and four outputs. Gray code is a
non-weighted code.

The input variable are designated as B3, B2, B1, B0 and the output variables are
designated as C3, C2, C1, Co. from the truth table, combinational circuit is designed. The
Boolean functions are obtained from K-Map for each output variable.

A code converter is a circuit that makes the two systems compatible even though
each uses a different binary code. To convert from binary code to Excess-3 code, the input
lines must supply the bit combination of elements as specified by code and the output lines
generate the corresponding bit combination of code. Each one of the four maps represents
one of the four outputs of the circuit as a function of the four input variables.

14
 A two-level logic diagram may be obtained directly from the Boolean expressions
derived by the maps. These are various other possibilities for a logic diagram that
implements this circuit. Now the OR gate whose output is C+D has been used to
implement partially each of three outputs.

BINARY TO GRAY CODE CONVERTOR

TRUTH TABLE:

Binary Input Gray Code Output

B3 B2 B1 B0 G3 G2 G1 G0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 0 1 1 1
0 1 1 0 0 1 0 1
0 1 1 1 0 1 0 0
1 0 0 0 1 1 0 0
1 0 0 1 1 1 0 1
1 0 1 0 1 1 1 1
1 0 1 1 1 1 1 0
1 1 0 0 1 0 1 0
1 1 0 1 1 0 1 1
1 1 1 0 1 0 0 1
1 1 1 1 1 0 0 0

K-Map for G3

G3 = B 3

15
K-Map for G2

K-Map for G1

K-Map for G0

16
 LOGIC DIAGRAM:

GRAY CODE TO BINARY CONVERTOR

TRUTH TABLE:

GRAY CODE BINARY CODE

G3 G2 G1 G0 B3 B2 B1 B0
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 1 0 0 1 0
0 0 1 0 0 0 1 1
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
0 1 0 1 0 1 1 0
0 1 0 0 0 1 1 1
1 1 0 0 1 0 0 0
1 1 0 1 1 0 0 1
1 1 1 1 1 0 1 0
1 1 1 0 1 0 1 1
1 0 1 0 1 1 0 0
1 0 1 1 1 1 0 1
1 0 0 1 1 1 1 0
1 0 0 0 1 1 1 1

17
K-Map for B3:

B3 = G3

K-Map for B2:

K-Map for B1:

18
K-Map for B0:

LOGIC DIAGRAM:

19
TRUTH TABLE: BCD TO EXCESS-3 CONVERTOR

| BCD input | Excess – 3 output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 0 0 0 0 1 1

0 0 0 1 0 1 0 0

0 0 1 0 0 1 0 1

0 0 1 1 0 1 1 0

0 1 0 0 0 1 1 1

0 1 0 1 1 0 0 0

0 1 1 0 1 0 0 1

0 1 1 1 1 0 1 0

1 0 0 0 1 0 1 1

1 0 0 1 1 1 0 0

1 0 1 0 x x x x

1 0 1 1 x x x x

1 1 0 0 x x x x

1 1 0 1 x x x x

1 1 1 0 x x x x

1 1 1 1 x x x X

K-Map for E3:

E3 = B3 + B2 (B0 + B1)
20
K-Map for E2:

K-Map for E1:

K-Map for E0:

21
 EXCESS-3 TO BCD CONVERTOR

TRUTH TABLE:

| Excess – 3 Input | BCD Output |

B3 B2 B1 B0 G3 G2 G1 G0

0 0 1 1 0 0 0 0

0 1 0 0 0 0 0 1

0 1 0 1 0 0 1 0

0 1 1 0 0 0 1 1

0 1 1 1 0 1 0 0

1 0 0 0 0 1 0 1

1 0 0 1 0 1 1 0

1 0 1 0 0 1 1 1

1 0 1 1 1 0 0 0

1 1 0 0 1 0 0 1

LOGIC DIAGRAM:

22
 EXCESS-3 TO BCD CONVERTOR

K-Map for A:

A = X1 X2 + X3 X4 X1

K-Map for B:

K-Map for C:

23
K-Map for D:

EXCESS-3 TO BCD CONVERTOR

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

24
RESULT:

Thus the following 4-bit converters are designed and constructed.

(i) Binary to gray code converter

(ii) Gray to binary code converter
(iii) BCD to excess-3 code converter
(iv) Excess-3 to BCD code converter

25
26
Ex.No.-3 4-BIT ADDER AND SUBTRACTOR

AIM:

To design and implement 4-bit adder and subtractor using basic gates and MSI
device IC 7483.

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. IC IC 7483 1
2. EX-OR GATE IC 7486 1
3. NOT GATE IC 7404 1
3. IC TRAINER KIT - 1
4. PATCH CORDS - 40

THEORY:

4 BIT BINARY ADDER:

A binary adder is a digital circuit that produces the arithmetic sum of two binary
numbers. It can be constructed with full adders connected in cascade, with the output carry
from each full adder connected to the input carry of next full adder in chain. The augends
bits of ‘A’ and the addend bits of ‘B’ are designated by subscript numbers from right to
left, with subscript 0 denoting the least significant bits. The carries are connected in chain
through the full adder. The input carry to the adder is C 0 and it ripples through the full
adder to the output carry C4.

4 BIT BINARY SUBTRACTOR:

The circuit for subtracting A-B consists of an adder with inverters, placed between
each data input ‘B’ and the corresponding input of full adder. The input carry C 0 must be
equal to 1 when performing subtraction.

4 BIT BINARY ADDER/SUBTRACTOR:

The addition and subtraction operation can be combined into one circuit with one
common binary adder. The mode input M controls the operation. When M=0, the circuit is
adder circuit. When M=1, it becomes subtractor.

4 BIT BCD ADDER:

Consider the arithmetic addition of two decimal digits in BCD, together with an
input carry from a previous stage. Since each input digit does not exceed 9, the output sum
cannot be greater than 19, the 1 in the sum being an input carry. The output of two decimal
digits must be represented in BCD and should appear in the form listed in the columns.

27
 ABCD adder that adds 2 BCD digits and produce a sum digit in BCD. The 2
decimal digits, together with the input carry, are first added in the top 4 bit adder to
produce the binary sum.

PIN DIAGRAM FOR IC 7483:

4-BIT BINARY ADDER

LOGIC DIAGRAM:

28
4-BIT BINARY SUBTRACTOR

LOGIC DIAGRAM:

4- BIT BINARY ADDER/SUBTRACTOR

LOGIC DIAGRAM:

34
TRUTH TABLE:

Input Data A Input Data B Addition Subtraction

A4 A3 A2 A1 B4 B3 B2 B1 C S4 S3 S2 S1 B D4 D3 D2 D1
1 0 0 0 0 0 1 0 0 1 0 1 0 1 0 1 1 0
1 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 0
0 0 1 0 1 0 0 0 0 1 0 1 0 0 1 0 1 0
0 0 0 1 0 1 1 1 0 1 0 0 0 0 1 0 1 0
1 0 1 0 1 0 1 1 1 0 0 1 0 0 1 1 1 1
1 1 1 0 1 1 1 1 1 1 0 1 0 0 1 1 1 1
1 0 1 0 1 1 0 1 1 0 1 1 1 0 1 1 0 1

PROCEDURE:

(i) Connections were given as per circuit diagram.

(ii) Logical inputs were given as per truth table
(iii) Observe the logical output and verify with the truth tables.

RESULT:

Thus the 4-bit adder and subtractor using basic gates and MSI device IC 7483 is
designed and implemented.

35
43
Ex.No.-4 IMPLEMENTATION OF FUNCTIONS USING MULTIPLEXER

AIM:

To design and implement the multiplexer and using logic gates and study of
IC 74150

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. 3 I/P AND GATE IC 7411 2
2. OR GATE IC 7432 1
3. NOT GATE IC 7404 1
2. IC TRAINER KIT - 1
3. PATCH CORDS - 32

THEORY:

MULTIPLEXER:
Multiplexer means transmitting a large number of information units over a smaller
number of channels or lines. A digital multiplexer is a combinational circuit that selects
binary information from one of many input lines and directs it to a single output line. The
selection of a particular input line is controlled by a set of selection lines. Normally there
n
are 2 input line and n selection lines whose bit combination determine which input is

selected.

4:1 MULTIPLEXER

BLOCK DIAGRAM FOR 4:1 MULTIPLEXER:

45
FUNCTION TABLE:
S1 S0 INPUTS Y
0 0 D0 → D0 S1’ S0’
0 1 D1 → D1 S1’ S0
1 0 D2 → D2 S1 S0’
1 1 D3 → D3 S1 S0

Y = D0 S1’ S0’ + D1 S1’ S0 + D2 S1 S0’ + D3 S1

S0 TRUTH TABLE:

S1 S0 Y = OUTPUT

0 0 D0
0 1 D1
1 0 D2
1 1 D3

46
CIRCUIT DIAGRAM FOR MULTIPLEXER:

47
PIN DIAGRAM FOR IC 74150:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
Thus the multiplexer using logic gates are designed and implemented.

48
Ex.No.-5 IMPLEMENTATION OF UNIVERSALSHIFT REGISTER

AIM:

To design and implement the following shift registers

(i) Serial in serial out
(ii) Serial in parallel out
(iii) Parallel in serial out
(iv) Parallel in parallel out

APPARATUS REQUIRED:

SL.NO. COMPONENT SPECIFICATION QTY.

1. D FLIP FLOP IC 7474 2

2. OR GATE IC 7432 1

3. IC TRAINER KIT - 1

4. PATCH CORDS - 35

THEORY:
A register is capable of shifting its binary information in one or both directions is
known as shift register. The logical configuration of shift register consist of a D-Flip flop
cascaded with output of one flip flop connected to input of next flip flop. All flip flops
receive common clock pulses which causes the shift in the output of the flip flop. The
simplest possible shift register is one that uses only flip flop. The output of a given flip flop
is connected to the input of next flip flop of the register. Each clock pulse shifts the content
of register one bit position to right.

PIN DIAGRAM OF IC 7474:

49
 SERIAL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

CLK Serial In Serial Out

1 1 0
2 0 0
3 0 0
4 1 1
5 X 0
6 X 0
7 X 1

SERIAL IN PARALLEL OUT

LOGIC DIAGRAM:

50
TRUTH TABLE:

OUTPUT
CLK DATA QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

PARALLEL IN SERIAL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

CLK Q3 Q2 Q1 Q0 O/P

0 1 0 0 1 1

1 0 0 0 0 0

2 0 0 0 0 0

3 0 0 0 0 1

51
 PARALLEL IN PARALLEL OUT

LOGIC DIAGRAM:

TRUTH TABLE:

DATA INPUT OUTPUT

CLK
DA DB DC DD QA QB QC QD

1 1 0 0 1 1 0 0 1

2 1 0 1 0 1 0 1 0

PROCEDURE:
(i) Connections are given as per circuit diagram.
(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:
The Serial in serial out, Serial in parallel out, Parallel in serial out and
Parallel in parallel out shift registers are designed and implemented.

52
Ex.No.-6 IMPLEMENTATION OF SYNCHRONOUS COUNTER
AIM:

To design and implement synchronous counter.

APPARATUS REQUIRED:

S.NO. NAME OF THE APPARATUS RANGE QUANTITY

1. Digital IC trainer kit 1
2. JK Flip Flop IC 7473 2
3. D Flip Flop IC 7473 1
4. NAND gate IC 7400 1
5. Connecting wires As required

THEORY:
Asynchronous decade counter is also called as ripple counter. In a ripple counter
the flip flop output transition serves as a source for triggering other flip flops. In other
words the clock pulse inputs of all the flip flops are triggered not by the incoming pulses
but rather by the transition that occurs in other flip flops. The term asynchronous refers to
the events that do not occur at the same time. With respect to the counter operation,
asynchronous means that the flip flop within the counter are not made to change states at
exactly the same time, they do not because the clock pulses are not connected directly to
the clock input of each flip flop in the counter.

A counter is a register capable of counting number of clock pulse arriving at its

clock input. Counter represents the number of clock pulses arrived. A specified sequence
of states appears as counter output. This is the main difference between a register and a
counter. There are two types of counter, synchronous and asynchronous. In synchronous
common clock is given to all flip flop and in asynchronous first flip flop is clocked by
external pulse and then each successive flip flop is clocked by Q or Q output of previous
stage. A soon the clock of second stage is triggered by output of first stage. Because of
inherent propagation delay time all flip flops are not activated at same time which results
in asynchronous operation.

53
PIN DIAGRAM FOR IC 7476:

CIRCUIT DIAGRAM:

TRUTH TABLE:

54
 LOGIC DIAGRAM FOR MOD - 10 RIPPLE COUNTER:

TRUTH TABLE:

CLK QA QB QC QD
0 0 0 0 0
1 1 0 0 0
2 0 1 0 0
3 1 1 0 0
4 0 0 1 0
5 1 0 1 0
6 0 1 1 0
7 1 1 1 0
8 0 0 0 1
9 1 0 0 1
10 0 0 0 0

55
PIN DIAGRAM:

SYNCHRONOUS COUNTER

LOGIC DIAGRAM:

TRUTH TABLE:

OUTPUT
CLK DATA
QA QB QC QD
1 1 1 0 0 0
2 0 0 1 0 0
3 0 0 0 1 1
4 1 1 0 0 1

56
PROCEDURE:

(i) Connections are given as per circuit diagram.

(ii) Logical inputs are given as per circuit diagram.
(iii) Observe the output and verify the truth table.

RESULT:

Thus the synchronous counter are designed and implemented.

57
EXP NO 7:DESIGN AND IMPLEMENTATION OF COMBINATIONAL CIRCUITS
USING GATE FOR ARBITRARY FUNCTIONS

AIM:

To design and implementation using NAND gate

OBJECTIVE:

To realize why NAND gate is known as the universal gate by implementation of :

a. NOT using NAND

b. AND using NAND

C. OR using NAND

D. XOR using NAND

COMPONENTS REQUIRED:

• Breadboard.

• Connecting wires.

• IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486

THEORY:

Boolean algebra is a branch of mathematical logic, where the variables are either
true (1) or false (0).In order to construct NOT, AND, OR, XOR gates from NAND gates
only, we need to be familiar with the following boolean algebra laws:

1. Involution Law

2. 2. Idempotency (Idempotent) law

3. 3. DeMorgan's Law

2 input AND gate

58
 PROCEDURE:

Check the components for their working.

Insert the appropriate IC into the breadboard.

Make connections as shown in the circuit diagram.

Provide the input data via the input switches and observe the output on output
LEDs Verify the Truth Table

RESULT: design and implementation of combinational circuits is realized using

NAND gate of arbitrary functions.

59
EXP NO 8 : IMPLEMENTATION OF BCD ADDER,ENCODER AND DECODER
CIRCUITS

AIM:

To design and implementation of BCD adder,encoder and decoder circuits

COMPONENTS REQUIRED:

• Breadboard.

• Connecting wires.

• IC 7400, IC 7408, IC 7432, IC 7406, IC 7402, IC 7404, IC 7486

CIRCUIT DIAGRAM:

Truth table:

60
ENCODER:

Circuit diagram :

61
DECODER :

62
TRUTH TABLE:

63
PROCEDURE:
(iv) Connections are given as per circuit diagram.
(v) Logical inputs are given as per circuit diagram.
(vi) Observe the output and verify the truth table.

RESULT:

Thus the implementation of BCD adder,encoder and decoder using was verified

64
 EXPNO 9 : SIMULATOR BASED STUDY OF COMPUTER ARCHITECTURE

AIM:

To study the simulator based study of computer architecture

TOOLS REQUIRED:

Computer simulator

THEORY:

In an introductory computer course , the assembly language is often used to ai d in the

comprehension of the fundamental s of computer structure and organization . The assembler can
also be used t o reinforce computer architecture concept s in an advanced course . Teaching
strategies are used i n computer laboratory activities in order t o illustrate various concepts
introduce d during lectures and/or to acquire experience with low level language . Therefore,
the following learning objectives can be attained with th e assembly language : skills in assembl
y language programming [1] ; informatio n representation and computer organization at internal
level [2] ; structure d programming techniques and the top-down approach [3-4] ; problem
solving, and elements of computer science [5-7] . A common tool adopted in the compute r
laboratory is a computer simulator . Th e simulator structure depends on th e teaching
objective . However, actua l simulators lack a feature which is commo n in simulation models :
the possibility for the student to dynamically change th e characteristics of the simulated system
i n order to verify the physical system performance . Regarding compute r organization, the
simulator should provid e the user with a simple manner o f experimenting with the following
capabilities : definition of a new register , definition of a new instruction type , modifying the
bit dimension of a register , and so on . The manipulation of architectural components is a
useful optiona l feature of the computer simulator in a n introductory course of computer
organization, but it is necessary structure in a n advanced computer architect,Lare course i n
order to require the students to master computer architecture concepts and also some skills in
architectural design . In the light of these considerations , it is opportune to reexamine the
effective role of the computer architectur e simulator in laboratory activities . A computer
simulator prototype base d on the Prolog functional language i s currently under development
at th e University of Bari . Besides adapting t o all previous teaching needs and conventional
learning objectives, the simulator design incorporates features fo r an easy alteration of compute
r architectural structures appropriate to the trainee's learning level . 2 . Foundations of computer
science with assembler language . For many years, the laboratory activities of the computer
organizatio n course in our university have followed th e organization of the theoretical
lectures . Therefore, the pedagogical objectives o f assembler language teaching were affecte d
by the emphasis given to different aspect s of the course i .e ., from the teaching o f skills in
assembly language programming t o reinforcing the basic concepts of th e computer
organization as presented by th e reference textbook [9] . Our beginner students learn computer
systems based on the level structure of figure 1 . The number of students (450 students per
year ) and the currently available computer type s have dictated this solution of laborator y
management . In our laboratory, we have always use d commercial computers representative of
a computer architecture class . In the past , for example, with the diffusion of th e market of the
first minicomputers, i t seemed useful to teach two differen t assembly languages in order to

65
illustrat e the different architectural structures o f the mainframe class, on the one hand, an d the
minicomputer class, on the other . The same set of programs in the two assembly Languages
demonstrated the difference between a general registe r based architecture and one based on a
dedicated register . In the first case , the general register organizatio n considerably reduces the
amount of data movement as compared.The role of the simulator in the laboratory course .

A common practice also adopted by our laboratory, is that of using a compute r simulator as an
aid to amplify the previous topics . The structure of the computer architecture simulators must b
e carefully examined in order to bette r understand their role in the laborator y activities of a
computer organization an d design course . In fact, a) several researchers [2,3,5,6,15] have
develope d simulators of simple hypothetical computers ; b) few researchers [7,16] hav e
developed simulators of simplified commercial architecture with a subset o f foreseen
instructions ; c) some [1,17] use real machines in the laboratory . In the case a), the simplified
computer architecture generally has th e following organization : 1) minimal set of registers :
the program counter, the accumulator, the inde x register, and occasionally the stac k pointer
register ; 2) simple addressing method : direct , indirect, indexed and occasionally, t o stack ; 3)
essential instruction set ; 4) representation of simple data type : positive and negative integer
numbers ; 5) limitated memory address space ; Normally, the student may use the simulator
programming in assembly languag e and/or in hexadecimal representatio n and/or even in
decimal representatio n [18] . Often, the evolution of the interna l situation (i .e ., registers and
memory contents) of the computer during th e simulation of the single instructions ca n be
verified . The reasons given by the authors fo r this approach are the following : -) to avoid
teaching a specific hardwar e and therefore a specific assembl y language . The virtual simplifie
d architecture must be the tool by which general concepts are introduced ; -) to avoid teaching
the unnecessar y complex details of the instruction se t of modern real computers . In this
approach the eventua l independent use of a real computer by th e student and his
comprehension, i s implicit . Although exact simulators of a real computers are not necessarily
th e best tools for providing students wit h necessary skills, the simulators o f simplified
fictitious machines do not see m to reach the proposed aim of generality . In fact, due to the
intrinsic nature o f the matter to teach, the computer organization, and consequently the
assembly language, are hardware dependent . This is also true when the hypothetica l
architecture of the computer simulator i s SIGCSE BULLETIN Vol . 22 No . 2 June 199 0 fixed
. In addition, no mention is made by the authors about the successive impac t with a real
computer, and therefore several doubts arise ; for example, it was previously stated that the
organizatio n and the use of the general register base d architecture of the major part of the
modern computer is quite different tha n the accumulator based architecture of th e majority of
the hypothetical computer simulators . Similarly, the high capacit y of memory space of actual
computers imposes efficient yet more comple x addressing methods with respect to th e
limitated capacity of memory space manage d in the hypothetical computer simulators , which
usually interpret fixed forma t instructions . In laboratory activities , it seems questionable to
use a simplifie d situation when compared to the complexit y of the theoretical lecture .
Moreover , sooner or later, the students will mee t the real modern computer, even if not a t the
machine level, and if the purpose i s to illustrate what happens at this level , the simplified
environment of this hypothetical computer illustrates a different organization with respect to th
e real one . This approach, with th e additional use of decimal notation, i s justifiable in the
theoretical lectures i n order to immediately fix the concepts but , in the laboratory, it is
necessary to compare with real situations, and rea l computers, for example, work in binary o r
hexadecimal representation . In fact , Denning et al . [19] states that "lectures emphasize
enduring principles and concept s while laboratories emphasize the transien t material and skills

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relating to the current technology" . The latter limitation also involve s approach b) (the use of
simplified commercial architecture with subset) , though in a lesser degree . The proper
approach to the real computer complexity (approach c) consist s in introducing progressively
more comple x architectural concepts at any opportun e point in the training cycle of laborator y
activities .

RESULT:

Thus the simulator based study of computer architecture was studied.

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