VLSI Design Cycle

Very Large Scale Integration (VLSI) is the process of making Integrated

Circuits (ICs) by combining a number of components like resistors, transistors,
and capacitors on a single chip.
VLSI Design is an iterative cycle. Designing a VLSI Chip includes a few
problems such as functional design, logic design, circuit design, and physical
design. The design is verified for accuracy by the process of simulation. If any
design errors are found at any stage of verification, at least one of the previous
design steps must be repeated to correct the error during the process of
designing.

What is VLSI Design Flow?

VLSI stands for Very Large Scale Integration where by Integration
Circuits (ICs) are formed by interconnecting a large number of components
including resistors, transistors, capacitors and other components on a single
chip. VLSI design is a process of designing these advanced ICs which are
miniaturized and involves one or more intrinsic loops to generate the final
product owning to certain specifications.
The VLSI design process includes several steps: software requirements,
architectural design, behavioral or functional design, logical design, circuit
design, physical design, exemplary design, fabrication and packaging, and
testing and packaging. All of them are essential for the creation of the new IC
starting from the idea and up to its turnkey functioning.
1. System specification: The objective of the desired final product is written
in this step. During system specification, the designated cost of the system, its
performance, architecture, and how the system will communicate with the
external world are to be determined. During this step, the design specification
should be provided by the users or clients.

2. Architectural design: The basic architecture of the desired design must

meet the system specifications of the desired design. The architecture of the
desired design is decided and the layout for the same is designed by design
engineers. Architectural design includes the integration of analog and mixed-
signal blocks, memory management, internal and external communication,
power requirements, and choice of process technology and layer stacks.
3. Functional design or Behavioural design: It consists of refining the design
specification of the desired design in order to design the functional behavior of
the desired system. The main objective of this is to generate design a high-
performance architectural design within the cost requirements posed by the
specifications.
4. Logic Design: In this step, the structure of the desired design is added to the
behavioral representation of the desired design. The main specifications to be
considered for logic design are logic minimization, performance enhancement,
and testability. Logic design must also consider the problems associated with
test vector generation, error detection, and error correction. Many logic
synthesis tools have been developed for the automation of the process of logic
design.
5. Circuit Design: In this step, the logic blocks of the desired design are
replaced by the electronic circuits, which are consists of electronic devices
such as resistors, capacitors, and transistors. Circuit simulation of the desired
design is done at this stage, in order to verify the timing behavior of the
desired system. Kirchhoff’s laws are used to know the behavior of the
electronic circuit in terms of node voltages and branch circuits. The result of
integrodifferential equations is then solved in discrete- time. SPICE is a well-
known program for circuit simulation.
6. Physical Design: In this step, the actual layout of the desired system is
done, where all the components will be placed in the circuit and all these
components are interconnected. The actual layout of the desired system can
affect the area, correctness, and performance of the final desired product. The
correctness of the chip is also controlled by the physical design. A circuit
design that passes the test of a circuit simulator may be faulty after it has been
packaged. This is because of geometric design rule errors. These design rules
must be followed to ensure the correctness of the chip fabrication. Errors such
as short circuits, open circuits, open channels, etc may result if the design rules
are not respected.
7. Fabrication: After the actual layout and verification of the desired design,
the design is sent for manufacturing. The handoff of the desired design to the
manufacturing process is called tapeout. Generation of the data for
manufacturing is referred to as streaming out. The desired design is onto the
different layers of the design using the photolithographic process. ICs are
manufactured on round silicon wafers with a diameter from 200mm to 300mm,
these ICs are then tested and are marked as either functional or defective ICs.
8. Packaging and Testing: After fabrication of desired design, functional
chips are then packed. Packaging is configured early in the desired design
process and the application along with the cost and form factor requirements.
Packaged types may include Dual In-Line Packaged (DIPs), Pin Grid Array
(PGAs), and Ball Grid Arrays (BGAs). After a die is positioned in the package
cavity, its pins are connected to the pins of the package, e.g., with wire
 bonding or solider bumps (flip-chip). The package of the desired design is then
sealed and then sent to the end-users or clients.

Types of VLSI Design Flow

VLSI design flows can be broadly classified into different types based on the
design methodology and tools used:
 Top-Down Design Flow: Initiates from high-level system specification and
advances to venturing the design at more and more detailed phases namely:
architectural design/functional design and logic design.
 Bottom-Up Design Flow: Starting the highest level of the system and
breaking it down to the lower levels of the system.
 Iterative Design Flow: Stresses the progressive elaboration and repeated
cycle of activities in each phase and sub phase in the design of a system
with the view to enhancing the design and correcting any shortcoming
realized through the simulation exercise and testing.
 Design for Testability (DFT) Flow: It contains provisions that would
make it possible to test the IC to check for faults with the view of
ascertaining its reliability.

In Very Large Scale Integrated (VLSI) design, the critical path is the longest
path in a circuit that limits the clock speed, and worst-case timing analysis is a
verification method that helps identify and address timing issues:

 Critical path
The critical path is the path between an input and an output with the maximum
delay. It's the longest path in a circuit and limits the clock speed.

 Worst-case timing analysis

This analysis is a key part of the design and optimization process, and is used
to determine if a chip can be released for fabrication.

The design hierarchy of VLSI (Very Large Scale Integration) is a process that
breaks down complex systems into smaller blocks for easier design and
verification. The design hierarchy is based on the principle of "divide and
conquer", which involves dividing a task into smaller tasks until it reaches its
simplest level.
 The design hierarchy for VLSI can be divided into six categories:
 System specifications: The first step in the design hierarchy
 Abstract high-level model: Provides details on how each block behaves and
interacts with other blocks
 Logic synthesis: A step in the design hierarchy
 Circuit designs: Involves the use of transistors as switches and Boolean
variables as changing voltage signals
 Manufacturing: The final phase, where the finished design is transferred to the
production line

The layers of abstraction in VLSI design are:

 Physical level: Uses rectangles and design rules
 Circuit level: Uses transistors, R and C, and analog voltage/current values
 Logic level: Uses Boolean logic gates and binary valued logic
 Register transfer level: Uses adders, datapaths, and binary valued words
 Functional level: Uses processors, programs, and data structures

The abstraction level increases from the inner to the outer circle in a Y chart
that defines the hierarchical levels in the design process.

Integration density is a key feature of Very Large Scale Integration (VLSI)

design, which is the process of packing a large number of transistors onto a
single chip:
 Definition
Integration density refers to the high number of transistors that can be packed
into a small area on a semiconductor chip.

 Applications
VLSI technology is used in many applications, including digital signal
processors, memory devices, and microprocessors.

 Design principles
VLSI design principles include abstraction, hierarchy, and Moore's Law.

 Fabrication processes
VLSI chips are typically made using semiconductor manufacturing processes
like CMOS (Complementary Metal-Oxide-Semiconductor) technology.

 Design hierarchy
VLSI design uses a hierarchical approach, breaking down complex systems
into smaller functional blocks for easier design and verification.

Moore's Law is a prediction that the number of transistors on an integrated

circuit (IC) will double every two years, with a minimal increase in cost. The
law has been a guiding principle for the very large-scale integration (VLSI)
industry for decades

CMOS Logic Gate

Last Updated : 06 Jun, 2024
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The logic gates are the basic building blocks of all digital circuits and
computers. These logic gates are implemented using transistors called
MOSFETs. A MOSFET transistor is a voltage-controlled switch. The MOSFET
acts as a switch and turns on or off depending on whether the voltage on it is
either high or low. There are two types of MOSFETs: NMOS and PMOS. The
NMOS turns on when the voltage is high and off when the voltage is low. The
PMOS, on the other hand, turns on whenever the voltage is low and goes off as
the voltage goes high. When the two are used together to realize the logic gates,
they are called CMOS (Complementary MOS). The reason they are called
complementary is that NMOS and PMOS work in a complementary fashion.
When the NMOS switch turns on, the PMOS gets off, and vice-versa.
CMOS Inverter:
The CMOS inverter is shown below. It consists of a series connection of a
PMOS and an NMOS. VDD represents the voltage of logic 1, while the ground
represents logic 0. Whenever the input is high or 1, the NMOS is switched on
while the PMOS is turned off. Thus output Y is directly connected to the ground
and thus comes to be logic 0. When the input is logic 0, the reverse happens –
NMOS goes off and PMOS goes on. This provides a direct path between VDD
and output Y. Hence Y becomes high. This is the basic principle of operation of
a CMOS inverter.

From the above analysis, we can infer that for implementing any boolean
function using CMOS technology, we need to make a switching circuit with
PMOS switches in the upper block that turns on when its inputs are low, and
NMOS switches in the lower block that turns on when its inputs are high. The
two blocks must operate in a complementary sense. The upper block
consisting of only PMOS is called a pull-up network (PUN) because it pulls
up the output to VDD or logic high. The lower block consisting of NMOS is
called a pull-down network (PDN) because it pulls down the output to
ground or logic low. Any boolean function can be realized using PUN and
PDN.

Suppose we have Y = F(A, B, C, D). We have to obtain the PDN and PUN
blocks from this given boolean expression.
For getting the PDN block, we need to obtain Y’ in terms of non-
complementary variables A, B, C, and D. If we have AND in the expression of
Y’, then it means two NMOS in series to ground. If there is an OR, it means
two NMOS in parallel.
For the PUN, we need Y in terms of complemented variables A’, B’, C’, and
D’. Again here if we have AND in the expression of Y, we need two PMOS in
series, and an OR means two PMOS in parallel.

AOI Gate and OAI Gate:

AOI (and-or-invert) and OAI (or-and-invert) gates are two basic
configurations that can be realized using CMOS logic. The CMOS realization
of these two types of gates is shown below. Note that the two gates are dual to
each other. The PDN of the AOI gate is structurally similar to the OAI gate’s
PUN, and the AOI gate’s PUN is structurally similar to the PDN of the OAI
gate.
NAND Gate and NOR Gate:
NAND and NOR gates can be easily realized using CMOS logic as shown
below.

AND and OR gates are usually realized by using a NAND gate in series with a
NOT gate, or a NOR gate in series with a NOT gate.