Voltage Total Harmonic Distortion

The total harmonic voltage distortion (THDV) reached 9% for some Mots, disrupting
voltage waveform for other equipment.

From: Comprehensive Energy Systems, 2018

Related terms:

Power Quality, Impedance, Current Harmonic, Micro-Grids, Power Factor, Total

Harmonic Distortion, Electric Potential, Inverter

View all Topics

Passive and Active Filters

Stefanos N. Manias, in Power Electronics and Motor Drive Systems, 2017

11.2 Inverter Output Passive Filter Design

In most inverter specifications, the output voltage total harmonic distortion (THD%)
factor, under worst operating conditions, is given to be ≤5%. Examining the fre-
quency spectrum of two possible inverter output voltage waveforms shown in
Fig. 11.4, it is obvious that they contain unwanted harmonic components, which
must be reduced so that a THD ≤ 5% can be obtained. For this reason as is shown
in Fig. 11.5 a low pass LC filter is applied between the inverter output and the load.
From the output filter of Fig. 11.5, the following relation is obtained:
Figure 11.4. Various output voltage waveforms of a single-phase inverter.(a) Qua-
si square-wave waveform and respective frequency spectrum; (b) sinusoidal pulse
width modulation waveform and respective frequency spectrum.

Figure 11.5. Single-phase inverter with input and output filters.

(11.8)

where
vo = load voltage
vif = output filter input voltage
ZL = load impedance
o = inverter output voltage frequency.

Furthermore, Eq. (11.8) for the nth harmonic component can be rewritten as:

(11.9)

where

Examining Eq. (11.9), it is clear that by keeping the values of Lo and Co constant for
ZL,n = ∞ (i.e., there is no load), the ratio takes its maximum value and, consequently,
it is the worst operating condition from harmonic content point of view. Therefore,
setting ZL,n = ∞, Eq. (11.9) under worst operating condition becomes:

(11.10)

The frequency response characteristic of a low pass LC filter is shown in Fig. 11.6.

Figure 11.6. Frequency response characteristic of a low pass LC filter.

It has been shown that if the inverter output voltage dominant high harmonic com-
ponent d is reduced to 3% of the inverter output voltage fundamental component,
then a THD ≤ 5% is achieved under worst operating condition (i.e., operation without
load).

Example 11.2
The output voltage waveform of a single-phase inverter is the same as that of
Fig. 11.4(a). Design an output filter so that the THD factor, THDvo ≤ 5%. The inverter
input voltage is 220 V dc and the output voltage fundamental component frequency
is 50 Hz.
Solution
As shown in Fig. 11.4(a) the dominant harmonic component is the fifth with an
amplitude of:

To achieve a THDvo ≤ 5%, an output filter must be designed so that the dominant
harmonic component, which is the fifth, to be reduced to 30% of the fundamental
component (i.e., from 0.20 Vin to 0.03 Vin). Therefore, using Eq. (11.10) the following
results are obtained:

Selecting a filter capacitor Co = 30 μF, the output filter inductance is:

The output filter cut-off or break frequency is:

The figure given below shows the designed output filter.

Example 11.3
The output voltage waveform of a single-phase sinusoidal pulse width modulation
inverter is the same as that of Fig. 11.4(b). Design an output filter so that he THD
factor, THD ≤ 5%. The inverter input voltage is 220 V dc, and the output voltage
fundamental component frequency is 50 Hz. The frequency modulation factor is
mf = 7.

Solution
According to Fig. 11.4(b)

i) the order of the dominant harmonic component = 2mf − 3 = 11th and

ii) the amplitude of the dominant harmonic component is:

To achieve a THDvo ≤ 5%, an output filter must be designed so that the dominant
harmonic component, which is the 11th, has to be reduced to 30% of the funda-
mental component (i.e., from 0.21 Vin to 0.03 Vin). Therefore, using Eq. (11.10) the
following results are obtained:

Selecting an output filter capacitance of Co = 30 μF capacitance, the output filter

inductance is:

Therefore, the output filter cut-off frequency is:

From the above results one can observe that the value of the output filter when
compared to the previous example has been reduced almost to one-fourth.

> Read full chapter

Uninterruptible Power Supplies

Adel Nasiri Ph.D., in Power Electronics Handbook (Third Edition), 2011

24.5 Control Techniques

The main task of the control system in a UPS unit is to minimize the output voltage
total harmonic distortion in different loading profiles. In addition, it should provide
the proper mechanism to recharge the battery set and maintain high input power
factor and low total input current harmonic distortion. Other factors considered for
a good control technique are nearly zero steady-state inverter output voltage error,
good voltage regulation, robustness, fast transient response, and protection of the
inverter against overload under linear/non-linear loads.

The most common switching technique is Sinusoidal PWM. This method can be uti-
lized for both single-phase and three-phase systems. The advantage of this method
is low output voltage harmonic and robustness. This strategy uses a single feedback
loop to provide well-regulated output voltage with low THD. The feedback control
can be continuous or discontinuous. Analog techniques are used in continuous
approach. The sinusoidal PWM (SPWM) can be of natural sampling type, average
type, or instantaneous type [17, 18].

In natural sampling type, the peak value of the output voltage is detected and
compared with a reference voltage in order to obtain the error, which is used to
control the reference to the modulator. The average approach is basically the same;
but, the sensed voltage is converted to an average value and after that, is compared
with a reference signal. These approaches control only the amplitude of the output
voltage and are good only at high frequencies. In an instantaneous voltage feedback
SPWM control, the output voltage is continuously compared with the reference
signal improving the dynamic performance of the UPS inverter.

A typical block diagram of a three-phase DC/AC inverter for UPS systems and
SPWM switching control technique is shown in Fig. 24.13. The disadvantage of
this method is lack of flexibility for non-linear loads. Other programmed PWM
techniques such as selective harmonic elimination, minimum THD, minimum loss,
minimum current ripple, and reduced acoustic noise may be used for the inverter.

FIGURE 24.13. (a) Configuration of a three-phase DC/AC inverter for UPS systems
and (b) simple voltage controller using PWM technique.

Better performance even with non-linear and step-changing loads can be achieved
by multiple control loop strategies [19]. As shown in Fig. 24.14, there are two control
loops: an outer and an inner. The outer control loop uses the output voltage as a
feedback signal, which is compared with a reference signal. The error is compensated
by a Pi-integrator to achieve stable output voltage under steady-state operation. This
error is also used as a reference signal for the inner current regulator loop, which
uses the inductor or the capacitor output filter current as the feedback signal. The
minor current loop ensures fast dynamic responses enabling good performance with
non-linear or step-changing loads. The basic current regulators employed as minor
current loop are: hysteresis regulators, sinusoidal PWM regulator, and predictive
regulators. In a typical hysteresis regulator, the reference signal is compared with the
feedback signal. The sign and predetermined amplitude of the error determine the
output of the modulator. The duration between two successive levels is determined
by the slope of the reference signal. The output voltage tracks the reference signal
within the upper and lower boundary levels. This hysteresis control has fast transient
response; but, the switching frequency varies widely [20].

FIGURE 24.14. Typical current and voltage control loops for UPS inverter.

In SPWM control technique, the output voltage feedback is compared with a sine
reference signal and the error voltage is compensated by a PI-regulator to produce
the current reference. The current through the inductor or the capacitor is sensed
and compared with the reference signal. After being compensated by a PI-regulator,
the error signal is compared with a triangular waveform to generate SPWM signal
for switching control. The SPWM current control has a constant switching frequency
and also provides fast dynamic responses. In predictive current control method, the
switching instants are determined by suitable error boundaries. When the current
vector touches the boundary line, the next switching state vector is determined by
prediction and optimization in order to minimize the error. Predictive current con-
trol requires a good knowledge of the load parameters. All these current regulators
are typically used as an inner loop to regulate the current in the filter inductor. The
current reference for the current regulator is obtained by summing together the
error in an outer voltage loop with the actual load current to yield the rated output
voltage.

With the increase of speed and reliability of digital processors and a decrease in
their cost, digital processors have been facing an enormous growth of popularity in
control applications in the past few years. Many digital and discrete control tech-
niques such as dead-beat control [21], dissipativity-based control [22], sliding-mode
control [23], space vector-based control [24], and multiple-feedback loop [25] have
been developed using digital signal processors (DSP).

In this section, fundamental analysis of a dead-beat control method is explained for

the three-phase UPS configuration shown in Fig. 24.13a. The state space equations
of one phase of this system in the continuous time-domain are as follows.

(24.1)

(24.2)

Considering Va and iLF as state variables, the state space equation of the system is as
follows:
(24.3)

These continuous time-domain state space equations are converted to the discon-
tinuous time domain with a sampling period of Ts [26].

(24.4)

Where 0 is the angular resonance frequency of LF and CF. The sampling frequency
of the system is always considered much higher than the resonance frequency of LF
and CF. With this assumption, Eq. (24.4) is simplified to Eq. (24.5). This conversion
is valid for almost fs ≥ 20f0.

(24.5)

The current equation according to Eq. (24.5) is given by:

(24.6)

Alternatively, this equation can be achieved by converting Eq. (24.2) from a differ-
ential equation to a difference equation. The same suggestion of fs ≥ 20f0 has to be
made for this conversion as well. If Va and i*LF are considered constant over the next
switching period, the output voltage of the inverter, which corrects the error of iLF
after two sampling periods, is described by:

(24.7)

A linear estimation of Va(k+1) can be achieved from previous values:

(24.8)

By substituting Eqs. (24.8) and (24.10) in Eq. (24.9) and updating reference current
for iLF in every two sampling periods, the dead-beat digital control for series con-
verter is described by:

(24.9)

Equation (24.9) ensures that the current error between iLF and i*LF at time k + 2 goes
to zero with a delay of two sampling periods. Avoiding interaction between voltage
and current control loops, load voltage, Va, is sampled at half of the current sampling
frequency. The voltage equation according to Eq. (24.5) is as follows.

(24.10)

(24.11)
As current control is suggested to be dead-beat with a delay of two sampling periods,
capacitor current at time k and (k + 1) are given by:

(24.12)

Substituting Eq. (24.12) in Eq. (24.11) and updating the reference current at each of
the two sampling periods, Va(k + 2) is given by:

(24.13)

The current of i*CF at time k which corrects the voltage error of Va at time k + 4 is as
follows.

(24.14)

A block diagram of the implementation of voltage and current control of the inverter
is shown in Fig. 24.15. Block diagram of the current and voltage controller for the
inverter is also shown in Fig. 24.16. Voltage regulator is a pure dead-beat controller
with a delay of two sampling periods including the consumed time for calculation.
G1 is the time delay needed for calculations and analog to digital conversions. G2 is
the time delay caused by the PWM inverter and G3 is the transfer function of the low
pass filter. Current regulator is also considered as a pure delay. The output voltage
of the inverter follows its reference with four sampling periods of delay. In practice,
the dynamics of the current regulator is not a pure delay and shows some deviation
from the dead-beat controller.

FIGURE 24.15. Implementation of the current and voltage control for the inverter
shown in Figure 24.13a.

FIGURE 24.16. Block diagram of the current and voltage controller for the inverter
shown in Figure 24.13a.

> Read full chapter

Application cases of industrial park mi-
crogrids' protection and control
Dehua Zheng, ... Jun Yue, in Microgrid Protection and Control, 2021

11.3.5.4 Seamless switching between grid-connected and is-

land modes
Seamless switching was undertaken to demonstrate the performance of the tran-
sient and dynamic control strategies. Firstly, the microgrid was switched to island
mode. The voltage, current, and power quality of the microgrid before switching to
island mode are shown in Table 11.12.

Table 11.12. Voltage, current, and power quality of grid-connected mode.

Testing point Parameters Phase A Phase B Phase C

Upper terminal of Voltage (V) 229.34 230.32 230.68
islanding switch
CB10
Current (A) 50.4 70.5 68.2
Voltage THD (%) 2.57 2.57 2.63
Active power (W) 5000.00 6000.00 9500.00
Reactive power (Var) 9500.00 14,500.00 12,000.00
Apparent power (VA) 11,500.00 16,500.00 15,500.00
System frequency (Hz) 50.02
Lower terminal of Voltage (V) 229.46 230.36 230.74
islanding switch
CB10
Current (A) 50.92 70.38 68.23
Voltage THD (%) 2.57 2.54 2.65
Active power (W) 5000.00 6000.00 9000.00
Reactive power (Var) 9500.00 14,500.00 12,000.00
Apparent power (VA) 11,500.00 16,000.00 15,500.00
System frequency (Hz) 50.02

Then, all PV generation power, ESS power, and load power at the lower terminal of
the switch CB10 were imposed to imbalance (convenient for unintentional seamless
switching). In this state, the islanding main breaker CB10 was tripped off, and the
microgrid was operating in the island mode. At the switching moment, the transient
disturbance control system detects the power imbalance of the island operation
system, and starts the supercapacitor battery instantly to balance the power in the
island microgrid. Due to its fast-discharging rate, the supercapacitor cannot support
the power balance of the system for a long time, but is suitable for a transient
disturbance support. Hence, the transient disturbance control system did quickly
adjust the power balance among PV generation, ESS, and loads. The voltage and
current power quality in the island mode of operation is as in Table 11.13.

Table 11.13. Voltage, current, and power quality of island mode.

Testing point Parameters Phase A Phase B Phase C

Upper terminal of Voltage (V) 229.74 231.17 231.26
islanding switch
CB10
Current (A) 0 0 0
Voltage THD (%) 2.63 2.57 2.54
System frequency (Hz) 50.05
Lower terminal of Voltage (V) 229.47 229.31 229.59
islanding switch
CB10
Current (A) 0 0 0
Voltage THD (%) 1.47 1.35 1.54
System frequency (Hz) 49.97

Comparing the grid-connected and island modes of operation of the microgrid, the
highest power quality voltage THD of 1.51 can be seen in island mode operation,
while the minimum voltage THD of 2.56 for grid-connected mode was recorded.

As illustrated in the real-time curve of the voltage of Fig. 11.14, the results show
that the power quality of the island microgrid system is better than that of power
grid due to the implementation of microgrid transient disturbance control systems
under the condition of seamless switching from grid-connected to island mode.

Figure 11.14. Waveforms of voltage with the implementation of transient distur-

bance control strategy under seamless switching from grid-connected to island
mode.

It can be seen from the real-time curve that there is no voltage sag in the seamless
switching process. The switching process only takes 60 ms to complete. There is
no equipment shutdown and power interruption during the switching process. The
system verifies unplanned seamless switching.
The test of switching from island to grid connection was also carried out on the above
setup. While the system started to operate in the island mode, the grid-connected
circuit breaker CB10 was closed. At the moment of closing the circuit breaker CB10,
the transient disturbance control system detected the closing command of the
islanding circuit breaker, and quickly adjusted the converter side of the equipment
in the closed-loop control system so that the island power system can complete
the synchronization task in a very short time. When the difference between the
amplitude, phase, and frequency of the island voltage and the amplitude, phase,
and frequency of the grid voltage reaches the synchronization standard, closing
of the breaker was carried out. The voltage, current, and power quality before the
synchronization of unplanned island to grid connection are shown in Table 11.14.

Table 11.14. Voltage, current, and power quality before unintentional island transfer
to grid connection.

Testing point Parameters Phase A Phase B Phase C

Upper terminal of Voltage (V) 229.79 230.5 230.61
islanding switch
CB10
Current (A) 0 0 0
Voltage THD (%) 1.72 1.69 1.63
System frequency (Hz) 50.02
Lower terminal of Voltage (V) 229.66 229.46 229.88
islanding switch
CB10
Current (A) 0 0 0
Voltage THD (%) 1.48 1.37 1.54
System frequency (Hz) 50.02

The voltage, current, and power quality curve after unintentional island mode to grid
connection is described in Table 11.15.

Table 11.15. Voltage, current, and power quality after unintentional island transfer
to grid connection.

Testing point Parameters Phase A Phase B Phase C

Upper terminal of Voltage (V) 229.14 229.66 229.79
islanding switch
CB10
Current (A) 48.82 69.90 68.03
Voltage THD (%) 1.65 1.64 1.65
Active power (W) 5000.00 5000.00 9500.00
Reactive power (Var) 9000.00 15,000.00 12,000.00
Apparent power (VA) 11,000.00 16,000.00 15,500.00
System frequency (Hz) 50.02
Lower terminal of Voltage (V) 229.29 229.78 230.00
islanding switch
CB10
Current (A) 48.90 69.50 67.90
Voltage THD (%) 1.67 1.65 1.67
Active power (W) 5000.00 5000.00 9500.00
Reactive power (Var) 11,000.00 16,000.00 15,500.00
Apparent power (VA) 9000.00 14,500.00 12,000.00
System frequency (Hz) 50.03

It can be seen from the power quality (Table 11.15) that the voltage THD of the
power grid-connected mode of operation of the microgrid is 1.67% before the
unplanned island to grid connection, while voltage THD in island mode is 1.37%.
After successful seamless switching, the system was in the grid-connected mode,
and the power quality of voltage THD recorded is 1.67%. The results show the
capability of the transient disturbance control system in the islanding state of the
microgrid, and the power quality is better than that of the grid-connected one.

In Fig. 11.15, the period before 03.52.068 was the synchronization process between
the grid voltage and the island microgrid carried out. At 03.52.068 the transient
disturbance system sent the closing instruction to the main breaker CB10, and
the island microgrid system was successfully closed. As shown on the curves from
the figure, the amplitude, phase, and frequency of the island microgrid voltage
are almost the same as that after the synchronization was adjustment made. There
was no equipment failure during the closing process, which realizes the seamless
unplanned switching from island to grid-connected mode.

Figure 11.15. Voltage waveform during switching from island to grid-connected

mode.

> Read full chapter

Fault analysis
Gevork B. Gharehpetian, ... Masoud M. Shabestary, in Microgrids and Methods of
Analysis, 2021

5 Simulation results
Before presenting the simulation results, it must be mentioned that in previous re-
searches, the following problems and limitations have been seen for current-limiting
methods.

In the case of using STRF or SYRF in a four-wire configuration, and also in the case
of using all the reference frames in a three-wire configuration, they cannot control
the voltage in healthy phases.

In using NARF in a three-wire configuration, the voltage and current power quality
are so poor.

In the case of using STRF or SYRF during an SLG fault, overvoltage can occur.

The first and third challenges have been addressed in the control system presented
in Refs. [3,28]. But they have not been discussed in Refs. [27,29–31], for DVC-based
controllers because there is no study on their robustness versus large-signal distur-
bances and balanced and unbalanced faults. In this study, there is no concern about
power quality because the NARF is not applied to hierarchical droop-controlled and
DVC IIDERs. Using the internal loop presented in Section 2.3, the current and
voltage controllers adjust the fundamentals and harmonics and can well operate
under an unbalanced current [2,3,28]. The DVC DER has not any problem with
stability and voltage control. Still, the capability of the DVC method for power quality
improvement has not exactly been discussed [27,29–31]. One possible solution
for DVC-based methods under unbalanced load conditions is applying a robust
controller in positive- and negative-sequence current controllers [46]. Improving
DVC DERs under unbalanced and nonlinear loads can be an investigation topic for
researchers.

5.1 Performance evaluation of the proposed strategy

To study the suggested strategy applied to islanded MG, the model and equivalent
circuits proposed and discussed in Section 4.4 are used in this section. The four-wire
and three-wire configurations under various balanced and unbalanced faults will be
investigated. The fault is simulated at t = 0.2 s and cleared at t = 0.3 s. The fault
resistance is 1.2 Ω. Table 4.1 summarizes the simulation results, including current
and voltage total harmonic distortion (THD) and their peaks. The suggested strategy
leads to the best current-limiting effect and better condition for current and voltage
THD compared with the current limiting strategies of ISL [19] and LL [15].
Table 4.1. Proposed current-limiting strategy compared with ISL [19] and LL [15]
strategies.

Topology SC fault type Voltage THD Current THD Peak of out- Peak of output
(%) (%) put current voltage (p.u.)
(p.u.)
ISL LL Pro- ISL LL Pro- ISL LL Pro- ISL LL Pro-
strate- strate- posed strategy
strate- strate- posed strategy
strate- strate- posed strategy
strate- strate- posed
gy [19] gy gy gy gy gy gy gy strate-
[15] [19] [15] [19] [15] [19] [15] gy

Three-wire
a-g 57.2 26.5 22.6 57.2 26.5 22.6 1.68 1.35 0.6 1.36 1.18 1
a-b-g 23.4 1.45 9.8 23.3 1.45 9.8 2 2 1.67 1 0.97 1
a-b 26.4 0.95 1.2 25.2 1.3 1.15 2 2 2 0.98 0.97 0.8
a-b-c-g 14.1 0.06 0.32 14.1 0.06 0.32 2 2 2 0.16 0.16 0.14
Four-wire
a-g 20.7 0.27 0.91 20.7 0.27 0.91 2 2 2 1 1 1
a-b-g 21 0.27 1.02 20.9 0.27 1.02 2 2 2 1 1 1
a-b 34.2 0.37 0.71 19.2 0.37 0.6 2 2 2 1 1 1
a-b-c-g 20.9 0.13 1.02 20.8 0.13 1.02 2 2 2 0.16 0.16 0.14
Three-wire
a-g 0.54 0.36 0.5 0.54 0.36 0.5 1.65 1.41 1.52 1.59 1.54 1.57
a-b-g 24.7 0.56 1.42 24.8 0.56 1.42 2.58 2 1.92 0.91 2.32 1
a-b 17.2 0.58 0.52 25.1 0.63 1.12 2.6 2 1.92 0.64 1.84 0.74
a-b-c-g 0.42 0.18 0.19 0.42 0.18 0.19 2 2 2 0.16 0.16 0.16
Four-wire
a-g 17.7 0.53 0.42 17.7 0.53 0.42 3.77 2 2 0.98 1.84 0.82
a-b-g 26.2 0.41 0.4 26.2 0.41 0.4 3.77 2 2 0.82 1.85 0.83
a-b 25.4 0.42 0.41 33 0.42 1.02 2.76 2 2 0.86 1.84 0.82
a-b-c-g 0.23 0.26 0.22 0.23 0.26 0.22 2 2 2 0.16 0.16 0.14

ISL, instantaneous saturation limit; LL, latched limit; THD, total harmonic distortion.

5.2 Fault studies on islanded inverter-interfaced distributed energy re-

sources in various reference frames
The studies are conducted in the MATLAB environment for IIDERs in three-wire
and four-wire configurations.Fig. 4.4A–C presents the simulation results for the
following faults:
Figure 4.4. The voltage of output, inductance current, current of output, and limited
inductance current, respectively, for faults (A) SLG (a–g) for four-wire configuration
(controller in NARF), (B) phase-to-phase (a–b) three-wire configuration (controller in
SYRF), and (C) phase-to-phase to ground (a-b-g) four-wire configuration (controller
in STRF). NARF, natural reference frame; SLG, single-line/phase to ground; STRF,
stationary reference frame; SYRF, synchronous reference frame.

• SLG: (a-g) for four-wire configuration including a controller developed in

NARF,
• Phase-to-Phase: (a-b) for 3-wire configuration including a controller devel-
oped in SYRF and,
• Phase-to-Phase to ground: (a-b-g) for 4-wire configuration including a con-
troller in STRF.

The voltage of the output, inductance current, current of output, and limited in-
ductance current can respectively be seen in each case of these figures. Considering
these figures, it can be said that the result of the application of the suggested current
limiting strategy is faulted current reduction, voltage (power) quality improvement,
and FRT capability enhancement.

5.3 Droop- and directly voltage-controlled–based methods performance

comparison versus dynamic loads
A three-phase 132-kW, 4-pole, 400-V, 50-Hz induction motor (IM) is modeled and
simulated at bus 2. Its parameters can be found in Ref. [27]. It has a Direct Online
(DOL) starting method, and it starts at t = 0.8 s under nominal load in the islanded
MG. The simulation results, including bus voltages and active and reactive powers,
are respectively, presented in Fig. 4.5A–C for the following cases.
Figure 4.5. (A) Voltage, (B) active power and, (C) reactive power variations due to
IM starting, respectively, using droop method controller [3,28], suggested solution
including current-limiting and DVC method controller [27]. DVC, directly volt-
age-controlled; IM, induction motor.

• Hierarchical droop-based control [3,28]

• Suggested hierarchical control system with the current limiting strategy

• DVC-based control system [27]

The strategy used for current limiting can reduce IM starting transients. In Fig. 4.5A,
it can be observed that after a temporary voltage drop, it is recovered to the rated
level. As shown in Fig. 4.5B–C, variations of powers have been reduced. Also, their
steady-state error is equal to zero.

It must be said that the hierarchical droop-based control [3,28], which includes the
stabilizing supplementary control loop, has a superior accomplishment compared
with the conventional droop-based controllers [22,23]. As a result, the conventional
droop-based controllers have not been compared with droop and DVC controllers
[3,28] discussed in Sections 2 and 4.2.

> Read full chapter

Optimal Placement and Sizing of Shunt

Capacitor Banks in the Presence of Har-
monics
Mohammad A.S. Masoum, Ewald F. Fuchs, in Power Quality in Power Systems and
Electrical Machines (Second Edition), 2015

Suitability of THDv (STHD)

For a given chromosome, define the average unacceptable value of THDv as

(10-17)

where NTHD is the number of buses with high total voltage harmonic distortions (e.g.,
THDj > THDvmax). The following steps are performed to compute STHD:

• Fuzzification of THDavghigh and NTHD (based on membership functions of Fig.

10.12a and 10.12b, respectively) to compute the corresponding membership
values (μTHD and μNTHD).Figure 10.12. Membership functions for (a) the average
of unacceptable (high) THDv values (Eq. 10-17), (b) number of buses with
unacceptable THDv or voltage, where “avg” means average.
• Fuzzy inferencing and defuzzification based on the decision matrix of Table
10.5, the membership function of Fig. 10.13, Mamdani max-prod implica-
tion, and center average methods [50]:(10-18)Table 10.5. Decision Matrix for
Determining Suitability of THDv (and V)THDv (or |V|)ANDLowMediumHighNTHD
(or NΔ|V|)LowHighMediumMediumMediumMediumLowLowHighMediumLow-
LowFigure 10.13. Membership functions for suitability of THDv, V, and cost.

> Read full chapter

Control Strategies of Shunt Active Pow-

er Filter
Shailendra Jain, in Modeling and Control of Power Electronics Converter System for
Power Quality Improvements, 2018

2.3.5 Frequency domain control

In frequency domain, control algorithm proposed by Jain et al. [52,53], characterized
as the “compensation of customer-generated harmonics,” for the control of SAPF.
It compensates harmonics and reactive power requirement of nonlinear loads, and
maintains similar distortion in the compensated current as present in the mains
voltage.

Therefore load behaves as a linear/resistive load, and the resultant source current will
have the same waveform as that of the supply voltage. By maintaining similar wave-
forms of the voltage and currents reactive power can be completely compensated,
and unity power factor (UPF) operation can be achieved. UPF operation also provides
more effective reduction of voltage THD at the network bus and lower harmonic
losses [54,55]. This scheme provides following additional features:

• It is capable to achieve only harmonic compensation in addition to the com-

pensation of both harmonics and reactive power simultaneously.
• It is capable to maintain similar distortion level in the source current as present
in the mains voltage, thereby attributing the responsibility of the customer and
utility at the point of common coupling (PCC).
• It works effectively under ideal mains condition as compared to other algo-
rithms.
• Also, unlike [7] it is applicable to the single-phase systems as well.

2.3.5.1 Mathematical expressions

Any nonsinusoidal signal can be expressed as a sum of sinusoidal signals of various
frequencies. Based on this the utility voltage and current can be expressed as:

(2.17)

(2.18)

where

vs(t), iL(t) are the instantaneous source voltage and load current,
Vn, In are the amplitudes (peak) of the nth order voltage and current,
n, n are the phase difference of nth order frequency component of voltage
and current, and
n is the order of harmonics.

The reference current drawn from the source should be the portion of the current,
which retains the same level of distortion as present in the voltage, at the same time
account for the entire fundamental frequency component. The reference current
should have the same graphical pattern of variation as of the voltage. It might have a
time leg/lead, or may be in phase with the voltage, depending on only harmonics, or
both harmonics and reactive power compensation capability. Thus the fundamental
frequency component of the reference current will be equal to the fundamental
frequency component of the load current I1 (plus loss component, ILoss) for harmonic
compensation, and I1 cos 1 (plus loss component) for both harmonic and reactive
power compensation. All other frequency components will be in the same proportion
as their counterparts in the voltage, which can be mathematically expressed as:

For harmonic compensation

(2.19)

For both harmonic and reactive power compensation

(2.20)

where is the instantaneous value of the estimated reference current.

Complete schematic diagram of the proposed control scheme along with Simulink
model of controller is shown in Fig. 2.31. A thyristor converter with R-L element
on its DC side is used as nonlinear load, and a voltage source PWM converter with
a DC-link capacitor is used as an APF. The source voltages and load currents of
two phases are measured and their harmonic components are computed. Using
fundamental load current (I1), fundamental voltage (V1), harmonic components of
voltage (V3, V5,…), and their respective angles ( 1, 1, 3, 5,…), reference currents
are obtained (for two phases) as per Eq. (2.19) or (2.20), based on the desired
compensation. Third reference current is obtained by a using a negative adding
circuit (in three-phase, three-wire system). DC-link voltage is regulated to obtain
the loss component and added with the fundamental component of load current.
Estimated reference currents and the actual source currents are then processed in
hysteresis controller, to obtain the switching signals. Simulink model for obtaining
different frequency components of voltage and currents, and obtaining the reference
current are given in Fig 2.32(A)–(C).
Figure 2.31. (A) Control scheme in frequency domain. (B) Simulink model of con-
troller.Simulation model: active_filter_frequency_domain.slx, R2014b
Figure 2.32. Simulation model for obtaining different frequency components of
voltage and current for (A) only harmonic compensation, (B) both harmonic and
reactive power compensation, and (C) simulation model for obtaining reference
current.

Fig. 2.33 shows the simulation results for only harmonic compensation case in
steady state. Three-phase compensated source currents with their respective source
voltages are shown in this figure. It is observed that, APF allows similar level of
distortion in the compensated source current as present in the source voltage. The
shape of the source voltages and currents are same (THD: Vsa—9.23%, Isa—9.3%)
but they are not in phase, hence no reactive power is compensated. Table 2.2 shows
various power components after compensation, from which it is clear that no reactive
power is compensated. Therefore capacity of APF installed is reduced as compared
to both harmonics and reactive power compensation case.

Figure 2.33. Three-phase source currents with their respective source voltages (only
harmonic compensation under distorted mains).

Table 2.2. Power components after compensation (phase “A”) (only harmonic com-
pensation with distorted mains)

Power component Load Source APF

Active power, P 2477.9 2544.2 72.83

Reactive power, Q 1804.0 1847.5 50.97

VA rating 3109.6 3183.2 952.2

Fundamental power 2433.9 2571.6 144.2
Harmonic power 43.98 −27.37 −71.36

Fig. 2.34 shows the waveforms for three-phase compensated source currents with
their respective source voltages under distorted mains, in steady state for the
compensation of both harmonics and reactive power simultaneously. It is observed
from the simulation results that, after compensation shape of the source voltages
and currents are same, and they are in phase with each other, so that reactive power is
fully compensated and UPF operation can be achieved, even under distorted mains.
Figure 2.34. Three-phase source currents with their respective source voltages (Both
harmonics and reactive power compensation under distorted mains).

Table 2.3 shows various power components after compensation. It is observed that
reactive power is completely compensated. At the same time, APF allows similar level
of harmonics in the compensated source currents as present in the source voltages
(THD: Vsa—9.23%, Isa—9.29%). Due to distorted mains, load current becomes
unbalanced.

Table 2.3. Power components (phase “A”) (both harmonic and reactive power com-
pensation with distorted mains)

Power component Load Source APF

Active power, P 2477.9 2990.6 512.7

Reactive power, Q 1804.0 −0.15 −1805.0

VA rating 3109.6 2980.8 1959.6

Fundamental power 2433.9 2964.3 530.4
Harmonic power 43.98 26.26 −17.72

Generally, it is desired to maintain source current sinusoidal irrespective of the

distortion present in the mains voltage. This algorithm is capable to maintain
compensated source currents sinusoidal even if the source voltages are distorted.
Fig. 2.35 shows the three compensated source currents with their respective source
voltages. It is observed that compensated source currents are sinusoidal irrespective
of the distorted mains, but displaced by an angle 1 with their respective source
voltages. Therefore only harmonics are compensated.
Figure 2.35. Three-phase source currents with their respective source voltages to
maintain sinusoidal source current under distorted mains (only harmonic compen-
sation).

Fig. 2.36 shows the three compensated source currents with their respective source
voltages in steady state for both harmonics and reactive power compensation. Com-
pensated source currents are observed sinusoidal and in phase with the respective
fundamental source voltages. After compensation THD of the source current is
reduced well below 5% limit, but reactive power is not completely compensated due
to waveform difference.

Figure 2.36. Three-phase source currents with their respective source voltages to
maintain sinusoidal source current under distorted mains (both harmonics and
reactive power compensation).

Hence, this algorithm is also capable to maintain the compensated source current
sinusoidal, in addition to maintaining similar shape and distortion (as of the voltage)
under distorted mains.

> Read full chapter

Modeling of a high-performance
three-phase voltage-source boost in-
verter with the implementation of
closed-loop control
P. Arvind, ... P.R. Thakura, in Renewable Energy Systems, 2021

10.4 Results and discussions

Fig. 10.13 shows the output waveform in the open-loop control mode of operation
at a duty cycle of 0.5. The input voltage is taken to be 150 V. The peak AC voltage is
seen to be around 600 V that is nearly four times that of the input DC voltage. It is
also seen that the voltage waveform is purely sinusoidal.

Figure 10.13. Open-loop waveforms: input voltage (top), open-loop output voltage
waveform (middle), and output current (bottom).

The output current is shown in Fig. 10.13C, which assumes a peak value of 3.5 A. It
is also seen that the output current is seen to be purely sinusoidal.

The THD plot for voltage and current is shown in Fig. 10.14. The voltage THD is
0.8% while the current THD is 2.9%, which is within the accepted range as per the
guidelines of IEEE Standard 519-2014.
Figure 10.14. Open-loop voltage and current THD plots.

Fig. 10.15 shows the closed-loop output voltage waveform. The peak value of the
output voltage waveform is seen to be four times the input voltage (for the same
value of DC voltage as taken in the previous case).

Figure 10.15. Closed-loop output voltage waveform.

Fig. 10.16 shows the closed-loop output current waveform. Slight variations could
be seen in the amplitude. Ths is due to the fact that the voltage controller tries to
maintain the output voltage constand by making a trade-off with current and power.
Figure 10.16. Closed-loop output current waveform.

The THD plots obtained for the output voltage and current are shown in Fig. 10.17.
Here the voltage THD is slightly reduced and attains the value of 0.79%, and the
current THD is 2.28%. The dominant harmonics are mostly the 3rd, 5th, and 13th
components. However, their effect on the sinusoidal waveform is quite minuscule.

Figure 10.17. Closed-loop voltage and current THD plot.

Fig. 10.18 shows the bode plots obtained for each transfer functions (as discussed
in Section 2.4).
Figure 10.18. Bode plots for the obtained transfer function.

According to the first transfer function mentioned above, it can be inferred that the
value of gain margin is −19.0 dB, which is considered as the positive gain margin
when phase cross over frequency is at −180 degrees and the value of phase margin is
−1 degree when gain cross over frequency is at 0-dB line. Hence, it can be concluded
that the transfer function is stable condition.

In the second transfer function and the third transfer function, it can be deduced that
the value of gain margin of both of the transfer function is infinity as phase cross
over frequency is at −180 degrees and the value of phase margin is −180 degrees
when gain cross over frequency is 0 dB. Therefore the transfer function derived is
unstable condition.

From the fouth transfer function, it can be deducted that the value of gain margin
is +40 dB when phase cross over frequency is at the position of −180 degrees and
the value of phase margin is 0 degrees when gain cross over frequency is 0 dB. As a
result, it can be concluded that the transfer function is conditionally stable condition.

Considering the fifth transfer function, it can be deducted that the calculated value
of gain margin having −19.1 dB when phase cross over frequency positioned at −180
degrees and the calculated value of phase margin which is equal to −180 degrees
when gain cross over frequency is positioned at 0 dB. Therefore transfer function is
stable condition.

From the sixth transfer function, the seventh transfer function, and the eighth
transfer function, it can be inferred that the calculated value of these transfer
functions of gain margin is +30 dB when phase cross over frequency just crossing at
−180 degrees and the calculated-phase margin of these transfer functions equals to
−2 degrees when gain cross over frequency positioned at 0 dB, which have resulted
in stable condition.

While in the ninth transfer function, it can be inferred that that the calculated value
of gain margin having −19 dB when phase cross over frequency is at −180 degrees
and the calculated value calculated −2 degree phase margin where gain cross over
frequency crosses at −180 dB. Therefore the obtained transfer function is stable at
large.

> Read full chapter

Lifetime Reduction of Transformers

and Induction Machines
Mohammad A.S. Masoum, Ewald F. Fuchs, in Power Quality in Power Systems and
Electrical Machines (Second Edition), 2015

6.11 Probabilistic and time-varying nature of harmonics

As mentioned in Section 6.1, the harmonic current or voltage spectra within a
distribution feeder are continually changing as a function of changes in the load
and the system’s condition. The rationale given for using the worst-case conditions,
where loads are operating for at least a few hours at rated operation generating the
“rated current/voltage spectra,” is the basis for the IEEE [35] and IEC [36] harmonic
guidelines and standards, respectively. Nevertheless it will be worthwhile to study the
time-varying nature [37,38] of harmonic spectra. In these publications continually
changing current (THDi) and voltage (THDv) total harmonic distortions are plotted as
a function of time. They indeed change widely from 2.5% to about 9% for THDi, and
from 1% to about 5% for the THDv for one site, and for another site the changes are
similar in magnitude. As mentioned in prior sections, the THDs are neither a good
measure for temperature rises nor for vibrations; instead harmonic components
should be used in any further studies. The measured THD data are characterized by
statistical measures (e.g., minimum, maximum, average or mean values, standard
deviation, probability distribution), histograms or probability density functions (pdf ),
probability distribution functions (PX(x)), statistical description of sub-time intervals,
and combined deterministic or statistical description [41–45]. These publications
address the harmonic summation and propagation by explaining the sum of random
harmonic phasors via the representation of harmonic phasors, marginal pdf of
x–y components, pdf of sum of projections of independent phasors, and pdf of
magnitude of sum of random phasors. These papers apply the methods described
to a 14-bus transmission system and provide general guidelines with respect to
their applicability. The probabilistic evaluation of the economic cost due to harmonic
losses in industrial energy systems is presented in the next section.

> Read full chapter

Power Quality and Adjustable Speed

Drives
STEFFANHANSEN , PETERNIELSEN , in Control in Power Electronics, 2002

12.4.2 Phase Multiplication

In applications with multiple converters, a solution combining several separated
standard 6-pulse diode rectifiers, the so-called quasi 12-pulse topology, can be
interesting. The quasi 12-pulse topology is well known. However, the topology has
the reputation of being sensitive to uneven load distribution and variations. The
reason for this may be that the quasi 12-pulse rectifier is not very well documented
in the literature and very few papers have exploited the possibilities of thisvery simple
scheme [15]. In this section the harmonic performance of the quasi 12-pulse rectifier
scheme is discussed by using the following example.

On a 1 MVA 10/0.4 kV supply transformer (ex= 5% and er= 1%) two 100 kW (input
power) ASDs are connected with a standard 6-pulse diode rectifier. Rectifier 1 and
rectifier 2 have a built-in dc-link inductance of 3%. Without any further measures,
the total harmonic current distortion THDi= 38% and the total harmonic voltage
distortion THDV = 3.6% measured at the secondary side of the supply transformer.
To reduce the harmonic distortion, rectifier 2 is phase shifted by 30° as shown in Fig.
12.20.
FIGURE 12.20. Quasi 12-pulse scheme with a 30° phase-shifting transformer.

Figure 12.21 shows the system current (isa) and the corresponding Fourier spectrum
when both rectifiers are fully loaded; the THDi = 10.5%. Figure 12.22 shows the
current THDi as a function of the load of both converter groups. As shown in Fig.
12.22 the current THDi is less than 20%) in the main operating area, namely between
40% and 100% of both converter groups. A THDi of close to 10% is achieved in the
operating area between 60% and 100%.
FIGURE 12.21. Quasi 12-pulse scheme. (a) Simulated system current, isa. (b) Fourier
spectrum of isa. Both rectifier 1 and rectifier 2 are fully loaded.
FIGURE 12.22. Contour plot of the current THDi as a function of the load of both
rectifiers in a quasi 12-pulse scheme.

Intuitively, one would assume that both the voltage and current THD are smallest
when both transformers are equally loaded. But Fig. 12.23 shows that this is not
necessarily true. The current THDi is smallest when both converter groups are fully
loaded, whereas the lowest voltage THDV is achieved at low load. The maximum
voltage distortion is achieved when either both converter groups are fully loaded or
only one converter group is fully loaded and the other converter group is unloaded.
It should be noted that the maximum voltage distortion is cut by almost a factor
of 2 compared with the voltage distortion obtained without the phase shifting
transformer (THDV = 3.6%).

FIGURE 12.23. Contour plot of the voltage THDV as a function of the load of both
rectifiers in a quasi 12-pulse scheme.

As shown, the quasi 12-pulse has an excellent performance even under wide load
variations. The reason for this is that the harmonic currents of the three-phase diode
rectifier are almost constant in the CCM as shown in [15].

> Read full chapter

Transient control of microgrids
Dehua Zheng, ... Jun Yue, in Microgrid Protection and Control, 2021

8.3.2.2 Energy storage system

For the case of loss of DGs or rapid increase of unscheduled loads, an energy
storage system control strategy can be implemented in the microgrid network. Such
a control strategy will provide a spinning reserve for energy sources which can very
quickly respond to the transient disturbances by adjusting the imbalance of the
power in the microgrid network.

Batteries, pumped hydro, compressed air energy storage, flywheel, and supercapac-
itor are some of the energy storage systems featuring in the microgrids. Energy
storage systems are a necessity for the stable operation of isolated microgrids
or island mode of nonisolated microgrids. The electrical energy storage units are
the most commonly utilized strategies in the microgrids. The electrical storage
systems (ESSs) may be suited to either of the energy intensive or power-intensive
applications based on their response rate and storage capacity. These ESSs can serve
as controllable AC voltage sources to ensure voltage and frequency stability in the
microgrids.

Power-intensive ESS shall be used to smooth the disturbances. If the disturbance is

caused by a fault, the total harmonic distortion (THD) values of the branch currents
and bus voltages are changed rapidly. The fault point should be isolated and the right
breaker should be tripped. If there is no fault, the current and voltage THD values
should return to the normal value, and hence no breakers are tripped. Transient
controls against transient disturbances play a key role in the microgrid operational
reliability. Since the fly wheel and supercapacitor have higher power density than
other ESSs, they are very suitable for transient disturbance control of the microgrids.
Testing and verification of the application of a supercapacitor for the transient
disturbance control system in the microgrid is included in this chapter. Such a
transient disturbance control system based on a single energy storage system with
no communication network is proven to be an economic and reliable solution for
voltage and frequency control in the transient disturbances.

Large changes in the current and voltage waveforms due to the switching of
large-generating units, unplanned mode switching, and fault clearance are how
severe transient disturbances are manifested in microgrids. The complexity and
diversity of the internal load of the network increase the degree of fluctuations
in the network due to load-side changes. The transient disturbance control of the
microgrid can be applied widely in large-scale distributed energy systems. Such
 a control system discussed in this book can realize smooth mode transfer during
unplanned switching from grid-connected mode to island mode and vice versa. The
switching between the two modes should be performed with the grid-connection
requirements fully obeyed. As discussed earlier, power-intensive type ESS, such
as supercapacitor and flywheel, have high-power density and very fast response.
Thus they can quickly supplement the energy gap in the microgrid, which in turn
suppresses the transient disturbance of the microgrid, and ensures voltage and
frequency stability.

In case of the grid-connected mode of operation of the microgrid, while transient

disturbances occur, the active/reactive power control (PQ control) strategy can be
suitably applied. In this mode of operation, the frequency and voltage are possibly
regulated by the main grid control system, and the microgrid system is supposed to
appropriately manage the power flow into or from the grid and within its network
as well. Fig. 8.7 shows the PQ control structure of the microgrid likely used to
regulate the power balance control during disturbances in the grid-connected mode
of operation.

Figure 8.7. The active/reactive power control (PQ control) system of the microgrid.

> Read full chapter

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