EHB 322E

Digital Electronic Circuits

Asst. Prof. Sheida Faraji

Lecture 2- MOS Fabrication 1

Week 2 (19th Feb 2024)

Spring 2024
Lecture Outline

• VLSI Fundamentals
• Digital CMOS Basics
• Fabrication Process
• Variation
• MOS fabrication 2 lecture is next week (week 3).
VLSI Hierarchical Representations
Oracle SPARC M7 Processor, 2015

• Complex digital systems can be sub-divided

in a hierarchical manner
• Highly automated techniques exist for
converting high level descriptions of system
behaviour to a detailed implementation
prescription to fabricate a chip.
• To do this, a set of abstractions and
domains have been developed to describe
integrated electronic systems.
Design Domains

• Designs are represented in three domains

• Behavioural – What does the system do?
• Structural – How are the elements connected?
• Physical – How the structure will be fabricated?
Design Abstractions

Abstraction is a way of simplifying complex systems by breaking them down

into smaller, more manageable parts.

Each domain can be specified at a variety of levels of abstraction:

• Architectural/System
• Algorithmic
• Module or Functional Block
• Logical
• Circuit
 Y-Chart: Abstractions in three Domains

Y-chart is basically used to reduce

the complexity of systems for users.

Y-chart is a methodological representation The Gajski–Kuhn chart (or Y diagram)

emphasising on the need to separate depicts the different perspectives in VLSI
applications from architecture at higher hardware design. It is mostly used for the
levels of abstraction. It introduces an development of integrated circuits.
explicit mapping step.
Y-Chart: Abstractions in three Domains
 Classification of Digital CMOS Circuits

Metal-Oxide Semiconductor
Static Circuit:
• In steady-state the output is evaluated via a low-impedance DC path between the output
and VDD (drain voltage) or GND (ground), respectively, i.e. the output is actively driven.
Dynamic Circuit:
• In steady-state the output is evaluated due to the presence or absence of charge,
respectively, stored on the output node capacitance.
MOS Capacitor

• MOS = Metal Oxide Silicon

• Sandwich of conductors separated by an insulator
• “Metal” is more commonly a heavily doped polysilicon layer n+ or p+ layer
• NMOS → p-type substrate, while PMOS → n-type substrate
MOS Capacitor Operating Modes
• Accumulation: VGB < VFB
• Essentially a parallel plate capacitor.
• Capacitance is determined by oxide thickness:

• Depletion: VFB< VGB < VT

• Positive charge on gate terminates negative charges in depletion
region.
• Potential drops across the oxide and depletion region.
• Charge has a square-root dependence on applied bias.

• Inversion: VT < VGB

The surface potential increases to a point where the electron density at
the surface equals the background ion density.
At this point, the depletion region stops growing and the extra
charge is provided by the inversion charge at surface.
ni : intrinsic electron concentration
Na: concentration of acceptor atoms
 Threshold Voltage
• The threshold voltage is defined as the gate-body voltage that causes the surface to change
from p-type to n-type
• For this condition, the surface potential has to equal the negative of the p-type potential.
• Apply KCL around loop: Φs= Electrostatic potential (both n
and p concentration) at the surface.

The VFB voltage is the gate voltage required to make

the energy bands in the semiconductor flat up to the
semiconductor-dielectric interface
 Q-V Curve for MOS Capacitor

• In accumulation, the charge is simply proportional to the applied gate-body bias.

• In inversion, the same is true.
• In depletion, the charge grows slower since the voltage is applied over a depletion region
CMOS Transistors – State-of-the-Art

13
CMOS Devices
• CMOS (Complementary Metal-Oxide Semiconductor)
• MOSFET (Metal Oxide Semiconductor Field Effect Transistor)
Cross-section View Top View

The gate acts like a capacitor. A high voltage on the gate attracts charge into the channel. If a
voltage exists between the source and drain, a current will flow. In its simplest approximation,
the device acts like a switch.
14
The MOS Transistor

15
MOS Transistor as a Switch

16
ON/OFF Switch Model of MOS Transistor

G
|VGS|

S D
Ron

S D S D
|VGS| < |VT| |VGS| ≥ |VT|

17
A More Realistic Switch

G
|VGS|

S D
Ron
Roff

S D S D
|VGS| < |VT| |VGS| > |VT|

18
A Logic Perspective

NMOS Transistor PMOS Transistor

G
G
VGS > 0
VGS < 0
S D
S D

X Ron X Ron
Y Z Y Z
Y=Z if X=1 Y=Z if X=0

19
Metal-oxide-semiconductor (MOS) Transistors
Metal-oxide-semiconductor (MOS) Transistors
MOSFET – Current-Voltage (IV) Characteristics
Output curve Transfer curve

N-channel MOSFET
 Transistor in Linear and Saturation
Lambda is a measure of how much the drain current changes as you
change Vds and hold Vgs constant in the active region.

VGS

VDS > VGS - VT

G

D
S

n+ - + n+
VGS - VT
 Current-Voltage Relations: A good transistor
-4
x 10
6
VGS= 2.5 V

5
MOSFET Operating Regions Resistive Saturation

Quadratic Relationship
4
• Strong Inversion VGS > VT VGS= 2.0 V

Linear (Resistive) VDS < VDSAT

ID (A)
3
Saturated (Constant Current) VDS  VDSAT VDS = VGS - VT
• Weak Inversion (Sub-Threshold) VGS  VT 2
VGS= 1.5 V
Exponential in VGS with linear VDS dependence
1
VGS= 1.0 V

0
0 0.5 1 1.5 2 2.5
VDS (V)
Threshold Voltage: Concept
• Threshold voltage (Vth) is the minimum gate-to-source voltage (VGS) that is needed to
create a conducting path between the source and drain terminals to turn on the device.

• It is an important scaling factor to maintain power efficiency. The smaller the Vth is, the
lower the operating voltage and power consumption will become.

+
S VGS D
G
-

n+ n+

n-channel Depletion
Region
p-substrate

B
 The Threshold Voltage

Electric potential (Φ) is the amount of work

needed to move a unit charge from a reference
point to another point against an electric field.
The Body Effect

0.9

0.85

The Body Effect: It is the voltage (potential) 0.8

0.75
difference (BS) between the source and the
0.7
substrate (body), which leads to an increase

VT (V)
0.65
or decrease in the threshold voltage.
0.6

For a low-voltage operation, a small Vth is 0.55

0.5
critical.
0.45

0.4
-2.5 -2 -1.5 -1 -0.5 0
V (V)
BS
NMOS and PMOS
• MOS transistors are built on top of silicon (P-si) wafers.
• This process uses semiconductor doping and oxide
growth to create N-type, P-type and insulating regions in
a layer-by-layer fashion. Geometric shapes are obtained
via photolithography and chemical etching.
• The drain and source regions are strongly doped with N-
dopants (NMOS) or P-dopants (PMOS), and the substrate
is doped with the opposite type (P-type for NMOS and N-
type for PMOS).
Ideal nMOS and pMOS Characteristics
Ideal nMOS and pMOS Characteristics
CMOS Inverter

pMOS

nMOS
CMOS Gates
Static CMOS Source/Drains
• With PMOS on top, NMOS on bottom.
• PMOS source always at top (near Vdd)
• NMOS source always at bottom (near Gnd).
PUN
• NMOS devices cannot fully pull the output to
high supply voltage.
• PMOS devices cannot fully pull the output
down to ground.
• All of the pull up gates must be made from
PDN
PMOS because a conductive path through an
NMOS transistor could not pull up all the way
to Vdd, it would have to remain below Vdd by
at least the threshold voltage.
Complementary Metal Oxide Semiconductor
CMOS Gates

• When the PUN is conducting, the output F will

be “1”. Hence, the PUN is determined by a
Boolean expression for the un-complemented
output F in terms of the complemented inputs
𝐴, 𝐵, 𝐶, 𝐷.

• When the PDN is conducting, the output F will

be “0”. Hence, the PDN is determined by a
Boolean expression for the complemented
output 𝐹 in terms of the un-complemented
inputs (A,B,C,D)
Static CMOS Gate Structure

• Drives rail-to-rail (input/output range is the

same as supply voltage levels).
• Power rails are Vdd and Gnd.
• Output is Vdd or Gnd.
• Input connects to gates.
• Load is capacitive.
• Once output node is charged, it doesn’t use
energy (no static current→ only leakage).
• Output actively driven
Two-Input CMOS NOR Gate
Two-Input CMOS NAND Gate
Gate Design Example
• Design gate to perform:

Strategy:

• Use static CMOS structure

• Design PMOS pullup for f
• Use DeMorgan’s Law to determine f’.
• Design NMOS pulldown for f’.
Gate Design Example
• Design gate to perform:
Fabrication Details
• Silicon Ingot and Wafer Manufacturing

*Image from Quirk & Serda

Silicon Wafer Manufacturing

• The ROI (return of investment) of 450mm wafers is compelling:

• A 450mm fab with equal wafer capacity to a 300mm fab can produce 2x the
amount of die.
• A 14nm die from a 450mm wafer will cost 23% less than the same die from a
300mm wafer.
Silicon Lattice
• Forms into crystal lattice
• Silicon crystallises in the so-called diamond lattice in which each atom covalently binds tetrahedrally
four adjacent atoms equivalently.
• The angle between the two binding partners of an atom is 109.5°, the distance between of the centres
of two bonded atoms 2.35 Å.
Doping Elements

http://chemistry.about.com/od/imagesclipartstructures/ig/Science-Pictures/Periodic-Table-of-the-Elements.htm
Doping
• Add impurities to Silicon Lattice.
• Replace a Si atom at a lattice site with another.
Doping Elements

• Doping means the introduction of intentional impurities into a

semiconductor crystal to the defined modification of conductivity.
• Two of the most important materials silicon can be doped with, are:
- Boron B (3 valence electrons = 3-valent) → P-type and
- Phosphorus P (5 valence electrons = 5-valent) → N-type.
• Other materials are aluminum, indium (3-valent) and arsenic,
antimony (5-valent).
• Doping concentration for silicon semiconductors may range anywhere
from 1013 cm-3 to 1018 cm-3.
Doping with P (N-type)

• End up with extra electrons.

- Donor electrons.
- The dopant is negatively charged.
• Not tightly bound to atom.
- Low energy to displace.
- Easy for these (free) electrons to move.
Doping with B (P-type)

• End up with electron vacancies, so-called Holes.

- Acceptor electron sites.
• Easy for electrons to shift into these sites.
- Low energy to displace.
- Easy for the electrons to move.
- Movement of an electron best viewed as
movement of hole.
Fabrication Process
• Process is carried out in a cleanroom
• Start with Silicon wafer.
• Dope (e.g. via thermal diffusion)
• Grow Oxide (SiO2) via thermal oxidation.
• Deposit Metal, e.g. aluminum, gold, etc. (via PVD*).
• Mask/Etch to define where features go.
Cleanrooms are classified according to the number
and size of particles permitted per volume of air.

*Physical vapour deposition

Fabrication Process
• Mask/Etch to define where features go.
- It includes photolithography, using light to
transfer a pattern onto a substrate.
- Deposit photoresist and bake.
Photoresist is a light sensitive solution.
Two type: positive or negative
In positive resist, the exposed areas are soluble.
In negative resist the exposed areas are insolubly.
- UV exposure through a photomask.
- Develop photoresist
- Etch unwanted areas.
Fabricated n-MOS Transistor
n-MOS Transistor Representations
Fabrication Process of a N-Well CMOS
Typical N-Well CMOS Process

2
7

3
8

9
5

6
CMOS Layers
“Standard” n-Well Process:

1. Active (Diffusion) (Drain/Source regions)

2. Polysilicon (Gate Terminals)
3. Metal 1, Metal 2, Metal3
4. Poly Contact (connects metal 1 to polysilicon)
5. Active Contact (connects metal 1 to active)
6. Via (connects metal to metal)
7. n Well (PMOS bulk region)
8. n Select (used with active to create n-type diffusion)
9. p Select (used with active to create p-type diffusion)
CMOS Process
Simplified CMOS Process Wiring with Metal and Contacts
Wiring and Contact Layout
MOS Layout
CMOS Inverter – Example Layout

Set Pitch (place n-well and power/ground busses)

CMOS Inverter – Example Layout

Add Transistors (active, select and poly)

CMOS Inverter – Example Layout

Make Connections (poly, metal, and contacts)

CMOS Inverter – Example Layout

Add Substrate and Well Contacts

CMOS Inverter – Example Layout

Add External Wiring and Resize

Goal of All VLSI Design Enterprises

• Convert system specs into an IC design in MINIMUM TIME and

with MAXIMUM LIKLIHOOD that the Design will PEFORM AS
SPECIFIED when fabricated.

MAX YIELD + MIN DEVELOPMENT TIME + MIN DIE AREA => MIN COST
Process Variation Types
• Many reasons why variation occurs and shows up in different ways.
• For instance, the scaling down of process technologies increases the process variation.
• Hence, delay variation increases and impact the frequency performance of the design.
• Scales of variation
- Wafer-to-wafer, die-to-die, transistor-to-transistor.
• Correlations of variation
• Systematic, spatial, random (uncorrelated)
Variation Types
Die-to-die: Variation between chips on the
same wafer or difference wafers

Intra-die or within-die: Variation between

elements on the chip.

Systematic variation: related to the location

and patterns. E.g. exposure pattern variation
during lithography process.

Random Transistor-to-Transistor:
• Random dopant fluctuation
• Local oxide variation
• Line edge roughness
• Etch and growth rates
• Transistors differ from each other in random
ways
Statistical Dopant Placement
• Statistical Dopant Placement is another reason for device variation.

[Bernstein et al, IBM JRD 2006]

Oxide Thickness and Interface roughness
• Oxide Thickness and Interface roughness also results in device variation.

• Line Edge Roughness

From: http://www.microtechweb.com/2d/lw_pict.htm
Line Edge & Line-Width Roughness
• Line Edge & Line-Width Roughness causes process and device variation.

Source: Kuhn et al.

 Impact

[Bernstein et al, IBM JRD 2006]

Vth Variability @ 65nm
Impact of Vth Variation?
Process Corners
• In semiconductor manufacturing, a process corner refers to a variation of fabrication
parameters used in applying an integrated circuit design to a semiconductor wafer.
• Process corners represent the extremes of these parameter variations within which a
circuit on a wafer must function correctly.

Try to identify the {worst, best} set of parameters.

• A circuit running on devices fabricated at these process corners may run slower or faster
than specified and at lower or higher temperatures and voltages.
• If circuit does not function at any of the process extremes, the design is considered to
have inadequate design margin.
Worst-case Corner Model
Statistical Corner Model

• For more realistic modeling for process variability than worst-case corner model.

• Using data from different dies, wafers, and wafer lots collected over a long enough
period of time to represents realistic process variability of the target technology.

• The difference between statistical corner model and worst-case corner-model:

- Statistical corner model use the realistic Probability Density Function (PDF) of
the corresponding model parameter of its typical model.
- PDF is obtained from the distribution of a large set of production data.

• Statistical models can pass a valid design, which were rejected in worst-corner
model
Speed Binning
• Speed binning determines the max speed of a chip and sell it accordingly.

Objective: performance
Metric: speed, delay fault coverage