Two Level Implementation of Logic Gates

( DLD BSCS 2ND )

The term “two-level logic” refers to a logic design that uses no more than two logic
gates between input and output. This does not mean that the entire design will only
have two logic gates, but it does mean that the single path from input to output will
only have two logic gates.
In two-level logic, irrespective of the total number of logic gates, the maximum
number of logic gates that can be cascaded between any input and output is two. The
outputs of first-level logic gates are connected to the inputs of second-level logic
gates in this configuration.

What is Logic Gate?

A Logic gates is a basic component of digital circuits which perform basic logical
operations. Just like algebraic structures or mathematical systems they execute basic
logical operations that are so critical in designing intricate digital networks. A gate
can operate applying Boolean algebra with input that can be given to it and yields
outputs as a result.
primary logic gates used in two-level logic design:
 AND Gate: Outputs true (1) only if all inputs are true.
 OR Gate: Outputs true (1) if at least one input is true.
 NAND Gate: Outputs true (1) unless all inputs are true.
 NOR Gate: Outputs true (1) only if all inputs are false.

Example of two-level logic implementation:

We explore four logic gates in two-level logic implementation: AND Gate, OR Gate,
NAND Gate, and NOR Gate. There are a total of 16 two-level logic combinations if
we choose one of these four gates at the first level and one at the second level. These
are
AND-AND, AND-OR, AND-NAND, AND-NOR,
OR-AND, OR-OR, OR-NAND, OR-NOR,
NAND-AND, NAND-OR, NAND-NAND, NAND-NOR,
NOR-AND, NOR-OR, NOR-NAND, NOR-NOR.

Each two-level combination implements a separate logic function. These 16

combinations are divided into two categories.
1. Degenerative form of logic gate Combination
2. Non-Degenerative form of logic gate Combination

Degenerative form:
Degenerative form occurs when the output of a two-level logic realization can be
achieved with only one logic gate. The advantage of degenerative form is that the
number of inputs of single Logic gate increases which results in the increment of
fan-in of logic gates.

AND-AND Implementation:
Because the entire function results in an AND function of all the inputs, this AND-
AND gate combination is a degenerate form.
The outputs of first-level logic gates: F1=AB and F2=CD. These outputs are applied
as inputs of the second level, so the output of the second level is F=F1F2, which
means F=ABCD.
OR-OR Implementation:
The output of an OR-OR gate combination is the Logic Function OR. With this
combination, the OR function can be implemented with several inputs.

The outputs of first-level logic gates: F1=A+B and F2=C+D. These outputs are
applied as inputs of the second level, so the output of the second level is F=F1+F2
which means F=A+B+C+D.

AND-NAND Implementation:

AND gate are present in the first level of this logic implementation, while NAND
gates are present in the second level. An example of AND-NAND logic realization
is shown in the diagram below.
AND-NAND Implementation

The outputs of first-level logic gates: F1=AB and F2=CD. These outputs are applied
as inputs of the second level, so the output of the second level is F= (F1F2)’ which
means F=(ABCD)’.

OR-NOR Implementation:
OR-NOR combination of gates results in NOR logic function. And this degenerate
form can be used for the NOR function with multiple inputs.

The outputs of first-level logic gates: F1=A+B and F2=C+D. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1+F2)’
which means F=(A+B+C+D)’.

NAND-NOR Implementation
The outcome function of NAND-NOR in two-level logic is AND logic. The
following is its expression and schematic:
The outputs of first level logic gates: F1=(AB) ‘ and F2=(CD)’. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1+F2)’
which means F=((AB)’+(CD)’)’.

NOR-NAND Implementation:
Because the NOR-NAND combination also produces an OR function, it is likewise a
degenerate form. The following is an example of it with a diagram;

The outputs of first level logic gates: F1=(A+B) ‘ and F2=(C+D)’. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1.F2)’
which means F=((A+B)'(C+D)’)’.

NAND-OR Implementation:
This combination, like the AND-NAND combination, produces a NAND logic
function.
The outputs of first level logic gates: F1=(AB) ‘ and F2=(CD)’. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1+F2)
which means F=((AB)’+(CD)’)=(ABCD)’.

NOR-AND Implementation:
This combination is identical to the OR-NOR combination since this combination
similarly results in a NOR function.

The outputs of first level logic gates: F1=(A+B) ‘ and F2=(C+D)’. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1.F2)
which means F=((A+B)'(C+D)’)=(A+B+C+D)’.

Non-Degenerative form:
A non-degenerative form occurs when the output of a two-level logic realization
cannot be achieved using a single logic gate. Non-degenerate forms are two-level
logic combinations that implement the Sum of Product form or the Product of Sum
form.
In those 16 combinations, there are 8 non-degenerate forms. Below are instances of
each of these non-degenerate types.
AND-OR implementation:
The first level gate in a While-OR combination is an AND gate, and the second level
gate is an OR gate. As shown in the diagram below, this combination implements
the Sum of Product (SOP) form.

The outputs of first-level logic gates: F1=AB and F2=CD. These outputs are applied
as inputs of the second level, so the output of the second level is F=(F1+F2) which
means F=(AB+CD).

NAND-NAND Implementation:
NAND is a universal gate, and its NAND-NAND combination, like the AND-OR
combination, is used to produce the Sum of Product form.

The outputs of first-level logic gates: F1=(AB)’ and F2=(CD)’. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1.F2)’
which means F=(AB)+(CD).

OR-AND Implementation:
The first level gate in an OR-AND combination is an OR gate, and the second level
gate is an AND gate. The Product of Sum form is implemented with an OR-AND
combination.
The outputs of first-level logic gates: F1=(A+B) and F2=(C+D). These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1.F2)
which means F=(A+B)(C+D).

NOR-NOR Implementation:
NOR is also a universal gate and its NOR-NOR combination can be used to
implement the Product of Sum form.

The outputs of first-level logic gates: F1=(A+B)’ and F2=(C+D)’. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1+F2)’
which means F=((A+B)’+(C+D)’)’=(A+B)(C+D).

AND-NOR Implementation:
The AND-NOR combination is used to implement the AND-OR-INVERT
compound logic (AOI).
The outputs of first-level logic gates: F1=(AB) and F2=(CD). These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1+F2)’
which means F=(AB+CD)’.

NAND-AND Implementation
The AND-OR-INVERT (AOI) form can also be implemented using NAND-AND.

The outputs of first-level logic gates: F1=(AB)’ and F2=(CD)’. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1F2)
which means F=(AB)'(CD)’=(AB+CD)’.

OR-NAND Implementation:
The OR-NAND form is used to implement the OR-AND-INVERT compound logic
(OAI).
The outputs of first-level logic gates: F1=(A+B) and F2=(C+D). These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1F2)’
which means F=[(A+B)(C+D)]’.

NOR-OR Implementation:
The NOR-OR combination, like the OR-NAND combination, is used to build OR-
AND-INVERT compound logic (OAI).

The outputs of first-level logic gates: F1=(A+B)’ and F2=(C+D)’. These outputs are
applied as inputs of the second level, so the output of the second level is F=(F1+F2),
which means F=(A+B)’+(C+D)’=[(A+B)(C+D)]’.

Advantages of Two-Level Logic:

 Simplified Design: Two level logic reduces the design complexity because all
that is used in the process is logic gates that only two levels deep. This can help
circuit design to be more feasible and less complex.
 Efficient Implementation: There are only two levels of gates where two-level
logic makes more sense of speed since the signal will only traverse through a few
gates at most.
 Reduced Gate Count: It can be useful in the first-level design for reducing the
total number of gates possibly bringing down the cost and power consumption of
a preferred design from the second level.

Disadvantages of Two-Level Logic

 Limited Complexity: The restriction to two levels means that the logic functions
that can be implemented are of a much more limited kind and this may not fit in
the more advanced or specialized applications.
 Design Constraints: If a system is designed with only two levels of gates, it is
also possible that to obtain the desired functions more complex logic is required
and hence the designs are not very easy ones.
 Potential for Increased Gate Usage: There are typical situations, where using
of two-level logic with required function may increase the number of gates
compared to the cases, where multi-level solution can be used.