Digital Logic Design

Lab Manual

faculty of computer science & engineering (FCSE)

Ghulam Ishaq Khan Institute of Engineering Sciences & Technology
 CE-221L – Digital Logic Design Lab

Version History

Version Updated in Updated by Approved by

1.0 Fall 2021 Engr. Abu Bakar Dr. M. Hanif

Engr. Zaheer
Dr. Waqar
2.0 Fall 2023 Ahmed
Ahmad
Engr. Irfanullah

FCSE, GIK Institute 1

 CE-221L – Digital Logic Design Lab

Table of contents
Instructions for Students ..…………………………………………………….…
3

Lab-1: Introduction to the Lab Equipment ……………………………...……………..

5

Lab-2: Basic Logic Gates & Truth Tables ……………………………………………….

16

Lab-3: Boolean Algebra & DeMorgan’s Law ……………………………….………...

27

Combinational Logic Circuits (CLC):-

Lab-4: Adders & Subtractors …………..…………………………………………..
37

Lab-5: Encoders & Decoders ……………...………………………………………..

50

Lab-6: Multiplexers & Demultiplexers ……...………………………………...

67

Sequential Logic Circuits (SLC):-

Lab-7: Flip Flops ………………………………………..………………………………..
83

Lab-8: Counters …………………………………………..............…………............

100

FCSE, GIK Institute 2

 CE-221L – Digital Logic Design Lab

Lab-9: Shift Registers ……………………………………...…......…………………

110

Introduction to Verilog HDL:-

Lab-10: Combinational Circuits ……………………….………………………..
117

Lab-11: Sequential Circuits ………………………………..……………………..

141

Lab-12: Finite State Machines ……………………………..…………………….

150

Lab-13: Open Ended Lab (OEL) …………………………………………......................

164

Instructions for Students:

1. Attendance is mandatory for students in all the labs. If a student is absent from a lab
due to any reason, he/she will have to get written permission of the Dean to perform
that lab. The Dean will allow students to perform lab if he feels that the student has a
genuine excuse.

2. The introductory lab provides working guidelines for the entire course of lab. Students
are advised to study it thoroughly before coming to the lab. Actual experiments which
will be graded start from lab 1, “Introduction to Digital Experiments”.

3. All labs have a section named Summary of Theory which provides necessary theory
related to the experiments. Since the purpose of a lab manual is to compliment a text
book, students should not rely completely on this manual.

4. Almost every lab is divided into two main parts, with each section having its own set of

FCSE, GIK Institute 3

 CE-221L – Digital Logic Design Lab

review questions. Labs will be graded on performance in these review questions.

5. Labs will be graded in double entry fashion; one entry in an assessment sheet given at
the end of every lab and another entry in the instructor’s record. This system of
keeping records will keep students aware of their performance throughout the lab.

6. The tentative marks distribution is as follows:

• Lab Performance – 40%

• Open Ended Lab – 10%
• Lab Mid-Term Exam – 20%
• Lab Final Exam – 30%

7. The assessment sheet at the end of every lab looks like this:

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can setup, and Can setup, and
Can independently Cannot setup or
Apparatus handle the handle the
setup, operate and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble Can assemble but Cannot
Apparatus design according to design inaccurately assemble
design within least time
Achieving Design objectives Design objectives Design objectives Design

FCSE, GIK Institute 4

 CE-221L – Digital Logic Design Lab

have been
have been achieved have been achieved
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements
Measurements are Measurements are Measurements are
are made and
Presentation made and results are made and results are made and results
results are not
of Results presented presented more are presented
presented
most accurately accurately much accurately
accurately
Much of the Most of the
Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

FCSE, GIK Institute 5

 CE-221L – Digital Logic Design Lab

Lab-1
Introduction to the Lab

1.1 Lab Objectives:

 To familiarize students with the essential lab equipment.
 To provide working guidelines for all the labs.
 To provide instructions on building a digital circuit.

1.2 Overview:
This section describes the procedure for wiring logic circuits with any general-purpose
white prototype board for your breadboard. One of these is contained in each lab kit.

1. Before wiring any circuit, generate a neat, complete logic.

2. Every time you add a wire or component to the physical circuit, mark off the
corresponding part of the wiring diagram with a colored pencil or marker. This makes it
easy to see what parts of the circuit have been built so far. If you make any circuit
changes, draw these on your wiring diagram.

3. Insert IC packages into the appropriate breadboard area before inserting any wires. You
will usually need to bend the IC leads (pins) slightly inward so that the spacing closely
matches the spacing of sockets on the breadboard. Be careful to check that all IC leads
actually make it into the correct sockets.

4. To remove an IC, use an extraction tool, screwdriver, pliers or tweezers to avoid

bending or breaking IC leads, or personal injury.

5. Use only solid-conductor wire in the size range of AWG 20 to AWG 26. Wire with larger
diameter may damage the socket spring clips of the breadboard. Wire strippers should
be used to cut wires to appropriate lengths and to check wires that are suspected of
having a larger diameter than permitted. Trim and re-strip the end of any jumper wire
that appears badly nicked or overly flexed.

6. It is possible to insert most wires by hand. In tight places, using the forceps from the

FCSE, GIK Institute 6

 CE-221L – Digital Logic Design Lab

tool kit can make the job much easier. In either case, wires are easier to insert if they
have been cut at an angle of approximately 45 degrees with respect to the axis of the
wire.

7. When removing wires, be sure to pull at a right angle to the socket to avoid damage.

8. Route wires around IC packages, not over them. Occasionally an IC turns out to be
defective. If wires have been placed over the IC, you will have to remove them so that
the IC can be replaced. It is best to wire a circuit in stages, beginning with power and
ground connections. Add wires with the power switch OFF. Before turning power ON,
remove all hand jewelry and make sure that no foreign metal objects are near the
circuit. Check every IC to make sure it is not overheating. If any IC is too hot to touch
immediately shut the power off and check all leads. (Be careful because shorted ICs can
become very hot and leave a brand on your finger!) Also make sure that no IC has been
inserted backwards.

9. IC devices can be damaged if the power level exceeds 5.5V. Damage may also occur if
the supply voltage connection is removed from the IC pin while power is still being
applied to the circuit.

10. To debug a circuit, use a Oscilloscope to check logic levels. Start at a position in the
circuit where the logic level is known to be correct and work outward from there. If an
IC does not appear to produce the correct signal, check that power and ground are
correctly connected to the IC; also check all inputs to the component. Finally, check
that the output of the IC is not incorrectly connected to some other signal.

11. If you cannot get your circuit to work, bring it and a current circuit diagram or
schematic to Engineer for help.

FCSE, GIK Institute 7

 CE-221L – Digital Logic Design Lab

Figure: Internal Connections of Bread Board

1.3 Wiring Guidelines:
1. Use new wire. A box of new wire is available in the Lab.

• Old wire can break inside the insulation, causing incorrect circuit behavior that is
difficult to troubleshoot.
• Old wire should be recycled; place old wires in the wire recycling box next to the
new wire box in Lab.

2. Strip for breadboard squares worth of insulation off the ends of a wire when using it
in the breadboard. This is approximately 5/16 inch or 8 mm.
• If you strip too much, the wires in adjacent breadboard columns can touch,
causing a short circuit and most likely incorrect behavior.
• If you don’t strip enough, the insulation can prevent the spring clips in the
breadboard holes from closing properly around the non-insulated part of the wire
that is inserted into the hole.

3. Create power and ground busses at the top and bottom of your breadboard.

• The connection pattern used in the breadboard is shown in figure (to follow
shortly).
• The top and bottom rows can be used to distribute +5VDC and ground to the ICs,
• Note that the top and bottom “bus” rows have a break in the very middle! If you
want a power or ground bus to run the length of the breadboard, you must insert
a jumper in the middle of the row to join the two half rows together. This makes
your wiring less crowded, and makes it easy to see power and ground connections.

4. The top and bottom rows can be used to distribute +5VDC and ground to the ICs.
Run all power signals in red wire and all ground signals in black wire.

• Do not use red or black wire for any other signals. This makes it easy to tell which
wires are power and ground wires, and which are actual signal wires.
• Use a single power or ground wire from the bus to the chip. Do not daisy chain
power or ground connections. Think parallel, not serial.
• You may wire from the bus to the breadboard hole next to the chip. This makes it
easy to see that the power and ground wires are connected to the correct pin.
• You may wire from the bus to the breadboard column that connects to the chip.
This allows more room for signal wires, without covering the power and ground
wires.

FCSE, GIK Institute 8

 CE-221L – Digital Logic Design Lab

5. Color codes your wiring in some way. Here are some suggestions that are meant to
make it easier to trace your wiring:
• Use the same color for all the wires of a signal that runs to multiple gates.
• Use different colors for different inputs of a gate.
• If you have a bus, make all the wires of the bus the same color. However, if you have
long runs of parallel wires that are the same color, it will be more difficult to trace
individual bits of the bus.

6. Wires should be routed no more than ½” (12 mm) above the breadboard.

• If the wires are too high, it will be difficult to trace signals through your circuit.
• If the wires are low, be sure the stripped wire ends are seated firmly in the
breadboard. Careful routing is essential for efficient troubleshooting. Tight wiring
can create sharp bends, which can cause trouble.

7. Avoid sharp bends in the wires. Sharp bends in the wire can cause the wire to break
inside the insulation.

8. Run wires around or between chips rather than over them.

• Your chips may be defective or be damaged while in use, and it is much easier to
remove chips for testing/replacement if you do not have to remove your wiring in
order to remove your chips.
• When possible, leave 2 or 3 rows of the breadboard between chips, to allow signals
to pass from one side of the IC to the other.

9. Make short wire lengths from source to destination.

• Route wires point to point, rather than squaring corners.

• Do not daisy chain power and ground wires. Think parallel, not serial.
• Do not daisy chain signal lines from a switch input to several gates. Think parallel,
not serial.

10. Wire from a complete schematic diagram. The chip’s pin numbers should match the
pin numbers in the diagram.

1.4 Digital – Analog Electronics Trainer:

Description:

FCSE, GIK Institute 9

 CE-221L – Digital Logic Design Lab

IT-400 is a comprehensive and self-contained system suitable for anyone engaged in

Digital and Analog circuit experiments. All necessary equipment for Digital and Analog
circuit experiments such as power supply, function generator, Data Switches, LEDs, Logic
Probe, 7-Segment Displays etc are installed on the main unit. The Bread board allows
students to perform a wide variety experiment relating to essential topics in the field of
digital and analog circuit. It is a time and cost saving device for both students and
researchers interested in developing and testing circuit prototypes.

IT-400 Digital / Analog Training System

Features:
 Bread Board Based
 Power Supplies Included

FCSE, GIK Institute 10

 CE-221L – Digital Logic Design Lab

 Basic Measuring Instruments Included

 Flexibility to Perform Custom Experiments
 Output Devices like LEDs and 7-Segment Included
 Input Devices like Push Switches, Toggle Switches Included
 Standard Function Generator Included
 Passive Components Included
 Protection Circuits Included

Technical Features:

Supplies:
 Fixed DC: +5V, -5V, +12V, -12V
 Dual DC Power Supply: 0 ~ +15V and 0 ~ -15V adjustable
 FIX Supply AC: 2V-0-2V, 12V-0-12V, 15V-0-15V

Function Generator:
 Output Waveform: Sine, Square, Triangle and TTL
 Output Frequency: up to 100KHz in five steps

3 ½-Digit Digital Voltmeter:

 Volt ranges 200mV, 2V, 20V, 200V

Data Switch:
 16-bit switch with TTL Output

Push Switch
 Two independent Switches
 Each with Q, Q’ output
 De-Bounce Switch

Logic Indicator
 24 independent LEDs indicate high and low logic state
Digital Display
 3 independent 7-segment LED display with BCD to 7-segment decoder/driver
input with 8-4-2-1 code

FCSE, GIK Institute 11

 CE-221L – Digital Logic Design Lab

Potentiometer:
 Carbon Track 1K and 100K

Interface Connectors
 2X BNC Connectors interfaced to 2mm gold plated pins
 1X Banana Connector interfaced to 2mm gold plated pin
 DB-9 Connector with all pins interfaced to 2mm gold plated pins
 DB-25 Connector with all pins interfaced to 2mm gold plated pins

Solderless Breadboard:
 2 Terminal Strips, Tie-point 1680
 4 Distribution Strips, Tie-point 400

Audio Output
 0.5W Speaker with Audio Amplifier and Volume Control

Accessories:
 2mm-1mm patch cords, Power Cord, User Manual

1.5 Digital Multimeter:

Description:

A multimeter or a multimeter, also known as a VOM (volt-ohm-milliammeter), is an

electronic measuring instrument that combines several measurement functions in one
unit. A typical multimeter can measure voltage, current, and resistance.
Analog multimeters use a microammeter with a moving pointer to display readings.

A digital multimeter is a test tool used to measure two or more electrical values—
principally voltage (volts), current (amps) and resistance (ohms). It is a standard
diagnostic tool for technicians in the electrical/electronic industries.

FCSE, GIK Institute 12

 CE-221L – Digital Logic Design Lab

Digital Multimeter

Specification:

 DC Voltage: 200mV / 2V / 20V / 200V / 1000V

best accuracy: +/- (0.5%+1)

 AC Voltage: 2V / 20V / 200V / 750V

best accuracy: +/- (0.8%+3)

 DC Current: 20mA / 200mA / 20A

best accuracy: +/- (0.8%+1)

 AC Current: 20mA / 200mA / 20A

best accuracy: +/- (1%+3)

 Resistance: 200 Ohm / 2 kOhm / 20 kOhm / 2 MOhm / 200 MOhm

best accuracy: +/- (0.8%+1)

FCSE, GIK Institute 13

 CE-221L – Digital Logic Design Lab

 Capacitance: 20nF / 200nF / 2µF / 100µF

best accuracy: +/- (4%+3)

 Temperature: -40 až +1000°C, -40 až +1832°F

best accuracy: +/- 1%+3 (°C), +/- 1%+4 (°F)

 Frequency: 2kHz / 20kHz

best accuracy: +/- (1.5+5)

Special Functions:

 Diode
 Continuity buzzer
 Data Hold
 Icon display
 Sleep mode
 Low battery display
 Input impedance for DC voltage: 10 MOhm
 Display backlight - auto sensor
 Max. display 1999 (59 x 25mm)

General Characteristics:

 Power: 9V bat. (6F22)

 Product size: 165 x 80 x 38mm
 Product weight: 275g

FCSE, GIK Institute 14

 CE-221L – Digital Logic Design Lab

1.6 The Oscilloscope:

Description:
An oscilloscope is easily the most useful instrument available for testing circuits because
it allows you to see the signals at different points in the circuit. The best way of
investigating an electronic system is to monitor signals at the input and output of each
system block, checking that each block is operating as expected and is correctly linked to
the next. With a little practice, you will be able to find and correct faults quickly and
accurately. An oscilloscope is an impressive piece of kit.

UTD2102CEX Digital Storage Oscilloscope Specifications:

 Dual analog channels width range 1mV/div~20V/div;
 7 inches’ widescreen LCD displays;
 The new interface style;
 Supports plug-and-play USB storage device. Communication with and remote
control of computer through the USB device;
 USB drive system software upgrade;
 Storage of waveforms setups and interfaces waveforms and setups
reproduction;
 Automatic measurement of 32 waveform parameters;
 Unique waveform recording and replay function;
 Multilingual menu displays.

FCSE, GIK Institute 15

 CE-221L – Digital Logic Design Lab

UTD2102CEX - Digital Storage Oscilloscope

Specification UTD2102CEX

Channels 2

Bandwidth 100MHz

Sample Rate 1Gs/s

Rise Time ≤3.5ns

Memory Depth 25kpts

Waveform Acquisition
≥2000wfms/s
Rate

Vertical Sensitivity(V/div) 1mV/div~20V/div

Timebase Range(s/div) 2ns/div~50s/div

Storage Setup,Wave,Bitmap

Trigger Modes Edge, Pluse, Video,Slope,Alternate

Interface USB OTG

General Characteristic

Power 100-240VAC, 45-440Hz

Display 7 Inches 64K Color TFT LCD, 800×480

Product Color White and Gray

Product Net Weight 2.2 Kg

Product Size (W×H×D) 306mm ×147mm × 122mm

Probe×2 (1×,10× switchable), Power Cord , USB Cable, PC

Standard Accessories
Software CD

Standard Individual
Gift Box, English Manual
Packing

Standard Quantity Per

2 PCs
Carton

Standard Carton
450mm× 420mm × 280mm
Measurement (L×W×H)

Standard Carton Cross

8.5 Kg
Weight

FCSE, GIK Institute 16

 CE-221L – Digital Logic Design Lab

Lab-2
Logic Gates & Truth Table
2.1 Lab Objectives:
 Learn to construct basic logic gates on a breadboard.
 Verify logic gate functionality through testing and truth tables.
 Gain proficiency in breadboard usage for electronic circuits.

2.2 Equipment Required:

 Trainer Board
 Connecting wires / Jumper wires
 14 pin ICs
• NOT (7404)
• AND (7408)
• OR (4071)
• NAND (7400)
• NOR (7402)
• XOR (7486)
• XNOR (4077)
 Power supply

2.3 Basic Logic Gates:

A logic gate is a basic building block of a digital circuit that has two inputs and one
output. The relationship between the i/p and the o/p is based on a certain logic. These
gates are implemented using electronic switches like transistors, and diodes. But, in
practice, basic logic gates are built using CMOS technology, FETS, and MOSFET (Metal
Oxide Semiconductor FET). Logic gates are used in microprocessors, microcontrollers,
embedded system applications, and in electronic and electrical project circuits. The
basic logic gates are categorized into seven: AND, OR, XOR, NAND, NOR, XNOR, and
NOT.
Digital Logic Gates can be made from discrete components such
as Resistors, Transistors , and Diodes to form RTL (resistor-transistor logic)
or DTL (diode-transistor logic) circuits, but today’s modern digital 74xxx series
integrated circuits are manufactured using TTL (transistor-transistor logic) based on NPN

FCSE, GIK Institute 17

 CE-221L – Digital Logic Design Lab

bipolar transistor technology or the much faster and low power CMOS based MOSFET
transistor logic used in the 74Cxxx, 74HCxxx, 74ACxxx and the 4000 series logic chips.

What are the 7 Basic Logic Gates?

The basic logic gates are classified into seven types: AND gate, OR gate, XOR gate, NAND
gate, NOR gate, XNOR gate, and NOT gate. The truth table is used to show the logic gate
function. All the logic gates have two inputs except the NOT gate, which has only one
input.
When drawing a truth table, the binary values 0 and 1 are used. Every possible
combination depends on the number of inputs. If you don’t know about the logic gates
and their truth tables and need guidance on them, please go through the following
infographic that gives an overview of logic gates with their symbols and truth tables.

Why do we use Basic Logic Gates?

The basic logic gates are used to perform fundamental logical functions. These are the
basic building blocks of the digital ICs (integrated circuits). Most of the logic gates use
two binary inputs and generate a single output like 1 or 0. In some electronic circuits,
few logic gates are used whereas in some other circuits, microprocessors include
millions of logic gates.
The implementation of Logic gates can be done through diodes, transistors, relays,
molecules, and optics otherwise different mechanical elements. Because of this reason,
basic logic gates are used like electronic circuits.

Binary & Decimal:

Before talking about the truth tables of logic gates, it is essential to know the
background of binary & decimal numbers. We all know the decimal numbers which we
utilize in everyday calculations like 0 to 9. This kind of number system includes the base
10. In the same way, binary numbers like 0 and 1 can be utilized to signify decimal
numbers wherever the base of the binary numbers is 2.
The significance of using binary numbers here is to signify the switching position or
otherwise voltage position of a digital component. Here 1 represents the High signal or
high voltage whereas “0” specifies low voltage or low signal. Therefore, Boolean algebra
was started. After that, each logic gate is discussed separately this contains the logic of
the gate, the truth table, and its typical symbol.

FCSE, GIK Institute 18

 CE-221L – Digital Logic Design Lab

IC Circuit Diagram:

74LS08 IC 74LS08 Pinout

Basic Logic Gates Pin Diagram
 AND Gate (7408 IC)

 OR Gate (7432 / 4071 IC)

FCSE, GIK Institute 19

 CE-221L – Digital Logic Design Lab

 NOT Gate (7404 IC)

 NAND Gate (7400 IC)

 NOR Gate (7402 IC)

FCSE, GIK Institute 20

 CE-221L – Digital Logic Design Lab

 XOR Gate (7486 IC)

 XNOR Gate (74266 / 4077 IC)

74266 IC 4077 IC

FCSE, GIK Institute 21

 CE-221L – Digital Logic Design Lab

2.4 Truth Table of Basic Gates:

Following is the truth table for the above-mentioned logic gates.

Input-A Input-B AND NAND OR NOR XOR XNOR

0 0 0 1 0 1 0 1
0 1 0 1 1 0 1 0
1 0 0 1 1 0 1 0
1 1 1 0 1 0 0 1

Table 2.1: Truth table for logic gates

2.5 Procedure:
1. Get the ICs and other required apparatus/equipment from the lab staff.

2. Plug in the IC in the breadboard of the Trainer board and while doing so; try to
avoid touching the IC pins for safety reasons.

3. Apply 5V DC power supply (Vcc) on pin 14 and ground (GND) on 7.

4. The IC used has four gates each having two inputs (quad 2- in). PIN 1 and 2 are
inputs whereas pin 3 is the output of the gate. Similarly, the input pair for other
gates are (4, 5) & (8, 9) & (10, 11) and the output is obtained from PIN 6, 10, and 13
respectively.

5. Once you have wired the circuit, check it with your instructor. If approved, power up
your circuit.

6. The output should be connected to the LED on the Logic Trainer for monitoring
purposes.

7. Apply different input combinations at the input note down the corresponding output
and fill in the following truth table.

FCSE, GIK Institute 22

 CE-221L – Digital Logic Design Lab

2.6 Standard Logic Gates:

The seven most “standard” individual Digital Logic Gates are summarized below along
with their corresponding truth tables.

 Task # 01 — AND Gate (7408):

The AND gate is a digital logic gate with ‘n’ i/ps one o/p, which performs logical
conjunction based on the combinations of its inputs. The output of this gate is true only
when all the inputs are true. When one or more inputs of the AND gate’s i/ps are false,
then only the output of the AND gate is false.

A B A.B

AND Gate Representation Truth Table for AND Gate

 Task # 02 — OR Gate (4071/7432):

The OR gate is a digital logic gate with ‘n’ i/ps and one o/p, that performs logical
conjunction based on the combinations of its inputs. The output of the OR gate is true
only when one or more inputs are true. If all the i/ps of the gate are false, then only the
output of the OR gate is false.

FCSE, GIK Institute 23

 CE-221L – Digital Logic Design Lab

A B A+B

OR Gate Representation Truth Table for OR Gate

2.7 Inverting Logic Gates:

 Task # 03 — NAND Gate (7400):

A Boolean operator gives the value zero if and only if all the operands have a value of
one, and otherwise have a value of one (equivalent to NOT AND). The NAND gate can be
formed using the AND gate & NOT gate. The Boolean expression & truth table is shown
below.

A B (A.B)’

NAND Gate Representation NAND Gate Truth Table

 Task # 04 — NOR Gate (7402):

A HIGH output results if both the inputs to the gate are LOW; if one or both inputs is
HIGH, a LOW output results. The NOR gate can be formed using the OR gate & NOT
gate. The Boolean expression & truth table is shown below.

FCSE, GIK Institute 24

 CE-221L – Digital Logic Design Lab

A B (A+B)’

NOR Gate Representation NOR Gate Truth Table

2.8 Exclusive Logic Gates:

 Task # 05 — XOR Gate (7486):

The Ex-OR gate can be formed using the NOT, AND & OR gate. The Boolean expression &
truth table is shown below. This logic gate can be defined as the gate that gives high
output once any input of this is high. If both the inputs of this gate are high then the
output will be low.

A B (A ⊕ B)

XOR Gate Representation XOR Gate Truth Table

 Task # 06 — XNOR Gate (4077/74266):

The Ex-NOR gate can be formed using the EX-OR gate & NOT gate. The Boolean
expression & truth table is shown below. In this logic gate, when the output is high “1”
then both the inputs will be either “0” or “1”.

FCSE, GIK Institute 25

 CE-221L – Digital Logic Design Lab

A B (A ⊕ B)’

XNOR Gate Representation XNOR Gate Truth Table

2.9 Exclusive Logic Gates:

 Task # 07 — NOT Gate (7404):

The NOT gate is a digital logic gate with one input and one output that operates an
inverter operation of the input. The output of the NOT gate is the reverse of the input.
When the input of the NOT gate is true then the output will be false and vice versa. The
symbol and truth table of a NOT gate with one input is shown below. By using this gate,
we can implement NOR and NAND gates

A A’

NOT Gate Representation NOT Gate Truth Table

FCSE, GIK Institute 26

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can set, and Can set, up and
Can independently Cannot set or
Apparatus handle the handle the
set, operate, and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble It can assemble Cannot
Apparatus design according to design but inaccurately assemble
design within least time
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements are Measurements
Measurements are Measurements are
made and results are made and
Presentation made and results are made and results are
are presented results are not
of Results presented presented more
much more presented
most accurately accurately
accurately accurately

FCSE, GIK Institute 27

 CE-221L – Digital Logic Design Lab

Most of the Many of the Most of the

All the questions are questions are questions are questions are not
answered correctly answered with answered but answered and
Viva
with information almost all with minimal information is
relevant to the topic. information information not relevant to
relevant to the topic relevant to topic the topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

Lab-3
Boolean Algebra & Demorgan’s Law
3.1 Lab Objectives:
 Understand the fundamentals of Boolean Algebra.
 Learn the principles of DeMorgan's Laws and their significance in simplifying logical
expressions.
 Build circuits that represent given Boolean expressions.
 Apply De Morgan's Laws to simplify complex logic expressions and construct equivalent
circuits.
 Verify the correctness of constructed circuits by comparing their truth tables to the
expected results.

3.2 Equipment Required:

 Trainer Board
 Connecting wires / Jumper wires
 14 pin ICs
• NOT (7404)
• AND (7408)
• OR (7432/4071)
 Power supply

FCSE, GIK Institute 28

 CE-221L – Digital Logic Design Lab

3.3 Summary of Theory:

As well as the logic symbols “0” and “1” being used to represent a digital input or
output, we can also use them as constants for a permanently “Open” or “Closed” circuit
or contact respectively.
A set of rules or Laws of Boolean Algebra expressions have been invented to help reduce
the number of logic gates needed to perform a particular logic operation resulting in a
list of functions or theorems known commonly as the Laws of Boolean Algebra.
Boolean Algebra is the mathematics we use to analyze digital gates and circuits. We can
use these “Laws of Boolean” to both reduce and simplify a complex Boolean expression
in an attempt to reduce the number of logic gates required. Boolean Algebra is
therefore a system of mathematics based on logic that has its own set of rules or laws
which are used to define and reduce Boolean expressions.
The variables used in Boolean Algebra only have one of two possible values, a logic “0”
and a logic “1” but an expression can have an infinite number of variables all labeled
individually to represent inputs to the expression, For example, variables A, B, C, etc.,
giving us a logical expression of A + B = C, but each variable can ONLY be a 0 or a 1.
Examples of these individual laws of Boolean, rules, and theorems for Boolean Algebra
are given in the following table.

3.4 Truth Tables for the Laws of Boolean:

Boolean Equivalent Boolean Algebra
Description
Expression Switching Circuit Law or Rule

In parallel with
Annulment
A+1=1 closed = “CLOSED”

In parallel with
A+0=A Identity
open = “A”

FCSE, GIK Institute 29

 CE-221L – Digital Logic Design Lab

An in series with
A.1=A Identity
closed = “A”

An in series with
A.0=0 Annulment
open = “OPEN”

In parallel with
A+A=A Idempotent
A = “A”

An in series with
A.A=A Idempotent
A = “A”

NOT NOT A
NOT A’ = A Double Negation
(double negative) = “A”

In parallel with
A + A’ = 1 Complement
NOT A = “CLOSED”

An in series with
A . A’ = 0 Complement
NOT A = “OPEN”

A in parallel with B =
A+B = B+A Commutative
B in parallel with A

An in series with B =
A.B = B.A Commutative
B in series with A

FCSE, GIK Institute 30

 CE-221L – Digital Logic Design Lab

A brief description of the various Laws of Boolean are given below with A representing a
variable input.

3.5 Description of the Laws of Boolean Algebra:

 Annulment Law –

A term AND´ed with a “0” equals 0 or OR´ed with a “1” will equal 1.

 A . 0 = 0; A variable AND’ed with 0 is always equal to 0.

 A + 1 = 1; A variable OR’ed with 1 is always equal to 1.

 Identity Law –

A term OR´ed with a “0” or AND´ed with a “1” will always equal that term.

 A + 0 = A; A variable OR’ed with 0 is always equal to the variable.

 A . 1 = A; A variable AND’ed with 1 is always equal to the variable.

 Idempotent Law –

An input that is AND´ed or OR´ed with itself is equal to that input

 A + A = A; A variable OR’ed with itself is always equal to the variable.

 A. A = A; A variable AND’ed with itself is always equal to the variable.

 Complement Law –

A term AND´ed with its complement equals “0” and a term OR´ed with its complement
equals “1”.

 A . A’ = 0; A variable AND’ed with its complement is always equal to 0.

 A + A’ = 1; A variable OR’ed with its complement is always equal to 1.

 Commutative Law –

The order of application of two separate terms is not important.

FCSE, GIK Institute 31

 CE-221L – Digital Logic Design Lab

 A . B = B . A; The order in which 2 variables are AND’ed makes no difference.

 A + B = B + A; The order in which two variables are OR’ed makes no difference.

 Double Negation Law –

A term that is inverted twice is equal to the original term.

 (A’)’ = A; A double complement of a variable is always equal to the variable.

 Task-1:
Consider an example for the following Boolean function: F1 = x+y’z

The function F1 is equal to 1 if x is equal to 1 or if both y` and z are equal to 1, F1 is equal to 0

otherwise. The complement operation dictates that when y`=1 then y=0.
Therefore, we can say that F1=1 if x=1 or if y=0 and z=1. A Boolean function expresses the
logical expression for all possible values of the variables.

 Design a circuit for the given Function (i.e., F1 = x+y’z) on the Trainer Board.
 Verify the given Truth table.
 Truth table for F1:

X Y Z Y’ Y’Z F1

0 0 0 1 0 0
0 0 1 1 1 1
0 1 0 0 0 0
0 1 1 0 0 0
1 0 0 1 0 1
1 0 1 1 1 1
1 1 0 0 0 1
1 1 1 0 0 1

 Gate implementation of F1 = x+y’z

FCSE, GIK Institute 32

 CE-221L – Digital Logic Design Lab

 Task-2:
Consider the following equation: F2 = x’y + y’z

 Design a circuit for the given equation (i.e., F2 = x’y + y’z) on the Trainer Board.
 Complete and Verify the given Truth table.

 Truth table for F2:

X X’ Y Y’ Z X’Y Y’Z F2

 Gate implementation of F2:

FCSE, GIK Institute 33

 CE-221L – Digital Logic Design Lab

3.6 De Morgan’s Theorem:

DeMorgan’s Theorems are basically two sets of rules or laws developed from the
Boolean expressions for AND, OR and NOT using two input variables, A and B. These two
rules or theorems allow the input variables to be negated and converted from one form
of a Boolean function into an opposite form.
DeMorgan’s first theorem states that two (or more) variables NOR´ed together is the
same as the two variables inverted (Complement) and AND´ed, while the second
theorem states that two (or more) variables NAND´ed together is the same as the two
terms inverted (Complement) and OR´ed. That is replace all the OR operators with AND
operators, or all the AND operators with an OR operators.

DeMorgan’s First Theorem [(A.B)’ = A’+B’]

DeMorgan’s First theorem proves that when two (or more) input variables
are AND’ed and negated, they are equivalent to the OR of the complements of the
individual variables. Thus, the equivalent of the NAND function will be a negative-OR
function, proving that [(A.B)’ = A’+B’]. We can show this operation using the following
table.

DeMorgan’s Second Theorem [(A+B)’ = A’.B’]:

DeMorgan’s Second theorem proves that when two (or more) input variables
are OR’ed and negated, they are equivalent to the AND of the complements of the
individual variables. Thus the equivalent of the NOR function is a negative-AND function
proving that [(A+B)’ = A’.B’], and again we can show operation this using the following
truth table.

 Task-3:
 Design a circuit on the trainer board for DeMorgan’s first theorem.
 Verify the given Truth table

 Truth table for DeMorgans’ First Theorem:

Inputs Outputs

FCSE, GIK Institute 34

 CE-221L – Digital Logic Design Lab

A B A.B (A.B)’ A’ B’ A’ + B’

0 0 0 1 1 1 1

0 1 0 1 1 0 1

1 0 0 1 0 1 1

1 1 1 0 0 0 0

 DeMorgan’s First Law Implementation using Logic Gates:

 Task-4:
 Design a circuit on the trainer board for DeMorgan’s second theorem.
 Complete and Verify the given Truth table.
 Draw a logic diagram for DeMorgan’s second theorem.

 Truth table for DeMorgans’ Second Theorem:

Inputs Outputs

A B A+B (A+B)’ A’ B’ A’ . B’

FCSE, GIK Institute 35

 CE-221L – Digital Logic Design Lab

 DeMorgan’s Second Law Implementation using Logic Gates:

FCSE, GIK Institute 36

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can setup, and Can setup, and
Can independently Cannot setup or
Apparatus handle the handle the
setup, operate and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble Can assemble but Cannot
Apparatus design according to design inaccurately assemble
design within least time
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements
Measurements are Measurements are Measurements are
are made and
Presentation made and results are made and results are made and results
results are not
of Results presented presented more are presented
presented
most accurately accurately much accurately
accurately
Much of the Most of the
Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

FCSE, GIK Institute 37

 CE-221L – Digital Logic Design Lab

Date: ______________________

Lab-4
Combinational Logic Circuits (CLC)
Adders and Subtractors
4.1 Lab Objectives:
 Understand the concept of binary addition and subtraction.
 Design and construct a half adder and half subtractor circuit on a breadboard to perform
binary addition and subtraction.
 Design and construct full adder and full subtractor circuits by combining two half adders
and subtractors.
 Understand the concept of n-bit addition/subtraction by combining multiple
adders/subtractors.

4.2 Equipment Required:

 Trainer Board
 Connecting wires / Jumper wires
 14 pin ICs
• NOT (7404)
• AND (7408)
• OR (4071)
• XOR (7486)
• XNOR (4077)
 Power supply

Combinational Logic Circuits:

Combinational Logic Circuits are memoryless digital logic circuits whose output at any
instant in time depends only on the combination of its inputs.

FCSE, GIK Institute 38

 CE-221L – Digital Logic Design Lab

In the combinational circuits, different logic gates are used to design encoder,
multiplexer, decoder & de-multiplexer. These circuits have some characteristics like the
output of this circuit mainly depends on the levels which are there at input terminals at
any time. This circuit doesn’t include any memory. The earlier state of the input doesn’t
have any influence on the current state of this circuit. The inputs and outputs of a
combinational circuit are ‘n’ no. of inputs & ‘m’ no. of outputs. Some of the
combinational circuits are half adder and full adder, subtractor, encoder, decoder,
multiplexer, and demultiplexer.
Unlike Sequential Logic Circuits whose outputs are dependent on both their present
inputs and their previous output state giving them some form of Memory. The outputs
of Combinational Logic Circuits are only determined by the logical function of their
current input state, logic “0” or logic “1”, at any given instant in time.
The result is that combinational logic circuits have no feedback, and any changes to the
signals being applied to their inputs will immediately have an effect at the output. In
other words, in a Combinational Logic Circuit, the output is dependent at all times on
the combination of its inputs. Thus, a combinational circuit is memoryless.
So, if one of its inputs condition changes state, from 0-1 or 1-0, so too will the resulting
output as by default combinational logic circuits have “no memory”, “timing” or
“feedback loops” within their design.
Combinational Logic Circuits are made up from basic logic NAND, NOR or NOT gates
that are “combined” or connected together to produce more complicated switching
circuits. These logic gates are the building blocks of combinational logic circuits. An
example of a combinational circuit is a decoder, which converts the binary code data
present at its input into a number of different output lines, one at a time producing an
equivalent decimal code at its output.

4.3 Half Adder (Binary Adder):

Half adder is a combinational circuit that performs simple addition of two binary
numbers. it adds two binary digits where the input bits are termed as augend and

FCSE, GIK Institute 39

 CE-221L – Digital Logic Design Lab

addend and the result will be two outputs one is the sum and the other is carry. To
perform the sum operation, XOR is applied to both the inputs, and AND gate is applied
to both inputs to produce carry.
The block diagram of a half adder is shown below.

 Task-1:
 Design a combinational logic circuit that performs arithmetic operation for adding two
bits.

 Verify the given Truth table and Boolean expression.

 Truth Table:

Total number of inputs = n = 2

Total number of outputs = 2^n = 2^2 = 4

 Boolean Expression:
Sum = S = A’B+AB’ = A ⊕ B
Carry = C = A.B

FCSE, GIK Institute 40

 CE-221L – Digital Logic Design Lab

 Logic Diagram:

4.4 Full Adder (Binary Adder):

Full adder is a digital circuit used to calculate the sum of three binary bits which is the
main difference between this and half adder. Full adders are complex and difficult to
implement when compared to half adders. Two of the three bits are same as before
which are A, the augend bit and B, the addend bit. The additional third bit is carry bit
from the previous stage and is called Carry – in generally represented by CIN. It
calculates the sum of three bits along with the carry. The output carry is called Carry –
out and is represented by COUT.
The block diagram of a full adder with A, B and CIN as inputs and S, Cout as outputs is
shown below:

FCSE, GIK Institute 41

 CE-221L – Digital Logic Design Lab

 Task-2:
 Design a combinational logic circuit that performs arithmetic operation for adding
three bits.
 Complete and verify the given truth table and Boolean expressions.
 Draw the Logic Diagram for Full Adder circuit.

 Truth Table:
Total number of inputs = n = 3
Total number of outputs = 2^n = 2^3 = 8

Inputs Outputs

A B Cin Sum Carry

Boolean Expression:

Sum = A’B’Cin + A’BC’in + AB’C’in + ABCin = A ⊕ B ⊕ Cin

Carry = A’BCin + A’BCin + ABC’in + ABCin = A.B + (A⊕B).Cin

FCSE, GIK Institute 42

 CE-221L – Digital Logic Design Lab

 Logic Diagram:

4.5 Half Subtractor (Binary Subtractor):

As their name implies, a Binary Subtractor is a decision-making circuit that subtracts
two binary numbers from each other, for example, X – Y to find the resulting difference
between the two numbers.
A half subtractor is a logical circuit that performs a subtraction operation on two binary
digits. The half subtractor produces a sum and a borrow bit for the next stage.

The block diagram of a half subtractor is shown below.

FCSE, GIK Institute 43

 CE-221L – Digital Logic Design Lab

 Task-3:
 Design a combinational logic circuit that performs arithmetic operation for subtracting
two bits.
 Verify the given Truth table and Boolean expressions.

 Truth Table:
Input Output

Total number of inputs = n = 2 X Y Difference Borrow

Total number of outputs = 2^n = 2^2 = 4 0 0 0 0

0 1 1 1

1 0 1 0

1 1 0 0

 Boolean Expression:

Difference = D = X’Y+XY’ = X ⊕ Y
Borrow = B = X’.Y

 Logic Diagram:

FCSE, GIK Institute 44

 CE-221L – Digital Logic Design Lab

4.6 Full Subtractor (Binary Subtractor):

The main difference between the Full Subtractor and the previous Half
Subtractor circuit is that a full subtractor has three inputs. The two single bit data
inputs X (minuend) and Y (subtrahend) the same as before plus an additional Borrow-
in (B-in) input to receive the borrow generated by the subtraction process from a previous
stage as shown below.
The block diagram of a Full subtractor is shown below.

 Task-4:
 Design a combinational logic circuit that performs arithmetic operation for
subtracting three bits.
 Complete and verify the given Truth table and Boolean expressions.
 Draw the Logic diagram for Full Subtractor circuit.

 Truth Table:

FCSE, GIK Institute 45

 CE-221L – Digital Logic Design Lab

Total number of inputs = n = 3

Total number of outputs = 2^n = 2^3 = 8

Input Output

X Y Bin Difference Bout

 Boolean Expression:
Difference = D = (X’.Y’.BIN) + (X’.Y.B’IN) + (X.Y’.B’IN) + (X.Y.BIN)

= X ⊕ Y ⊕ BIN

Borrow-Out = Bout = (X’.Y’.BIN) + (X’.Y.B’IN) + (X’.Y.BIN) + (X.Y.BIN)

= X’.Y + X’. BIN + Y. BIN

 Logic Diagram:

FCSE, GIK Institute 46

 CE-221L – Digital Logic Design Lab

4.7 Two-bit Adder:

A two-bit adder is a circuit that adds together two, 2-bit numbers. The first number, A, can be
represented using bits A1 and A0. The second number, B, is similarly represented. The
output consists of the sum of A and B, represented as two bits (S1 and S0) and one carry bit
(C).

Schematic diagram of a 2-bit adder: (a) 2-bit half adder is implemented by joining 1-bit half
adder and 1-bit full adder; (b) 2-bit full adder is implemented by joining two 1-bit full adders.

 Task-5:
 Design a combinational logic circuit that performs addition of two, 2-
bit numbers.

 Complete and verify the given Truth table.

 Draw the Logic Diagram for this circuit.

 Truth Table:

Inputs Outputs

FCSE, GIK Institute 47

 CE-221L – Digital Logic Design Lab

A1 A0 B1 B0 C1 S1 S0

 Logic Diagram:

FCSE, GIK Institute 48

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can setup, and Can setup, and
Can independently Cannot setup or
Apparatus handle the handle the
setup, operate and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble Can assemble but Cannot
Apparatus design according to design inaccurately assemble
design within least time
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements
Measurements are Measurements are Measurements are
are made and
Presentation made and results are made and results are made and results
results are not
of Results presented presented more are presented
presented
most accurately accurately much accurately
accurately

FCSE, GIK Institute 49

 CE-221L – Digital Logic Design Lab

Much of the Most of the

Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

Lab # 05
Combinational Logic Circuits (CLC)
Encoders & Decoders
5.1 Lab Objectives:
 Understand the fundamental concepts of encoding and decoding in digital systems.
 Learn the purpose and applications of encoders and decoders.
 Design and construct simple encoder and decoder circuits.
 Create a more advanced encoder (Decimal to BCD encoder).

5.2 Equipment Required:

 Trainer Board
 Connecting wires / Jumper wires
 14 pin ICs
• NOT (7404)
• AND (7408)
• OR (7432/4071)
 Power supply

5.3 Decoders:

FCSE, GIK Institute 50

 CE-221L – Digital Logic Design Lab

The name “Decoder” means to translate or decode coded information from one format
into another, so a binary decoder transforms “n” binary input signals into an equivalent
code using 2n outputs.
Binary Decoders are another type of digital logic device that has inputs of 2-bit, 3-bit or
4-bit codes depending upon the number of data input lines, so a decoder that has a set
of two or more bits will be defined as having an n-bit code, and therefore it will be
possible to represent 2n possible values. Thus, a decoder generally decodes a binary
value into a non-binary one by setting exactly one of its n outputs to logic “1”.
If a binary decoder receives n inputs (usually grouped as a single Binary or Boolean
number) it activates one and only one of its 2n outputs based on that input with all other
outputs deactivated.
A Binary Decoder converts coded inputs into coded outputs, where the input and output
codes are different, and decoders are available to “decode” either a Binary or BCD (8421
code) input pattern to typically a Decimal output code. Commonly available BCD-to-
Decimal decoders include the TTL 7442 or the CMOS 4028. Generally, a decoders output
code normally has more bits than its input code and practical “binary decoder” circuits
include, 2-to-4, 3-to-8 and 4-to-16 line configurations.

2-to-4 Line Decoders:

This simple example above of a 2-to-4 line binary decoder consists of an array of
four AND gates. The 2 binary inputs labelled A and B are decoded into one of 4 outputs,
hence the description of 2-to-4 binary decoder.
The binary inputs A and B determine which output line from Q0 to Q3 is “HIGH” at logic
level “1” while the remaining outputs are held “LOW” at logic “0” so only one output
can be active (HIGH) at any one time. Therefore, whichever output line is “HIGH”
identifies the binary code present at the input, in other words it “de-codes” the binary
input.
Some binary decoders have an additional input pin labelled “Enable” that controls the
outputs from the device. This extra input allows the decoders outputs to be turned
“ON” or “OFF” as required. These types of binary decoders are commonly used as
“memory address decoders” in microprocessor memory applications. The block
diagram of 2 to 4 decoder is shown in the following figure.

FCSE, GIK Institute 51

 CE-221L – Digital Logic Design Lab

2-to-4 Line Binary Decoder

 Task-1:
 Design a circuit for 2-to-4 Line DECODER with E=1 (i.e., enable is HIGH) on the trainer
board.
 Verify the given truth table and the Boolean expression.
 Draw the Logic Diagram for 2-to-4 line decoder circuit.

 Truth Table:

Enable Inputs Outputs

E A1 A0 Y3 Y2 Y1 Y0

0 X X 0 0 0 0

1 0 0 0 0 0 1

1 0 1 0 0 1 0

FCSE, GIK Institute 52

 CE-221L – Digital Logic Design Lab

1 1 0 0 1 0 0

1 1 1 1 0 0 0

 Boolean Expression:
Y0 = E.A1’.A0’

Y1 = E.A1’.A0

Y2 = E.A1.A0’

Y3 = E.A1.A0

 Logic Diagram:

FCSE, GIK Institute 53

 CE-221L – Digital Logic Design Lab

3-to-8 Line Decoders:

let us implement 3 to 8 decoder using 2 to 4 decoders. We know that 2 to 4 Decoder has
two inputs, A1 & A0 and four outputs, Y3 to Y0. Whereas, 3 to 8 Decoder has three inputs A 2,
A1 & A0 and eight outputs, Y7 to Y0.
Therefore, we require two 2 to 4 decoders for implementing one 3 to 8 decoder. The block
diagram of 3 to 8 decoder using 2 to 4 decoders is shown in the following figure.

3-to-8 Line Binary Decoder

FCSE, GIK Institute 54

 CE-221L – Digital Logic Design Lab

 Task-2:
 Design a circuit for 3-to-8 Line DECODER with E=1 (i.e., enable is HIGH) on the trainer
board.
 Complete and verify the given truth table.
 Write down the Boolean expression for the Output terms.
 Draw the Logic Diagram for 3-to-8 line decoder circuit.

 Truth Table:

Enable Inputs Outputs

E A2 A1 A0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0

0 X X X

1 0 0 0

1 0 0 1

1 0 1 0

1 0 1 1

1 1 0 0

1 1 0 1

1 1 1 0

1 1 1 1

FCSE, GIK Institute 55

 CE-221L – Digital Logic Design Lab

 Boolean Expression:

Y0 = _________________________________

Y1 = _________________________________

Y2 = _________________________________

Y3 = _________________________________

Y4 = _________________________________

Y5 = _________________________________

Y6 = _________________________________

Y7 = _________________________________

 Logic Diagram:

FCSE, GIK Institute 56

 CE-221L – Digital Logic Design Lab

5.4 Encoders:
An Encoder is a combinational circuit that performs the reverse operation of Decoder. It
has maximum of 2n input lines and ‘n’ output lines. It will produce a binary code
equivalent to the input, which is active High. Therefore, the encoder encodes 2 n input
lines with ‘n’ bits. It is optional to represent the enable signal in encoders.
Digital Encoder more commonly called a Binary Encoder takes ALL its data inputs one at
a time and then converts them into a single encoded output. So we can say that a binary
encoder, is a multi-input combinational logic circuit that converts the logic level “1” data
at its inputs into an equivalent binary code at its output.
Generally, digital encoders produce outputs of 2-bit, 3-bit or 4-bit codes depending
upon the number of data input lines. An “n-bit” binary encoder has 2n input lines and n-
bit output lines with common types that include 4-to-2, 8-to-3 and 16-to-4 line
configurations.
The output lines of a digital encoder generate the binary equivalent of the input line
whose value is equal to “1” and are available to encode either a decimal or hexadecimal
input pattern to typically a binary or “B.C.D” (binary coded decimal) output code.

4-to-2 Line Encoders:

The 4 to 2 Encoder consists of four inputs Y3, Y2, Y1 & Y0 and two outputs A1 & A0. At
any time, only one of these 4 inputs can be ‘1’ in order to get the respective binary code
at the output.
The block diagram of 4 to 2 Encoder is shown in the following figure.

4-to-2 Line Binary Encoder

FCSE, GIK Institute 57

 CE-221L – Digital Logic Design Lab

 Task-3:
 Design a circuit for 4-to-2 Line ENCODER on the trainer board.
 Verify the given truth table and the Boolean expression.
 Draw the Logic Diagram for 4-to-2 Line decoder circuit.

 Truth Table:

Inputs Outputs
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

 Boolean Expression:
A1 = Y3 + Y2 ; A0 = Y3 + Y1

 Logic Diagram:

FCSE, GIK Institute 58

 CE-221L – Digital Logic Design Lab

8-to-3 Line Encoders:

The working and usage of 8:3 Encoder is also similar to the 4:2 Encoder except for the
number of input and output pins. The 8:3 Encoder is also called as Octal to Binary Encoder.
Octal to binary Encoder has eight inputs, Y7 to Y0 and three outputs A2, A1 & A0. Octal to
binary encoder is nothing but 8 to 3 encoder. At any time, only one of these eight inputs can
be ‘1’ in order to get the respective binary code. The block diagram of octal to binary
Encoder is shown in the following figure.

4-to-2 Line Binary Encoder

FCSE, GIK Institute 59

 CE-221L – Digital Logic Design Lab

 Task-4:
 Design a circuit 8-to-3 Line ENCODER on the trainer board.
 Complete and verify the given truth table.
 Write down the Boolean expression for the Output terms.
 Draw the Logic Diagram for 8-to-3 Line ENCODER circuit.

 Truth Table:

Inputs Outputs
Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 A2 A1 A0

 Boolean Expression:
A2 = ______________________________ ; A0 = _________________________

FCSE, GIK Institute 60

 CE-221L – Digital Logic Design Lab

A1 = ______________________________

 Logic Diagram:

FCSE, GIK Institute 61

 CE-221L – Digital Logic Design Lab

Decimal to BCD Encoder:

A decimal to BCD (binary coded decimal) encoder is also known as 10-line to 4-line encoder.
It accepts 10- inputs and produces a 4-bit output corresponding to the activated decimal
input. Figure-5 shows the logic symbol of decimal to BCD encoder.

Decimal to BCD Encoder

 Task-5:
 Design a circuit for Decimal to BCD Encoder on the trainer board.
 Complete and verify the given truth table.
 Write down the Boolean expression for the Output terms.
 Draw the Logic Diagram for Decimal to BCD ENCODER circuit.

FCSE, GIK Institute 62

 CE-221L – Digital Logic Design Lab

 Truth Table:
No. Inputs Outputs

I9 I8 I7 I6 I5 I4 I3 I2 I1 I0 Y3 Y2 Y1 Y0

0 0 0 0 0 0 0 0 0 0 1

1 0 0 0 0 0 0 0 0 1 0

2 0 0 0 0 0 0 0 1 0 0

3 0 0 0 0 0 0 1 0 0 0

4 0 0 0 0 0 1 0 0 0 0

5 0 0 0 0 1 0 0 0 0 0

6 0 0 0 1 0 0 0 0 0 0

7 0 0 1 0 0 0 0 0 0 0

8 0 1 0 0 0 0 0 0 0 0

9 1 0 0 0 0 0 0 0 0 0

 Boolean Expression:
A3 = _________________________________

A2 = _________________________________

A1 = _________________________________

FCSE, GIK Institute 63

 CE-221L – Digital Logic Design Lab

A0 = _________________________________

 Logic Diagram:

FCSE, GIK Institute 64

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can setup, and Can setup, and
Can independently Cannot setup or
Apparatus handle the handle the
setup, operate and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble Can assemble but Cannot
Apparatus design according to design inaccurately assemble
design within least time
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements
Measurements are Measurements are Measurements are
are made and
Presentation made and results are made and results are made and results
results are not
of Results presented presented more are presented
presented
most accurately accurately much accurately
accurately
Much of the Most of the
Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

FCSE, GIK Institute 65

 CE-221L – Digital Logic Design Lab

Date: ______________________

Lab # 06
Combinational Logic Circuits (CLC)
Multiplexers & Demultiplexers
6.1 Lab Objectives:
 Understand the fundamental concepts of multiplexers and demultiplexers in digital
systems.
 Learn the purpose and applications of multiplexers and demultiplexers.
 Design and construct different multiplexers and demultiplexers on breadboard.

6.2 Equipment Required:

 Trainer Board
 Connecting wires / D Jumper wires
 14 pin ICs
• NOT (7404)
• AND (7408)
• OR (7432/4071)
 Power supply

6.3 Multiplexers (MUX):

Multiplexing is the generic term used to describe the operation of sending one or more
analogue or digital signals over a common transmission line at different times or speeds
and as such, the device we use to do just that is called a Multiplexer.
The multiplexer, shortened to “MUX” or “MPX”, is a combinational logic circuit designed
to switch one of several input lines through to a single common output line by the
application of a control signal. Multiplexers operate like very fast acting multiple
position rotary switches connecting or controlling multiple input lines called “channels”
one at a time to the output.
Multiplexers, or MUX’s, can be either digital circuits made from high speed logic gates
used to switch digital or binary data or they can be analogue types using transistors,

FCSE, GIK Institute 66

 CE-221L – Digital Logic Design Lab

MOSFET’s or relays to switch one of the voltage or current inputs through to a single
output.

The most basic type of multiplexer device is that of a one-way rotary switch as shown.

Basic Multiplexing Switch

The rotary switch, also called a wafer switch as each layer of the switch is known as a
wafer, is a mechanical device whose input is selected by rotating a shaft. In other words,
the rotary switch is a manual switch that you can use to select individual data or signal
lines simply by turning its inputs “ON” or “OFF”. So how can we select each data input
automatically using a digital device.
In digital electronics, multiplexers are also known as data selectors because they can
“select” each input line, are constructed from individual Analogue Switches encased in
a single IC package as opposed to the “mechanical” type selectors such as normal
conventional switches and relays.
Generally, the selection of each input line in a multiplexer is controlled by an additional
set of inputs called control lines and according to the binary condition of these control
inputs, either “HIGH” or “LOW” the appropriate data input is connected directly to the
output. Normally, a multiplexer has an even number of 2n data input lines and a number
of “control” inputs that correspond with the number of data inputs.
Note that multiplexers are different in operation to Encoders. Encoders are able to
switch an n-bit input pattern to multiple output lines that represent the binary coded
(BCD) output equivalent of the active input.

FCSE, GIK Institute 67

 CE-221L – Digital Logic Design Lab

4-to-1 Channel Multiplexer (4x1 MUX):

4x1 Multiplexer has four data inputs I3, I2, I1 & I0, two selection lines s1 & s0 and one output Y.
One of these 4 inputs will be connected to the output based on the combination of inputs
present at these two selection lines.
The block diagram of 4x1 Multiplexer is shown in the following figure.

4 x 1 Multiplexer

 Task-1:
 Design a circuit for 4x1 MUX on the trainer board.
 Verify the given truth table and the Boolean expression.
 Draw the Logic Diagram for 4x1 MUX circuit.

 Truth Table:

Inputs Select Lines Output

I3 I2 I1 I0 S1 S0 Y
0 0 0 1 0 0 I0
0 0 1 0 0 1 I1
0 1 0 0 1 0 I2

FCSE, GIK Institute 68

 CE-221L – Digital Logic Design Lab

1 0 0 0 1 1 I3

 Boolean Expression:
Y = I0 + I 1 + I 2 + I 3
Y = S1’.S0’.I0 + S1’.S0.I1 + S1’.S0.I2 + S1.S0.I3

 Logic Diagram:

FCSE, GIK Institute 69

 CE-221L – Digital Logic Design Lab

8-to-1 Channel Multiplexer (8x1 MUX):

In this section, let us implement 8x1 Multiplexer using 4x1 Multiplexers and 2x1
Multiplexer. We know that 4x1 Multiplexer has 4 data inputs, 2 selection lines and one
output. Whereas 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output.
So, we require two 4x1 Multiplexers in first stage in order to get the 8 data inputs. Since,
each 4x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.
Let the 8x1 Multiplexer has eight data inputs I 7 to I0, three selection lines s2, s1 & s0 and one
output Y. The block diagram of 4x1 Multiplexer is shown in the following figure.

8 x 1 Multiplexer
The same selection lines, s1 & s0 are applied to both 4x1 Multiplexers. The data inputs of
upper 4x1 Multiplexer are I7 to I4 and the data inputs of lower 4x1 Multiplexer are I 3 to I0.

FCSE, GIK Institute 70

 CE-221L – Digital Logic Design Lab

Therefore, each 4x1 Multiplexer produces an output based on the values of selection lines,
s1 & s 0.
The outputs of first stage 4x1 Multiplexers are applied as inputs of 2x1 Multiplexer that is
present in second stage. The other selection line, s2 is applied to 2x1 Multiplexer.
 If s2 is zero, then the output of 2x1 Multiplexer will be one of the 4 inputs I 3 to
I0 based on the values of selection lines s1 & s0.
 If s2 is one, then the output of 2x1 Multiplexer will be one of the 4 inputs I 7 to
I4 based on the values of selection lines s1 & s0.
Therefore, the overall combination of two 4x1 Multiplexers and one 2x1 Multiplexer
performs as one 8x1 Multiplexer.

Similarly, we can implement 16x1 Multiplexer using 8x1 Multiplexers and 2x1 Multiplexer.
We know that 8x1 Multiplexer has 8 data inputs, 3 selection lines and one output. Whereas,
16x1 Multiplexer has 16 data inputs, 4 selection lines and one output.
So, we require two 8x1 Multiplexers in first stage in order to get the 16 data inputs. Since,
each 8x1 Multiplexer produces one output, we require a 2x1 Multiplexer in second stage by
considering the outputs of first stage as inputs and to produce the final output.

 Task-2:
 Design a circuit for 8x1 MUX on the trainer board.
 Complete and verify the given truth table.
 Write down the Boolean expression for the Output terms.
 Draw the Logic Diagram for 8x1 MUX circuit.

FCSE, GIK Institute 71

 CE-221L – Digital Logic Design Lab

 Truth Table:

Inputs Select Lines Output

I7 I6 I5 I4 I3 I2 I1 I0 S2 S1 S0 Y

 Boolean Expression:

Y = _____________________________

Y = __________________________________________________

FCSE, GIK Institute 72

 CE-221L – Digital Logic Design Lab

 Logic Diagram:

FCSE, GIK Institute 73

 CE-221L – Digital Logic Design Lab

6.4 De-Multiplexers (De-Mux):

De-Multiplexer is a combinational circuit that performs the reverse operation of
Multiplexer. It has single input, ‘n’ selection lines and maximum of 2 n outputs. The input
will be connected to one of these outputs based on the values of selection lines.
Since there are ‘n’ selection lines, there will be 2 n possible combinations of zeros and
ones. So, each combination can select only one output. De-Multiplexer is also called
as De-Mux.

1-to-4 Channel De-multiplexer (1x4 De-Mux):

1x4 De-Multiplexer has one input I, two selection lines, s 1 & s0 and four outputs Y3, Y2,
Y1 &Y0. The single input ‘I’ will be connected to one of the four outputs, Y 3 to Y0 based on
the values of selection lines s1 & s0.
The block diagram of 1x4 De-Multiplexer is shown in the following figure.

1 x 4 De-Multiplexer

FCSE, GIK Institute 74

 CE-221L – Digital Logic Design Lab

 Task-3:
 Design a circuit for 1x4 De-Mux on the trainer board.
 Verify the given truth table and the Boolean expression.
 Draw the Logic Diagram for 1x4 De-Mux circuit.

 Truth Table:

Input Select Lines Outputs

I/p S1 S0 Y3 Y2 Y1 Y0

I 0 0 0 0 0 I

I 0 1 0 0 I 0

I 1 0 0 I 0 0

I 1 1 I 0 0 0

 Boolean Expression:

Y3 = S1.S0.I

Y2 = S1.S0’.I

Y1 = S1’.S0.I

Y0 = S1’.S0’.I

FCSE, GIK Institute 75

 CE-221L – Digital Logic Design Lab

 Logic Diagram:

FCSE, GIK Institute 76

 CE-221L – Digital Logic Design Lab

1-to-8 Channel De-multiplexer (1x8 De-Mux):

In this section, let us implement 1x8 De-Multiplexer using 1x4 De-Multiplexers and 1x2 De-
Multiplexer. We know that 1x4 De-Multiplexer has single input, two selection lines and four
outputs. Whereas, 1x8 De-Multiplexer has single input, three selection lines and eight
outputs.
So, we require two 1x4 De-Multiplexers in second stage in order to get the final eight
outputs. Since, the number of inputs in second stage is two, we require 1x2 De-
Multiplexer in first stage so that the outputs of first stage will be the inputs of second stage.
Input of this 1x2 De-Multiplexer will be the overall input of 1x8 De-Multiplexer.
Let the 1x8 De-Multiplexer has one input I, three selection lines s 2, s1 & s0 and outputs Y7 to
Y0. The block diagram of 1x8 De-Multiplexer is shown in the following figure.

FCSE, GIK Institute 77

 CE-221L – Digital Logic Design Lab

1 x 8 De-Multiplexer

The common selection lines, s1 & s0 are applied to both 1x4 De-Multiplexers. The outputs of
upper 1x4 De-Multiplexer are Y7 to Y4 and the outputs of lower 1x4 De-Multiplexer are Y 3 to
Y0 .
The other selection line, s2 is applied to 1x2 De-Multiplexer. If s 2 is zero, then one of the
four outputs of lower 1x4 De-Multiplexer will be equal to input, I based on the values of
selection lines s1 & s0. Similarly, if s2 is one, then one of the four outputs of upper 1x4 De-
Multiplexer will be equal to input, I based on the values of selection lines s1 & s0.
Similarly, we can implement 1x16 De-Multiplexer using 1x8 De-Multiplexers and 1x2 De-
Multiplexer. We know that 1x8 De-Multiplexer has single input, three selection lines and
eight outputs. Whereas, 1x16 De-Multiplexer has single input, four selection lines and
sixteen outputs.
So, we require two 1x8 De-Multiplexers in second stage in order to get the final sixteen
outputs. Since, the number of inputs in second stage is two, we require 1x2 De-
Multiplexer in first stage so that the outputs of first stage will be the inputs of second stage.
Input of this 1x2 De-Multiplexer will be the overall input of 1x16 De-Multiplexer.

 Task-4:
 Design a circuit for 1x8 De-Mux on the trainer board.
 Complete and verify the given truth table.
 Write down the Boolean expression for the Output terms.
 Draw the Logic Diagram for 1x8 De-Mux circuit.

FCSE, GIK Institute 78

 CE-221L – Digital Logic Design Lab

 Truth Table:

Input Select Lines Outputs

I/p S2 S1 S0 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0
I

 Boolean Expression:

Y7 = _____________________________________ ; Y3 = ________________________________

Y6 = _____________________________________ ; Y2 = ________________________________

Y5 =______________________________________ ; Y1 = ________________________________

Y4 = _____________________________________ ; Y0 = ________________________________

FCSE, GIK Institute 79

 CE-221L – Digital Logic Design Lab

 Logic Diagram:

FCSE, GIK Institute 80

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can setup, and Can setup, and
Can independently Cannot setup or
Apparatus handle the handle the
setup, operate and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble Can assemble but Cannot
Apparatus design according to design inaccurately assemble
design within least time
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements
Measurements are Measurements are Measurements are
are made and
Presentation made and results are made and results are made and results
results are not
of Results presented presented more are presented
presented
most accurately accurately much accurately
accurately
Much of the Most of the
Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

FCSE, GIK Institute 81

 CE-221L – Digital Logic Design Lab

Lab-7
Sequential Logic Circuits (SLC)
Flip Flops
7.1 Lab Objectives:
 Understand the principles of sequential logic circuits.
 Understand the concept of feedback in flip-flop operation.
 Construct SR and D flip-flop circuit on a breadboard.
 Verify the functionality of the flip-flop by applying different input scenarios.
 Understand the working of JK and T flip-flop.
 Construct JK and T flip-flop circuit on a breadboard.
 Verify the functionality of the flip-flop by applying different input scenarios.

7.2 Equipment Required:

 Trainer Board
 Connecting wires / Jumper wires
 14 pin ICs
• NOT (7404)
• AND (7408)
• NAND (7400)
• NOR (7402)
 Power supply

7.3 Sequential Logic Circuits:

We discussed various combinational circuits in earlier chapters. All these circuits have a
set of outputs, which depends only on the combination of present inputs. The following
figure shows the block diagram of sequential circuit.

FCSE, GIK Institute 82

 CE-221L – Digital Logic Design Lab

This sequential circuit contains a set of inputs and outputs. The outputs of sequential
circuit depend not only on the combination of present inputs but also on the previous
outputs. Previous output is nothing but the present state. Therefore, sequential circuits
contain combinational circuits along with memory storage elements. Some sequential
circuits may not contain combinational circuits, but only memory elements.
The following table shows the differences between combinational circuits and
sequential circuits.

Types of Sequential Circuits:

Following are the two types of sequential circuits:
 Asynchronous sequential circuits
 Synchronous sequential circuits

FCSE, GIK Institute 83

 CE-221L – Digital Logic Design Lab

Asynchronous sequential circuits:

If some or all the outputs of a sequential circuit do not change affect with respect to
active transition of clock signal, then that sequential circuit is called Asynchronous
sequential circuit. That means, all the outputs of asynchronous sequential circuits do
not change affect at the same time. Therefore, most of the outputs of asynchronous
sequential circuits are not in synchronous with either only positive edges or only
negative edges of clock signal.

Synchronous sequential circuits:

If all the outputs of a sequential circuit change affect with respect to active transition of
clock signal, then that sequential circuit is called Synchronous sequential circuit. That
means, all the outputs of synchronous sequential circuits change affect at the same
time. Therefore, the outputs of synchronous sequential circuits are in synchronous with
either only positive edges or only negative edges of clock signal.

7.4 Clock Signal and Triggering:

Clock Signal:
Clock signal is a periodic signal and its ON time and OFF time need not be the same. We
can represent the clock signal as a square wave, when both its ON time and OFF time
are same. This clock signal is shown in the following figure.

FCSE, GIK Institute 84

 CE-221L – Digital Logic Design Lab

In the above figure, square wave is considered as clock signal. This signal stays at logic
High 5V for some time and stays at logic Low 0V for equal amount of time. This pattern
repeats with some time period. In this case, the time period will be equal to either twice
of ON time or twice of OFF time.
The reciprocal of the time period of clock signal is known as the frequency of the clock
signal. All sequential circuits are operated with clock signal. So, the frequency at which
the sequential circuits can be operated accordingly the clock signal frequency has to be
chosen.

Triggering:
While applying the clock pulse to the flip flop, it gets triggered by two ways, Level
triggering and edge triggering.

Level Triggering:
In this, the flip flop is triggered only during the high-level or the low level of the clock
pulse. In other words, the output changes its state, when active low or high level is
maintained at the clock signal. Based on the level of triggering, it is of two types:-
 Positive Level Triggering — If the sequential circuit is operated with the clock
signal when it is in Logic High, then that type of triggering is known as Positive
level triggering. It is highlighted in below figure.

 Negative Level Triggering — If the sequential circuit is operated with the clock
signal when it is in Logic Low, then that type of triggering is known as Negative
level triggering. It is highlighted in the following figure.

FCSE, GIK Institute 85

 CE-221L – Digital Logic Design Lab

Edge Triggering:
In edge triggering, the flip flop changes its state during the positive edge or negative
edge of the clock pulse. There are two types of edge triggering.
 Positive Edge Triggering — If the sequential circuit is operated with the clock
signal that is transitioning from Logic Low to Logic High, then that type of
triggering is known as Positive edge triggering. It is also called as rising edge
triggering. It is shown in the following figure.

 Negative Edge Triggering — If the sequential circuit is operated with the clock
signal that is transitioning from Logic High to Logic Low, then that type of
triggering is known as Negative edge triggering. It is also called as falling edge
triggering. It is shown in the following figure.

FCSE, GIK Institute 86

 CE-221L – Digital Logic Design Lab

7.5 Latches:
There are two types of memory elements based on the type of triggering that is suitable
to operate it.
 Latches
 Flip-flops
Latches operate with enable signal, which is level sensitive. Whereas flip-flops are edge
sensitive. Let us discuss about SR Latch & D Latch one by one.

SR Latch:
SR Latch is also called as Set Reset Latch. This latch affects the outputs as long as the
enable, E is maintained at ‘1’. The circuit diagram of SR Latch is shown in the following
figure.

FCSE, GIK Institute 87

 CE-221L – Digital Logic Design Lab

This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The upper NOR gate has
two inputs R & complement of present state, Q(t)’ and produces next state, Q(t+1)
when enable, E is ‘1’.
Similarly, the lower NOR gate has two inputs S & present state, Q t and produces
complement of next state, Qt+1t+1’ when enable, E is ‘1’.
We know that a 2-input NOR gate produces an output, which is the complement of
another input when one of the input is ‘0’. Similarly, it produces ‘0’ output, when one of
the input is ‘1’.
 If S = 1, then next state Q(t+1) will be equal to ‘1’ irrespective of present state,
Q(t) values.
 If R = 1, then next state Q(t+1) will be equal to ‘0’ irrespective of present state,
Q(t) values.
At any time, only of those two inputs should be ‘1’. If both inputs are ‘1’, then the next
state Q(t+1) value is undefined.
The following table shows the state table of SR latch.

S R Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 -

Therefore, SR Latch performs three types of functions such as Hold, Set & Reset based
on the input conditions.

D Latch:
There is one drawback of SR Latch. That is the next state value can’t be predicted when
both the inputs S & R are one. So, we can overcome this difficulty by D Latch. It is also
called as Data Latch. The circuit diagram of D Latch is shown in the following figure.

FCSE, GIK Institute 88

 CE-221L – Digital Logic Design Lab

This circuit has single input D and two outputs Q(t) & Q(t)’. D Latch is obtained from SR
Latch by placing an inverter between S and R inputs and connect D input to S. That
means we eliminated the combinations of S & R are of same value.
 If D = 0 → S = 0 & R = 1, then next state Q(t+1) will be equal to ‘0’ irrespective of
present state, Q(t) values. This is corresponding to the second row of SR Latch
state table.
 If D = 1 → S = 1 & R = 0, then next state Q(t+1) will be equal to ‘1’ irrespective of
present state, Q(t) values. This is corresponding to the third row of SR Latch state
table.
The following table shows the state table of D latch.

D Q(t+1)

0 0

1 1

Therefore, D Latch Hold the information that is available on data input, D. That means
the output of D Latch is sensitive to the changes in the input, D as long as the enable is
High.
In this chapter, we implemented various Latches by providing the cross coupling
between NOR gates. Similarly, you can implement these Latches using NAND gates.

FCSE, GIK Institute 89

 CE-221L – Digital Logic Design Lab

7.6 Flip-Flops (SR & D):

A flip flop is an electronic circuit with two stable states that can be used to store binary
data. The stored data can be changed by applying varying inputs. Flip-flops and latches
are fundamental building blocks of digital electronics systems used in computers,
communications, and many other types of systems. Both are used as data
storage elements. It is the basic storage element in sequential logic.

SR Flip-Flop:
SR flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas SR latch operates with enable signal. The block diagram of SR flip-flop is shown
in the following figure.

The simplest way to make any basic single bit set-reset SR flip-flop is to connect
together a pair of cross-coupled 2-input NAND gates as shown, to form a Set-Reset
Bistable also known as an active LOW SR NAND Gate Latch, so that there is feedback
from each output to one of the other NAND gate inputs. This device consists of two
inputs, one called the Set, S and the other called the Reset, R with two corresponding
outputs Q and its inverse or complement Q (not-Q). The circuit diagram of SR flip-flop is
shown below:

FCSE, GIK Institute 90

 CE-221L – Digital Logic Design Lab

SR Flip-Flop using NAND Gates

This circuit has two inputs S & R and two outputs Q(t) & Q(t)’. The operation of SR
flipflop is similar to SR Latch. But, this flip-flop affects the outputs only when positive
transition of the clock signal is applied instead of active enable.

 Task-1:
 Design a circuit for SR Flip-Flop (using NAND Gates only) on the trainer board.
 Verify the given State & Characteristics table.

 State Table:
The following table shows the state table of SR flip-flop.

S R Q(t+1)

0 0 Q(t) No Change/
Present State

0 1 0 Reset

1 0 1 Set

1 1 - Undetermined

FCSE, GIK Institute 91

 CE-221L – Digital Logic Design Lab

Here, Q(t) & Q(t+1) are present state & next state respectively. So, SR flip-flop can be
used for one of these three functions such as Hold, Reset & Set based on the input
conditions, when positive transition of clock signal is applied. The following table shows
the characteristic table of SR flip-flop.

Present Inputs Present State Next State

S R Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 x

1 1 1 x

D Flip-Flop:
D flip-flop is a better alternative that is very popular with digital electronics. They are
commonly used for counters and shift-registers and input synchronization. The logic
symbol of D flip-flop is shown in the following figure.

FCSE, GIK Institute 92

 CE-221L – Digital Logic Design Lab

D flip-flop operates with only positive clock transitions or negative clock transitions.
Whereas D latch operates with enable signal. That means, the output of D flip-flop is
insensitive to the changes in the input, D except for active transition of the clock signal.
The circuit diagram of D flip-flop is shown below:

D Flip-Flop using NAND Gates

This circuit has single input D and two outputs Q(t) & Q(t)’. The operation of D flip-flop is
similar to D Latch. But this flip-flop affects the outputs only when positive transition of
the clock signal is applied instead of active enable.

 Task-2:
 Design a circuit for D Flip-Flop (using NAND Gates only) on the trainer board.
 Verify the given State table.

 State Table:
The following table shows the state table of D flip-flop.

D Q(t + 1)

0 0

1 1

7.7 Flip-Flops (JK & T):

FCSE, GIK Institute 93

 CE-221L – Digital Logic Design Lab

JK Flip-Flop:
JK flip-flop is the modified version of SR flip-flop. It operates with only positive clock
transitions or negative clock transitions. Due to the undefined state in the SR flip-flop,
another flip-flop is required in electronics. The JK flip-flop is an improvement on the SR
flip-flop where S=R=1 is not a problem. The logic symbol of D flip-flop is shown in the
following figure.

A gated S R flip flop with the addition of a clock input circuitry is basically the J k flip flop.
This circuit prevents the invalid output condition which occurs when both inputs are
high. The new addition here gives us four possible outputs of the flip flop. The output
may be – No Change, Logic 0, Logic 1 & Toggle. The circuit diagram of JK flip-flop is
shown in the following figure.

JK Flip-Flop using NAND Gates

The input condition of J=K=1, gives an output inverting the output state. However, the
outputs are the same when one tests the circuit practically.

FCSE, GIK Institute 94

 CE-221L – Digital Logic Design Lab

In simple words, If J and K data input are different (i.e. high and low) then the output Q
takes the value of J at the next clock edge. If J and K are both low then no change
occurs. If J and K are both high at the clock edge then the output will toggle from one
state to the other. JK Flip-Flops can function as Set or Reset Flip-flops.

 Task-3:
 Design a circuit for JK Flip-Flop (using NAND Gates only) on the trainer board.
 Verify the given State & Characteristics table.
 State Table:
The following table shows the state table of JK flip-flop.

J K Q(t+1)
0 0 Q(t) Present State
0 1 0 0
1 0 1 1
1 1 Q(t)' Q(t)’

Here, Q(t) & Q(t+1) are present state & next state respectively. So, JK flip-flop can be
used for one of these four functions such as Hold, Reset, Set & Complement of present
state based on the input conditions, when positive transition of clock signal is applied.
The following table shows the characteristic table of JK flip-flop.

Present Inputs Present State Next State

J K Q(t) Q(t+1)
0 0 0 0
0 0 1 1
0 1 0 0
0 1 1 0
1 0 0 1
1 0 1 1
1 1 0 1
1 1 1 0

FCSE, GIK Institute 95

 CE-221L – Digital Logic Design Lab

T Flip-Flop:
T flip-flop is the simplified version of JK flip-flop. It is obtained by connecting the same
input ‘T’ to both inputs of JK flip-flop. It operates with only positive clock transitions or
negative clock transitions. The logic symbol of T flip-flop is shown in the following figure.

A T flip-flop is like a JK flip-flop. These are basically a single input version of JK flip-flops.
This modified form of JK flip-flop is obtained by connecting both inputs J and K together.
It has only one input along with the clock input.

JK Flip-Flop using NAND Gates

This circuit has single input T and two outputs Q(t) & Qt()’. The operation of T flip-flop is
same as that of JK flip-flop. Here, we considered the inputs of JK flip-flop as J = T and K =
T in order to utilize the modified JK flip-flop for 2 combinations of inputs. So, we
eliminated the other two combinations of J & K, for which those two values are
complement to each other in T flip-flop.

FCSE, GIK Institute 96

 CE-221L – Digital Logic Design Lab

 Task-4:
 Design a circuit for T Flip-Flop (using NAND Gates only) on the trainer board.
 Verify the given State table.

 State Table:
The following table shows the state table of T flip-flop.

D Q(t+1)

0 Q(t)

1 Q(t)’

Here, Q(t) & Q(t+1) are present state & next state respectively. So, T flip-flop can be
used for one of these two functions such as Hold, & Complement of present state based
on the input conditions, when positive transition of clock signal is applied. The following
table shows the characteristic table of T flip-flop.

Inputs Present State Next State

T Q(t) Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

The output of T flip-flop always toggles for every positive transition of the clock signal
when input T remains at logic High 1. Hence, T flip-flop can be used in counters.

FCSE, GIK Institute 97

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can setup, and Can setup, and
Can independently Cannot setup or
Apparatus handle the handle the
setup, operate and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble Can assemble but Cannot
Apparatus design according to design inaccurately assemble
design within least time
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements
Measurements are Measurements are Measurements are
are made and
Presentation made and results are made and results are made and results
results are not
of Results presented presented more are presented
presented
most accurately accurately much accurately
accurately
Much of the Most of the
Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

FCSE, GIK Institute 98

 CE-221L – Digital Logic Design Lab

Lab-8
Sequential Logic Circuits (SLC)
Counters
8.1 Lab Objectives:
 Understand the concept of binary counters and their significance in digital circuits.
 Learn the difference between binary up counters and binary down counters.
 Comprehend the concept of toggle or "T" flip-flops and their role in binary counting.
 Design a 2-bit asynchronous binary up/down counter and verify its operation.

8.2 Equipment Required:

 Trainer Board
 Connecting wires / Jumper wires
 14 pin ICs
• NOT (7404)
• AND (7408)
• NAND (7400)
• NOR (7402)
• JK Flip Flop (7473)
• D Flip Flop (7474)
 Power supply

8.3 Binary Counters:

An ‘N’ bit binary counter consists of ‘N’ T flip-flops. If the counter counts from 0 to 2 𝑁 −
1, then it is called as binary up counter. Similarly, if the counter counts down from 2 𝑁 −
1 to 0, then it is called as binary down counter.
There are two types of counters based on the flip-flops that are connected in
synchronously or not.
 Asynchronous counters
 Synchronous counters

FCSE, GIK Institute 99

 CE-221L – Digital Logic Design Lab

Asynchronous Counters:
If the flip-flops do not receive the same clock signal, then that counter is called
as Asynchronous counter. The output of system clock is applied as clock signal only to
first flip-flop. The remaining flip-flops receive the clock signal from output of its previous
stage flip-flop. Hence, the outputs of all flip-flops do not change affect at the same time.

Now, let us discuss the following two counters one by one.

 Asynchronous Binary up counter
 Asynchronous Binary down counter

Asynchronous Binary Up Counter:

An ‘N’ bit Asynchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0 to
2𝑁 − 1. The block diagram of 3-bit Asynchronous binary up counter is shown in the
following figure.

The 3-bit Asynchronous binary up counter contains three T flip-flops and the T-input of
all the flip-flops are connected to ‘1’. All these flip-flops are negative edge triggered but
the outputs change asynchronously. The clock signal is directly applied to the first T flip-
flop. So, the output of first T flip-flop toggles for every negative edge of clock signal.
The output of first T flip-flop is applied as clock signal for second T flip-flop. So, the
output of second T flip-flop toggles for every negative edge of output of first T flip-flop.

FCSE, GIK Institute 100

 CE-221L – Digital Logic Design Lab

Similarly, the output of third T flip-flop toggles for every negative edge of output of
second T flip-flop, since the output of second T flip-flop acts as the clock signal for third
T flip-flop.
Assume the initial status of T flip-flops from rightmost to leftmost is Q2Q1Q0 = 000.
Here, Q2 & Q0 are MSB & LSB respectively. We can understand the working of 3-bit
asynchronous binary counter from the following table.

No of negative Q0 LSB Q1 Q2 MSB

edge of Clock

0 0 0 0

1 1 0 0

2 0 1 0

3 1 1 0

4 0 0 1

5 1 0 1

6 0 1 1

7 1 1 1

Here Q0 toggled for every negative edge of clock signal. Q1 toggled for every Q0 that
goes from 0 to 1, otherwise remained in the previous state. Similarly, Q2 toggled for
every Q1 that goes from 0 to 1, otherwise remained in the previous state.
The initial status of the T flip-flops in the absence of clock signal is Q2Q1Q0=000. This is
decremented by one for every negative edge of clock signal and reaches to the same
value at 8th negative edge of clock signal. This pattern repeats when further negative
edges of clock signal are applied.

Asynchronous Binary Down Counter:

FCSE, GIK Institute 101

 CE-221L – Digital Logic Design Lab

An ‘N’ bit Asynchronous binary down counter consists of ‘N’ T flip-flops. It counts from
2𝑁 − 1 to 0. The block diagram of 3-bit Asynchronous binary down counter is shown in
the following figure.

The block diagram of 3-bit Asynchronous binary down counter is similar to the block
diagram of 3-bit Asynchronous binary up counter. But, the only difference is that instead
of connecting the normal outputs of one stage flip-flop as clock signal for next stage flip-
flop, connect the complemented outputs of one stage flip-flop as clock signal for next
stage flip-flop. Complemented output goes from 1 to 0 is same as the normal output
goes from 0 to 1.
Assume the initial status of T flip-flops from rightmost to leftmost is Q2Q1Q0=0000.
Here, Q2 & Q0 are MSB & LSB respectively. We can understand the working of 3-bit
asynchronous binary down counter from the following table.

FCSE, GIK Institute 102

 CE-221L – Digital Logic Design Lab

No of negative Q0 Q1 Q2
edge of Clock LSB MSB

0 0 0 0

1 1 1 1

2 0 1 1

3 1 0 1

4 0 0 1

5 1 1 0

6 0 1 0

7 1 0 0

Here Q0 toggled for every negative edge of clock signal. Q1 toggled for every Q0 that
goes from 0 to 1, otherwise remained in the previous state. Similarly, Q2 toggled for
every Q1 that goes from 0 to 1, otherwise remained in the previous state.
The initial status of the T flip-flops in the absence of clock signal is Q2Q1Q0 = 000. This is
decremented by one for every negative edge of clock signal and reaches to the same
value at 8th negative edge of clock signal. This pattern repeats when further negative
edges of clock signal are applied.

Synchronous Counters:
If all the flip-flops receive the same clock signal, then that counter is called
as Synchronous counter. Hence, the outputs of all flip-flops change affect at the same
time.

FCSE, GIK Institute 103

 CE-221L – Digital Logic Design Lab

Now, let us discuss the following two counters one by one.

 Synchronous Binary up counter
 Synchronous Binary down counter

Synchronous Binary Up Counter:

An ‘N’ bit Synchronous binary up counter consists of ‘N’ T flip-flops. It counts from 0 to
2𝑁 − 1. The block diagram of 3-bit Synchronous binary up counter is shown in the
following figure.

The 3-bit Synchronous binary up counter contains three T flip-flops & one 2-input AND
gate. All these flip-flops are negative edge triggered and the outputs of flip-flops
change affect synchronously. The T inputs of first, second and third flip-flops are 1, Q0
& Q1Q0 respectively.
The output of first T flip-flop toggles for every negative edge of clock signal. The output
of second T flip-flop toggles for every negative edge of clock signal if Q0 is 1. The output
of third T flip-flop toggles for every negative edge of clock signal if both Q0 & Q1 are 1.

FCSE, GIK Institute 104

 CE-221L – Digital Logic Design Lab

Synchronous Binary Down Counter:

An ‘N’ bit Synchronous binary down counter consists of ‘N’ T flip-flops. It counts from
2𝑁 − 1 to 0. The block diagram of 3-bit Synchronous binary down counter is shown in
the following figure.

The 3-bit Synchronous binary down counter contains three T flip-flops & one 2-input
AND gate. All these flip-flops are negative edge triggered and the outputs of flip-flops
change affect synchronously. The T inputs of first, second and third flip-flops are 1, Q0’
& Q1′ Q0′ respectively.
The output of first T flip-flop toggles for every negative edge of clock signal. The output
of second T flip-flop toggles for every negative edge of clock signal if Q0′ is 1. The output
of third T flip-flop toggles for every negative edge of clock signal if both Q1′ & ′Q0′ are
1.

FCSE, GIK Institute 105

 CE-221L – Digital Logic Design Lab

 Task-1:
 Design a circuit for 2-bit UP/DOWN Counter on the Trainer Board such that:
 When UP/DOWN = 0, the counter counts down &
 When UP/DOWN = 1, the counter counts up

 Verify the given State diagram.

 Circuit Diagram:

Circuit Diagram for 2-bit UP/DOWN Counter

 State Diagram:

Illustration States for 2-bit UP/DOWN Counter

FCSE, GIK Institute 106

 CE-221L – Digital Logic Design Lab

 Task-2:
 Design a circuit for 3-bit Johnson Counter on the Trainer Board:
A Johnson counter is a counter where the inverted output from the last flip-flop is connected
to the input of the first flip-flop. Generally, it is implemented by using D flip-flops or JK flip-
flops. It is also known as an inverse feedback counter or twisted ring counter. This follows
the sequence of bit patterns. When compared to the ring counter, it uses only half of the
number of flip-flops.

FCSE, GIK Institute 107

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can setup, and Can setup, and
Can independently Cannot setup or
Apparatus handle the handle the
setup, operate and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble Can assemble but Cannot
Apparatus design according to design inaccurately assemble
design within least time
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements
Measurements are Measurements are Measurements are
are made and
Presentation made and results are made and results are made and results
results are not
of Results presented presented more are presented
presented
most accurately accurately much accurately
accurately
Much of the Most of the
Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

FCSE, GIK Institute 108

 CE-221L – Digital Logic Design Lab

Lab-9
Shift Registers
9.1 Lab Objectives:
 Understand the concept of shift registers and their significance in digital circuits.
 Design a 2-bit shift register and demonstrate its functionality in shifting data left or right.

9.2 Equipment Required:

 Trainer Board
 Connecting wires / Jumper wires
 14 pin ICs
• NOT (7404)
• AND (7408)
• NAND (7400)
• NOR (7402)
• JK Flip Flop (7473)
• D Flip Flop (7474)
 Power supply

9.3 Shift Registers:

Flip flops can be used to store a single bit of binary data (1or 0). However, in order to
store multiple bits of data, we need multiple flip flops. N flip flops are to be connected in
an order to store n bits of data. A Register is a device which is used to store such
information. It is a group of flip flops connected in series used to store multiple bits of
data.
The information stored within these registers can be transferred with the help of shift
registers. Shift Register is a group of flip flops used to store multiple bits of data. The
bits stored in such registers can be made to move within the registers and in/out of the
registers by applying clock pulses. An n-bit shift register can be formed by connecting n
flip-flops where each flip flop stores a single bit of data.
The registers which will shift the bits to left are called “Shift left registers”.
The registers which will shift the bits to right are called “Shift right registers”.

FCSE, GIK Institute 109

 CE-221L – Digital Logic Design Lab

Shift registers are basically of 4 types. These are:

1. Serial In Serial Out shift register
2. Serial In parallel Out shift register
3. Parallel In Serial Out shift register
4. Parallel In parallel Out shift register

Serial-In Serial-Out Shift Register (SISO) –

The shift register, which allows serial input (one bit after the other through a single data
line) and produces a serial output is known as Serial-In Serial-Out shift register. Since
there is only one output, the data leaves the shift register one bit at a time in a serial
pattern, thus the name Serial-In Serial-Out Shift Register.
The logic circuit given below shows a serial-in serial-out shift register. The circuit
consists of four D flip-flops which are connected in a serial manner. All these flip-flops
are synchronous with each other since the same clock signal is applied to each flip flop.

Serial-In Parallel-Out shift Register (SIPO) –

The shift register, which allows serial input (one bit after the other through a single data
line) and produces a parallel output is known as Serial-In Parallel-Out shift register.
The logic circuit given below shows a serial-in-parallel-out shift register. The circuit
consists of four D flip-flops which are connected. The clear (CLR) signal is connected in
addition to the clock signal to all the 4 flip flops in order to RESET them. The output of
the first flip flop is connected to the input of the next flip flop and so on. All these flip-
flops are synchronous with each other since the same clock signal is applied to each flip
flop.

FCSE, GIK Institute 110

 CE-221L – Digital Logic Design Lab

Parallel-In Serial-Out Shift Register (PISO) –

The shift register, which allows parallel input (data is given separately to each flip flop
and in a simultaneous manner) and produces a serial output is known as Parallel-In
Serial-Out shift register.
The logic circuit given below shows a parallel-in-serial-out shift register. The circuit
consists of four D flip-flops which are connected. The clock input is directly connected to
all the flip flops but the input data is connected individually to each flip flop through a
multiplexer at the input of every flip flop. The output of the previous flip flop and
parallel data input are connected to the input of the MUX and the output of MUX is
connected to the next flip flop. All these flip-flops are synchronous with each other since
the same clock signal is applied to each flip flop.

FCSE, GIK Institute 111

 CE-221L – Digital Logic Design Lab

Parallel-In Parallel-Out Shift Register (PIPO) –

The shift register, which allows parallel input (data is given separately to each flip flop
and in a simultaneous manner) and also produces a parallel output is known as Parallel-
In parallel-Out shift register.
The logic circuit given below shows a parallel-in-parallel-out shift register. The circuit
consists of four D flip-flops which are connected. The clear (CLR) signal and clock signals
are connected to all the 4 flip flops. In this type of register, there are no
interconnections between the individual flip-flops since no serial shifting of the data is
required. Data is given as input separately for each flip flop and in the same way, output
also collected individually from each flip flop.

FCSE, GIK Institute 112

 CE-221L – Digital Logic Design Lab

 Task-1:
 Design a circuit for 2-bit Shift Register on the Trainer Board such that:

 At the first clock signal, the value Data is stored and displayed at Q1.
 At the second clock signal, the value of Q1 is stored at the second flip-flop and
displayed at Q0. At the same time a new value Data is stored and displayed
at Q1.

By doing this, you have "shifted" the stored value by one flip-flop to the right.

 Circuit Diagram:

Circuit Diagram for 2-bit Shift Register

FCSE, GIK Institute 113

 CE-221L – Digital Logic Design Lab

 Task-2:
 Design a circuit for 4-bit Bidirectional Shift Register on the Trainer Board:

 Circuit Diagram:

FCSE, GIK Institute 114

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Can setup, and Can setup, and
Can independently Cannot setup or
Apparatus handle the handle the
setup, operate and handle the
Handling apparatus with apparatus with
handle the apparatus apparatus
minimal help some help
Can assemble
Assembly/ according to the Can assemble Can assemble but Cannot
Apparatus design according to design inaccurately assemble
design within least time
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications
Measurements
Measurements are Measurements are Measurements are
are made and
Presentation made and results are made and results are made and results
results are not
of Results presented presented more are presented
presented
most accurately accurately much accurately
accurately
Much of the Most of the
Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

FCSE, GIK Institute 115

 CE-221L – Digital Logic Design Lab

Lab-10
Introduction to Verilog HDL
Combinational circuits in Verilog
HDL
10.1 Lab Objectives:
 Understand the fundamental concepts of Verilog Hardware Description Language
(HDL).
 Learn the syntax and structure of Verilog code for designing digital circuits.
 Implement basic logic gates (AND, OR, NOT) using Verilog and simulate their behavior.
 Design and simulate combinational circuits such as multiplexers, decoders, and encoders
in Verilog.
 Gain proficiency in using Verilog modeling techniques for sequential circuits.
 Develop skills in writing testbenches to verify the functionality of Verilog designs.
 Understand the concept of waveform simulation and analyze simulation results.
 Learn how to use Verilog for simple arithmetic and data manipulation tasks.
 Explore the concept of gate-level modeling and its applications in Verilog.
 Practice documenting Verilog code and creating clear design descriptions for future
reference and collaboration.

10.2 Verilog:
Verilog is the combination of the terms “Verification” and “Logic”. It is hardware description
language or a special type of programming language which describes the hardware
implementations of digital systems and circuits. It is most commonly used in the design and
verification of digital circuits at the register-transfer level of abstraction. It is also used in the
verification of analog circuits and mixed-signal circuits.

Verilog module:
Verilog provides the concept of a module. A module is the basic building block in Verilog. A
module can be an element or a collection of lower-level design blocks.

In Verilog, a module is declared by the keyword module. A corresponding keyword endmodule

must appear at the end of the module definition. Each module must have a module_name,

FCSE, GIK Institute 116

 CE-221L – Digital Logic Design Lab

which is the identifier for the module, and a module_terminal_list, which describes the input
and output terminals of the module.

module <module_name> (<module_terminal_list>); //outputs first then inputs

...

<module internals> // Also called module body.

...

endmodule

Verilog is case sensitive.

Reserved keywords are written in lower cases.

A semicolon is used to terminate the statement.

The comment rule is same as C Programming Language.

Purpose of a module:
A module represents a design unit that implements certain behavioral characteristics and well
get converted into a digital circuit during synthesis. Any combination of the inputs can be given
to the module, and it will provide a corresponding output. This allows the same module to be
reused to form bigger modules that implement more complex hardware.

Single line comment starts with “//”.

For example – //Example of a Verilog single line comment

Multiline comments start with – ‘ /*’ and end with ‘*/’.

For example –

/* Example

Of Verilog multiple

Line comment*/

FCSE, GIK Institute 117

 CE-221L – Digital Logic Design Lab

Verilog Data Types:

The primary intent of data types in the Verilog language is to represent data storage elements
like bits in a flipflop and transmission elements like wires in that connects logic gates and
sequential circuits.

Verilog Operators:
Verilog has three fundamental operators for Verilog HDL. They are given below.

Unary Verilog operators: These types of Verilog operators come first of the operands.

For example: x = ~ y; Here ‘~’ is a unary operator

Binary Verilog operators: These types of Verilog operators come in between two operands.

For example: x = y || z; Here ‘||’ is a binary operator.

Ternary Verilog operators: These types of Verilog operators use two different operators to
differentiate three operators.

For example: x = y? z: w; here ‘?’ and ‘:’ are ternary operators.

Verilog HDL’s categorical operators are – arithmetical, logical, relational, bitwise, shift,
concatenation, and equality. Different types of Verilog operators and their symbols are given in
the below table.

10.6 Dataflow Modeling: Dataflow modeling provides the means of describing combinational
circuits by their function rather than by their gate structure. Dataflow modeling uses several
operators that act on operands to produce the desired results. Verilog HDL provides about 30
operator types.

Type of Operator Symbol Operation Operands needed

Arithmetic * Multiplication Two

/ Division Two

FCSE, GIK Institute 118

 CE-221L – Digital Logic Design Lab

+ Addition Two

– Subtraction Two

% Modulus Two

! Negation One

Logical
&& AND Two

|| OR Two

> Greater than Two

< Less than Two

Relational

>= Greater than or equal to Two

<= Less than or equal to Two

== Equals to Two

!= Not equals to Two

Equality
=== Case equal Two

! == Case not equal Two

~ Negation One
Bitwise
& Bitwise AND Two

| Bitwise OR Two

^ Bitwise XOR Two

FCSE, GIK Institute 119

 CE-221L – Digital Logic Design Lab

~^ Bitwise XNOR Two

& Reduction AND One

~& Reduction NAND One

| Reduction OR One
Reduction
~| Reduction NOR One

^ Reduction XOR One

^~ Reduction XNOR One

>> Right Shift Two

Shift
<< Left Shift Two

Concatenation {} Concatenation Can be of any numbers

Replication {{}} Replication Can be of any numbers

Conditional ?: Conditional Three

Verilog Number Specifications

Verilog numbers are of two types, sized numbers and unsized numbers.

Sized Verilog numbers: The general structure for representing sized numbers in Verilog HDL is
given below.

<size>’<base format><numbers>

For example – 8’b3456.

FCSE, GIK Institute 120

 CE-221L – Digital Logic Design Lab

size: Size is the number of digits the main number has. Size is described using decimal values.

base format: Base format suggests which type of number it would be. There are several types –
binary (given by – ‘b’), decimal (given by – ‘d’), octal (given by – ‘o’), hexadecimal (given by –
‘h’). If there is no specification for base format, then by default it is a decimal number.

numbers: The main number you want to put in.

Unsized Verilog numbers: These numbers do not require any specified size.

The general structure for representing unsized numbers in Verilog HDL is given below.

’<base format><numbers>

For example – ’h3456.

This is an unsized Verilog number which describes that it is a hexadecimal number.

Negative Numbers: If you want to declare a number as a negative number, then put a minus
symbol (-) before the number.

For example: – 345; it is a negative, unsized, decimal number.

Starting a New Project

1. To create a new project, open Project Navigator either from the Desktop icon or by selecting

Start > Programs > Xilinx ISE Design Suite 11 > ISE > Project Navigator. In Project Navigator,

Select the New Project option from the Getting Started menu (or by selecting Select File > New
Project).

This brings up a Dialog box where you can enter the desired project name and project location.

Choose a meaningful name for easy reference. Here we call this project “example1-Verilog” and
save it in a local directory. You can place comments for your project in the Description text box.
We use HDL for our top-level source type in this tutorial.

FCSE, GIK Institute 121

 CE-221L – Digital Logic Design Lab

Open New Project

Choose the location to create a New Project. Always choose something other than User folder
as it is read only. The best way is to create a folder on desktop, name it and copy its url and
paste it in the “location” of the “new project wizard”.

FCSE, GIK Institute 122

 CE-221L – Digital Logic Design Lab

2. The next step is to select the proper Family, Device, and Package for your project. This
depends on the chip you are targeting for this project. The appropriate settings for a project
suited for the Nexys2 500k board are as follows:

Since this lab does not require physically burn the logic on a chip so we will leave this window
as it is. Just click Next.

3. Once the appropriate settings have been entered, click Next. The next two dialog boxes give
you the option of adding new or existing source files to your project. Since we will fulfill these
steps later, click Next without adding any source files.

FCSE, GIK Institute 123

 CE-221L – Digital Logic Design Lab

Project Navigator Overview

Once the new project has been created, ISE opens the project in Project Navigator. Click the
Design tab to show the Design panel and click the Console tab to show the Console panel.

FCSE, GIK Institute 124

 CE-221L – Digital Logic Design Lab

The Design panel (1) contains two windows: a Sources window that displays all source files
associated with the current design and a Process window that displays all available processes
that can be run on a selected source file.

The Console panel (2) displays status messages including error and warning messages.

The HDL editor window (3) displays source code from files selected in the Design panel.

Adding New Source Files

Once the new project is created, two sources are listed under sources in the Design panel: the
Project file name and the Device targeted for design.

You can add a new or existing source file to the project. To do this, right-click the target device
and select one of the three options for adding source files.

FCSE, GIK Institute 125

 CE-221L – Digital Logic Design Lab

We create a new source file, so select New Source from the list. This starts the New Source
Wizard, which prompts you for the Source type and file name. Select Verilog Module and give it
a meaningful name e.g. circuit1.

When you click Next, you have the option of defining top-level ports for the new Verilog
module. We chose A, B, and C as input ports and Y as an output port.

FCSE, GIK Institute 126

 CE-221L – Digital Logic Design Lab

HDL Editor Window

Once you have created the new Verilog file, the HDL Editor Window displays the circuit1.v
source code.

The Xilinx tools automatically generate lines of code in the file to get you started with circuit
development. This generated code includes:

1. a module statement

2. a comment block template for documentation

The actual behavioral or structural description of the given circuit is to be placed between the
“module” and “endmodule” statements in the file. Between these statements, you can define
any Verilog circuit you wish. In this tutorial, we use a simple combinational logic example, and
then show how it can be used as a structural component in another Verilog module. We start
with the basic logic equation: Y= (A·B) + C.

If there are any syntax errors in the source file, ISE can help you find them. For example, the
parentheses around the A and B inputs are crucial to this implementation; without them, ISE
would return an error during synthesis info.

RTL Schematics and Syntax Checking

The RTL schematics can be viewed using the following set of steps, the example used here is
that of a Nand gate. Double click on synthesize-XST, on the left-hand side.

FCSE, GIK Institute 127

 CE-221L – Digital Logic Design Lab

Example of NAND gate in Verilog

Code
module nand_gate(
input a,
input b,
output c
);
assign c = ~(a & b);
endmodule

To create a Test bench, create New Source. Select Verilog Test Fixture. Template of Test bench
will be created instantiating the Nand gate module.

Stimulus/Testbench
Code
module nand1_stimulas;
reg a;
reg b;
wire c;

FCSE, GIK Institute 128

 CE-221L – Digital Logic Design Lab

// Instantiate the Unit Under Test (UUT)

nand_gate uut (
.a(a),
.b(b),
.c(c)
);
initial begin
// Initialize Inputs
a = 0; b = 0;
#10 a = 0; b = 1;
#10 a = 1; b = 0;
#10 a = 1; b = 1;
#10 $finish;
end
endmodule

Initial block: Initial blocks cause particular instructions to be performed at the beginning of the
simulation before any other instructions operate. Initial blocks only operate once.

Verilog test benches are used for the verification of the digital hardware design. Verification is
required to ensure the design meets the timing and functionality requirements. Verilog Test
benches are used to simulate and analyze designs without the need for any physical hardware
or any hardware device.

FCSE, GIK Institute 129

 CE-221L – Digital Logic Design Lab

Double click on Simulate Behavioral Model option.

FCSE, GIK Institute 130

 CE-221L – Digital Logic Design Lab

RTL

OUTPUT
This is the simulation window. You can verify the working using waveforms.

FCSE, GIK Institute 131

 CE-221L – Digital Logic Design Lab

10.3 Verilog Gate Level modelling.

In Verilog, most of the digital designs are done at a higher level of abstraction like RTL.
However, it becomes natural to build smaller deterministic circuits at a lower level by using
combinational elements such as AND and OR. Modeling done at this level is called gate-level
modeling as it involves gates and has a one-to-one relationship between a hardware schematic
and the Verilog code. Verilog supports a few basic logic gates known as primitives, as they can
be instantiated, such as modules, and they are already predefined.

Gate level modeling is virtually the lowest level of abstraction because switch-level abstraction
is rarely used. Gate level modeling is used to implement the lowest-level modules in a design,
such as multiplexers, full-adder, etc. Verilog has gate primitives for all basic gates.

Gate Types
A logic circuit can be designed using logic gates. Verilog supports basic logic gates as predefined
primitives. These primitives are instantiated like modules except that they are predefined in
Verilog and do not need a module definition. All logic circuits can be designed by using basic
gates. There are two classes of basic gates: and/or gates and buf /not gates.
And/ Or Gates

And/or gates have one scalar output and multiple scalar inputs. The first terminal in the list of
gate terminals is an output and the other terminals are inputs. The output of a gate is evaluated
as soon as one of the inputs changes. And /or gates available in Verilog are shown below.

And, or, xor, nand, nor, xnor

Buf /Not Gates

Buf/not gates have one scalar input and one or more scalar outputs. The last terminal in the
port list is connected to the input. Other terminals are connected to the outputs. We will
discuss gates that have one input and one output.

Two basic buf/not gate primitives are provided in Verilog.

Buf, not
The corresponding logic symbols for these gates are shown in Figure A. We consider gates with
two inputs.

FCSE, GIK Institute 132

 CE-221L – Digital Logic Design Lab

Fig. A. Basic Logic gates

Syntax
module and_gate (z,x,y);
input x,y;
output z;
and a1 (z,x,y);
endmodule

FCSE, GIK Institute 133

 CE-221L – Digital Logic Design Lab

Example # 1 Implementation of all basic gates

Implement all basic gates (Gate level designing) in Xilinx. implement test benches to verify their
working. Visualize their behavior in waveforms.

Code
module all_gates(
input a,
input b,
output x1,
output x2,
output x3,
output x4,
output x5,
output x6
);
and (x1,a,b);
or (x2,a,b);
nand (x3,a,b);
xor (x4,a,b);
xnor (x5,a,b);
nor (x6,a,b);
endmodule

RTL

FCSE, GIK Institute 134

 CE-221L – Digital Logic Design Lab

Waveform

Example # 2
Implement 4x1 MUX (gate level designing) in Xilinx ISE. Implement test benches to verify their
working. Visualize their behavior in waveforms.

FCSE, GIK Institute 135

 CE-221L – Digital Logic Design Lab

Code
module mux_4x1(op,i0,i1,i2,i3,s0,s1);
input i0,i1,i2,i3;
input s1,s0;
output op;
wire s1bar,s0bar;
wire w1,w2,w3,w4;

not n1(s1bar,s1);
not n2 (s0bar,s0);
and a1(w1,i0,s1bar,s0bar);
and a2 (w2,i1,s1bar,s0);
and a3(w3,i2,s1,s0bar);
and a4(w4,i3,s1,s0);
or o1 (op,w1,w2,w3,w4);
endmodule

FCSE, GIK Institute 136

 CE-221L – Digital Logic Design Lab

RTL

Schematics

FCSE, GIK Institute 137

 CE-221L – Digital Logic Design Lab

Waveform

Lab Tasks:
A) Implement the following logic gates in Xilinx ISE and implement test benches to verify their
working. Visualize their behavior in waveforms.
1. AND
2. OR
3. XOR
4. NOT
B) F = (AB) + (CD)
C) G = (A|B) & (C|D)
D) Implement full adder and implement test benches to verify their working. Visualize their
behavior in waveforms.
E) Implement the following in Xilinx (Gate Level Designing). implement test benches to verify
their working. Visualize their behavior in waveforms.
I. Full adder
II. Full subtractor
III. 8 X 1 multiplexer
IV. 4 to 2 encoders
V. 4 to 1 demultiplexer

FCSE, GIK Institute 138

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Satisfactory
Coding Exceptional coding Good coding with with noticeable Struggles with
Skills with minimal errors minor errors errors frequent errors

Effectively
Struggles with Frequently
Problem identifies and solves Capably identifies
significant fails to identify
Solving complex problems and resolves issues
assistance or solve
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications

Results are Results are Results are not

Presentation Results are
presented presented much presented
of Results presented accurately
most accurately accurately accurately

Much of the Most of the

Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

FCSE, GIK Institute 139

 CE-221L – Digital Logic Design Lab

Date: ______________________

Lab-11
Sequential Circuits in Verilog HDL
11.1 Lab Objectives:
 Gain a deep understanding of implementing sequential circuits in Verilog.
 Learn to use high-level abstractions and Verilog constructs for digital system
descriptions.
 Represent algorithms and functions behaviorally using Verilog.
 Simulate behavioral models written in Verilog and verify their accuracy.

11.2 Structured Procedures:

Initial Statement:
All statements inside an initial statement constitute an initial block. An initial block starts
at time 0, executes exactly once during a simulation, and then does not execute again. If
there are multiple initial blocks, each block starts to execute concurrently at time 0.
Each block finishes execution independently of other blocks. Multiple behavioral
statements must be grouped, typically using the keywords begin and end. If there is only
one behavioral statement, grouping is not necessary. Example illustrates the use of the
initial statement.
Example of initial Statement:
module stimulus;
reg x,y, a,b, m;
initial
m = 1'b0; //single statement; does not need to be grouped
initial begin
#5 a = 1'b1; //multiple statements; need to be grouped
#25 b = 1'b0;
end

FCSE, GIK Institute 140

 CE-221L – Digital Logic Design Lab

initial begin
#10 x = 1'b0;
#25 y = 1'b1;
end
initial
#50 $finish;
Endmodule

In the above example, the three initial statements start to execute in parallel at time 0.
If a delay #<delay> is seen before a statement, the statement is executed <delay> time
units after the current simulation time. Thus, the execution sequence of the statements
inside the initial blocks will be as follows.
time statement executed
0 m = 1'b0;
5 a = 1'b1;
10 x = 1'b0;
30 b = 1'b0;
#50 $finish;
35 y = 1'b1;

Always Statement:
All behavioral statements inside an always statement constitute an always block. The
always statement starts at time 0 and executes the statements in the always block
continuously in a looping fashion. This statement is used to model a block of activity
that is repeated continuously in a digital circuit. An example is a clock generator module
that toggles the clock signal every half cycle. In real circuits, the clock generator is active
from time 0 to as long as the circuit is powered on. Example illustrates one method to
model a clock generator in Verilog

FCSE, GIK Institute 141

 CE-221L – Digital Logic Design Lab

Example of Always Statement:

module clock_gen (output reg clock);
//Initialize clock at time zero
initial clock = 1'b0;
//Toggle clock every half-cycle (time period = 20)
always #10
clock = ~clock;
initial #1000
$finish;
endmodule

In Example, the always statement starts at time 0 and executes the statement clock =
~clock every 10 time units. Notice that the initialization of clock has to be done inside a
separate initial statement. If we put the initialization of clock inside the always block,
clock will be initialized every time the always is entered. Also, the simulation must be
halted inside an initial statement. If there is no $stop or $finish statement to halt the
simulation, the clock generator will run forever. The activity is stopped only by power off
($finish) or by an interrupt ($stop).

11.3 Procedural Assignments:

Procedural assignments update values of reg, integer, real, or time variables. The
value placed on a variable will remain unchanged until another procedural assignment
updates the variable with a different value.

Blocking Assignments:
Blocking assignment statements are executed in the order they are specified in a
sequential block. A blocking assignment will not block execution of statements that
follow in a parallel block., The = operator is used to specify blocking assignments.
Example of Blocking Statement:
reg x, y, z;

FCSE, GIK Institute 142

 CE-221L – Digital Logic Design Lab

reg [15:0] reg_a, reg_b;

integer count;
//All behavioral statements must be inside an initial or always block
initial begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0;
//Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //initialize vectors
#15 reg_a[2] = 1'b1; //Bit select assignment with delay
#10 reg_b[15:13] = {x, y, z}
//Assign result of concatenation to part select of a vector
count = count + 1; //Assignment to an integer (increment)
end

In Example , the statement y = 1 is executed only after x = 0 is executed. The behavior in

a particular block is sequential in a begin-end block if blocking statements are used,
because the statements can execute only in sequence. The statement count = count + 1
is executed last. The simulation times at which the statements are executed are as
follows:
• All statements x = 0 through reg_b = reg_a are executed at time 0.
• Statement reg_a[2] = 0 at time = 15.
• Statement reg_b[15:13] = {x, y, z} at time = 25.
• Statement count = count + 1 at time = 25.
• Since there is a delay of 15 and 10 in the preceding statements, count = count
+ 1 will be executed at time = 25 units

Non-Blocking Assignments:

FCSE, GIK Institute 143

 CE-221L – Digital Logic Design Lab

Nonblocking assignments allow scheduling of assignments without blocking execution of

the statements that follow in a sequential block. A <= operator is used to specify
nonblocking assignments. Note that this operator has the same symbol as a relational
operator, less_than_equal_to. The operator <= is interpreted as a relational operator in
an expression and as an assignment operator in the context of a nonblocking
assignment. To illustrate the behavior of nonblocking statements and its difference from
blocking statements, let us consider below example where we convert some blocking
assignments to nonblocking assignments, and observe the behavior.
Example of Non-Blocking Statement:
reg x, y, z;
reg [15:0] reg_a, reg_b;
integer count;
//All behavioral statements must be inside an initial or always block initial begin
x = 0; y = 1; z = 1; //Scalar assignments
count = 0; //Assignment to integer variables
reg_a = 16'b0; reg_b = reg_a; //Initialize vectors
reg_a[2] <= #15 1'b1; //Bit select assignment with delay
reg_b[15:13] <= #10 {x, y, z};
//Assign result of concatenation to part select of a vector
count <= count + 1; //Assignment to an integer (increment)
end

In this example, the statements x = 0 through reg_b = reg_a are executed sequentially at
time 0.
Then the three nonblocking assignments are processed at the same simulation time:
1. reg_a[2] = 0 is scheduled to execute after 15 units (i.e., time = 15)
2. reg_b[15:13] = {x, y, z} is scheduled to execute after 10 time units (i.e., time =
10)
3. count = count + 1 is scheduled to be executed without any delay (i.e., time =

FCSE, GIK Institute 144

 CE-221L – Digital Logic Design Lab

0)

Thus, the simulator schedules a nonblocking assignment statement to execute and

continues to the next statement in the block without waiting for the nonblocking
statement to complete execution. Typically, nonblocking assignment statements are
executed last in the time step in which they are scheduled, that is, after all the blocking
assignments in that time step are executed.

11.4 Examples:
 4-bit Counter:
//4-bit Binary counter module counter(Q , clock, clear);
// I/O ports
output [3:0] Q; //output defined as register reg [3:0] Q
input clock, clear;
always @( posedge clear or negedge clock)
begin
if (clear)
Q <= 4'd0;
//Nonblocking assignments are recommended for creating sequential logic such
as flipflops else
Q <= Q + 1;// Modulo 16 is not necessary because Q is a 4-bit value and wraps
around.
end
endmodule

 D Flip Flop:
module d_FF(Clock,Data,Q,Reset);

FCSE, GIK Institute 145

 CE-221L – Digital Logic Design Lab

input Clock,Data,Reset;
output Q; reg Q;
always@(posedge clock)
begin
if (reset==1) Q<=0;
else Q<=Data;
end
endmodule

11.5 Lab Tasks:

 Task-1:
 Implement JK Flip flop using behavioral modeling, Truth table is given below.

J K Q(t+1)

0 0 Q(t)(No change)

0 1 0 (Set)

1 0 1 (Reset)

1 1 Q’(t) (Toggle)

 Task-2:
 Implement T Flip flop using behavioral modeling, Truth table is given below.

FCSE, GIK Institute 146

 CE-221L – Digital Logic Design Lab

T Q(t+1)

0 Q(t)(No change)

1 Q’(t) (Toggle)

 Task-3:
 Implement 4 bit ripple counter, Figure is given below

FCSE, GIK Institute 147

 CE-221L – Digital Logic Design Lab

Lab Rubrics

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Satisfactory
Coding Exceptional coding Good coding with with noticeable Struggles with
Skills with minimal errors minor errors errors frequent errors

Effectively
Struggles with Frequently
Problem identifies and solves Capably identifies
significant fails to identify
Solving complex problems and resolves issues
assistance or solve
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications

Results are Results are Results are not

Presentation Results are
presented presented much presented
of Results presented accurately
most accurately accurately accurately

Much of the Most of the

Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

Lab-12
FCSE, GIK Institute 148
 CE-221L – Digital Logic Design Lab

Introduction to Finite State Machine

(FSM) & Implementation of FSM in
Verilog HDL
12.1 Lab Objectives:
 Understand the fundamental concept of Finite State Machines (FSMs) and their
significance in digital design.
 Learn about the different components of an FSM, including states, inputs, outputs, and
state transitions.
 Familiarize yourself with the types of FSMs, such as Mealy and Moore machines, and
understand the differences between them.
 Gain proficiency in drawing state transition diagrams to represent the behavior of FSMs.
 Explore the role of Verilog Hardware Description Language (HDL) in modeling and
implementing FSMs in digital circuits.
 Learn how to write Verilog code for simple FSMs, including state register, state
transition logic, and output logic.
 Develop the ability to simulate FSMs using Verilog and understand how to test and
debug your designs.
 Practice designing and implementing FSMs for real-world applications, such as sequence
detectors or simple control systems.

12.2 Finite State Machines (FSM)

FSM are sequential circuits used in many digital systems to control the behavior of systems and
dataflow paths. Examples of FSM include control units and sequencers.

A finite state machine is a mathematical model used to describe and analyze the behavior of
systems that have a finite number of states. It consists of a set of states, a set of inputs or
events that cause state transitions, and a set of rules that determine how the system transitions
from one state to another in response to these events.

An FSM consists of following parameters:

Q: finite set of states

∑: finite set of input symbol
q0: initial state

FCSE, GIK Institute 149

 CE-221L – Digital Logic Design Lab

F: final state
δ: Transition function

The behavior of an FSM can be visualized using a state transition diagram, which is a directed
graph where the nodes represent the states, and the edges represent the transitions between
them. The FSM can be in only one state at a time, and the current state determines how the
system will respond to the next input or event.

This lab introduces the concept of two types of FSMs, Moore and Mealy, and the modeling
styles to develop such machines.

12.3 Moore Machine:

A Moore machine is a type of finite state machine that produces an output based only on its
current state. The output is associated with the state itself, rather than with the transition from
one state to another. The Moore machine is named after its inventor Edward F. Moore.

In a Moore machine, the output is a function of the current state, and does not depend on the
input received. The output is generated when the machine transitions from one state to
another.

12.4 Mealy Machine:

A Mealy machine is a type of finite state machine that produces an output based on both its
current state and the input it receives. The output is generated when a transition from one
state to another occurs and is a function of the current input and current state.

In a Mealy machine, the output is associated with the transition from one state to another,
rather than with the state itself. This means that the output can change as the machine
transitions from one state to another, depending on the input received.

FCSE, GIK Institute 150

 CE-221L – Digital Logic Design Lab

Block diagram of Moore and Mealy Machine

Parameter: In Verilog, a parameter is a value that is declared at the module level and is used to
define constants or default values for a module's inputs, outputs, or internal signals.
Parameters are like constants in other programming languages and can be used to make a
module more flexible and reusable. A parameter is declared using the parameter keyword,
followed by the parameter name and value.

Note: A Mealy machine typically has one less state than a Moore machine is because Mealy
machines can encode some of the output information in the transitions between states, rather
than requiring a separate state for each possible output. This means that fewer states are
needed to represent the same behavior.

Example# 1: Design a Moore (FSM) circuit to detect a sequence (101) if the input signal is:
Input signal = 10100101010010101010

First, we need to create a state diagram that represents the states and transitions of the Moore
machine. In this case, we need to design a Moore machine that recognizes the input sequence
"110". We can do this by creating three states: S0, S1, and S2.
State S0 is the starting state, which means the machine has not yet detected any part of the
sequence "101". State S1 represents that the machine has detected the first "1" in the
sequence, while state S2 represents that the machine has detected both "1" and "0" in the
sequence. state S3 represents that the machine has detected all the corresponding inputs that
is “1", "0” and “1” in the sequence.

FCSE, GIK Institute 151

 CE-221L – Digital Logic Design Lab

Next, we need to determine the output of each state. In state S0, the output will be 0. In state
S1, the output will also be 0. In state S2, the output will be 1 and State 3 the output is also 1.
Finally, we can create a state transition table and a state transition.

State Diagram

State transition Table

State Input Next State Output

S0 0 S0 0

S0 1 S1 0

S1 0 S2 0

S1 1 S1 0

S2 0 S0 0

S2 1 S3 1

S3 0 S2 1

S3 1 S1 1

CODE

FCSE, GIK Institute 152

 CE-221L – Digital Logic Design Lab

`timescale 1ns / 1ps

module moore_machine_sequence_detector(y,Clk,Rst,x);
input Clk,Rst,x;
output y;
reg [1:0] crntstate,nxtstate;

parameter s0 = 2'b00;
parameter s1 = 2'b01;
parameter s2 = 2'b10;
parameter s3 = 2'b11;

always @ (crntstate or x)
begin
case(crntstate)
s0: begin
//y = 0;
if (x==1)
nxtstate = s1;
else
nxtstate = crntstate;
end
s1: begin
//y = 0;
if (x==0)
nxtstate = s2;
else
nxtstate = crntstate;
end
s2: begin
//y = 0;
if (x==1)
nxtstate = s3;
else
nxtstate = s0;
end
s3: begin
//y = 1;
if (x==1)
nxtstate = s1;
else
nxtstate = s2;
end
default:nxtstate = s0;

FCSE, GIK Institute 153

 CE-221L – Digital Logic Design Lab

endcase
end
always @ (posedge Clk)
begin
if (Rst)
crntstate = s0;
else
crntstate = nxtstate;
end
assign y = (crntstate == s3);
endmodule

Test-Bench
`timescale 1ns / 1ps
module moore_tb;

// Inputs
reg Clk;
reg Rst;
reg x;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

moore_machine_sequence_detector uut (
.y(y), .Clk(Clk), .Rst(Rst), .x(x));

reg [19:0] data;

integer k;
initial begin
data =20'b10100101010010101010;
k = 0;
Rst = 1; #20;
Rst = 0; #200;
$finish;
end
initial begin
Clk = 0;
forever begin

FCSE, GIK Institute 154

 CE-221L – Digital Logic Design Lab

#5;
Clk = ~Clk;
end
end
always @(posedge Clk) begin
x = data>>k;
k = k+1;

end
endmodule

RTL

Technology Schematics

Output Wave Form

FCSE, GIK Institute 155

 CE-221L – Digital Logic Design Lab

Example # 2 : Design a Mealy (FSM ) circuit to detect a sequence (101) if the input signal is
Input signal = 10100101010010101010

State Diagram

State transition Table

FCSE, GIK Institute 156

 CE-221L – Digital Logic Design Lab

State Input Next State Output

S0 0 S0 0

S0 1 S1 0

S1 0 S2 0

S1 1 S1 0

S2 0 S0 0

S2 1 S1 1

CODE
`timescale 1ns / 1ps
module mealy_machine_sequence_detector(y,Clk,Rst,x);

input Clk,Rst,x;
output y;
reg [1:0] crntstate,nxtstate;

parameter s0 = 2'b00;
parameter s1 = 2'b01;
parameter s2 = 2'b10;

always @ (crntstate or x)
begin
case(crntstate)
s0: begin
if (x==1)
nxtstate = s1;
else
nxtstate = crntstate;
end
s1: begin
if (x==0)
nxtstate = s2;
else

FCSE, GIK Institute 157

 CE-221L – Digital Logic Design Lab

nxtstate = crntstate;
end
s2: begin
if (x==1)
nxtstate = s2;
else
nxtstate = s0;
end
default:nxtstate = s0;
endcase
end
always @ (posedge Clk)
begin
if (Rst)
crntstate <= s0;
else
crntstate <= nxtstate;
end
assign y = (crntstate == s2)&x;

endmodule

Test-Bench
`timescale 1ns / 1ps
module mealy_tb;

// Inputs
reg Clk;
reg Rst;
reg x;

// Outputs
wire y;

// Instantiate the Unit Under Test (UUT)

mealy_machine_sequence_detector uut (
.y(y),
.Clk(Clk),
.Rst(Rst),
.x(x)
);

FCSE, GIK Institute 158

 CE-221L – Digital Logic Design Lab

reg [19:0] data;

integer k;
initial begin
data =20'b10100101010010101010;
k = 0;
Rst = 1; #20;
Rst = 0; #180;
$finish;
end

initial begin
Clk = 0;
forever begin
#5;
Clk = ~Clk;
end
end
always @(posedge Clk) begin
x = data>>k;
k = k+1;

end
endmodule

RTL

Technology Schematics

FCSE, GIK Institute 159

 CE-221L – Digital Logic Design Lab

OUTPUT Wave from

Task # 1:

FCSE, GIK Institute 160

 CE-221L – Digital Logic Design Lab

 Write a Verilog code for a Moore (FSM) that detects the sequence (X) from given input
Signal in Xilinx ISE and implement test benches to verify their working. Visualize their
behavior in waveforms.

Task # 2:
 Write a Verilog code for a Mealy (FSM) that detects the sequence (X) from given input
Signal in Xilinx and implement test benches to verify their working. Visualize their
behavior in waveforms.

Instructions for task

Draw State diagram and make a state transition table for above tasks.

Input signals in hexadecimal is your registration number. (4-bit in binary)

for example 20X22X34X (00100000X00100001X00110100X)
X = last digit of your registration number. (0101)

Lab Rubrics

FCSE, GIK Institute 161

 CE-221L – Digital Logic Design Lab

Reg. No. : _______________________ Date of Lab: ____________________

Excellent Good Satisfactory Poor Score

3 2 1 0
Satisfactory
Coding Exceptional coding Good coding with with noticeable Struggles with
Skills with minimal errors minor errors errors frequent errors

Effectively
Struggles with Frequently
Problem identifies and solves Capably identifies
significant fails to identify
Solving complex problems and resolves issues
assistance or solve
Design objectives
Design objectives Design objectives
have been
Achieving have been achieved have been achieved Design
achieved within
Design within 10% of the within 25% of the objectives are
40% of the
Objectives desired desired not met
specifications desired
specifications
specifications

Results are Results are Results are not

Presentation Results are
presented presented much presented
of Results presented accurately
most accurately accurately accurately

Much of the Most of the

Most of the
All the questions are questions are questions are not
questions are
answered correctly answered but answered and
Viva answered with
with information with minimal information is
almost information
relevant to topic. information not relevant to
relevant to topic
relevant to topic topic

Total Score in Lab /15

Instructor Signature: ______________________

Date: ______________________

Lab-13
FCSE, GIK Institute 162
 CE-221L – Digital Logic Design Lab

Open Ended lab (OEL)

13.1 Lab Objective:

To make a joint project within the lab addressing a real life task/problem using all the
available apparatus in the lab.

13.2 Pre-Lab Reading:

All the Labs that have been done.

13.3 Exercise:
To be announced on the spot or in previous lab.

FCSE, GIK Institute 163