Programmable Logic Devices

Important features that all PLDs have in

common:
• No customized mask layers or logic cells
• Fast design turnaround
• A single large block of programmable
interconnect
• A matrix of logic macrocells that usually
consist of programmable array logic
followed by a flip-flop or latch
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 A field-programmable gate array (FPGA) or
complex PLD

• A step above the PLD in complexity is the field-programmable

gate array (FPGA ).
• There is very little difference between an FPGA and a PLD an FPGA
is usually just larger and more complex than a PLD.
 A field-programmable gate array (FPGA) or
complex PLD
• None of the mask layers are customized
• A method for programming the basic
logic cells and the interconnect
• The core is a regular array of
programmable basic logic cells that can
implement combinational as well as
sequential logic (flip-flops)
• A matrix of programmable interconnect
surrounds the basic logic cells
• Programmable I/O cells surround the
core
• Design turnaround is a few hours
 Design Flow
A design flow is a sequence of steps to design an ASIC
1. Design entry. Using a hardware description
language (HDL) or schematic entry.
2. Logic synthesis. Produces a netlist—logic cells and
their connections.
3. System partitioning. Divide a large system into
ASIC-sized pieces.
4. Prelayout simulation. Check to see if the design
functions correctly.
5. Floorplanning. Arrange the blocks of the netlist on
the chip.
6. Placement. Decide the locations of cells in a block.
7. Routing. Make the connections between cells and
blocks.
8. Extraction. Determine the resistance and
capacitance of the interconnect.
9. Postlayout simulation. Check to see the design
still works with the added loads of the
interconnect.
 ASIC Cell Libraries

You can:
1. use a design kit from the ASIC vendor
2. buy an ASIC-vendor library from a library vendor
3. you can build your own cell library
(1) is usually a phantom library—the cells are empty boxes, or phantoms, you hand off your
design to the ASIC vendor and they perform phantom instantiation (Synopsys CBA)
(2) involves a buy-or-build decision. You need a qualified cell library (qualified by the ASIC
foundry) If you own the masks (the tooling) you have a customer-owned tooling (COT)
solution (which is becoming very popular)
(3) involves a complex library development process: cell layout • behavioural model •
Verilog/VHDL model • timing model • test strategy • characterization • circuit extraction
• process control monitors (PCMs) or drop-ins • cell schematic • cell icon • layout versus
schematic (LVS) check • cell icon• logic synthesis • retargeting • wire-load model•
routing model
• we have looked at the difference between full-custom
ASICs, semi-custom ASICs, and programmable ASICs.

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CMOS Logic:
Datapath Logic Cells

• Suppose we wish to build an n -bit adder (that adds two n -

bit numbers) and to exploit the regularity of this function in
the layout. We can do so using a datapath structure.

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 4-bit ripple-carry adder ( RCA )

FIGURE 2.20 A datapath adder. (a) A full-adder (FA) cell with inputs (A and B), a carry in, CIN, sum output, S, and carry out, COUT.
(b) A 4-bit adder. (c) The layout, using two-level metal, with data in m1 and control in m2. In this example the wiring is completed
outside the cell; it is also possible to design the datapath cells to contain the wiring. Using three levels of metal, it is possible to
9/4/20XX wire over the top of the datapath
Presentationcells.
Title (d) The datapath layout. 22
4-bit ripple-carry adder ( RCA )

• What is the difference between using a datapath, standard cells,

or gate arrays?
• Cells are placed together in rows on a CBIC or an MGA, but
there is generally no regularity to the arrangement of the cells
within the rows we let software arrange the cells and complete
the interconnect.
• Datapath layout automatically takes care of most of the
interconnect between the cells with the following advantages:
• Regular layout produces predictable and equal delay for each bit.
• Interconnect between cells can be built into each cell.
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4-bit ripple-carry adder ( RCA )

There are some disadvantages of using a datapath:

• The overhead (buffering and routing the control signals, for example)
can make a narrow (small number of bits) datapath larger and slower
than a standard-cell (or even gate-array) implementation.
• Datapath cells have to be predesigned (otherwise we are using full-
custom design) for use in a wide range of datapath sizes. Datapath
cell design can be harder than designing gate-array macros or
standard cells.
• Software to assemble a datapath is more complex and not as widely
used as software for assembling standard cells or gate arrays.
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Datapath Elements

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Datapath Elements

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 Adders

• The delay of an n -bit RCA is proportional to n and is limited by the

propagation of the carry signal through all of the stages.
• We can reduce delay by using pairs of go-faster bubbles to change AND
and OR gates to fast two-input NAND gates
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