Course Administration

• Required Textbooks:
• Joseph Yiu, “The Definitive Guide to the ARM Cortex-M0/M0+
processors, 2nd Ed., Newnes, (Elsevier), 2015
• Gaonkar R. S., "Microprocessor Architecture, Programming and
Applications with 8085", 6th Ed., Penram International, Indian, 2013
• Few handouts from course instructor
• Grading (Theory):
• 30 midsem + 20 internal + 50 endsem + 25 (Tuto)
• Total marks=125
• Grading (Practical):
• 25 Conti. + 25 Final exam = 50 marks

Dr. Z.M.Patel, NIT Surat 1

 Historical Perspective

• 1944: Electronic Numerical Integrator and Calculator (ENIAC) computer using

Vacuum tubes
• 1947 : Bardeen, Brattain and Shockley invented transistor at Bell labs
• 1958: Jack Kilbey demonstrated working of integrated transistor
• 1971: Intel introduce 1st processor with 4-bit bus, 8-bit instructions & 12-bit address
• 1978 : John Birkner and H. T. Chua developed easy-to-use programmable array
logic (PAL)
• 1981 => IBM personal computer "Acorn," is introduced. It uses Microsoft's MS-
DOS OS
• 1991: ARM introduced its first embeddable RISC IP core

Dr. Z.M.Patel, NIT Surat 2

 Introduction

Microprocessor:
• Programmable general purpose logic device
• Executes prerecorded set of instruction in well defined manner
• 8-bit to 64-bit variants with variety of computing capabilities
• Architectures: intel x86 CISC, ARM RISC processors

Microcomputer:
• Programmable machine having Microprocessor as one of the key element
• It also consists various types of memory, Input devices, Output devices
• Additionally, it contains GPU, Network interfaces, Hard disk drives
• Examples: PC, Mainframe and Super computers

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 Introduction

• Many units are connected to common bus.

• Address is used for both memory and I/O devices

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 Introduction

Programming languages that computing system deal with

• Machine Language : Binary code or hex code
• Assembly Language : Mnemonics such as ADD, ADC, LDA, INC etc.
• High level Language : Looks like English vocabulary and grammer

Dr. Z.M.Patel, NIT Surat 5

Introduction

Fig. VonNeuman Architecture

Fig. Harvard Architecture

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 Introduction
Instruction Format:
• Mainly contains two fields : Opcode Operands
• Opcode => control code that tells CPU what to do
• Operand => Register value or Constant data or Address or Memory value
• CISC instructions are variable size (1 byte /2 byte/ 3 byte …)

Dr. Z.M.Patel, NIT Surat 7

 Introduction
Data Format:
• BCD => 4-bit BCD code. A byte can store one (unpacked) or two (packed)
BCD digits
• ASCII => 7-bit ASCII code for a character stored as byte
• Signed Integer => integer data with Sign bit
• Unsigned Integer => integer data without sign bit
• Floating Point => real numbers with mantissa and exponent

Dr. Z.M.Patel, NIT Surat 8

8085 internal block diagram

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 8085 Microprocessor

• Flag Register

Operations and Machine cycles

• Opcode fetch
• Memory Read and Wrtie
• I/O Read and Write

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8085: Memory Access

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8085: Opcode fetch Operation

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 Interfacing

• Memories (RAM and ROM chips) are interfaced using Address bus, Data bus and
Control signals (MEMR & MEMW)
• Each memory has chip enable (CE) pin. Memory chip can be enabled /disabled by
applying LOW or HIGH on CE pin
• Input /Output devices use IOR and IOW control signals

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 Memory Interfacing

• N address line can access 2N bytes of memory

• Tristate buffer are required to keep output port of memory in high impedance state
when no read/write operation is performed

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 Memory Interfacing

• The total memory map of 8085 : 0x0000 to 0xFFFF (64 Kbytes)

• Above ROM chip occupies range : 0x8000 to 0xFFFF (4K bytes)

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Timing diagram

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 Memory Interfacing
• Problem 1: Design and draw interfacing circuit to interface 2K EEPROM and 1K
RAM chip to 8085 with 2x4 Decoder and NAND gates. The starting address of
EEPROM is B800H and that of RAM is A400H. Use control signals directly.
Assume active LOW chip enable for memory chips.

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Timing diagram

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 I/O Interfacing
• Problem 2: Interface one input port of I/O address 44H and one output port having
I/O address 55H using NAND based decoding logic. Eight simple LEDs and eight
keys are connected to output and input port respectively. Assume active HIGH
enable for Latches and Buffers.

Dr. Z.M.Patel, NIT Surat 19

 8085- Few Concepts

• Subroutine Call – to call function

• Stack – A dedicated portion of RAM for saving and retrieving data when subroutine is
called or interrupt occurs
• Interrupts – Vectored: RST7.5, RST6.5, RST5.5 & TRAP Non-vectored: INTR

Dr. Z.M.Patel, NIT Surat 20

 8051 Architecture

• Above block diagram is of “Basic or Generic 8051 microcontroller”.

• Advanced 8051 microcontrollers may have additional peripherals, more timers,
large memory, less number of clocks per machine cycles, less number of pins etc.

Dr. Z.M.Patel, NIT Surat 21

 8051 Memory

• Internal RAM is accessed with direct/indirect addressing

• SFR area is reserved for special function registers
• External RAM is accessed with indirect addressing (using @Ri or @DPTR)
• ROM is accessed using PC or DPTR with index addressing only

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8051 Internal RAM

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 Addressing Modes

 The CPU can access data in various ways, which are called addressing modes
◦ Immediate (mov A, #0A5h; mov DPTR, #1234h)
– Operand is part of instruction itself
◦ Register (mov A, R1; mov R7, A)
‒ Operand is in register
◦ Direct (mov R0, 4Fh; mov 55H, A)
‒ Operand is in memory whose address specified in instruction
◦ Register indirect (mov A, @R0; mov @R1, A)
‒ Operand is in memory whose address is pointed by register
◦ Indexed (movx @A+DPTR, A; movc A, @A+PC)
‒ Operand is accessed from memory whose address given by (BaseReg.+IndexReg.)

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 External Memory Access

• MOVX : to access only external RAM (register indirect addressing mode)

• MOVC : to access internal ROM or external ROM (indexed addressing mode)

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PIC Microcontroller (16 bit)

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 Popular MCUs

• ST Microelectronics
• NXP
• Texas Instruments
• Microchip
• Infineon

There are many factors to be considered when

selecting a microcontroller device for a product.
• Peripherals and interface features
• Memory size requirements of the application
• Low power requirements
• Performance and maximum frequency
• Operation conditions (voltage, temperature,
electromagnetic interference)
• Cost and availability
• Software development tool support and
development kits
• Future upgradability
• Firmware packages and firmware security

Dr. Z.M.Patel, SVNIT Surat 27

 Performance
DMIPS:
• Dhryston is a benchmark program that includes integer arithmetic, string manipulation,
logic and memory access operations
• The Dhrystone figure of given computing system is calculated by measuring the number
of Dhrystones executed per second and dividing that by 1757. So if a computing system
able to execute 140560 dhrystones per second, then its DMIPS rating is 140560/1757 =
80 DMIPS.
• Above figure can be normalized by Clock freq. E.g. if clock freq. is 50MHz then
performance of computing system 1.6 DMIPS/MHz
Coremark MIPS:
• Core mark is new Bench mark program for embedded processors that also commonly
used algorithms such as Matrix multiplication, Linked list, FSM and CRC (cyclic
redundancy check)
• Performance in terms of Coremark /MHz
Power & Performance:
GOPS/mW (@ Clk freq., Tech., Supply),
nA/MHz (@ Tech., Supply), mW/MHz (@ Tech., Supply)

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