GS-065-030-2-L

650 V E-mode GaN transistor

Datasheet

Features
• 650 V enhancement mode power transistor
• Bottom-cooled, 8x8 mm PDFN package
• RDS(on) = 50 mΩ
• IDS(max) = 30 A
• Simple gate drive requirements (0 V to 6 V)
Top View
• Transient tolerant gate drive (-20 V / +10 V)
• High switching frequency (> 1 MHz)
• Fast and controllable fall and rise times
• Reverse conduction capability
• Zero reverse recovery loss
• Source Sense (SS) pin for optimized gate drive
• RoHS 3 (6+4) compliant
Bottom View

Applications Description
• Bridgeless Totem Pole PFC The GS-065-030-2-L is an enhancement mode GaN-
• Consumer, Industrial and Datacenter High on-Silicon power transistor. The properties of GaN
Density Power Supply allow for high current, high voltage breakdown and
• High Power Adapters high switching frequency. GaN Systems innovates
• LED Lighting Drivers with industry leading advancements such as
• Appliance and Industrial Motor Drives patented Island Technology® cell layout which
• Solar Inverter realizes high-current die and high yield. The GS-065-
• Uninterruptable Power Supplies 030-2-L is a bottom-side cooled transistor that offers
• Laser Drivers low junction-to-case thermal resistance for
• Wireless Power Transfer demanding high power applications. These features
combine to provide very high efficiency power
switching.

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650 V E-mode GaN transistor
Datasheet

Absolute Maximum Ratings (Tcase = 25 °C except as noted)

Parameter Symbol Value Unit
Operating Junction Temperature TJ -55 to +150 °C
Storage Temperature Range TS -55 to +150 °C
Drain-to-Source Voltage VDS 650 V
Drain-to-Source Voltage - transient (Note 1) VDS(transient) 850 V
Gate-to-Source Voltage VGS -10 to +7 V
Gate-to-Source Voltage - transient (Note 1) VGS(transient) -20 to +10 V
Continuous Drain Current (Tcase = 25 °C) IDS 30 A
Continuous Drain Current (Tcase = 100 °C) IDS 20 A
Pulse Drain Current (Pulse width 10 µs, VGS = 6 V) (Note 2) IDS Pulse 60 A
(1) For < 100 µs
(2) Defined by product design and characterization. Value is not tested to full current in production.

Thermal Characteristics (Typical values unless otherwise noted)

Parameter Symbol Value Units
Thermal Resistance (junction-to-case) – bottom side RΘJC 0.5 °C / W
Thermal Resistance (junction-to-ambient) (Note 3) RΘJA 35 °C / W
Maximum Soldering Temperature (MSL3 rated) TSOLD 260 °C
(3) Device mounted on 1.6 mm PCB thickness FR4, 4-layer PCB with 2 oz. copper on each layer. The recommendation
for thermal vias under the thermal pad is 0.3 mm diameter (12 mil) with 0.635 mm pitch (25 mil). The copper
layers under the thermal pad and drain pad are 25 x 25 mm2 each. The PCB is mounted in horizontal position
without air stream cooling.

Ordering Information
Packing Reel Reel
Ordering code Package type Qty
method Diameter Width
GS-065-030-2-L-TR 8x8 mm PDFN Tape-and-Reel 3000 13” (330 mm) 16 mm

GS-065-030-2-L-MR 8x8 mm PDFN Mini-Reel 250 7” (180 mm) 16 mm

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650 V E-mode GaN transistor
Datasheet

Electrical Characteristics (Typical values at TJ = 25 °C, VGS = 6 V unless otherwise noted)

Parameters Sym. Min. Typ. Max. Units Conditions
Drain-to-Source Blocking Voltage V(BL)DSS 650 V VGS = 0 V, IDSS ≤ 58 µA
VGS = 6 V, TJ = 25°C
Drain-to-Source On Resistance RDS(on) 50 68 mΩ
IDS = 5.5 A
VGS = 6 V, TJ = 150 °C
Drain-to-Source On Resistance RDS(on) 127 mΩ
IDS = 5.5 A
Gate-to-Source Threshold VGS(th) 1.1 1.7 2.6 V VDS = VGS, IDS = 7.5 mA
Gate-to-Source Current IGS 182 µA VGS = 6 V, VDS = 0 V
Gate Plateau Voltage Vplat 3.5 V VDS = 400 V, IDS = 30 A
VDS = 650 V, VGS = 0 V
Drain-to-Source Leakage Current IDSS 2 58 µA
TJ = 25 °C
VDS = 650 V, VGS = 0 V
Drain-to-Source Leakage Current IDSS 70 µA
TJ = 150 °C
Internal Gate Resistance RG 1.3 Ω f = 5 MHz, open drain
Input Capacitance CISS 235 pF VDS = 400 V
Output Capacitance COSS 60 pF VGS = 0 V
Reverse Transfer Capacitance CRSS 0.6 pF f = 100 kHz

Effective Output Capacitance

CO(ER) 96 pF
Energy Related (Note 4) VGS = 0 V
Effective Output Capacitance VDS = 0 to 400 V
CO(TR) 150 pF
Time Related (Note 5)
Total Gate Charge QG 6.7 nC
VGS = 0 to 6 V
Gate-to-Source Charge QGS 1.9 nC
VDS = 400 V
Gate-to-Drain Charge QGD 2 nC
Output Charge QOSS 61 nC VGS = 0 V, VDS = 400 V
Reverse Recovery Charge QRR 0 nC
(4) CO(ER) is the fixed capacitance that would give the same stored energy as COSS while VDS is rising from 0 V to the
stated VDS
(5) CO(TR) is the fixed capacitance that would give the same charging time as COSS while VDS is rising from 0 V to the
stated VDS.

3
 GS-065-030-2-L
650 V E-mode GaN transistor
Datasheet

Electrical Characteristics cont’d (Typical values at TJ = 25 °C, VGS = 6 V unless otherwise noted)
Parameters Sym. Min. Typ. Max. Units Conditions
Turn-On Delay tD(on) 8.2 ns

Rise Time tR 6.3 ns

VDD = 400 V, VGS = +6/-3 V,
Turn-Off Delay tD(off) 10.8 ns IDS = 15 A,
RG(on) = 15 Ω, RG(off) = 2 Ω,
Fall Time tF 5.7 ns L = 90 µH, LP = 12 nH
(Notes 6, 7, 8)
Switching Energy during turn-on Eon 50 µJ

Switching Energy during turn-off Eoff 10 µJ

Output Capacitance Stored VDS = 400 V
EOSS 8 µJ
Energy VGS = 0 V, f = 100 kHz
(6) See Figure 16 for switching test circuit diagram.
(7) See Figure 17 for switching time definition waveforms.
(8) LP = parasitic inductance.

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650 V E-mode GaN transistor
Datasheet

Electrical Performance Graphs

IDS vs. VDS Characteristics IDS vs. VDS Characteristics

Figure 1: Typical IDS vs. VDS @ TJ = 25 ⁰C Figure 2: Typical IDS vs. VDS @ TJ = 150 ⁰C

RDS(on) vs. IDS Characteristics RDS(on) vs. IDS Characteristics

Figure 3: RDS(on) vs. IDS at TJ = 25 ⁰C Figure 4: RDS(on) vs. IDS at TJ = 150 ⁰C

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650 V E-mode GaN transistor
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Electrical Performance Graphs

IDS vs. VDS, TJ dependence Gate Charge, QG Characteristics

Figure 5: Typical IDS vs. VDS @ VGS = 6 V Figure 6: Typical VGS vs. QG @ VDS = 100, 400 V

Capacitance Characteristics Stored Energy Characteristics

Figure 7: Typical CISS, COSS, CRSS vs. VDS Figure 8: Typical COSS Stored Energy

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650 V E-mode GaN transistor
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Electrical Performance Graphs

Reverse Conduction Characteristics Reverse Conduction Characteristics

Figure 9: Typical ISD vs. VSD @ TJ = 25 ⁰C Figure 10: Typical ISD vs. VSD @ TJ = 150 ⁰C
IDS vs. VGS Characteristics RDS(on) Temperature Dependence

Figure 11: Typical IDS vs. VGS Figure 12: Normalized RDS(on) as a function of TJ

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650 V E-mode GaN transistor
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Thermal Performance Graphs

IDS vs VDS SOA Power Dissipation Temperature Derating

Figure 13: Safe Operating Area

Figure 14: Derating vs. Case Temperature
@ Tcase = 25C
Transient RΘjc

50 t C c

20

10

Figure 15: Transient Thermal Impedance

(1.00 = Nominal DC thermal impedance)

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650 V E-mode GaN transistor
Datasheet

Test Circuits

Figure 16: Switching Test Circuit

Figure 17: Switching Time Waveforms

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650 V E-mode GaN transistor
Datasheet

Application Information

Pin Configurations
Note that the Pin 1 (Source) is located at the bottom left corner from the top view indicated by the
pin 1 marking.

The package features a dedicated Source Sense (SS) pin (3) which enhances the switching performance
by eliminating the common source inductance. Source Sensing (or Kelvin Source) can be implemented
by using pin 3 (SS) as the gate driver signal ground return.

The thermal pad / Source (Pin 9) is designed to provide a low thermal resistance path to the external
main circuit board for optimum heat dissipation. It is internally connected to the die substrate and the
Source, which can be used for both thermal and electrical conduction. The Source pin 1 & 2 can also
be used together to enhance thermal conductivity, but it is NOT recommended to carry main current
with only Pin 1 & 2.

Pin Name Description

1-2 S Source
PDFN 8x8
3 SS Source Sense pin. Used for gate driver kelvin
Top View
source connection
4 G Gate
5-8 D Drain
9 S / TP Source and thermal pad. Recommend to join
pin 1, 2 and 9 together with large copper
polygon for optimum thermal dissipation
and source connection

Gate Drive
The recommended gate drive voltage range, VGS, is 0 V to + 6 V for optimal RDS(on) performance. Also,
the repetitive gate to source voltage, maximum rating, V GS(AC), is +7 V to -10 V. The gate can survive
non-repetitive transients up to +10 V and – 20 V for pulses up to 100 µs. These specifications allow
designers to easily use 6.0 V or 6.5 V gate drive settings. At 6 V gate drive voltage, the enhancement
mode high electron mobility transistor (E-HEMT) is fully enhanced and reaches its optimal efficiency
point. A 5 V gate drive can be used but may result in lower operating efficiency. Inherently, GaN
Systems E-HEMT do not require negative gate bias to turn off. Negative gate bias, typically V GS = -3 V,
ensures safe operation against the voltage spike on the gate, however it may increase reverse
conduction losses if not driven properly. For more details, please refer to the gate driver application
not "GN001 How to rv GaN Enhanc m nt Mod ow r w tch n Tran tor ” at
www.gansystems.com

Similar to a silicon MOSFET, an external gate resistor can be used to control the switching speed and
slew rate. Adjusting the resistor to achieve the desired slew rate may be needed. Lower turn-off gate
resistance, RG(OFF) is recommended for better immunity to cross conduction. Please see the gate driver
application note (GN001) for more details.

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A standard MOSFET driver can be used as long as it supports 6 V for gate drive and the UVLO is suitable
for 6 V operation. Gate drivers with low impedance and high peak current are recommended for fast
switching speed. GaN Systems E-HEMTs have significantly lower QG when compared to equally sized
RDS(on) MOSFETs, so high speed can be reached with smaller and lower cost gate drivers.

Some non-isolated half bridge MOSFET drivers are not compatible with 6 V gate drive due to their high
under-voltage lockout threshold. Also, a simple bootstrap method for high side gate drive may not be
able to provide tight tolerance on the gate voltage. Therefore, special care should be taken when you
select and use the half bridge drivers. Please see the gate driver application note (GN001) for more
details.

Parallel Operation
Design wide tracks or polygons on the PCB to distribute the gate drive signals to multiple devices. Keep
the drive loop length to each device as short and equal length as possible.

GaN enhancement mode HEMTs have a positive temperature coefficient on-state resistance which
helps to balance the current. However, special care should be taken in the driver circuit and PCB layout
since the device switches at very fast speed. It is recommended to have a symmetric PCB layout and
equal gate drive loop length (star connection if possible) on all parallel devices to ensure balanced
dynamic current sharing. Adding a small gate resistor (1-2 Ω) on ach at tron r comm nd d
to minimize the gate parasitic oscillation.

Thermal Modeling
RC thermal models are available to support detailed thermal simulation using SPICE. The thermal
models are created using the Cauer model, an RC network model that reflects the real physical property
and packaging structure of our devices. This approach allows our customers to extend the thermal
model to their system by adding extra Rθ and Cθ to simulate the Thermal Interface Material (TIM) or
Heatsink.

RC thermal model:

RC breakdown of RΘJC
Rθ (°C/W) Cθ (W∙s/°C)
Rθ1 = 0.02 Cθ1 = 9.0E-05
Rθ2 = 0.25 Cθ2 = 6.5E-04
Rθ3 = 0.21 Cθ3 = 7.0E-03
Rθ4 = 0.02 Cθ4 = 5.0E-03

For mor d ta , p a r f r to App cat on Not GN007 “Mod n Th rma B hav or of GaN t m ’
GaNPX® U n RC Th rma ICE Mod ” ava ab at www.gansystems.com
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Reverse Conduction
GaN Systems enhancement mode HEMTs do not have an intrinsic body diode and there is zero reverse
recovery charge. The devices are naturally capable of reverse conduction and exhibit different
characteristics depending on the gate voltage. Anti-parallel diodes are not required for GaN Systems
transistors as is the case for IGBTs to achieve reverse conduction performance.

On-state condition (VGS = +6 V): The reverse conduction characteristics of a GaN Systems enhancement
mode HEMT in the on-state is similar to that of a silicon MOSFET, with the I-V curve symmetrical about
the origin and it exhibits a channel resistance, RDS(on), similar to forward conduction operation.

Off-state condition (VGS ≤ 0 V): Th r v r charact r t c n th off-state are different from silicon
MOSFETs as the GaN device has no body diode. In the reverse direction, the device starts to conduct
when the gate voltage, with respect to the drain, VGD, exceeds the gate threshold voltage. At this point
th d v c xh b t a chann r tanc . Th cond t on can b mod d a a “bod d od ” w th ht
higher VF and no reverse recovery charge.

If negative gate voltage is used in the off-state, the source-drain voltage must be higher than
VGS(th)+VGS(off) in order to turn the device on. Therefore, a negative gate voltage will add to the reverse
vo ta drop “VF” and h nc ncr a th r v r cond ct on o .

Blocking Voltage
The blocking voltage rating, V(BL)DSS, is defined by the drain leakage current. The hard (unrecoverable)
breakdown voltage is approximately 30 % higher than the rated V (BL)DSS. As a general practice, the
maximum drain voltage should be de-rated in a similar manner as IGBTs or silicon MOSFETs. All GaN
E-HEMTs do not avalanche and thus do not have an avalanche breakdown rating. The maximum drain-
to-source rating is 650 V and does not change with negative gate voltage. GaN Systems tests devices
in production with a 850V Drain-to-source voltage pulse to insure blocking voltage margin.

Packaging and Soldering

The package is a standard PDFN and it can handle at least 3 reflow cycles.

It is recommended to use the reflow profile in IPC/JEDEC J-STD-020 REV D.1 (March 2008)

The basic temperature profiles for Pb-free (Sn-Ag-Cu) assembly are:

• Preheat/Soak: 60 - 120 seconds. Tmin = 150 °C, Tmax = 200 °C.

• Reflow: Ramp up rate 3 °C/sec, max. Peak temperature is 260 °C and time within 5 °C of peak
temperature is 30 seconds.

• Cool down: Ramp down rate 6 °C/sec max.

Usin “No-C an” o d r n pa t and op rat n at h h t mp rat r ma ca a r act vat on of th
“No-C an” f x r d . In xtr m cond t on , nwant d cond ct on path ma b cr at d. Th r for ,
when the product operates at greater than 100 C it is recomm nd d to a o c an th “No-C an”
paste residues.

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Recommended PCB Footprint

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Package Dimensions

Part Marking

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Tape and Reel Information

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Tape and Reel Box Dimensions

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Important Notice – Unless expressly approved in writing by an authorized representative of GaN Systems, GaN
Systems components are not designed, authorized or warranted for use in lifesaving, life sustaining, military, aircraft, or
space applications, nor in products or systems where failure or malfunction may result in personal injury, death, or property
or environmental damage. The information given in this document shall not in any event be regarded as a guarantee of
performance. GaN Systems hereby disclaims any or all warranties and liabilities of any kind, including but not limited to
warranties of non-infringement of intellectual property rights. All other brand and product names are trademarks or
registered trademarks of their respective owners. Information provided herein is intended as a guide only and is subject to
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conditions apply. All rights reserved.

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