ou

MARVELL CONFIDENTIAL
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
m Cover

4o
2vd
ih
o60
zs

D
z4
f5

PHYs
M 9stk
AR b

Datasheet
VE jm
LL 8vd

88Q5050
CO z1m
m NF jx
4o ID -jq
2vd

Marvell. Moving Forward Faster

EN 23
ih TI tlfs
o6 AL *
0z , U Sh
sz ND an
4f
5 ER gh
a

with 5 Integrated 100BASE-T1

M 9stk ND i H
AR b
VE jm A# ing
LL 8vd 8-Port Automotive Ethernet Switch
12 e E
16 lec
CO z1m 9 0 tr
NF jx 35 on
ID -jq ic
EN 23 Te
TI tlfs ch
AL * no
, U Sh lo

March 07, 2018

CONFIDENTIAL
ND an gy
ER gh Co
a
ND i H
A# ing

Doc. No. MV-S111158-00, Rev. –

12 e E
16 lec
90 tr
35 on
ic

Document Classification: Proprietary Information

Te
ch
no
lo
g y
Co
., L
ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technologyt Co., Ltd. * UNDER NDA# 121690
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Document Conventions
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Note: Provides related information or information of special importance.

9 0 tr
16 lec
12 e E
Caution: Indicates potential damage to hardware or software, or loss of data.

A# ing
ND i H
Warning: Indicates a risk of personal injury.

a
ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh

Co
AL *
TI tlfs

yg
EN 23

lo
no
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

For more information, visit our website at: http://www.marvell.com

AL *
4o

TI tlfs

Disclaimer
m
MARVELL CONFIDENTIAL

No part of this document may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, for any purpose,
EN 23

without the express written permission of Marvell. Marvell retains the right to make changes to this document at any time, without notice. Marvell makes no warranty of any
kind, expressed or implied, with regard to any information contained in this document, including, but not limited to, the implied warranties of merchantability or fitness for any
ID -jq

particular purpose. Further, Marvell does not warrant the accuracy or completeness of the information, text, graphics, or other items contained within this document.
ou

Marvell products are not designed for use in life-support equipment or applications that would cause a life-threatening situation if any such products failed. Do not use
NF jx

Marvell products in these types of equipment or applications.

With respect to the products described herein, the user or recipient, in the absence of appropriate U.S. government authorization, agrees:
CO z1m

1) Not to re-export or release any such information consisting of technology, software or source code controlled for national security reasons by the U.S. Export Control
Regulations ("EAR"), to a national of EAR Country Groups D:1 or E:2;
2) Not to export the direct product of such technology or such software, to EAR Country Groups D:1 or E:2, if such technology or software and direct products thereof are
LL 8vd

controlled for national security reasons by the EAR; and,

3) In the case of technology controlled for national security reasons under the EAR where the direct product of the technology is a complete plant or component of a plant,
not to export to EAR Country Groups D:1 or E:2 the direct product of the plant or major component thereof, if such direct product is controlled for national security reasons
VE jm

by the EAR, or is subject to controls under the U.S. Munitions List ("USML").
At all times hereunder, the recipient of any such information agrees that they shall be deemed to have manually signed this document in connection with their receipt of any
AR b

such information.
M 9stk

Copyright © 1999–2018. Marvell International Ltd. All rights reserved. Alaska, ARMADA, Avanta, Avastar, CarrierSpan, FLC, HyperDuo, Kirkwood, Link Street, LinkCrypt,
Marvell logo, Marvell, Marvell EZ-Connect, Marvell Smart, Marvell VSoC, MoChi, Moving Forward Faster, PISC, Prestera, Virtual Cable Tester, The World as YOU See It,
Xelerated, and Yukon are registered trademarks of Marvell or its affiliates. ArmadaBoard, Marvell COFFEEbin, Marvell ESPRESSObin, Marvell MACCHIATObin, and
NANDEdge are trademarks of Marvell or its affiliates.
5
4f

Patent(s) Pending—Products identified in this document may be covered by one or more Marvell patents and/or patent applications.
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 2 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Table of Contents

no
ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table of Contents

9 0 tr
16 lec
12 e E
Introduction ............................................................................................................................................. 11
Document Scope ................................................................................................................................................ 11

A# ing
Related Documentation ...................................................................................................................................... 11

ND i H
a
1 88Q5050 Functional Description ................................................................................................... 12

ER gh
1.1 Overview ............................................................................................................................................................. 12

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
1.2 Device Configuration ........................................................................................................................................... 14

., L
, U Sh
1.3 Application Cases ............................................................................................................................................... 16

Co
AL *

1.3.1 Switch Managed by the Internal CPU ................................................................................................... 16

TI tlfs

1.3.2 Switch Managed by an External CPU .................................................................................................. 16

g y
1.3.3 Unmanaged Switch .............................................................................................................................. 17
EN 23

lo
1.4 Data Path and Control Paths .............................................................................................................................. 18

no
ID -jq

ch
NF jx

2 Signal Description .......................................................................................................................... 20

CO z1m

Te
2.1 Pinout .................................................................................................................................................................. 20

ic
2.2 Pin Descriptions .................................................................................................................................................. 21
LL 8vd

35 on
2.2.1 Clock, Reset, Interrupt, and Reference ................................................................................................ 21

90 tr
2.2.2 100BASE-T1 Interface (Ports 1 to 5) .................................................................................................... 22
VE jm

16 lec
2.2.3 100BASE-TX Interface (Port 6) ............................................................................................................ 22
AR b

2.2.4 Gigabit SERDES Interface (Port 7) ...................................................................................................... 23

M 9stk

12 e E
2.2.5 xMII (Port 5/6/7) .................................................................................................................................... 23
2.2.6 xMII/GMII (Port 8) ................................................................................................................................. 26

A# ing
f5

2.2.7 SMI ....................................................................................................................................................... 28

z4

2.2.8 ND i H
QSPI ..................................................................................................................................................... 29
zs

2.2.9 TWSI ..................................................................................................................................................... 30

a
60

ER gh

2.2.10 GPIO Interface ...................................................................................................................................... 30

2.2.11 LED and EEPROM Interface ................................................................................................................ 31
o

ND an
ih

2.2.12 JTAG Interface ..................................................................................................................................... 33

, U Sh
vd

2.2.13 Test ....................................................................................................................................................... 33

2.2.14 Internal CPU Trace Interface ................................................................................................................ 33
2

AL *
4o

2.2.15 Low-Power Signal Detect ..................................................................................................................... 34

TI tlfs

2.2.16 Power and Ground ............................................................................................................................... 35

m
MARVELL CONFIDENTIAL

EN 23

2.3 Configuration Pins (Bootstrapping) ..................................................................................................................... 36

ID -jq

2.3.1 Bootstrap Options ................................................................................................................................. 36

ou

2.3.2 Pin Connection Information .................................................................................................................. 39

NF jx

2.3.2.1 Slave Address (MDC/MDIO_CPU Interface) .................................................................... 39

CO z1m

2.3.2.2 CPU State ........................................................................................................................ 40

2.3.2.3 Port State ......................................................................................................................... 40
LL 8vd

2.3.2.4 100BASE-T1 PHY Mode .................................................................................................. 40

2.3.2.5 100BASE-T1 Wake Mode ................................................................................................ 41
VE jm

2.3.2.6 P567 Mode ....................................................................................................................... 41

AR b

2.3.2.7 P567 Interface Select ....................................................................................................... 41

M 9stk

2.3.2.8 P567 Power Supply Voltage Select .................................................................................. 42

2.3.2.9 P8 Mode ........................................................................................................................... 43
5

2.3.2.10 P8 Power Supply Voltage Select ...................................................................................... 43

4f

2.3.2.11 RMU Port Select ............................................................................................................... 43

sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 3

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
3 Device Physical Interfaces ............................................................................................................. 44
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
3.1 Port Configuration ............................................................................................................................................... 44

35 on
3.2 Interfaces ............................................................................................................................................................ 46

9 0 tr
3.2.1 100BASE-T1 PHY Interface ................................................................................................................. 46

16 lec
3.2.2 100BASE-TX PHY Interface ................................................................................................................. 46

12 e E
3.2.3 SERDES Interface ................................................................................................................................ 47
3.2.3.1 Triple-Speed PHY SERDES Interface Option .................................................................. 47

A# ing
3.2.3.2 IEEE 1000BASE-X SERDES Interface Option ................................................................. 47
3.2.3.3 Port Status Registers ....................................................................................................... 47

ND i H
3.2.4 Digital Interface Options ....................................................................................................................... 47

a
3.2.4.1 MII MAC Mode ................................................................................................................. 48

ER gh
3.2.4.2 MII PHY Mode .................................................................................................................. 49

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
3.2.4.3 RMII MAC Mode ............................................................................................................... 49

., L
3.2.4.4 RMII PHY Mode ............................................................................................................... 50
, U Sh
3.2.4.5 RGMII Mode ..................................................................................................................... 51

Co
AL *

3.2.4.6 GMII MAC Mode ............................................................................................................... 52

TI tlfs

3.2.4.7 GMII PHY Mode ............................................................................................................... 53

g y
3.2.5 PHY Polling Unit (PPU) ........................................................................................................................ 54
EN 23

lo
no
ID -jq

4 Electrical Specifications ................................................................................................................ 55

ch
NF jx

4.1 Absolute Maximum Ratings ................................................................................................................................ 55

CO z1m

Te
4.2 Recommended Operating Conditions ................................................................................................................. 56

ic
LL 8vd

4.3 DC Electrical Characteristics .............................................................................................................................. 56

35 on
4.3.1 Main Clock ............................................................................................................................................ 56

90 tr
VE jm

4.3.2 100BASE-T1 Transceiver ..................................................................................................................... 57

16 lec
4.3.3 100BASE-TX Transceiver .................................................................................................................... 57
AR b
M 9stk

4.3.4 SGMII ................................................................................................................................................... 58

12 e E
4.3.4.1 Common Mode Voltage (VOffset) Calculations .................................................................. 59

A# ing
4.3.5 Digital Pins ............................................................................................................................................ 62
f5

4.3.6 Internal Resistors .................................................................................................................................. 67

z4

4.3.7
ND i H
Low Power Signal Detect ..................................................................................................................... 67
zs

a
4.4 AC Electrical Characteristics ............................................................................................................................... 67
60

ER gh

4.4.1 Main Clock ............................................................................................................................................ 67

o

ND an

4.4.2 Power-On Reset ................................................................................................................................... 68

ih

4.4.3 100BASE-T1 Transceiver ..................................................................................................................... 68

, U Sh
vd

4.4.4 100BASE-TX Transceiver .................................................................................................................... 68

2

AL *

4.4.5 SGMII ................................................................................................................................................... 69

4o

TI tlfs

4.4.6 MII ......................................................................................................................................................... 70

m
MARVELL CONFIDENTIAL

4.4.6.1 PHY Mode ........................................................................................................................ 70

EN 23

4.4.6.2 MAC Mode ....................................................................................................................... 71

ID -jq
ou

4.4.7 RMII ...................................................................................................................................................... 73

4.4.8 RGMII ................................................................................................................................................... 75
NF jx

4.4.8.1 Output Timing With/Without Delay Control ....................................................................... 77

CO z1m

4.4.8.2 Input Timing With/Without Delay Control ......................................................................... 78

4.4.9 GMII ...................................................................................................................................................... 79
LL 8vd

4.4.10 SMI ....................................................................................................................................................... 80

4.4.10.1 SMI Clock – CPU Set (Slave) ........................................................................................... 80
VE jm

4.4.10.2 SMI Data – CPU Set (Slave) ............................................................................................ 81

AR b

4.4.10.3 SMI – PHY Set (Master) ................................................................................................... 82

M 9stk

4.4.11 QSPI ..................................................................................................................................................... 83

4.4.12 TWSI ..................................................................................................................................................... 83
5

4.4.13 EEPROM Interface ............................................................................................................................... 84

4f

4.4.14 JTAG Interface ..................................................................................................................................... 85

sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 4 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Table of Contents

no
ch
Te
4.4.15 Low Power Signal Detect ..................................................................................................................... 85
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
5 Package Specifications .................................................................................................................. 86

9 0 tr
5.1 Thermal Information ............................................................................................................................................ 86

16 lec
5.2 Mechanical Drawing ............................................................................................................................................ 87

12 e E
6 Part Order Numbering/Package Marking ...................................................................................... 89

A# ing
6.1 Part Order Numbering ......................................................................................................................................... 89

ND i H
6.2 Package Marking ................................................................................................................................................ 90

a
ER gh
A Acronyms and Abbreviations ........................................................................................................ 91

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
B Revision History ............................................................................................................................. 96

Co
AL *
TI tlfs

gy
EN 23

lo
no
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 5

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
List of Tables

9 0 tr
16 lec
12 e E
Introduction............................................................................................................................................... 11

A# ing
1 88Q5050 Functional Description ..................................................................................................... 12
Table 1: Interface Combinations .....................................................................................................................13

ND i H
a
2 Signal Description ............................................................................................................................ 20

ER gh
Table 2: Pin Type Definitions ..........................................................................................................................21

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
Table 3: Clock, Reset, Interrupt, and Reference ............................................................................................21
, U Sh
Table 4: 100BASE-T1 Interface (Ports 1 to 5) ................................................................................................22

Co
AL *

Table 5: 100BASE-TX Interface (Port 6) ........................................................................................................22

TI tlfs

y
Table 6: Gigabit SERDES Interface (Port 7)...................................................................................................23

g
EN 23

lo
Table 7: xMII (Port 5/6/7) ................................................................................................................................23

no
ID -jq

Table 8: xMII/GMII (Port 8) .............................................................................................................................26

ch
NF jx

Table 9: SMI ...................................................................................................................................................28

CO z1m

Te
Table 10: QSPI .................................................................................................................................................29

ic
Table 11: TWSI .................................................................................................................................................30
LL 8vd

35 on
Table 12: GPIO Interface ..................................................................................................................................30

90 tr
VE jm

Table 13: LED and EEPROM Interface ............................................................................................................31

16 lec
AR b

Table 14: LED Port-to-PHY Mapping................................................................................................................32

M 9stk

12 e E
Table 15: JTAG Interface..................................................................................................................................33

A# ing
Table 16: Test ...................................................................................................................................................33
f5

Table 17: Internal CPU Trace Interface ............................................................................................................33

z4

ND i H
Table 18: Low-Power Signal Detect .................................................................................................................34
zs

a
60

Table 19: Power and Ground............................................................................................................................35

ER gh
o

Table 20: Bootstrap Options .............................................................................................................................37

ND an
ih

Table 21: ADDRn[4], ADDRn[2:0] Configuration ..............................................................................................39

, U Sh
vd

Table 22: CPU_EN Configuration .....................................................................................................................40

2

AL *
4o

Table 23: Px_ACTIVEn Configuration ..............................................................................................................40

TI tlfs
m

Table 24: Px_MASTER Configuration ..............................................................................................................40

MARVELL CONFIDENTIAL

EN 23

Table 25: Px_WAKE_DIS Pin Configuration ....................................................................................................41

ID -jq
ou

Table 26: P567_MODE[2:0] Configuration .......................................................................................................41

NF jx

Table 27: P567_SEL[1], P567_SELn[0] Configuration .....................................................................................41

CO z1m

Table 28: P567_VDDO_SEL[1:0] Configuration ...............................................................................................42

Table 29: P8_MODEn[2], P8_MODE[1:0] Configuration ..................................................................................43
LL 8vd

Table 30: P8_VDDO_SEL[1:0] Configuration ...................................................................................................43

VE jm

Table 31: RMU_SELn[1:0] Configuration .........................................................................................................43

AR b
M 9stk

3 Device Physical Interfaces............................................................................................................... 44

Table 32: Interface Combinations .....................................................................................................................44
5

Table 33: Port 5/6/7 Configuration ....................................................................................................................45

4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 6 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
List of Tables

no
ch
Te
Table 34: Port 8 Configuration ..........................................................................................................................46
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
4 Electrical Specifications .................................................................................................................. 55

9 0 tr
Table 35: Absolute Maximum Ratings ..............................................................................................................55

16 lec
Table 36: Recommended Operating Conditions...............................................................................................56

12 e E
Table 37: Main Clock (XTAL_IN) DC Characteristics .......................................................................................56
Table 38: 100BASE-T1 Transceiver DC Characteristics ..................................................................................57

A# ing
Table 39: 100BASE-TX Transceiver DC Characteristics..................................................................................57

ND i H
Table 40: SGMII Output DC Characteristics .....................................................................................................58

a
Table 41: Programmable SGMII Output Amplitude (SERDES Page 1 Register 26) ........................................58

ER gh
Table 42: SGMII Input DC Characteristics........................................................................................................62

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
Table 43: DC Characteristics for Pins GPIO[4:0], INTn, MDC_CPU, MDC_PHY, MDIO_CPU,
, U Sh
MDIO_PHY, RESETn, SPI_CS, SPI_SCLK, SPI_SIO[3:0], TCK, TDI, TDO, TEST, TMS,

Co
TRSTn ..............................................................................................................................................62
AL *
TI tlfs

Table 44: DC Characteristics for Pins P567_INCLK, P567_IND[3:0], P567_INDV, P8_INCLK,

gy
P8_IND[3:0], P8_INDV .....................................................................................................................63
EN 23

lo
Table 45: DC Characteristics for Pins P567_OUTCLK, P567_OUTD[3:0], P567_OUTEN, P8_OUTCLK,

no
ID -jq

P8_OUTD[3:0], P8_OUTEN .............................................................................................................64

ch
NF jx

Table 46: DC Characteristics for Pins C_LED[3:0] ..........................................................................................65

CO z1m

Te
Table 47: DC Characteristics for Pins TRACECLK, TRACEDATA[3:0], TRACESWO .....................................65

ic
Table 48: DC Characteristics for Pin R_LEDn[2:0] ..........................................................................................66
LL 8vd

35 on
Table 49: DC Characteristics for 5V Tolerant OC Pins TWSI_SCK, TWSI_SDA ............................................66

90 tr
VE jm

Table 50: Low Power Signal Detect DC Characteristics...................................................................................67

16 lec
AR b

Table 51: Main Clock (XTAL_IN) AC Characteristics .......................................................................................67

M 9stk

12 e E
Table 52: Power-On Reset AC Characteristics ................................................................................................68

A# ing
Table 53: 100BASE-T1 Transceiver AC Characteristics ..................................................................................68
f5
z4

Table 54: 100BASE-TX Transceiver AC Characteristics ..................................................................................68

ND i H
zs

Table 55: SGMII Output AC Characteristics .....................................................................................................69

a
60

ER gh

Table 56: SGMII Input AC Characteristics ........................................................................................................69

o

ND an

Table 57: MII PHY Mode Input AC Characteristics Timing ...............................................................................70

ih

Table 58: MII PHY Mode Output AC Characteristics ........................................................................................71

, U Sh
vd

Table 59: MII MAC Mode Input AC Characteristics ..........................................................................................72

2

AL *
4o

Table 60: MII MAC Mode Output AC Characteristics .......................................................................................72

TI tlfs
m
MARVELL CONFIDENTIAL

Table 61: RMII Input AC Characteristics, Using OUTCLK................................................................................73

EN 23

Table 62: RMII Output AC Characteristics, Using OUTCLK .............................................................................74

ID -jq
ou

Table 63: RGMII AC Characteristics.................................................................................................................75

NF jx

Table 64: Output (OUTCLK (TXC)) Timing when RGMII Tx Delay Control (Offset 0x01, Bit 14) = 0...............77
CO z1m

Table 65: Output (OUTCLK (TXC)) Timing when RGMII Tx Delay Control (Offset 0x01, Bit 14) = 1...............77
Table 66: Input (INCLK (RXC)) Timing when RGMII Rx Delay Control (Offset 0x01, Bit 15) = 0.....................78
LL 8vd

Table 67: Input (INCLK (RXC)) Timing when RGMII Rx Delay Control (Offset 0x01, Bit 15) = 1.....................78
VE jm

Table 68: GMII Input AC Characteristics ..........................................................................................................79

AR b

Table 69: GMII Output AC Characteristics .......................................................................................................79

M 9stk

Table 70: SMI Clock AC Characteristics – CPU Set.........................................................................................80

Table 71: SMI Data AC Characteristics – CPU Set ..........................................................................................81
5
4f

Table 72: SMI AC Characteristics – PHY Set ...................................................................................................82

sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 7

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 73: QSPI AC Characteristics ..................................................................................................................83
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
Table 74: TWSI AC Characteristics ..................................................................................................................83

35 on
Table 75: EEPROM AC Characteristics ...........................................................................................................84

9 0 tr
Table 76: JTAG AC Characteristics ..................................................................................................................85

16 lec
Table 77: Low Power Signal Detect AC Characteristics ...................................................................................85

12 e E
5 Package Specifications.................................................................................................................... 86

A# ing
Table 78: 128-Pin LQFP Package Thermal Information ...................................................................................86

ND i H
Table 79: 128-Pin LQFP Package Dimensions ................................................................................................88

a
ER gh
6 Part Order Numbering/Package Marking........................................................................................ 89

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Table 80: 88Q5050 Part Order Options ............................................................................................................89

., L
, U Sh
A Acronyms and Abbreviations .......................................................................................................... 91

Co
AL *
TI tlfs

B Revision History ............................................................................................................................... 96

gy
EN 23

Table 1: Revision History ................................................................................................................................96

lo
no
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 8 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
List of Figures

no
ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
List of Figures

9 0 tr
16 lec
12 e E
Introduction............................................................................................................................................... 11

A# ing
1 88Q5050 Functional Description ..................................................................................................... 12

ND i H
Figure 1: 88Q5050 Block Diagram...................................................................................................................14
Figure 2: Device Configuration During Boot Process ......................................................................................15

a
ER gh
Figure 3: Switch Managed by Internal CPU .....................................................................................................16

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Figure 4: Switch Managed by External CPU (Connected over SMI)................................................................16

., L
, U Sh
Figure 5: Switch Managed by External CPU (Connected over Ethernet) ........................................................17

Co
Figure 6: Unmanaged Switch...........................................................................................................................17
AL *
TI tlfs

Figure 7: Unmanaged Switch with External EEPROM ....................................................................................17

gy
Figure 8: Data Path and Control Paths ............................................................................................................19
EN 23

lo
no
ID -jq

2 Signal Description ............................................................................................................................ 20

ch
NF jx

Figure 9: 88Q5050 128-Pin LQFP Package (Top View) ..................................................................................20

CO z1m

Te
ic
3 Device Physical Interfaces............................................................................................................... 44
LL 8vd

35 on
Figure 10: MII MAC Interface Pins .....................................................................................................................48

90 tr
VE jm

Figure 11: MII PHY Interface Pins .....................................................................................................................49

16 lec
AR b

Figure 12: RMII MAC Interface Pins ..................................................................................................................49

M 9stk

12 e E
Figure 13: RMII PHY Interface Pins ...................................................................................................................50

A# ing
Figure 14: RGMII Pins .......................................................................................................................................51
f5

Figure 15: GMII MAC Interface Pins ..................................................................................................................52

z4

ND i H
Figure 16: GMII PHY Interface Pins...................................................................................................................53
zs

a
60

ER gh

4 Electrical Specifications .................................................................................................................. 55

o

ND an
ih

Figure 17: CML I/Os...........................................................................................................................................59

, U Sh
vd

Figure 18: AC Connections (CML or LVS Receiver) or DC Connection LVDS Receiver...................................60

2

AL *

Figure 19: DC Connection to a CML Receiver...................................................................................................61

4o

TI tlfs

Figure 20: Input Differential Hysteresis ..............................................................................................................62

m
MARVELL CONFIDENTIAL

EN 23

Figure 21: Power-On Reset Timing ...................................................................................................................68

ID -jq

Figure 22: Serial Interface Rise and Fall Times .................................................................................................69

ou

NF jx

Figure 23: MII PHY Mode Input Timing..............................................................................................................70

CO z1m

Figure 24: MII PHY Mode Output Timing ...........................................................................................................71

Figure 25: MII MAC Mode Input Timing .............................................................................................................72
LL 8vd

Figure 26: MII MAC Mode Output Timing ..........................................................................................................73

Figure 27: RMII Input Timing, Using OUTCLK...................................................................................................74
VE jm

Figure 28: RMII Output Timing, Using OUTCLK ................................................................................................75

AR b
M 9stk

Figure 29: RGMII Multiplexing and Timing.........................................................................................................76

Figure 30: Output (OUTCLK (TXC)) Timing when RGMII Tx Delay Control (Bit 14) = 0 ...................................77
5
4f

Figure 31: Output (OUTCLK (TXC)) Timing when RGMII Tx Delay Control (Bit 14) = 1 ...................................77
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 9

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Figure 32: Input (INCLK (RXC)) Timing when RGMII Rx Delay Control (Bit 15) = 0 .........................................78
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
Figure 33: Input (INCLK (RXC)) Timing when RGMII Rx Delay Control (Bit 15) = 1 .........................................78

35 on
Figure 34: GMII Input Timing .............................................................................................................................79

9 0 tr
Figure 35: GMII Output Timing ..........................................................................................................................80

16 lec
Figure 36: SMI Clock Timing – CPU Set............................................................................................................81

12 e E
Figure 37: SMI Data Timing – CPU Set .............................................................................................................81

A# ing
Figure 38: SMI Output Timing – PHY Set ..........................................................................................................82
Figure 39: SMI Input Timing – PHY Set .............................................................................................................83

ND i H
Figure 40: TWSI Timing .....................................................................................................................................84

a
ER gh
Figure 41: EEPROM Interface Timing ...............................................................................................................84

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
5 Package Specifications.................................................................................................................... 86
, U Sh
Figure 42: 128-Pin LQFP Package Drawing ......................................................................................................87

Co
AL *
TI tlfs

y
6 Part Order Numbering/Package Marking........................................................................................ 89

g
EN 23

lo
Figure 43: Sample Part Number ........................................................................................................................89

no
ID -jq

Figure 44: Sample Package Marking and Pin 1 Location ..................................................................................90

ch
NF jx

A Acronyms and Abbreviations .......................................................................................................... 91

CO z1m

Te
ic
B Revision History ............................................................................................................................... 96
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 10 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Introduction

no
ch
Te
Introduction
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
9 0 tr
Document Scope

16 lec
12 e E
This document is intended to provide information about the Marvell® 88Q5050 device for system design. It includes the
device’s pinout, electrical specifications, package type, and high level functionalities.

A# ing
Related Documentation

ND i H
a
The following documents are related to this datasheet:

ER gh
 88Q5050 Functional Specification, MV-S111254-00

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
88Q5050 Register Specification, MV-S111251-00

., L
 , U Sh
 RD-ACE-88Q5050-1 Automotive Ethernet Switch Reference Design, MV-L101155

Co
AL *
TI tlfs

yg
EN 23

lo
no
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 11

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
88Q5050 Functional Description

9 0 tr
16 lec
12 e E
1.1 Overview

A# ing
The Marvell® 88Q5050 device is an AEC-Q100 qualified 8-port Ethernet switch, which is optimized
for Automotive applications. Being equipped with configurable interfaces that support a combination

ND i H
of eight IEEE 100BASE-T1, 100BASE-TX, RGMII/RMII/MII, GMII, and SGMII ports, the switch is

a
ideally suited for various application cases. The switching core is designed to support all MAC ports

ER gh
operating at 1000 Mbps.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
The 88Q5050 includes an ARM® CPU featured with a dedicated on-chip RAM, to support AVB

., L
, U Sh
protocols such as Precision Time Protocol (PTP). It provides support for TCAM with a Policy Control

Co
List (PCL) engine that supports 256 rules.
AL *
TI tlfs

Both the low-power PHYs and the MACs integrated in the device comply fully with the applicable

yg
sections of the IEEE 802.3 standards. The IEEE 100BASE-T1 PHYs are all fully interoperable with
EN 23

lo
the OPEN Alliance BroadR-Reach® (OABR) PHYs.

no
ID -jq

The 88Q5050 device's feature set is complemented by comprehensive local and remote

ch
NF jx

management capabilities, which allow for easy access and configuration of the device.
CO z1m

Te
Package Characteristics

ic
LL 8vd

35 on
 128-pin LQFP package, 0.5 mm pitch, 14 mm × 20 mm

90 tr
Power supplies: 1.0V, 1.8V, 2.5V (optional), 3.3V
VE jm

16 lec
 Estimated power consumption: ~ 1.5W
AR b
M 9stk

12 e E
General Features

A# ing
f5

 Integrated CPU: ARM® Cortex®-M7, 250 MHz

z4

with instruction cache and 512 KB Tightly Coupled Memory (TCM)

ND i H
zs

 AEC-Q100 Grade 2 qualified

a
60

ER gh

 Automotive security implemented

o

Multiple boot options available

ND an


ih

, U Sh
vd

Environment
2

AL *

 Rated for Automotive Grade 2 operation: -40 to +105 degrees C ambient temperature
4o

TI tlfs
m
MARVELL CONFIDENTIAL

Interfaces
EN 23

4 × IEEE 100BASE-T1 (IEEE 802.3bw™)

ID -jq


ou

 Additional 6 configurable interfaces (4 ports active concurrently):

NF jx

• 1 × IEEE 100BASE-T1
CO z1m

• 1 × 100BASE-TX
LL 8vd

• 2 × MII / RMII / RGMII

• 1 × GMII
VE jm

• 1 × SGMII
AR b
M 9stk

 2 × SMI
• Master interface to connect to external PHYs or additional switches
5

• Slave interface to manage the switch

4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 12 Document Classification: Proprietary Information March 07, 2018

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050 Functional Description

no
Overview

ch
Te
Configurable GPIOs
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
 QSPI with configurable frequencies of 19.2 MHz up to 83.3 MHz

35 on
• Supported commands: Single (Read, Fast Read, Write (PP)), Dual (Output Read, I/O Read),

9 0 tr
Quad (Output Read, I/O Read)

16 lec
• Supported single data rate clock modes: Mode 0 and Mode 3

12 e E
 EEPROM Slave interface with loader that can be used to configure the switch
Supported EEPROM devices: 32 Kb up to 512 Kb

A# ing
 TWSI Master interface

ND i H
 Shared JTAG interface for either ATE or debugging

a
Table 1 lists the possible interface combinations that can be configured for the 88Q5050 device’s

ER gh
ports. “xMII” stands for “MII/ RMII/ RGMII”. Each table row shows one combination, that is, there is a

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
total of 5 possible interface combinations.

., L
, U Sh
Table 1: Interface Combinations

Co
AL *

Ports 1 to 4 Port 5 Port 6 Port 7 Port 8 Notes

TI tlfs

y
100BASE-T1 100BASE-T 100BASE-T SGMII xMII /

g
EN 23

lo
1 X GMII

no
ID -jq

100BASE-T1 xMII 100BASE-T SGMII xMII Ports 5, 6, and 7 are shared. If any of

ch
NF jx

X these ports is configured as MII, RMII, or

CO z1m

RGMII, the two other ports can only be

Te
100BASE-T1 100BASE-T xMII SGMII xMII
PHY or SERDES, respectively (that is,
1

ic
port 5 configured as 100BASE-T1
LL 8vd

35 on
100BASE-T1 100BASE-T 100BASE-T xMII xMII interface, port 6 as 100BASE-TX interface,
1 X and port 7 as SGMII).

90 tr
VE jm

16 lec
100BASE-T1 100BASE-T 100BASE-T SGMII GMII If port 8 is configured as GMII, ports 5, 6,
AR b

1 X and 7 can only be PHY or SERDES,

M 9stk

12 e E
respectively.

A# ing
f5
z4

ND i H
Figure 1 shows the 88Q5050 device’s block diagram.
zs

a
60

ER gh

Figure 1 shows a high-level block diagram of the 88Q5050 device; Figure 2 provides a more detailed
view.
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 13

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 1: 88Q5050 Block Diagram

ic
35 on
9 0 tr
Packet Memory CPU

16 lec
GPIO
+ 1 KB MAC Memory ARM Cortex-M7

12 e E
with Integrated SRAM
QSPI
Queue Controller

A# ing
Master
8-Level QoS per Port
256-Entry TCAM

ND i H
JTAG

a
ER gh
Gigabit Switch Fabric

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
PLL

., L
, U Sh
AVB/TSN Queue Shaping Ingress AVB Policy

Co
802.1Qav/Qbv and Rate Limiting SMI
AL *
TI tlfs

yg
EN 23

802.1AS

lo
TWSI

no
ID -jq

ch
NF jx

4× 6 Configurable Interfaces EEPROM

100BASE-T1 T1 / TX / 2 × xMII / GMII / SGMII Interface
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
1.2 Device Configuration
AR b
M 9stk

12 e E
The initial configuration of the 88Q5050 device takes place during the boot process, as shown in

A# ing
Figure 2. There are three options available for configuring the 88Q5050 device:
f5
z4

 Configuration pins (bootstrapping) ND i H

zs

 Configuration data stored in an optional EEPROM

a
60

ER gh

 Configuration done by firmware (which requires an attached SPI memory device)

o

Which of these options are used depends on the application case, and additionally on the timing
ND an
ih

requirements. The bootstrap option is very fast, that is, the configuration pin settings already take
, U Sh
vd

effect even before a PHY link is established. The EEPROM interface runs at a speed of up to
2

200 kHz. Once the EEPROM loader is finished (in case an EEPROM is attached), the SPI firmware
AL *
4o

TI tlfs

continues with the device configuration. The load time of the firmware in the SPI memory device
m

depends on the size of the firmware, boot procedure (trusted/non-trusted), and the SPI configuration
MARVELL CONFIDENTIAL

EN 23

(single/dual/quad read and read speed).

ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 14 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050 Functional Description

no
Device Configuration

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 2: Device Configuration During Boot Process

ic
35 on
9 0 tr
Power On

16 lec
12 e E
A# ing
ND i H
Bootstrap Pins

a
ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh

Co
AL *
TI tlfs

EEPROM

yg
Configuration Data1
EN 23

lo
no
ID -jq

ch
NF jx
CO z1m

Te
ic
1
Only if an EEPROM is attached
LL 8vd

35 on
SPI Firmware2 2
Only if the internal CPU is enabled

90 tr
VE jm

(in this case, an SPI memory device needs

16 lec
to be attached)
AR b
M 9stk

12 e E
After the boot process is finished, the 88Q5050 device can be configured further by RMU, JTAG,

A# ing
f5

SMI, and the internal CPU’s firmware (if CPU enabled).

z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 15

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
1.3 Application Cases
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Depending on its configuration, the 88Q5050 device can be used for various application cases:

9 0 tr
 Switch managed by the internal CPU

16 lec
 Switch managed by an external CPU

12 e E
 Unmanaged switch
In all cases, an external EEPROM can optionally be attached. For a detailed description of the

A# ing
application cases, see the following subsections.

ND i H
1.3.1 Switch Managed by the Internal CPU

a
ER gh
In this application case, the internal CPU is enabled and manages the switch. It requires an external

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
SPI memory device being attached.

., L
, U Sh
Figure 3: Switch Managed by Internal CPU

Co
AL *
TI tlfs

y
88Q5050

g
EN 23

lo
CPU

no
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
1.3.2 Switch Managed by an External CPU
AR b
M 9stk

12 e E
In this application case, the internal CPU is disabled, and an external CPU manages the switch. The
external CPU can be connected either over the SMI or over Ethernet.

A# ing
f5
z4

External CPU Connected over SMI ND i H

zs

a
Figure 4: Switch Managed by External CPU (Connected over SMI)
60

ER gh
o

ND an
ih

88Q5050 SMI
, U Sh

Management
vd

CPU
2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m

External CPU Connected over Ethernet

LL 8vd

If the external CPU is connected over Ethernet, either of the following ports can be used for Remote
Management Unit (RMU) management frames: port 1 (IEEE 100BASE-T1 PHY), port 7
VE jm

(SGMII/xMII), or port 8 (GMII/xMII). The RMU port configuration is done by the configuration pins.
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 16 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050 Functional Description

no
Application Cases

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 5: Switch Managed by External CPU (Connected over Ethernet)

ic
35 on
9 0 tr
88Q5050

16 lec
12 e E
A# ing
Ethernet Management
RMU
CPU

ND i H
a
ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
1.3.3 Unmanaged Switch

., L
, U Sh

Co
In this application case, the internal CPU and RMU are disabled, that is, the switch is unmanaged.
AL *

Optionally, an external EEPROM can be attached.

TI tlfs

yg
Unmanaged Switch without External EEPROM
EN 23

lo
no
ID -jq

Without an external EEPROM, the switch can be configured by bootstrapping only.

ch
NF jx

Figure 6: Unmanaged Switch

CO z1m

Te
ic
88Q5050
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

Unmanaged Switch with External EEPROM

60

ER gh
o

With an external EEPROM attached, configuration data can be loaded using a register loader.
ND an
ih

, U Sh
vd

Figure 7: Unmanaged Switch with External EEPROM

2

AL *
4o

TI tlfs

88Q5050
m
MARVELL CONFIDENTIAL

EEPROM
EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 17

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
1.4 Data Path and Control Paths
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
The 88Q5050 device consists of two main blocks: the switch core and the CPU subsystem.
As shown in Figure 8, the so-called UniMacAV connects the switch core’s network ports directly to

9 0 tr
16 lec
the internal CPU’s RAM (a Tightly Coupled Memory (TCM)). The paths available for control of the
88Q5050 device depend on the application case (also see Section 1.3, Application Cases):

12 e E
 Switch managed by the internal CPU – Configuration is done via boot ROM, SPI firmware, and
by the internal CPU.

A# ing
 Switch managed by an external CPU – Configuration is done by the external CPU that is

ND i H
connected either over SMI (direct register access) or over Ethernet (register access through the
Remote Management Unit (RMU)).

a
ER gh
 Unmanaged switch – Configuration only (no control) is done via an EEPROM, if attached.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
(An EEPROM can also be attached in the other application cases.)

., L
, U Sh
The 88Q5050 device’s JTAG interface offers additional programming and debugging options; it has

Co
direct access to the QSPI, the internal CPU, and the switch core.
AL *
TI tlfs

yg
EN 23

lo
no
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 18 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050 Functional Description

no
Data Path and Control Paths

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
Figure 8: Data Path and Control Paths

35 on
9 0 tr
16 lec
Flash JTAG
Memory Interface

12 e E
Legend

A# ing
88Q5050 Data Path

ND i H
CPU Subsystem Control Path if Internal CPU

a
Control Path if External CPU

ER gh
Boot ROM QSPI JTAG (SMI or Ethernet)
Master

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh Configuration Path if EEPROM

Co
JTAG Access
AL *
TI tlfs

yg
Internal CPU
EN 23

lo
no
RAM
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
Switch Core

90 tr
VE jm

16 lec
EEPROM
AR b

Registers
UniMacAV
M 9stk

12 e E
SMI

A# ing
f5

RMU
z4

ND i H
zs

a
External
60

ER gh

CPU
o

ND an
ih

, U Sh
vd

Ethernet
2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 19

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Signal Description

9 0 tr
16 lec
12 e E
2.1 Pinout

A# ing
Figure 9 shows the pinout for the 88Q5050 chip, manufactured in a 14 mm × 20 mm 128-pin
LQFP package.

ND i H
For shared/multi-function pins, the functionality in their default operational mode is shown first, then

a
ER gh
the extra functionality that they have under certain conditions. They are described in detail in the
following sections.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
The colors represent the 88Q5050 chip’s different I/O domains.
, U Sh

Co
AL *

Figure 9: 88Q5050 128-Pin LQFP Package (Top View)

TI tlfs

yg
EN 23

C_LED[0] / EE_CLK / P8_VDDO_SEL[1]

lo
no
R_LEDn[1] / P567_VDDO_SEL[1]
R_LEDn[0] / P567_VDDO_SEL[0]
ID -jq

TRACEDATA[0] / P1_MASTER
TRACEDATA[1] / P2_MASTER
TRACEDATA[2] / P3_MASTER

TRACEDATA[3] / P4_MASTER

R_LEDn[2] / P8_VDDO_SEL[0]
TRACESWO / P5_MASTER

C_LED[3] / P567_MODE[2]

C_LED[2] / P567_MODE[1]

ch
NF jx

TRACECLK / CPU_EN
CO z1m

C_LED[1] / EE_DIO

Te
TDO / ADDRn[4]
XTAL_OUT

ic
WAKE_IN
XTAL_IN
LL 8vd

AVDD18

RESETn
AVSSC
TSTPT

TRSTn
VDDO

VDDO

VDDO

VDDO

VDDO

VDDO

35 on
RSET

VLPR
VLPF

VDD

VDD

VDD

TMS

TCK
INH

TDI

90 tr
VE jm

102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65

16 lec
HSDACP 103 64 VDD
AR b

HSDACN 104 63 VDDO_P8

M 9stk

AVDD18 105 62 P8_IND3

12 e E
P1_MDIP 106 61 P8_IND2
P1_MDIN 107 60 P8_IND1

A# ing
f5

AVDD33 108 59 P8_IND0

AVDD18 109 58 P8_INDV
z4

P2_MDIP 110 ND i H 57 P8_INCLK

zs

P2_MDIN 111 56 VDDO_P8

a
P3_MDIP 112 55 P8_OUTCLK / P3_ACTIVEn
60

ER gh

P3_MDIN 113 54 P8_OUTEN / P8_MODEn[2]

AVDD33 114 53 VDD
o

ND an

AVDD18 115 52 P8_OUTD0 / P5_ACTIVEn

ih

P4_MDIP 116 51 VDDO_P8

, U Sh
vd

P4_MDIN 117 50 P8_OUTD1 / P6_ACTIVEn

P5_MDIP 118 49 P8_OUTD2 / P7_ACTIVEn
88Q5050-LKJ2
2

AL *

P5_MDIN 119 48 P8_OUTD3 / P8_ACTIVEn

4o

AVDD33 120 47 MDIO_CPU

TI tlfs

AVDD18 121 46 MDC_CPU

m
MARVELL CONFIDENTIAL

P6_TXN 122 45 VDDO_P567

EN 23

P6_TXP 123 E-PAD – VSS 44 P567_IND3

AVDD18 124 43 P567_IND2
ID -jq
ou

P6_RXN 125 42 P567_IND1

P6_RXP 126 41 P567_IND0
NF jx

VDD 127 40 P567_INDV

CO z1m

TEST 128 39 P567_INCLK

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
GPIO[0] / P8_MODE[0]

GPIO[1] / P8_MODE[1]

GPIO[2] / P4_ACTIVEn

VDDO
VDD
GPIO[3] / RMU_SELn[0]
GPIO[4] / RMU_SELn[1]
INTn
TWSI_SDA
TWSI_SCK
VDD
VDDO
SPI_CS / ADDRn[2]
SPI_SIO0 / P2_WAKE_DIS
SPI_SCLK / P1_WAKE_DIS
SPI_SIO3 / P5_WAKE_DIS
VDDO
SPI_SIO2 / P4_WAKE_DIS
SPI_SIO1 / P3_WAKE_DIS
VDDO
VDDO_EFUSE
P7_S_RXN
P7_S_RXP
S_AVDD18
P7_S_TXN
P7_S_TXP
VDD
MDC_PHY / P567_MODE[0]
MDIO_PHY
P567_OUTD3 / P2_ACTIVEn
P567_OUTD2 / P1_ACTIVEn
VDDO_P567
P567_OUTD1 / P567_SELn[0]
P567_OUTD0 / ADDRn[1]
VDDO_P567
P567_OUTEN / P567_SEL[1]
P567_OUTCLK / ADDRn[0]
VDD
LL 8vd
VE jm
AR b
M 9stk
5
4f

Note: The above drawing is not drawn to scale.

sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 20 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Pin Descriptions

ch
Te
2.2 Pin Descriptions
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 2: Pin Type Definitions

9 0 tr
16 lec
P in Typ e D e f in it io n

12 e E
A Analog

A# ing
I Input

ND i H
I/O Input/Output

a
ER gh
O Output

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
OD Open Drain

., L
, U Sh
PU Internal Pull-Up

Co
AL *
TI tlfs

PD Internal Pull-Down

yg
EN 23

lo
no
ID -jq

ch
NF jx

If not specified otherwise, the information in the pin type column of the following tables
CO z1m

Te
is valid when the pins are in their default operational mode. It does not reflect the pins’
behavior in other possible modes

ic
Note
LL 8vd

35 on
90 tr
VE jm

2.2.1 Clock, Reset, Interrupt, and Reference

16 lec
AR b
M 9stk

12 e E
Table 3: Clock, Reset, Interrupt, and Reference

A# ing
f5

P in # P in N a m e P in Ty p e Description
z4

96 XTAL_IN I ND i H
25 MHz System Reference Clock Input provided from
zs

the board
a
This is the only clock required. The clock source can
60

ER gh

be provided by an external crystal or by an external

o

ND an

oscillator.
ih

, U Sh
vd

94 XTAL_OUT O System Reference Clock Output provided to the board

Can only be used to drive an external crystal, not to
2

AL *
4o

drive an external logic.

TI tlfs

Must be left open when an external oscillator is used.

m
MARVELL CONFIDENTIAL

EN 23

83 RESETn I, PU Global Power-On Reset, active low

ID -jq
ou

8 INTn I/O, PU Interrupt I/O, active low

NF jx

• Internal CPU enabled (CPU_EN = 1): Input

CO z1m

• Internal CPU disabled (CPU_EN = 0): Output

If output, this pin is open drain.
LL 8vd

102 RSET A Resistor Reference

Must be connected to an external 4.99 kΩ 1% resistor
VE jm

to ground.
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 21

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
2.2.2 100BASE-T1 Interface (Ports 1 to 5)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 4: 100BASE-T1 Interface (Ports 1 to 5)

9 0 tr
P in # P in N a m e P in Ty p e Description

16 lec
106 P1_MDIP I/O Media Dependent Interface – Positive/Negative

12 e E
107 P1_MDIN In 100BASE-T1, MDIN/P are used for transmit and
receive.

A# ing
110 P2_MDIP
Can be left open if not used.
111 P2_MDIN

ND i H
112 P3_MDIP

a
113 P3_MDIN

ER gh
116 P4_MDIP

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
117 P4_MDIN

., L
, U Sh
118 P5_MDIP

Co
119 P5_MDIN
AL *
TI tlfs

yg
2.2.3 100BASE-TX Interface (Port 6)
EN 23

lo
no
ID -jq

Table 5: 100BASE-TX Interface (Port 6)

ch
NF jx
CO z1m

P in # P in N a m e P in Ty p e Description

Te
126 P6_RXP I/O Receiver Input – Positive

ic
LL 8vd

• MDI: Connects to another device’s TXP.

35 on
• MDIX: Connects to another device’s RXP.

90 tr
VE jm

Must be connected to a 50  termination resistor to

16 lec
ground.
AR b
M 9stk

Can be left open if not used.

12 e E
125 P6_RXN I/O Receiver Input – Negative

A# ing
f5

• MDI: Connects to another device’s TXN.

z4

• MDIX: Connects to another device’s RXN.

ND i H
Must be connected to a 50  termination resistor to
zs

a
ground.
60

ER gh

Can be left open if not used.

o

ND an

123 P6_TXP I/O Transmitter Output – Positive

ih

, U Sh

• MDI: Connects to another device’s RXP.

vd

• MDIX: Connects to another device’s TXP.

2

AL *

Must be connected to a 50  termination resistor to

4o

TI tlfs

ground.
m
MARVELL CONFIDENTIAL

Can be left open if not used.

EN 23

122 P6_TXN I/O Transmitter Output – Negative

ID -jq
ou

• MDI: Connects to another device’s RXN.

NF jx

• MDIX: Connects to another device’s TXN.

CO z1m

Must be connected to a 50  termination resistor to

ground.
Can be left open if not used.
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 22 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Pin Descriptions

ch
Te
2.2.4 Gigabit SERDES Interface (Port 7)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 6: Gigabit SERDES Interface (Port 7)

9 0 tr
P in # P in N a m e P in Ty p e Description

16 lec
23 P7_S_RXP I Receiver Input – Positive

12 e E
Connects directly to another device’s TXP.
Can be left open if not used.

A# ing
22 P7_S_RXN I Receiver Input – Negative

ND i H
Connects to another device’s TXN.
Can be left open if not used.

a
ER gh
26 P7_S_TXP O Transmitter Output – Positive

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Connects directly to another device’s RXP.

., L
Can be left open if not used.
, U Sh

Co
25 P7_S_TXN O Transmitter Output – Negative
AL *

Connects directly to another device’s RXN.

TI tlfs

y
Can be left open if not used.

g
EN 23

lo
no
ID -jq

2.2.5 xMII (Port 5/6/7)

ch
NF jx

This interface can be configured as MII, RMII, or RGMII. For further details, see Section 3.2.4,
CO z1m

Te
Digital Interface Options, on page 47.

ic
LL 8vd

Table 7: xMII (Port 5/6/7) (Sheet 1 of 3)

35 on
P in # P in N a m e P in Ty p e Description

90 tr
VE jm

16 lec
39 P567_INCLK I/O Input Clock
AR b
M 9stk

Reference for P567_INDV and P567_IND[3:0]

12 e E
Expected speeds:

A# ing
125 MHz, 50 MHz, 25 MHz, or 2.5 MHz,
f5

depending on the port speed and configuration

z4

ND i H
Mode-dependent functionality:
zs

• In MII PHY mode, this pin is an output.

a
60

ER gh

• In RMII modes, this pin is not used.

• In RGMII mode, this pin is used as RXC.
o

ND an
ih

, U Sh
vd

41 P567_IND0 I Input Data 0

2

Receives the data to be sent to the switch.

AL *
4o

Must be synchronous to P567_INCLK for all modes

TI tlfs

except RMII modes, where it must be synchronous to

m
MARVELL CONFIDENTIAL

EN 23

P567_OUTCLK.
Mode-dependent functionality:
ID -jq
ou

• If the P8 interface is configured as GMII, this pin is

NF jx

used as IND[4].
CO z1m

42 P567_IND1 I Input Data 1

LL 8vd

Receives the data to be sent to the switch.

Must be synchronous to P567_INCLK for all modes
VE jm

except RMII modes, where it must be synchronous to

P567_OUTCLK.
AR b
M 9stk

Mode-dependent functionality:
• If the P8 interface is configured as GMII, this pin is
used as IND[5].
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 23

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 7: xMII (Port 5/6/7) (Sheet 2 of 3)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
43 P567_IND2 I Input Data 2

9 0 tr
16 lec
Receives the data to be sent to the switch.
Must be synchronous to P567_INCLK for all modes

12 e E
except RMII modes.
Mode-dependent functionality:

A# ing
• In RMII modes, this pin is not used.
• If the P8 interface is configured as GMII, this pin is

ND i H
used as IND[6].

a
ER gh
44 P567_IND3 I Input Data 3

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Receives the data to be sent to the switch.

., L
, U Sh Must be synchronous to P567_INCLK for all modes
except RMII modes.

Co
AL *

Mode-dependent functionality:
TI tlfs

• In RMII modes, this pin not used.

yg
• If the P8 interface is configured as GMII, this pin is
EN 23

lo
used as IND[7].

no
ID -jq

If the P8 interface is configured as GMII, this pin is

used as IND[7].

ch
NF jx
CO z1m

40 P567_INDV I Input Data Valid

Te
Used to indicate whether P567_IND[3:0] contain frame

ic
information.
LL 8vd

35 on
Must be synchronous to P567_INCLK for all modes
except RMII modes, where it must be synchronous to

90 tr
VE jm

16 lec
P567_OUTCLK.
AR b

Mode-dependent functionality:
M 9stk

12 e E
• In RGMII mode, this pin is used as RX_CTL.

A# ing
f5

37 P567_OUTCLK / I/O, PU Output Clock

z4

ADDRn[0] ND i H
Reference for P567_OUTEN and P567_OUTD[3:0]
zs

when the port is in MII modes

a
60

ER gh

Expected speeds:
125 MHz, 50 MHz, 25 MHz, or 2.5 MHz,
o

ND an
ih

depending on the port speed and configuration.

, U Sh

Mode-dependent functionality:
vd

• In MII PHY mode, this pin is an output.

2

AL *

In MII MAC mode, this pin is an input.

4o

TI tlfs

• In RMII PHY mode, this pin is an output.

m
MARVELL CONFIDENTIAL

In RMII MAC mode, this pin is an input.

EN 23

• If the P8 interface is configured as GMII and for

ID -jq
ou

1000 Mbps (both MAC/PHY mode), this pin is

used as GTX_CLK output.
NF jx
CO z1m

Multi-function pin, which is used as ADDRn[0]

LL 8vd

during hardware reset. For details, see Section 2.3,

Configuration Pins (Bootstrapping), on page 36.
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 24 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Pin Descriptions

ch
Te
Table 7: xMII (Port 5/6/7) (Sheet 3 of 3)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
36 P567_OUTEN / O, PD Output Enable

9 0 tr
16 lec
P567_SEL[1] Used to indicate whether P567_OUTD[3:0] or P567_
OUTD[1:0] contain frame information.

12 e E
Is synchronous to P567_OUTCLK in all modes.
Mode-dependent functionality:

A# ing
• In RGMII mode, this pin is used as TX_CTL.
Multi-function pin, which is used as P567_SEL[1]

ND i H
during hardware reset. For details, see Section 2.3,

a
Configuration Pins (Bootstrapping), on page 36.

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
34 P567_OUTD0 / O, PU Output Data 0

., L
, U Sh
ADDRn[1] Transmits the data to be sent from the switch.
Is synchronous to P567_OUTCLK in all modes.

Co
AL *

Mode-dependent functionality:
TI tlfs

• If the P8 interface is configured as GMII, this pin is

yg
used as OUTD[4].
EN 23

lo
Multi-function pin, which is used as ADDRn[1]

no
ID -jq

during hardware reset. For details, see Section 2.3,

Configuration Pins (Bootstrapping), on page 36.

ch
NF jx
CO z1m

33 P567_OUTD1 / O, PU Output Data 1

Te
P567_SELn[0] Transmits the data to be sent from the switch.

ic
Is synchronous to P567_OUTCLK in all modes.
LL 8vd

35 on
Mode-dependent functionality:
• If the P8 interface is configured as GMII, this pin is

90 tr
VE jm

16 lec
used as OUTD[5].
AR b

Multi-function pin, which is used as P567_SELn[0]

M 9stk

12 e E
during hardware reset. For details, see Section 2.3,
Configuration Pins (Bootstrapping), on page 36.

A# ing
f5

31 P567_OUTD2 / O, PU Output Data 2

z4

P1_ACTIVEn ND i H
Transmits the data to be sent from the switch.
zs

Is synchronous to P567_OUTCLK in all P567 modes.

a
60

ER gh

Mode-dependent functionality:
• In RMII modes, this pin is tri-stated.
o

ND an
ih

• If the P8 interface is configured as GMII, this pin is

, U Sh

used as OUTD[6].
vd

Multi-function pin, which is used as P1_ACTIVEn

2

AL *

during hardware reset. For details, see Section 2.3,

4o

TI tlfs

Configuration Pins (Bootstrapping), on page 36.

m
MARVELL CONFIDENTIAL

EN 23

30 P567_OUTD3 / O, PU Output Data 3

P2_ACTIVEn Transmits the data to be sent from the switch.
ID -jq
ou

Is synchronous to P567_OUTCLK in all P567 modes.

NF jx

Mode-dependent functionality:
CO z1m

• In RMII modes, this pin is tri-stated.

• If the P8 interface is configured as GMII, this pin is
LL 8vd

used as OUTD[7].
Multi-function pin, which is used as P2_ACTIVEn
during hardware reset. For details, see Section 2.3,
VE jm

Configuration Pins (Bootstrapping), on page 36.

AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 25

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
2.2.6 xMII/GMII (Port 8)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
This interface can be configured as MII, RMII, RGMII, or GMII. For further details, see Section 3.2.4,
Digital Interface Options, on page 47.

9 0 tr
16 lec
Table 8: xMII/GMII (Port 8) (Sheet 1 of 3)

12 e E
P in # P in N a m e P in Ty p e Description

A# ing
57 P8_INCLK I/O Input Clock
Reference for P8_INDV and P8_IND[3:0].

ND i H
Expected speeds:

a
125 MHz, 50 MHz, 25 MHz, or 2.5 MHz,

ER gh
depending on the port speed and configuration
Mode-dependent functionality:

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
• In MII PHY mode, this pin is an output.

., L
, U Sh
• In RMII modes, this pin is not used.

Co
• In RGMII mode, this pin is used as RXC.
AL *

• In GMII modes, this pin is used as RX_CLK input.

TI tlfs

yg
59 P8_IND0 I Input Data
EN 23

lo
Receives the data to be sent to the switch.

no
ID -jq

Must be synchronous to P8_INCLK for all modes

except for RMII modes, where it must be synchronous

ch
NF jx

to P8_OUTCLK.
CO z1m

Te
60 P8_IND1 I Input Data

ic
Receives the data to be sent to the switch.
LL 8vd

35 on
Must be synchronous to P8_INCLK for all modes
except for RMII modes, where it must be synchronous

90 tr
VE jm

to P8_OUTCLK.

16 lec
AR b
M 9stk

61 P8_IND2 I Input Data

12 e E
Receives the data to be sent to the switch.
Must be synchronous to P8_INCLK for all modes

A# ing
f5

except for RMII modes.

z4

ND i H
Mode-dependent functionality:
zs

• In RMII modes, this pin is not used.

a
60

ER gh

62 P8_IND3 I Input Data

o

Receives the data to be sent to the switch.

ND an
ih

Must be synchronous to P8_INCLK for all modes

, U Sh
vd

except for RMII modes.

Mode-dependent functionality:
2

AL *
4o

• In RMII modes, this pin is not used.

TI tlfs
m
MARVELL CONFIDENTIAL

58 P8_INDV I Input Data Valid

EN 23

Used to indicate whether P8_IND[3:0] contain frame

ID -jq

information.
ou

Must be synchronous to P8_INCLK for all modes

NF jx

except RMII modes, where it must be synchronous to

CO z1m

P8_OUTCLK.
Mode-dependent functionality:
LL 8vd

• In RGMII mode, this pin is used as RX_CTL.

• In GMII modes, this pin is used as RX_DV.
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 26 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Pin Descriptions

ch
Te
Table 8: xMII/GMII (Port 8) (Sheet 2 of 3)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
55 P8_OUTCLK / I/O, PU Output Clock

9 0 tr
16 lec
P3_ACTIVEn Reference for P8_OUTEN and P8_OUTD[3:0] when
the port is in MII modes.

12 e E
Expected speeds:
125 MHz, 50 MHz, 25 MHz, or 2.5 MHz,

A# ing
depending on the port speed and configuration
Mode-dependent functionality:

ND i H
• In MII PHY mode, this pin is an output.

a
In MII MAC mode, this pin is an input.

ER gh
• In RMII PHY mode, this pin is an output.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
In RMII MAC mode, this pin is an input.

., L
, U Sh • In GMII 10/100 Mbps MAC mode, this pin is used
as TX_CLK input.

Co
In GMII PHY mode, this pin is not used.
AL *

Multi-function pin, which is used as P3_ACTIVEn

TI tlfs

y
during hardware reset. For details, see Section 2.3,

g
EN 23

Configuration Pins (Bootstrapping), on page 36.

lo
no
ID -jq

54 P8_OUTEN / O, PD Output Enable

P8_MODEn[2] Used to indicate whether P8_OUTD[3:0] or P8_

ch
NF jx

OUTD[1:0] contain frame information.

CO z1m

Te
Is synchronous to P8_OUTCLK in all modes.
Mode-dependent functionality:

ic
LL 8vd

• In RGMII mode, this pin is used as TX_CTL.

35 on
• In GMII modes, this pin is used as TX_EN.

90 tr
VE jm

Multi-function pin, which is used as P8_MODEn[2]

16 lec
during hardware reset. For details, see Section 2.3,
AR b
M 9stk

Configuration Pins (Bootstrapping), on page 36.

12 e E
52 P8_OUTD0 / O, PU Output Data 0

A# ing
f5

P5_ACTIVEn Transmits the data to be sent from the switch.

z4

Is synchronous to P8_OUTCLK in all modes.

ND i H
Multi-function pin, which is used as P5_ACTIVEn
zs

a
during hardware reset. For details, see Section 2.3,
60

ER gh

Configuration Pins (Bootstrapping), on page 36.

o

ND an
ih

50 P8_OUTD1 / O, PU Output Data 1

, U Sh

P6_ACTIVEn Transmits the data to be sent from the switch.

vd

Is synchronous to P8_OUTCLK in all modes.

2

AL *

Multi-function pin, which is used as P6_ACTIVEn

4o

TI tlfs

during hardware reset. For details, see Section 2.3,

m
MARVELL CONFIDENTIAL

Configuration Pins (Bootstrapping), on page 36.

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 27

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 8: xMII/GMII (Port 8) (Sheet 3 of 3)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
49 P8_OUTD2 / O, PU Output Data 2

9 0 tr
16 lec
P7_ACTIVEn Transmits the data to be sent from the switch.
Is synchronous to P8_OUTCLK in all modes.

12 e E
Mode-dependent functionality:
• In RMII modes, this pin is tri-stated.

A# ing
Multi-function pin, which is used as P7_ACTIVEn
during hardware reset. For details, see Section 2.3,

ND i H
Configuration Pins (Bootstrapping), on page 36.

a
48 P8_OUTD3 / O, PU Output Data 3

ER gh
P8_ACTIVEn Transmits the data to be sent from the switch.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Is synchronous to P8_OUTCLK in all modes.

., L
, U Sh Mode-dependent functionality:
• In RMII modes, this pin is tri-stated.

Co
AL *

Multi-function pin, which is used as P8_ACTIVEn

TI tlfs

during hardware reset. For details, see Section 2.3,

yg
Configuration Pins (Bootstrapping), on page 36.
EN 23

lo
no
ID -jq

2.2.7 SMI

ch
NF jx
CO z1m

Te
Table 9: SMI (Sheet 1 of 2)

ic
LL 8vd

P in # P in N a m e P in Ty p e Description

35 on
46 MDC_CPU I, PU Management Data Clock, Slave

90 tr
VE jm

Reference clock input for the SMI, which connects to

16 lec
AR b

an external SMI master, typically a CPU

M 9stk

12 e E
A continuous clock stream is not expected. The
maximum frequency supported is 20 MHz.

A# ing
Powered by VDDO_P8.
f5

Internally pulled high by a resistor, that is, it can be left

z4

ND i H
open when unused.
zs

a
28 MDC_PHY / O, PU Management Data Clock, Master
60

ER gh

P567_MODE[0] Reference clock output for the SMI, which connects to

o

ND an

an external SMI slave device, typically external PHYs

ih

Powered by VDDO_P567.
, U Sh
vd

Multi-function pin, which is used as P567_MODE[0]

2

during hardware reset. For details, see Section 2.3,

AL *
4o

TI tlfs

Configuration Pins (Bootstrapping), on page 36.

m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 28 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Pin Descriptions

ch
Te
Table 9: SMI (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
47 MDIO_CPU I/O, PU Management Data I/O, Slave

9 0 tr
16 lec
Used to transfer management data in and out of the
device, synchronously to MDC_CPU.

12 e E
The 88Q5050 device uses one or all of the 32 possible
SMI port addresses (two modes are supported). The

A# ing
configuration pins ADDRn[4] and ADDRn[2:0] together
with ADDR[3] (which is fixed) specify the initial

ND i H
address(es) to be used. For details, see Section 2.3,

a
Configuration Pins (Bootstrapping), on page 36.

ER gh
Requires an external 1.5 kpull-up resistor.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Internally pulled high by a resistor, that is, it can be left

., L
, U Sh open when unused.
Powered by VDDO_P8.

Co
AL *

29 MDIO_PHY I/O, PU Management Data I/O, Master

TI tlfs

Used to transfer management data in and out of the

yg
device, synchronously to MDC_PHY.
EN 23

lo
Requires an external 1.5 kpull-up resistor.

no
ID -jq

Internally pulled high by a resistor, that is, it can be left

open when unused.

ch
NF jx

Powered by VDDO_P567.
CO z1m

Te
ic
LL 8vd

2.2.8 QSPI

35 on
90 tr
VE jm

Table 10: QSPI (Sheet 1 of 2)

16 lec
AR b

P in # P in N a m e P in Ty p e Description
M 9stk

12 e E
13 SPI_CSn / O, PU QSPI Chip Select, low active

A# ing
ADDRn[2] Used to access an SPI memory device containing the
f5

firmware image for the internal CPU.

z4

ND i H
Multi-function pin, which is used as ADDRn[2]
zs

during hardware reset. For details, see Section 2.3,

a
60

ER gh

Configuration Pins (Bootstrapping), on page 36.

o

ND an

15 SPI_SCLK / O, PU QSPI Clock

ih

P1_WAKE_DIS Reference clock output for the QSPI

, U Sh
vd

Maximum frequency provided: 85 MHz

2

Multi-function pin, which is used as P1_WAKE_DIS

AL *
4o

TI tlfs

during hardware reset. For details, see Section 2.3,

m

Configuration Pins (Bootstrapping), on page 36.

MARVELL CONFIDENTIAL

EN 23

14 SPI_SIO0 / I/O, PU • Single I/O mode: SPI Data Output

ID -jq
ou

P2_WAKE_DIS • Dual or quad I/O mode: SPI Data I/O 0

Transfers data (O, I/O) and address (I/O).
NF jx

Multi-function pin, which is used as P2_WAKE_DIS

CO z1m

during hardware reset. For details, see Section 2.3,

Configuration Pins (Bootstrapping), on page 36.
LL 8vd

19 SPI_SIO1 / I/O, PU • Single I/O mode: SPI Data Input

P3_WAKE_DIS • Dual or quad I/O mode: SPI Data I/O 1
VE jm

Transfers data (O, I/O) and address (I/O).

AR b

Multi-function pin, which is used as P3_WAKE_DIS

M 9stk

during hardware reset. For details, see Section 2.3,

Configuration Pins (Bootstrapping), on page 36.
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 29

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 10: QSPI (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
18 SPI_SIO2 / I/O, PU • Single I/O mode: SPI Write Protect

9 0 tr
• Dual I/O mode: Not used

16 lec
P4_WAKE_DIS
• Quad I/O mode: SPI Data I/O 2

12 e E
Transfers data (O, I/O) and address (I/O).
Multi-function pin, which is used as P4_WAKE_DIS

A# ing
during hardware reset. For details, see Section 2.3,
Configuration Pins (Bootstrapping), on page 36.

ND i H
16 SPI_SIO3 / I/O, PU • Single I/O mode: SPI Hold

a
P5_WAKE_DIS • Dual I/O mode: Not used

ER gh
• Quad I/O mode: SPI Data Input/Output 3

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Transfers data (O, I/O) and address (I/O).

., L
Multi-function pin, which is used as P5_WAKE_DIS
, U Sh
during hardware reset. For details, see Section 2.3,

Co
AL *

Configuration Pins (Bootstrapping), on page 36.

TI tlfs

yg
2.2.9 TWSI
EN 23

lo
no
ID -jq

Table 11: TWSI

ch
NF jx
CO z1m

P in # P in N a m e P in Ty p e Description

Te
10 TWSI_SCK O, OD TWSI Clock

ic
LL 8vd

5V tolerant pin.

35 on
9 TWSI_SDA I/O, OD TWSI Data

90 tr
VE jm

16 lec
5V tolerant pin.
AR b
M 9stk

12 e E
2.2.10 GPIO Interface

A# ing
f5
z4

Table 12: GPIO Interface (Sheet 1 of 2) ND i H

zs

P in # P in N a m e P in Ty p e Description
a
60

ER gh

1 GPIO[0] / I/O, PU General Purpose I/O 0

o

ND an

P8_MODE[0] Can be configured to be input or output signal.

ih

Multi-function pin, which is used as P8_MODE[0]

, U Sh
vd

during hardware reset. For details, see Section 2.3,

2

Configuration Pins (Bootstrapping), on page 36.

AL *
4o

TI tlfs

2 GPIO[1] / I/O, PU General Purpose I/O 1

m
MARVELL CONFIDENTIAL

P8_MODE[1] Can be configured to be input or output signal.

EN 23

Multi-function pin, which is used as P8_MODE[1]

ID -jq
ou

during hardware reset. For details, see Section 2.3,

Configuration Pins (Bootstrapping), on page 36.
NF jx
CO z1m

3 GPIO[2] / I/O, PU General Purpose I/O 2

P4_ACTIVEn Can be configured to be input or output signal.
LL 8vd

Multi-function pin, which is used as P4_ACTIVEn

during hardware reset. For details, see Section 2.3,
Configuration Pins (Bootstrapping), on page 36.
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 30 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Pin Descriptions

ch
Te
Table 12: GPIO Interface (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
6 GPIO[3] / I/O, PU General Purpose I/O 3

9 0 tr
16 lec
RMU_SELn[0] Can be configured to be input or output signal.
Multi-function pin, which is used as RMU_SELn[0]

12 e E
during hardware reset. For details, see Section 2.3,
Configuration Pins (Bootstrapping), on page 36.

A# ing
7 GPIO[4] / I/O, PU General Purpose I/O 4

ND i H
RMU_SELn[1] Can be configured to be input or output signal.
Multi-function pin, which is used as RMU_SELn[1]

a
during hardware reset. For details, see Section 2.3,

ER gh
Configuration Pins (Bootstrapping), on page 36.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
2.2.11 LED and EEPROM Interface

Co
AL *
TI tlfs

Table 13: LED and EEPROM Interface (Sheet 1 of 2)

yg
EN 23

lo
P in # P in N a m e P in Ty p e Description

no
ID -jq

76 C_LED[0] / I/O, PU LED Column 0

ch
EE_CLK / Used to connect to the anode of LED column 0 for
NF jx

P8_VDDO_SEL[1] each row, if used in the multiplexed LED mode.

CO z1m

Te
EEPROM Clock

ic
If an external EEPROM is connected, this pin provides
LL 8vd

35 on
the clock for the EEPROM at system start. Afterwards,
the functionality changes to C_LED[0].

90 tr
VE jm

Multi-function pin, which is used as P8_VDDO_SEL[1]

16 lec
AR b

during hardware reset. For details, see Section 2.3,

M 9stk

12 e E
Configuration Pins (Bootstrapping), on page 36.
79 C_LED[1] / I/O, PU LED Column 1

A# ing
f5

EE_DIO Used to connect to the anode of LED column 1 for

z4

each row, if used in the multiplexed LED mode.

ND i H
zs

EEPROM Data I/O

a
If an external EEPROM is connected, this pin is used
60

ER gh

to load data from the EEPROM at system start.

o

ND an

Afterwards, the functionality changes to C_LED[1].

ih

, U Sh
vd

80 C_LED[2] / I/O, PU LED Column 2

P567_MODE[1] Used to connect to the anode of LED column 2 for
2

AL *
4o

each row, if used in the multiplexed LED mode.

TI tlfs

Multi-function pin, which is used as P567_MODE[1]

m
MARVELL CONFIDENTIAL

during hardware reset. For details, see Section 2.3,

EN 23

Configuration Pins (Bootstrapping), on page 36.

ID -jq
ou

82 C_LED[3] / I/O, PU LED Column 3

NF jx

P567_MODE[2] Used to connect to the anode of LED column 3 for

CO z1m

each row, if used in the multiplexed LED mode.

Multi-function pin, which is used as P567_MODE[2]
LL 8vd

during hardware reset. For details, see Section 2.3,

Configuration Pins (Bootstrapping), on page 36.
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 31

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 13: LED and EEPROM Interface (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
73 R_LEDn[0] / I/O, PU LED Row 0, active low

9 0 tr
16 lec
P567_VDDO_ The R_LEDn pins directly drive the ports’ LEDs,
SEL[0] supporting a range from 1 to 12 LEDs in a multiplexed

12 e E
fashion. In this mode, the cathode of each LED
connects to these pins through a series current limiting

A# ing
resistor. The anode of each LED connects to one of
the C_LED pins.

ND i H
Multi-function pin, which is used as P567_VDDO_

a
SEL[0] during hardware reset. For details, see

ER gh
Section 2.3, Configuration Pins (Bootstrapping),

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
on page 36.

., L
74
, U Sh
R_LEDn[1] / I/O, PU LED Row 1, active low
P567_VDDO_ For details, see the description of the R_LEDn[0]n pin.

Co
AL *

SEL[1] Multi-function pin, which is used as P567_VDDO_

TI tlfs

SEL[1] during hardware reset. For details, see

yg
Section 2.3, Configuration Pins (Bootstrapping),
EN 23

lo
on page 36.

no
ID -jq

75 R_LEDn[2] / I/O, PU LED Row 2, active low

ch
NF jx

P8_VDDO_SEL[0] For details, see the description of the R_LEDn[0]n pin.

CO z1m

Multi-function pin, which is used as P8_VDDO_SEL[0]

Te
during hardware reset. For details, see Section 2.3,

ic
Configuration Pins (Bootstrapping), on page 36.
LL 8vd

35 on
90 tr
VE jm

The physical LEDs on the 88Q5050 device’s pins are organized as 3 rows with 2 columns.

16 lec
AR b

Table 14 shows the port-to-PHY mapping.

M 9stk

12 e E
Table 14: LED Port-to-PHY Mapping

A# ing
f5

C_LED[0] C_LED[1] C_LED[2] C _L E D [ 3 ]

z4

R_LEDn[0] Port 1 LED 0 Port 1 LED 1 ND i H Port 2 LED 0 Port 2 LED1

zs

a
R_LEDn[1] Port 3 LED 0 Port 3 LED 1 Port 4 LED 0 Port 4 LED1
60

ER gh

R_LEDn[2] Port 5 LED 0 Port 5 LED 1 Port 6 LED 0 Port 6 LED1

o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 32 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Pin Descriptions

ch
Te
2.2.12 JTAG Interface
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
The JTAG interface is shared between the system Debug Access Port (DAP) and the Test Access
Port (TAP).

9 0 tr
16 lec
Table 15: JTAG Interface

12 e E
P in # P in N a m e P in Ty p e Description

A# ing
128 TEST I, PD Test Mode Enable
• 0: JTAG interface connected to system DAP

ND i H
controller

a
• 1: JTAG interface connected to TAP controller

ER gh
66 TCK I, PD JTAG Test Clock

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
68 TDI I, PU JTAG Test Data In

., L
, U Sh
70 TDO / O, PU JTAG Test Data Out

Co
AL *

ADDRn[4] Multi-function pin, which is used as ADDRn[4]

TI tlfs

during hardware reset. For details, see Section 2.3,

yg
Configuration Pins (Bootstrapping), on page 36.
EN 23

lo
69 TMS I, PU JTAG Test Mode Select

no
ID -jq

65 TRSTn I, PD JTAG Test Reset, active low

ch
NF jx
CO z1m

Te
2.2.13 Test

ic
LL 8vd

35 on
Table 16: Test

90 tr
VE jm

16 lec
P in # P in N a m e P in Ty p e Description
AR b
M 9stk

103 HSDACP A, O AC Test Point – Positive/Negative

12 e E
104 HSDACN Brings out TX_TCLK for IEEE testing and AC test

A# ing
points for debugging.
f5

Must be connected to a 50Ω termination resistor to

z4

ground. ND i H
zs

Must be left open if not used.

a
60

ER gh

101 TSTPT A, O Test Point

o

Must be left open if not used.

ND an
ih

, U Sh
vd

2.2.14 Internal CPU Trace Interface

2

AL *
4o

TI tlfs

Table 17: Internal CPU Trace Interface (Sheet 1 of 2)

m
MARVELL CONFIDENTIAL

EN 23

P in # P in N a m e P in Ty p e Description
ID -jq
ou

91 TRACECLK / O, PU Trace Clock

NF jx

CPU_EN Multi-function pin, which is used as CPU_EN

CO z1m

during hardware reset. For details, see Section 2.3,

Configuration Pins (Bootstrapping), on page 36.
LL 8vd

90 TRACEDATA[0] / O, PU Trace Data 0

P1_MASTER Multi-function pin, which is used as P1_MASTER
VE jm

during hardware reset. For details, see Section 2.3,

AR b

Configuration Pins (Bootstrapping), on page 36.

M 9stk

89 TRACEDATA[1] / O, PU Trace Data 1

P2_MASTER Multi-function pin, which is used as P2_MASTER
5

during hardware reset. For details, see Section 2.3,

4f

Configuration Pins (Bootstrapping), on page 36.

sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 33

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 17: Internal CPU Trace Interface (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e P in Ty p e Description

35 on
88 TRACEDATA[2] / O, PU Trace Data 2

9 0 tr
16 lec
P3_MASTER Multi-function pin, which is used as P3_MASTER
during hardware reset. For details, see Section 2.3,

12 e E
Configuration Pins (Bootstrapping), on page 36.
86 TRACEDATA[3] / O, PU Trace Data 3

A# ing
P4_MASTER Multi-function pin, which is used as P4_MASTER

ND i H
during hardware reset. For details, see Section 2.3,
Configuration Pins (Bootstrapping), on page 36.

a
ER gh
85 TRACESWO / O, PU Trace Serial Wire Output
P5_MASTER Multi-function pin, which is used as P5_MASTER

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
during hardware reset. For details, see Section 2.3,

., L
, U Sh
Configuration Pins (Bootstrapping), on page 36.

Co
AL *
TI tlfs

2.2.15 Low-Power Signal Detect

yg
EN 23

lo
Table 18: Low-Power Signal Detect

no
ID -jq

ch
P in # P in N a m e P in Ty p e Description
NF jx
CO z1m

Te
97 WAKE_IN A, I Wake Signal
Used to trigger INH.

ic
LL 8vd

Can be connected to ground or left open if LPSD is not

35 on
used.

90 tr
VE jm

98 INH A, O Used to enable the external regulator, which wakes up

16 lec
the 88Q5050 device.
AR b
M 9stk

12 e E
Triggered by WAKE_IN or by the 100BASE-T1 PHY’s
signal detect.

A# ing
Must be left open if LPSD is not used.
f5

NOTE: If INH needs more than 50 A current, external

z4

ND i H
buffer components will be required.
zs

a
100 VLPF A, I Used as feedback pin for the external regulator.
60

ER gh

Must be left open if LPSD is not used.

o

ND an
ih

99 VLPR A, I Regulated voltage for detection circuitry derived from

, U Sh
vd

VBAT
Must be left open if LPSD is not used.
2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 34 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Pin Descriptions

ch
Te
2.2.16 Power and Ground
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 19: Power and Ground (Sheet 1 of 2)

9 0 tr
P in # P in N a m e Description

16 lec
93 AVDD18 Analog 1.8V Supply

12 e E
Power to the analog core used to power the on-chip
XTAL (pins 94, 96).

A# ing
105, 109, 115, 121 AVDD18 Analog 1.8V Supply

ND i H
Power to the analog core used to power the interfaces
of ports 1 to 5 (pins 106, 107, 110–113, 116–119), the

a
ER gh
test pins (pins 101, 103, 104), and the RSET pin
(pin 102).

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
124 AVDD18 Analog 1.8V Supply
, U Sh
Power to the analog core used to power the interface

Co
of port 6 (pins 122, 123, 125, 126).
AL *
TI tlfs

y
108, 114, 120 AVDD33 Analog 3.3V Supply

g
Power to the analog core used to power the interfaces
EN 23

lo
of ports 1 to 5 (pins 106, 107, 110–113, 116–119), the

no
ID -jq

test pins (pins 101, 103, 104), the RSET pin (pin 102),

ch
NF jx

and the LPSD pins (pins 96–100).

CO z1m

Te
95 AVSSC Ground
Used for the on-chip XTAL.

ic
LL 8vd

35 on
24 S_AVDD18 Analog 1.8V Supply
Power to the analog core used to power the interface

90 tr
VE jm

of port 7 (pins 22, 23, 25, 26).

16 lec
AR b

Can be left unconnected if the SERDES is not used.

M 9stk

12 e E
5, 11, 27, 38, 53, 64, VDD 1.0V Core Supply
71, 78, 84, 127

A# ing
f5

4, 12, 17, 20 VDDO 3.3V Supply

z4

ND i H
Power to the GPIO pins (pins 1–3, 6, 7), to the TWSI
zs

(pins 9, 10), to the QSPI (pins 13–16, 18, 19), and to

a
60

ER gh

the TEST pin (pin 128).

o

ND an

67, 72, 77, 81, 87, 92 VDDO 3.3V Supply

ih

Power to the JTAG interface (pins 65, 66, 68–70), to

, U Sh
vd

the LED interface (pins 79–82), to the RESETn pin

2

(pin 83), to the internal CPU trace interface (pins 85,

AL *
4o

TI tlfs

86, 88–91).
m
MARVELL CONFIDENTIAL

21 VDDO_EFUSE Supply for the internal eFUSE logic

EN 23

• 1.8V or 2.5V required for read-only operation

ID -jq
ou

• 2.5V required for programming (for example, to

NF jx

program a security key)

CO z1m

32, 35, 45 VDDO_P567 1.8V/2.5V/3.3V Supply

Power to the MDC_PHY and MDIO_PHY pins (pins
LL 8vd

28, 29) and to the interfaces of port 5/6/7 (pins 30, 31,
33, 34, 36, 37, 39–44).
VE jm

Configured by P567_VDDO_SEL[1:0]. For details, see

Section 2.3, Configuration Pins (Bootstrapping),
AR b

on page 36.
M 9stk

NOTE: If configured to 2.5V, the supplied pins are

NOT 3.3V tolerant.
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 35

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 19: Power and Ground (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
P in # P in N a m e Description

35 on
51, 56, 63 VDDO_P8 1.8V/2.5V/3.3V Supply

9 0 tr
16 lec
Power to the MDC_CPU and MDIO_CPU pins (pins
46, 47) and to the interface of port 8 (pins 48–50, 52,

12 e E
54, 55, 57–62).
Configured by P8_VDDO_SEL[1:0]. For details, see

A# ing
Section 2.3, Configuration Pins (Bootstrapping),
on page 36.

ND i H
NOTE: If configured to 2.5V, the supplied pins are

a
NOT 3.3V tolerant.

ER gh
E-PAD N/A Ground

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
The 88Q5050 device is packaged in a 128-pin LQFP

., L
, U Sh package with an exposed die pad on the bottom of the
package. This E-PAD must be soldered to VSS as it is

Co
AL *

the device’s only VSS connection.

TI tlfs

yg
EN 23

lo
2.3 Configuration Pins (Bootstrapping)

no
ID -jq

ch
NF jx

2.3.1 Bootstrap Options

CO z1m

Te
The configuration pins are used to configure the 88Q5050 device during hardware reset. When

ic
RESETn is asserted, these configuration pins become input pins, and their configuration information
LL 8vd

35 on
is latched at the rising edge of RESETn.

90 tr
VE jm

Table 20 lists the 88Q5050 device’s configuration pins and describes their functionality. In the

16 lec
AR b

descriptions, a High signal is represented by a 1, and a Low signal is represented by a 0. There are
M 9stk

12 e E
two types of configuration pins:
Pins that specify a setting per portAn example of pins that specify a setting per port are the Px_

A# ing
f5

ACTIVEn pins. P1_ACTIVEn specifies the setting for port 1, P2_ACTIVEn specifies the setting
z4

for port 2, and so on. ND i H

zs

 Pins that are combined to specify a certain configuration

a
60

ER gh

An example of pins that specify a certain configuration are the P567_VDDO_SEL[1:0] pins,
o

which are configured to the power supply voltage that is connected to the P567 interface. The
ND an
ih

pins’ signals are combined as follows (with the higher-numbered pin representing the higher
, U Sh
vd

value):
2

AL *

• 0b00 – P567_VDDO_SEL[1] low (0) and P567_VDDO_SEL[0] low (0) – selects 3.3V
4o

TI tlfs

• 0b01 – P567_VDDO_SEL[1] low (0) and P567_VDDO_SEL[0] high (1) – selects 2.5V
m
MARVELL CONFIDENTIAL

EN 23

• 0b10 – P567_VDDO_SEL[1] high (1) and P567_VDDO_SEL[0] low (0) – selects 1.8V
ID -jq

• 0b11 – P567_VDDO_SEL[1] high (1) and P567_VDDO_SEL[0] high (1) – selects 3.3V
ou

(default)
NF jx
CO z1m

The default setting (here: 0b11) is the setting that the configuration pins have if they are left
unconnected. To achieve the default settings, all configuration pins have an internal pull-down
LL 8vd

or pull-up resistor. For the P567_VDDO_SEL[1:0] pins, the default setting is achieved by
internal pull-up resistors.
VE jm
AR b
M 9stk

The external signals for some of the listed pins are inverted. In these cases, the actual
5

external signals to be applied are shown in brackets.

Caution
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 36 Document Classification: Proprietary Information March 07, 2018

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Configuration Pins (Bootstrapping)

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Table 20: Bootstrap Options (Sheet 1 of 3)

ic
35 on
Pi n # D e f au l t C o n fi gu r a t io n F un c ti o na l it y
Pin Name P in N a m e

9 0 tr
16 lec
37 P567_OUTCLK ADDRn[0] These pins specify the slave address for the MDC/MDIO_
34 P567_OUTD0 ADDRn[1] CPU interface.

12 e E
13 SPI_CSn ADDRn[2] • 0b00000 [0b1-111]: Slave address = 0x0 (default)
70 TDO ADDRn[4] • 0b00001 [0b1-110]: Slave address = 0x1

A# ing
• …

ND i H
• 0b10111 [0b0-000]: Slave address = 0x17
NOTE: These pins are internally pulled high.

a
NOTE: ADDR[3] is tied to 0, that is, slave addresses

ER gh
0x8…0xF and 0x18…0x1F are not supported.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
91 TRACECLK CPU_EN This pin specifies whether the internal CPU is enabled or

., L
, U Sh
disabled.

Co
• 0b0: CPU disabled
AL *

• 0b1: CPU enabled (default)

TI tlfs

y
NOTE: This pin is internally pulled high.

g
EN 23

lo
31 P567_OUTD2 P1_ACTIVEn These pins specify the state that the appropriate port will have

no
ID -jq

30 P567_OUTD3 P2_ACTIVEn after reset.

55 P8_OUTCLK P3_ACTIVEn • 0b0 [0b1]: Port disabled or blocking, depending on the

ch
NF jx

50 P8_OUTD1 P6_ACTIVEn setting of the RMU_SELn[1:0] pins (default)

CO z1m

Te
49 P8_OUTD2 P7_ACTIVEn • 0b1 [0b0]: Port enabled/forwarding
48 P8_OUTD3 P8_ACTIVEn NOTE: These pins are internally pulled high.

ic
LL 8vd

35 on
90 TRACEDATA[0] P1_MASTER These pins specify the PHY mode for the appropriate
89 TRACEDATA[1] P2_MASTER 100BASE-T1 port.

90 tr
VE jm

88 TRACEDATA[2] P3_MASTER • 0b0: Slave

16 lec
AR b

• 0b1: Master (default)

M 9stk

12 e E
NOTE: These pins are internally pulled high.
15 SPI_SCLK P1_WAKE_DIS These pins specify whether the appropriate 100BASE-T1 PHY

A# ing
f5

14 SPI_SIO0 P2_WAKE_DIS is enabled to wake up the device from a low-power state.

z4

19 SPI_SIO1 P3_WAKE_DIS ND i H
• 0b0: PHY able to wake up the device
zs

• 0b1: PHY not able to wake up the device (default)

a
NOTE: These pins are internally pulled high.
60

ER gh

These pins specify the P567 mode1.

o

28 MDC_PHY P567_MODE[0]
ND an
ih

80 C_LED[2] P567_MODE[1] • 0b000: MII PHY mode (full duplex only)

, U Sh
vd

82 C_LED[3] P567_MODE[2] P567_INCLK/OUTCLK will be inputs (but can be

outputs).
2

AL *
4o

• 0b001: MII PHY mode

TI tlfs

P567_INCLK/OUTCLK will be outputs.

m
MARVELL CONFIDENTIAL

EN 23

• 0b010: MII MAC mode

P567_INCLK/OUTCLK will be inputs.
ID -jq
ou

• 0b011: Reserved
NF jx

• 0b100: RMII PHY mode

CO z1m

P567_OUTCLK will be output.

• 0b101: RMII MAC mode
P567_OUTCLK will be input.
LL 8vd

• 0b110: xMII disabled, that is, tri-state

• 0b111: RGMII mode (default)
VE jm

NOTE: These pins are internally pulled high.

AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 37

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 20: Bootstrap Options (Sheet 2 of 3)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
Pi n # D e f au l t C o n fi gu r a t io n F un c ti o na l it y

35 on
Pin Name P in N a m e

9 0 tr
These pins select which of the P567 is connected to xMII1.

16 lec
33 P567_OUTD1 P567_SELn[0]
36 P567_OUTEN P567_SEL[1] • 0b00 [0b01]: Port 5 connected to 100BASE-T1 PHY,

12 e E
port 6 connected to 100BASE-TX PHY,
port 7 connected to SERDES (SGMII)

A# ing
(default)
• 0b01 [0b00]: Port 5 connected to xMII (instead of being

ND i H
connected to the 100BASE-T1 PHY of

a
port 5, which is powered down)

ER gh
• 0b10 [0b11]: Port 6 connected to xMII (instead of being

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
connected to the 100BASE-TX PHY of

., L
, U Sh port 6, which is powered down)
• 0b11 [0b10]: Port 7 connected to xMII (instead of being

Co
connected to the SERDES of port 7, which is
AL *

powered down)
TI tlfs

y
NOTE: P567_SELn[0] is internally pulled high, whereas

g
EN 23

P567_SEL[1] is internally pulled low.

lo
no
ID -jq

73 R_LEDn[0] P567_VDDO_SEL[0] These pins must be configured to the power supply voltage
74 R_LEDn[1] P567_VDDO_SEL[1] that is connected to the P567 interface (including SMI master).

ch
NF jx

• 0b00: 3.3V
CO z1m

Te
• 0b01: 2.5V
• 0b10: 1.8V

ic
LL 8vd

• 0b11: 3.3V (default)

35 on
NOTE: These pins are internally pulled high.

90 tr
VE jm

NOTE: In P8 GMII mode, the voltages configured by P567_

16 lec
VDDO_SEL and by P8_VDDO_SEL must be the
AR b
M 9stk

same.

12 e E
1 GPIO[0] P8_MODE[0] These pins specify the P8 mode1.

A# ing
f5

2 GPIO[1] P8_MODE[1] • 0b000 [0b100]: MII PHY mode (full duplex only)
z4

54 P8_OUTEN P8_MODEn[2] P8_INCLK/OUTCLK will be inputs (but

ND i H
can be outputs).
zs

a
• 0b001 [0b101]: MII PHY mode
60

ER gh

P8_INCLK/OUTCLK will be outputs.

o

ND an

• 0b010 [0b110]: MII MAC mode

ih

P8_INCLK/OUTCLK will be inputs.

, U Sh
vd

• 0b011 [0b111]: GMII mode

2

• 0b100 [0b000]: RMII PHY mode

AL *
4o

TI tlfs

P8_OUTCLK will be output.

m

• 0b101 [0b001]: RMII MAC mode

MARVELL CONFIDENTIAL

EN 23

P8_OUTCLK will be input.

• 0b110 [0b010]: xMII disabled, that is, tri-state
ID -jq
ou

• 0b111 [0b011]: RGMII mode (default)

NF jx

NOTE: P8_MODE[0] and P8_MODE[1] are internally pulled

CO z1m

high, whereas P8_MODEn[2] is internally pulled low.

LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 38 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Configuration Pins (Bootstrapping)

ch
Te
Table 20: Bootstrap Options (Sheet 3 of 3)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
Pi n # D e f au l t C o n fi gu r a t io n F un c ti o na l it y

35 on
Pin Name P in N a m e

9 0 tr
16 lec
75 R_LEDn[2] P8_VDDO_SEL[0] These pins must be configured to the power supply voltage
76 C_LED[0] / EE_CLK P8_VDDO_SEL[1] that is connected to the P8 interface (including SMI slave).

12 e E
• 0b00: 3.3V
• 0b01: 2.5V

A# ing
• 0b10: 1.8V
• 0b11: 3.3V (default)

ND i H
NOTE: These pins are internally pulled high.

a
NOTE: In P8 GMII mode, the voltages selected by P8_

ER gh
VDDO_SEL and by P567_VDDO_SEL must be the

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
same.

., L
6 GPIO[3]
, U Sh RMU_SELn[0] These pins select the RMU port.
7 GPIO[4] RMU_SELn[1] If RMU is enabled for a port, this port allows RMU

Co
AL *

management frames (EtherType DSA). Whether the port will

TI tlfs

forward other frames too depends on its Px_ACTIVEn setting.

yg
• 0b00 [0b11]: RMU disabled (default)
EN 23

lo
• 0b01 [0b10]: RMU enabled on port 1

no
ID -jq

• 0b10 [0b01]: RMU enabled on port 7

• 0b11 [0b00]: RMU enabled on port 8

ch
NF jx

NOTE: These pins are internally pulled high.

CO z1m

Te
1. For an overview of the configuration options for ports 5/6/7 and port 8, also see Section 3.1, Port Configuration, on page 44.

ic
LL 8vd

35 on
2.3.2 Pin Connection Information

90 tr
VE jm

16 lec
This section lists the possible configuration combinations and specifies how to connect the
AR b
M 9stk

12 e E
appropriate pins. In the following tables, “Pull-Down” stands for an external pull-down resistor and
“Pull-Up” for an external pull-up resistor; both with a recommended resistance value of 4.7 k.

A# ing
“Unconnected” means no external bootstrap resistor at the pin.
f5
z4

ND i H
2.3.2.1 Slave Address (MDC/MDIO_CPU Interface)
zs

a
60

ER gh

The ADDRn[4] and ADDRn[2:0] pins specify the slave address for the MDC/MDIO_CPU interface.
Table 21 shows how to connect the pins for the different configurations.
o

ND an
ih

, U Sh
vd

Table 21: ADDRn[4], ADDRn[2:0] Configuration (Sheet 1 of 2)

2

AL *

Slave ADDRn[4] ADDRn[2] ADDRn[1] ADDRn[0]

4o

TI tlfs

Address
m
MARVELL CONFIDENTIAL

0x0 (default) Unconnected / Pull-Up Unconnected / Pull-Up Unconnected / Pull-Up Unconnected / Pull-Up
EN 23
ID -jq

0x1 Unconnected / Pull-Up Unconnected / Pull-Up Unconnected / Pull-Up Pull-Down

ou

NF jx

0x2 Unconnected / Pull-Up Unconnected / Pull-Up Pull-Down Unconnected / Pull-Up

CO z1m

0x3 Unconnected / Pull-Up Unconnected / Pull-Up Pull-Down Pull-Down

0x4 Unconnected / Pull-Up Pull-Down Unconnected / Pull-Up Unconnected / Pull-Up
LL 8vd

0x5 Unconnected / Pull-Up Pull-Down Unconnected / Pull-Up Pull-Down

VE jm

0x6 Unconnected / Pull-Up Pull-Down Pull-Down Unconnected / Pull-Up

AR b

0x7 Unconnected / Pull-Up Pull-Down Pull-Down Pull-Down

M 9stk

0x10 Pull-Down Unconnected / Pull-Up Unconnected / Pull-Up Unconnected / Pull-Up

5

0x11 Pull-Down Unconnected / Pull-Up Unconnected / Pull-Up Pull-Down

4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 39

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 21: ADDRn[4], ADDRn[2:0] Configuration (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
Slave ADDRn[4] ADDRn[2] ADDRn[1] ADDRn[0]

35 on
Address

9 0 tr
16 lec
0x12 Pull-Down Unconnected / Pull-Up Pull-Down Unconnected / Pull-Up
0x13 Pull-Down Unconnected / Pull-Up Pull-Down Pull-Down

12 e E
0x14 Pull-Down Pull-Down Unconnected / Pull-Up Unconnected / Pull-Up

A# ing
0x15 Pull-Down Pull-Down Unconnected / Pull-Up Pull-Down

ND i H
0x16 Pull-Down Pull-Down Pull-Down Unconnected / Pull-Up

a
0x17 Pull-Down Pull-Down Pull-Down Pull-Down

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
2.3.2.2 CPU State
, U Sh

Co
The CPU_EN pin specifies whether the internal CPU is enabled or disabled. Table 22 shows how to
AL *

connect the pins for the different configurations.

TI tlfs

yg
Table 22: CPU_EN Configuration
EN 23

lo
no
ID -jq

C P U S ta t e C P U _E N

ch
NF jx

CPU enabled (default) Unconnected / Pull-Up

CO z1m

Te
CPU disabled Pull-Down

ic
LL 8vd

35 on
2.3.2.3 Port State

90 tr
VE jm

The Px_ACTIVEn pins specify the state that the appropriate port will have after reset (the “x” in the

16 lec
AR b

pin name refers to ports 1 to 8). Table 23 shows how to connect the pins for the different
M 9stk

12 e E
configurations.

A# ing
f5

Table 23: Px_ACTIVEn Configuration

z4

P or t S ta t e ND i H
P x _A C T I VE n
zs

a
• Port disabled, if RMU disabled for the port Unconnected / Pull-Up
60

ER gh

• Port blocking, if RMU enabled for the port

o

(default)
ND an
ih

, U Sh

Port enabled/forwarding Pull-Down

2 vd

AL *
4o

2.3.2.4 100BASE-T1 PHY Mode

TI tlfs
m
MARVELL CONFIDENTIAL

The Px_MASTER pins specify the PHY mode for the appropriate 100BASE-T1 port (the “x” in the
EN 23

pin name refers to ports1 to 5). Table 24 shows how to connect the pins for the different
ID -jq
ou

configurations.
NF jx
CO z1m

Table 24: Px_MASTER Configuration

100BASE-T1 PHY Mode P x _M A S TE R
LL 8vd

Master (default) Unconnected / Pull-Up

VE jm

Slave Pull-Down
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 40 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Configuration Pins (Bootstrapping)

ch
Te
2.3.2.5 100BASE-T1 Wake Mode
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
The Px_WAKE_DIS pins specify whether the appropriate 100BASE-T1 PHY is enabled to wake up

35 on
the device from a low-power state (the “x” in the pin name refers to ports1 to 5). Table 25 shows how

9 0 tr
to connect the pins for the different configurations.

16 lec
Table 25: Px_WAKE_DIS Pin Configuration

12 e E
1 0 0 B A S E - T 1 Wa k e M od e P x _ WA K E _ D I S

A# ing
PHY not able to wake up the device (default) Unconnected / Pull-Up

ND i H
PHY able to wake up the device Pull-Down

a
ER gh
2.3.2.6 P567 Mode

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
The P567_MODE[2:0] pins specify the P567 mode. Table 26 shows how to connect the pins for the
different configurations.

Co
AL *
TI tlfs

Table 26: P567_MODE[2:0] Configuration

yg
EN 23

lo
P567 Mode P 56 7 _ M O D E [ 2 ] P 5 67 _ M O D E [ 1 ] P 5 6 7_ M O D E [ 0 ]

no
ID -jq

RGMII (default) Unconnected / Pull-Up Unconnected / Pull-Up Unconnected / Pull-Up

ch
NF jx

xMII disabled Unconnected / Pull-Up Unconnected / Pull-Up Pull-Down

CO z1m

Te
RMII MAC Unconnected / Pull-Up Pull-Down Unconnected / Pull-Up

ic
LL 8vd

RMII PHY Unconnected / Pull-Up Pull-Down Pull-Down

35 on
Reserved Pull-Down Unconnected / Pull-Up Unconnected / Pull-Up

90 tr
VE jm

16 lec
MII MAC Pull-Down Unconnected / Pull-Up Pull-Down
AR b
M 9stk

12 e E
MII PHY Pull-Down Pull-Down Unconnected / Pull-Up
MII PHY (full duplex only) Pull-Down Pull-Down Pull-Down

A# ing
f5
z4

ND i H
2.3.2.7 P567 Interface Select
zs

a
60

ER gh

The P567_SEL[1] and P567_SELn[0] pins select which of the P567 is connected to xMII. Table 27
shows how to connect the pins for the different configurations.
o

ND an
ih

, U Sh

Table 27: P567_SEL[1], P567_SELn[0] Configuration

2 vd

P 56 7 In t e r f a c e P 5 67 _ S E L[ 1 ] P 5 6 7_ S E L n [ 0 ]
AL *
4o

TI tlfs

• Port 5 connected to 100BASE-T1 PHY Unconnected / Pull-Down Unconnected / Pull-Up

m
MARVELL CONFIDENTIAL

• Port 6 connected to 100BASE-TX PHY

EN 23

• Port 7 connected to SERDES (SGMII)

ID -jq
ou

(default)
NF jx

Port 5 connected to xMII Unconnected / Pull-Down Pull-Down

CO z1m

Port 6 connected to xMII Pull-Up Unconnected / Pull-Up

Port 7 connected to xMII Pull-Up Pull-Down
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 41

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
2.3.2.8 P567 Power Supply Voltage Select
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
The P567_VDDO_SEL[1:0] pins must be configured to the power supply voltage that is connected

35 on
to the P567 interface (including SMI master). Table 28 shows how to connect the pins for the

9 0 tr
different configurations.

16 lec
Table 28: P567_VDDO_SEL[1:0] Configuration

12 e E
P 56 7 P ow e r S u p pl y P 5 67 _ V D D O _ S E L [ 1 ] P 5 6 7_ V D D O _ S E L [ 0]

A# ing
3.3V (default) Unconnected / Pull-Up Unconnected / Pull-Up

ND i H
1.8V Unconnected / Pull-Up Pull-Down

a
ER gh
2.5V Pull-Down Unconnected / Pull-Up

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
3.3V Pull-Down Pull-Down

., L
, U Sh

Co
AL *
TI tlfs

yg
EN 23

lo
no
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 42 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Signal Description

no
Configuration Pins (Bootstrapping)

ch
Te
2.3.2.9 P8 Mode
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
The P8_MODEn[2] and P8_MODE(1:0] pins specify the P8 mode. Table 29 shows how to connect

35 on
the pins for the different configurations.

9 0 tr
16 lec
Table 29: P8_MODEn[2], P8_MODE[1:0] Configuration

12 e E
P8 M o d e P 8_ M O D E n [2 ] P 8 _M O D E [1 ] P 8 _ M O D E [ 0]

A# ing
RGMII (default) Unconnected / Pull-Down Unconnected / Pull-Up Unconnected / Pull-Up
xMII disabled Unconnected / Pull-Down Unconnected / Pull-Up Pull-Down

ND i H
RMII MAC Unconnected / Pull-Down Pull-Down Unconnected / Pull-Up

a
ER gh
RMII PHY Unconnected / Pull-Down Pull-Down Pull-Down

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
GMII Pull-Up Unconnected / Pull-Up Unconnected / Pull-Up

., L
, U Sh
MII MAC Pull-Up Unconnected / Pull-Up Pull-Down

Co
AL *

MII PHY Pull-Up Pull-Down Unconnected / Pull-Up

TI tlfs

y
MII PHY (full duplex only) Pull-Up Pull-Down Pull-Down

g
EN 23

lo
no
ID -jq

2.3.2.10 P8 Power Supply Voltage Select

ch
NF jx

The P8_VDDO_SEL[1:0] must be configured to the power supply voltage that is connected to the P8
CO z1m

Te
interface (including SMI slave). Table 30 shows how to connect the pins for the different

ic
configurations.
LL 8vd

35 on
Table 30: P8_VDDO_SEL[1:0] Configuration

90 tr
VE jm

16 lec
P 8 P ow e r S u p pl y P 8 _V D D O _ S E L[ 1 ] P 8 _ VD D O _ S E L[ 0 ]
AR b
M 9stk

12 e E
3.3V (default) Unconnected / Pull-Up Unconnected / Pull-Up
1.8V Unconnected / Pull-Up Pull-Down

A# ing
f5

2.5V Pull-Down Unconnected / Pull-Up

z4

ND i H
3.3V Pull-Down Pull-Down
zs

a
60

ER gh

2.3.2.11 RMU Port Select

o

ND an
ih

, U Sh

The RMU_SELn[1:0] pins select the RMU port. Table 31 shows how to connect the pins for the
vd

different configurations.
2

AL *
4o

TI tlfs

Table 31: RMU_SELn[1:0] Configuration

m
MARVELL CONFIDENTIAL

EN 23

RMU Port R M U _ S EL n [ 1 ] R M U _ S EL n [ 0 ]
ID -jq
ou

RMU disabled (default) Unconnected / Pull-Up Unconnected / Pull-Up

NF jx

RMU enabled on port 1 Unconnected / Pull-Up Pull-Down

CO z1m

RMU enabled on port 7 Pull-Down Unconnected / Pull-Up

RMU enabled on port 8 Pull-Down Pull-Down
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 43

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Device Physical Interfaces

9 0 tr
16 lec
12 e E
The 88Q5050 device contains a number of interfaces that support copper media. Table 32 shows
the possible interface combinations that can be configured for the 88Q5050 device’s ports. “xMII”

A# ing
stands for “MII / RMII / RGMII”.

ND i H
Each table row shows one combination, that is, there is a total of 5 possible interface combinations.
For connection details, see Section 3.2, Interfaces, on page 46.

a
ER gh
Table 32: Interface Combinations

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
Po rt s 1 to 4 P or t 5 P or t 6 P or t 7 P or t 8 N o t es
, U Sh

Co
100BASE-T1 100BASE-T 100BASE-T SGMII xMII
AL *

1 X
TI tlfs

y
100BASE-T1 xMII 100BASE-T SGMII xMII Ports 5, 6, and 7 are shared. If any of

g
EN 23

lo
X these ports is configured as MII, RMII, or

no
ID -jq

RGMII, the two other ports can only be

100BASE-T1 100BASE-T xMII SGMII xMII
PHY or SERDES, respectively (that is,

ch
NF jx

1
port 5 configured as 100BASE-T1
CO z1m

Te
100BASE-T1 100BASE-T 100BASE-T xMII xMII interface, port 6 as 100BASE-TX interface,
1 X and port 7 as SGMII).

ic
LL 8vd

35 on
100BASE-T1 100BASE-T 100BASE-T SGMII GMII If port 8 is configured as GMII, ports 5, 6,
1 X and 7 can only be PHY or SERDES,

90 tr
VE jm

respectively.

16 lec
AR b
M 9stk

12 e E
3.1 Port Configuration
A# ing
f5
z4

ND i H
The configuration of ports 5/6/7 and port 8 is done once at reset by the configuration pins P567_
zs

SELx[1:0], P567_MODE[2:0], and P8_MODEx[2:0]. For details, also see Section 2.3, Configuration
a
60

ER gh

Pins (Bootstrapping), on page 36.

o

ND an

Table 33 and Table 34 list the possible settings for the port configuration pins and their
ih

dependencies
, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23

The external signals for some of the listed pins are inverted. In these cases, the actual
external signals to be applied are shown in brackets.
ID -jq
ou

Caution
NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 44 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Device Physical Interfaces

no
Port Configuration

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Table 33: Port 5/6/7 Configuration

ic
35 on
P567_ P567 P8_ R e s u lt in g P o r t Resulting Port R e s u lti n g Notes
S E L [1 ] , _ M O D E n [2 ], 5 6 Port 7

9 0 tr
P567_ MOD P8_ C o n fi gu r a t io n C o nf ig u r a ti on C o nf ig u r a ti o

16 lec
SE L n [0 ] E M O D E [1 : 0 ] n

12 e E
[ 2 :0 ]
0x0 [0x1] don’t don’t care 100BASE-T1 PHY 100BASE-TX PHY SERDES

A# ing
(default) care (SGMII)

ND i H
0x1 [0x0] 0x0 All values Full-duplex MII 100BASE-TX PHY SERDES Setting

a
except 0x3 [0x7] PHY (SGMII) P567_

ER gh
MODE[2:
0x1 MII PHY
0]

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
0x2 MII MAC to 0x3

., L
, U Sh
[0x2] is
0x4 RMII PHY

Co
not
AL *

0x5 RMII MAC allowed

TI tlfs

y
0x6 Disabled (undefine

g
d).
EN 23

lo
0x7 RGMII

no
ID -jq

(defaul P8_

ch
NF jx

t) MODEx[
CO z1m

2:0] must

Te
0x2 [0x3] 0x0 All values 100BASE-T1 PHY Full-duplex MII SERDES
except 0x3 [0x7] PHY (SGMII) not

ic
be set to
LL 8vd

35 on
0x1 MII PHY 0x3 [0x7]
(GMII

90 tr
VE jm

0x2 MII MAC

16 lec
mode).
AR b

0x4 RMII PHY

M 9stk

12 e E
0x5 RMII MAC

A# ing
0x6 Disabled
f5
z4

0x7 RGMII
ND i H
zs

(defaul
a
t)
60

ER gh

0x3 [0x2] 0x0 All values 100BASE-T1 PHY 100BASE-TX PHY Full-duplex MII
o

ND an
ih

except 0x3 [0x7] PHY

, U Sh
vd

0x1 MII PHY

2

AL *

0x2 MII MAC

4o

TI tlfs
m

0x4 RMII PHY

MARVELL CONFIDENTIAL

EN 23

0x5 RMII MAC

ID -jq
ou

0x6 Disabled
NF jx

0x7 RGMII
CO z1m

(defaul
t)
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 45

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Table 34: Port 8 Configuration

ic
35 on
P8_ P 56 7 _ S E L[ 1 ], P567_ Resulting Port 8 Notes
MODEn[2], P 56 7 _ S E Ln [0 ] M O D E [2 : 0 ] C o nf ig u r a ti on

9 0 tr
P8_

16 lec
MODE[1:0]

12 e E
0x0 [0x4] don’t care Full-duplex MII PHY

A# ing
0x1 [0x5] MII PHY

ND i H
0x2 [0x6] MII MAC
0x3 [0x7] 0x0 [0x1] don’t care GMII • P567_SELx[1:0] must be

a
ER gh
set to 0x0 [0x1].
• P567_VDDO_SEL and

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
P8_VDDO_SEL must be

., L
, U Sh
set to the same value.

Co
0x4 [0x0] don’t care RMII PHY
AL *
TI tlfs

y
0x5 [0x1] RMII MAC

g
EN 23

lo
0x6 [0x2] Disabled

no
ID -jq

0x7 [0x3] RGMII

ch
(default)
NF jx
CO z1m

Te
ic
LL 8vd

35 on
3.2 Interfaces

90 tr
VE jm

16 lec
AR b

3.2.1 100BASE-T1 PHY Interface

M 9stk

12 e E
Ports1 to 5 of the 88Q5050 device support a 100 Mbps PHY interface that is compliant to the

A# ing
f5

100BASE-T1 copper IEEE standard. The MAC inside the switch works the same way regardless of
z4

ND i H
the external interface being used. Each PHY’s link, speed, duplex, and flow control information is
zs

directly communicated to the MAC that it is attached to, so the MAC tracks (and follows) the mode
a
60

ER gh

the PHY links up in.

o

ND an

For a detailed description of the PHY functionality and registers, see the 88Q5050 Functional
ih

Specification and 88Q5050 Register Specification.

, U Sh
2 vd

AL *

3.2.2 100BASE-TX PHY Interface

4o

TI tlfs
m
MARVELL CONFIDENTIAL

Port 6 of the 88Q5050 device supports a 10/100 Mbps PHY interface that is compliant to the
EN 23

10BASE-T and 100BASE-TX copper IEEE standards. The MAC inside the switch works the same
ID -jq

way regardless of the external interface being used. Each PHY’s link, speed, duplex, and flow
ou

control information is directly communicated to the MAC that it is attached to, so the MAC tracks
NF jx

(and follows) the mode the PHY links up in.

CO z1m

For a detailed description of the PHY functionality and registers, see the 88Q5050 Functional
LL 8vd

Specification and 88Q5050 Register Specification.

VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 46 Document Classification: Proprietary Information March 07, 2018

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Device Physical Interfaces

no
Interfaces

ch
Te
3.2.3 SERDES Interface
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Port 7 is a SERDES interface. It can be used for the following options:
Connection to Marvell® triple speed 10/100/1000 Mbps copper PHYs

9 0 tr


16 lec
 Connection to 1000BASE-X fiber modules
SGMII

12 e E

 Cross-chip connection to other Marvell switch devices

A# ing
For a detailed description of the SERDES functionality and registers, see the 88Q5050 Functional
Specification and 88Q5050 Register Specification.

ND i H
a
3.2.3.1 Triple-Speed PHY SERDES Interface Option

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Port 7’s SERDES can be configured to use a triple-speed PHY interface to an external PHY. In this

., L
mode, the SERDES uses the SGMII protocol. The in-band link, speed, and duplex signals in the
, U Sh
SGMII protocol are ignored. The external PHY’s link, speed, duplex, and flow control information

Co
AL *

must be transferred to the port’s MAC so that the MAC is in the correct mode. This can either be
TI tlfs

done in the software (if the port’s PHYDetect bit is 0 – switch core’s PORT offset 0x00), or it is done

yg
automatically by the PHY Polling Unit (see Section 3.2.5, PHY Polling Unit (PPU), on page 54).
EN 23

lo
no
ID -jq

3.2.3.2 IEEE 1000BASE-X SERDES Interface Option

ch
NF jx

Port 7’s SERDES can be configured for 100BASE-FX or 1000BASE-X/SGMII modes. If configured
CO z1m

Te
for 1000BASE-X mode, the port enters 1000BASE-X mode even if an external PHY is detected at
the port’s SMI address.

ic
LL 8vd

35 on
The 1000BASE-X mode uses a PCS to auto-negotiate with a link partner to determine if flow control
should be supported or not (auto-negotiation can be disabled). The link will be automatically

90 tr
VE jm

16 lec
established if the port’s PCS determines Sync is OK (sets the port’s SyncOK to 1). The link will
AR b

automatically go down if SyncOK is 0. The speed is always 1000 Mbps, and the duplex mode is
M 9stk

12 e E
always full-duplex on 1000BASE-X ports. An interrupt can be generated on the ports when the link
changes its state (see switch core’s GLB2 offsets 0x00 and 0x01).

A# ing
f5
z4

3.2.3.3 Port Status Registers ND i H

zs

a
Each switch port of the 88Q5050 device has a status register that reports information about that
60

ER gh

port’s MAC, SERDES, or digital interface. These registers can be used to check the current port
o

ND an

configuration. For details, see the 88Q5050 Register Specification.

ih

, U Sh
vd

3.2.4 Digital Interface Options

2

AL *
4o

TI tlfs

The xMII/GMII digital interface supports many different modes defined in the following sections. The
m
MARVELL CONFIDENTIAL

mode to use is configured once at reset by the configuration pins (see Section 2.3, Configuration
EN 23

Pins (Bootstrapping), on page 36). If any of the ports is not connected to an external device, the port
ID -jq
ou

should be disabled.
NF jx
CO z1m

xMII/GMII PHY mode and xMII/GMII MAC mode are discussed in the following
sections. Electrically, there is no difference since the interface uses
LL 8vd

source-synchronous clocks. Each concept is discussed separately since the port can
Note be connected to either an external PHY (that is, MAC mode—where the port looks like
VE jm

a MAC supporting 10/100/1000 Mbps) or to an external MAC (that is, PHY mode—
AR b

where the port looks like a PHY supporting 1000 Mbps only).
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 47

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
3.2.4.1 MII MAC Mode
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
MII MAC mode, sometimes called “Forward MII”, configures port 5/6/7’s and/or port 8’s GMAC

35 on
inside the 88Q5050 device to act as a MAC so that it can be directly connected to an external

9 0 tr
MII-based PHY. In this mode, the 88Q5050 device receives the interface clocks (Px_OUTCLK and

16 lec
Px_INCLK) from the PHY and will work at any frequency from DC to 50 MHz. Both full-duplex and

12 e E
half-duplex modes are supported and need to be selected to match the mode of the link partner’s
MAC. The MII MAC mode is compliant with IEEE 802.3 clause 22. For auto-negotiation results to be

A# ing
properly communicated from the PHY to the MAC by the internal PPU, the PHY’s SMI address must
be set to the appropriate port number (0x05 for port 5, 0x06 for port 6, and so on) .

ND i H
Figure 10: MII MAC Interface Pins

a
ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
88Q5050

., L
, U Sh

Co
AL *

Px_INCLK RX_CLK
TI tlfs

Px_IND[3:0] RXD[3:0]

yg
Px_INDV RX_DV
EN 23

lo
no
ID -jq

ch
NF jx

Port 5/6/7
CO z1m

and/or Port 8 PHY Device

Te
acting as a with MII

ic
MAC
LL 8vd

35 on
90 tr
VE jm

Px_OUTCLK TX_CLK

16 lec
AR b

Px_OUTD[3:0] TXD[3:0]
M 9stk

12 e E
Px_OUTEN TX_EN
TX_ER

A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 48 Document Classification: Proprietary Information March 07, 2018

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Device Physical Interfaces

no
Interfaces

ch
Te
3.2.4.2 MII PHY Mode
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
MII PHY mode, sometimes called “Reverse MII”, configures port 5/6/7’s and/or port 8’s GMAC inside

35 on
the 88Q5050 device to act as a PHY so that it can be directly connected to an external MAC. In this

9 0 tr
mode, the 88Q5050 device drives the interface clocks (INCLK and OUTCLK). The MII PHY mode is

16 lec
compliant with IEEE 802.3 clause 22.

12 e E
Figure 11: MII PHY Interface Pins

A# ing
ND i H
88Q5050

a
ER gh
Px_INCLK TX_CLK
Px_IND[3:0] TXD[3:0]

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
Px_INDV
, U Sh TX_EN

Co
AL *
TI tlfs

Port 5/6/7

yg
and/or Port 8 CPU Device
EN 23

lo
acting as a with MII MAC

no
ID -jq

PHY

ch
NF jx
CO z1m

Te
Px_OUTCLK RX_CLK

ic
LL 8vd

Px_OUTD[3:0] RXD[3:0]

35 on
Px_OUTEN RX_DV

90 tr
VE jm

RX_ER

16 lec
AR b
M 9stk

12 e E
3.2.4.3 RMII MAC Mode

A# ing
f5
z4

RMII MAC mode supports 10 Mbps or 100 Mbps and full-duplex or half-duplex. In RMII MAC mode,
ND i H
REFCLK is an input and is expected to be 50 MHz for all data rates.
zs

a
60

ER gh

Figure 12: RMII MAC Interface Pins

o

ND an
ih

, U Sh

88Q5050
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23

Px_IND[1:0] RXD[1:0]
Px_INDV CRS_DV
ID -jq
ou

NF jx
CO z1m

Port 5/6/7
and/or Port 8
RMII PHY
acting as a
LL 8vd

MAC
VE jm

Px_OUTCLK REFCLK
AR b

Px_OUTD[1:0] TXD[1:0]
M 9stk

Px_OUTEN TX_EN
RX_ER
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 49

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
3.2.4.4 RMII PHY Mode
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
RMII PHY mode, sometimes called “Reduced MII”, configures the desired MAC inside the 88Q5050

35 on
device to act as a 10 Mbps or 100 Mbps PHY, enabling it to be directly connected to an external

9 0 tr
CPU supporting an RMII. In RMII PHY mode, REFCLK is sourced internally and is 50 MHz for all

16 lec
data rates.

12 e E
Figure 13: RMII PHY Interface Pins

A# ing
ND i H
88Q5050

a
ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Px_IND[1:0] TXD[1:0]

., L
, U Sh
Px_INDV TX_EN

Co
AL *
TI tlfs

y
Port 5/6/7

g
and/or Port 8
EN 23

lo
RMII MAC
acting as a

no
ID -jq

PHY

ch
NF jx
CO z1m

Px_OUTCLK REFCLK

Te
Px_OUTD[1:0] RXD[1:0]

ic
Px_OUTEN CRS_DV
LL 8vd

35 on
RX_ER

90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 50 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Device Physical Interfaces

no
Interfaces

ch
Te
3.2.4.5 RGMII Mode
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
RGMII mode configures port 5/6/7’s and/or port 8’s GMAC to act as a Reduced Gigabit Media

35 on
Independent Interface (RGMII) so that it can be directly connected to an external RGMII-based

9 0 tr
Gigabit PHY or CPU. When RGMII mode is selected, transmit control (Px_OUTEN) is presented on

16 lec
both clock edges of Px_OUTCLK. Receive control (Px_INDV) is presented on both clock edges of

12 e E
Px_INCLK. A triple-speed interface is supported in RGMII mode (that is, 10 Mbps, 100 Mbps, and
1000 Mbps). When the PHY completes auto-negotiation and brings the link up, the auto-negotiated

A# ing
speed, duplex, and flow control information must be moved from the PHY to the MAC so that the
MAC matches the PHY’s settings. This is done automatically by the PPU if the port’s PHYDetect bit

ND i H
is set to 1 (switch core’s PORT offset 0x00).

a
ER gh
Figure 14: RGMII Pins

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
88Q5050

Co
AL *
TI tlfs

y
Px_INCLK RXC

g
EN 23

lo
Px_IND[3:0] RXD[3:0]

no
ID -jq

Px_INDV RX_CTL

ch
NF jx
CO z1m

Te
Port 5/6/7 Device

ic
LL 8vd

and/or Port 8 with RGMII

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

Px_OUTCLK TXC

12 e E
Px_OUTD[3:0] TXD[3:0]

A# ing
Px_OUTEN TX_CTL
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 51

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
3.2.4.6 GMII MAC Mode
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
GMII MAC mode, sometimes called “Forward GMII”, configures port 8’s GMAC inside the 88Q5050

35 on
device to act as a Gigabit MAC (GMAC) so that it can be directly connected to an external

9 0 tr
GMII-based Gigabit PHY. In this mode, the 88Q5050 device receives the interface clocks (OUTCLK

16 lec
and INCLK) from the PHY, but generates GTX_CLK for the PHY. 10 Mbps, 100 Mbps, or 1000 Mbps

12 e E
is supported in this configuration. Full-duplex and half-duplex modes are supported at 10 Mbps or
100 Mbps. Full-duplex is supported at 1000 Mbps. When the PHY completes auto-negotiation and

A# ing
brings the link up, the auto-negotiated speed, duplex, and flow control information must be moved
from the PHY to the MAC so that the MAC matches the PHY’s settings. This is done automatically

ND i H
by the PPU if the port’s PHYDetect bit is set to 1 (switch core’s PORT offset 0x00). The interface

a
pins will track the speed that the MAC is set to.

ER gh
The speed and mode in the external PHY’s auto-negotiation must be restricted from advertising the

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
1000BASE, half-duplex case as the GMAC inside the 88Q5050 device does not support that mode.

., L
, U Sh
This is done automatically by the PPU. The GMII MAC mode is compliant with IEEE 802.3

Co
clause 28. For auto-negotiation results to be properly communicated from the PHY to the MAC by
AL *

the internal PPU, the PHY’s SMI address must be set to 0x08 for port 8.
TI tlfs

yg
Figure 15: GMII MAC Interface Pins
EN 23

lo
no
ID -jq

88Q5050

ch
NF jx
CO z1m

Te
1
IND[7:4] = P567_IND[3:0]
P8_INCLK RX_CLK IND[3:0] = P8_IND[3:0]

ic
IND[7:0]1 RXD[7:0]
LL 8vd

2
OUTCLK = P8_OUTCLK

35 on
P8_INDV RX_DV 3
GTX_CLK = P567_OUTCLK

90 tr
VE jm

16 lec
4
OUTD[7:4] = P567_OUTD[3:0]
AR b

OUTD[3:0] = P8_OUTD[3:0]
M 9stk

12 e E
Port 8
PHY Device

A# ing
acting as a
f5

with GMII
GMAC
z4

ND i H
zs

OUTCLK2 TX_CLK
a
60

ER gh

GTX_CLK3 GTX_CLK
o

OUTD[7:0]4
ND an

TXD[7:0]
ih

P8_OUTEN TX_EN
, U Sh
vd

TX_ER
2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx

If port 8 is configured as GMII, it uses some of the port 5/6/7 interface pins.
CO z1m

Note
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 52 Document Classification: Proprietary Information March 07, 2018

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Device Physical Interfaces

no
Interfaces

ch
Te
3.2.4.7 GMII PHY Mode
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
GMII PHY mode, sometimes called “Reverse GMII”, configures port 8’s GMAC inside the 88Q5050

35 on
device to act as a Gigabit PHY so that it can be directly connected to an external GMAC. In this

9 0 tr
mode, the 88Q5050 device drives the transmit interface clock (GTX_CLK) and accepts the receive

16 lec
interface clock (INCLK). Only Gigabit full-duplex mode is supported, and it must match the mode of

12 e E
the link partner’s GMAC. The GMII PHY mode is compliant with IEEE 802.3 clause 28 in Gigabit
full-duplex. In this mode, there is no external PHY for port 8, so it is skipped by the PPU.

A# ing
This configuration is identical to the GMII MAC mode described above, except that a CPU is

ND i H
connected instead of a PHY. The lack of an external PHY device restricts the interface to Gigabit
speed only, with the link initially being down. This grants the CPU time to initialize itself before it

a
ER gh
enables the switch port connected to it by forcing link up in the switch port’s MAC (in the port’s
Physical Control Register – switch core’s PORT offset 0x01).

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
Figure 16: GMII PHY Interface Pins

Co
AL *
TI tlfs

88Q5050

yg
EN 23

1
IND[7:4] = P567_IND[3:0]

lo
INCLK GTX_CLK IND[3:0] = P8_IND[3:0]

no
ID -jq

IND[7:0]1 TXD[7:0] 2
GTX_CLK = P567_OUTCLK

ch
NF jx

INDV TX_EN 3
OUTD[7:4] = P567_OUTD[3:0]
CO z1m

Te
OUTD[3:0] = P8_OUTD[3:0]

ic
LL 8vd

35 on
Port 8
CPU Device
acting as a

90 tr
VE jm

with GMII MAC

16 lec
PHY
AR b
M 9stk

12 e E
A# ing
GTX_CLK2 RX_CLK
f5

OUTD[7:0]3
z4

RXD[7:0]
OUTEN RX_DV
ND i H
zs

a
RX_ER
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs

If port 8 is configured as GMII, it uses some of the port 5/6/7 interface pins.
m
MARVELL CONFIDENTIAL

EN 23

Note
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 53

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
3.2.5 PHY Polling Unit (PPU)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
The 88Q5050 device contains a PHY Polling Unit (PPU) to transfer link, speed, duplex, and pause
information from an external 100BASE-TX or 1000BASE-T PHY to its associated MAC (the internal

9 0 tr
PHYs use a direct approach such that this information is transferred even if PHY polling is disabled

16 lec
on the port by its PHYDetect bit being 0 – switch core’s PORT offset 0x00). The PPU can perform

12 e E
this job only if the SMI address of the external PHY matches the physical port number that it is
connected to in the switch (that is,the PHY connected to port 5 uses SMI address 0x05, the PHY

A# ing
connected to port 6 uses SMI address 0x06 and so on) .

ND i H
If PHY polling is disabled on a port (that is, the port’s PHYDetect bit is 0), the software must perform
the job of setting the switch MAC’s mode to the mode of the PHY (for the external PHYs) by forcing

a
ER gh
the MAC’s link, speed, duplex, and pause settings (in the port’s Physical Control Register – switch
core’s PORT offset 0x01) based upon what it sees in the PHY’s registers. Link up must be the last

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
mode register set, and link down must be the first mode register cleared (that is, the port’s speed,

., L
, U Sh
duplex, and pause modes must only be changed while the port’s link is down).

Co
AL *

Even though the PPU has full access to the external and internal PHY’s registers, the software can
TI tlfs

access all PHY registers at any time by using the SMI PHY Command and Data registers (switch

yg
core’s GLB2 offsets 0x18 and 0x19).
EN 23

lo
no
ID -jq

ch
NF jx

The PPU is designed to work with 100BASE-TX and 1000BASE-T PHYs. It does not
CO z1m

Te
support 100BASE-T1 or 1000BASE-T1 PHYs.
If 100BASE-T1 or 1000BASE-T1 PHYs are connected externally, the CPU must poll

ic
Note
LL 8vd

those PHYs manually to detect link, speed, and duplex changes.

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 54 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
Absolute Maximum Ratings

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Electrical Specifications

9 0 tr
16 lec
12 e E
4.1 Absolute Maximum Ratings

A# ing
Table 35: Absolute Maximum Ratings

ND i H
Stresses above the absolute maximum ratings listed here may cause permanent device failure. Functionality at or above
these limits is not implied. Exposure to absolute maximum ratings for extended periods may affect device reliability.

a
ER gh
Sy m b o l Parameter Min Ty p Max U ni t

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
1
VDDA(18) 1.8V Power Supply Voltage on AVDD18 and -0.30 -- 2.16 V

., L
, U Sh
S_AVDD18

Co
VDDA(33) 3.3V Power Supply Voltage1 on AVDD33 -0.30 -- 3.60 V
AL *
TI tlfs

y
VDD(1.0) 1.0V Power Supply Voltage on VDD -0.30 -- 1.20 V

g
EN 23

lo
VDDO Power Supply Voltage on VDDO, VDDO_P567, -0.30 -- 3.60 V

no
and VDDO_P8
ID -jq

Power Supply Voltage1 on VDDO_EFUSE

ch
VDDO(EFUS -0.30 -- 2.75 V
NF jx
CO z1m

E)

Te
VPIN Voltage applied to any Digital Input Pin -0.30 -- 3.60 V

ic
LL 8vd

or VDDO + 0.7

35 on
whichever is less

90 tr
VE jm

VBAT Battery Voltage 5 12 28 V

16 lec
AR b

TJ Junction Temperature -40 -- +125 °C

M 9stk

12 e E
2
TSTORAGE Storage Temperature -55 -- +125 °C

A# ing
f5

1. Supply voltages are referenced to VSS.

z4

2. 125°C is the re-bake temperature. ND i H

zs

For extended storage time greater than 24 hours, +85°C should be the maximum.
a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *

VDDO(EFUSE) must be powered after VDD(1.0).

4o

TI tlfs

Caution
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 55

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
4.2 Recommended Operating Conditions
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 36: Recommended Operating Conditions

9 0 tr
16 lec
Sy m b o l Parameter C o n d iti o n Min Ty p Max Un
it

12 e E
VDDA(18) AVDD18 Supply1 For AVDD18 and S_AVDD18 1.71 1.80 1.89 V

A# ing
1
VDDA(33) AVDD33 Supply For AVDD33 3.14 3.30 3.46 V
VDD Supply1

ND i H
VDD(1.0) For VDD 0.95 1.00 1.05 V
VDDO Supply1,2 • For VDDO at 1.8V

a
VDDO 1.71 1.80 1.89 V

ER gh
• For VDDO at 2.5V 2.37 2.50 2.63 V

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
• For VDDO at 3.3V 3.14 3.30 3.46 V

., L
, U Sh
VDDO(EFUS VDDO Supply1,3 • For VDDO_EFUSE at 1.71 1.80 1.89 V

Co
1.8V
AL *

E)
TI tlfs

y
• For VDDO_EFUSE at 2.37 2.50 2.63 V

g
2.5V
EN 23

lo
no
TA Ambient Operating For AEC-Q100 Grade 2 -40 -- 105 °C
ID -jq

Temperature

ch
NF jx

TJ Junction Temperature -- -- 125 °C

CO z1m

Te
RSET Internal Bias Reference External resistor value 4950 5000 5050 

ic
LL 8vd

required to be placed

35 on
between RSET and VSS pins

90 tr
VE jm

1. Maximum noise allowed on supplies is 50 mW peak-peak.

16 lec
AR b

2. Some VDDO pins can be configured to either 1.8V, 2.5V, or 3.3V. To guarantee proper operation, the voltage must be set within the
M 9stk

12 e E
appropriate ranges in this table. VDDO voltages between 1.89V and 2.37V and between 2.63V and 3.14V are not supported.
3. The VDDO_EFUSE pin can be configured to either 1.8V or 2.5V. To guarantee proper operation, the voltage must be set within the

A# ing
appropriate ranges in this table. VDDO(EFUSE) voltages between 1.89V and 2.37V are not supported.
f5
z4

ND i H
zs

4.3 DC Electrical Characteristics

a
60

ER gh
o

ND an

4.3.1 Main Clock

ih

, U Sh
vd

Table 37: Main Clock (XTAL_IN) DC Characteristics

2

AL *
4o

(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)
TI tlfs
m

S ym bo l P ar a m e te r Min Ty p Max U ni t
MARVELL CONFIDENTIAL

EN 23

VXTAL_IN Input Voltage for XTAL_IN pin -- -- 1.8 V

ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 56 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
DC Electrical Characteristics

ch
Te
4.3.2 100BASE-T1 Transceiver
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
IEEE tests are typically based on templates and cannot simply be specified by a number. For an
exact description of the template and the test conditions, see the IEEE Standard 802.3bw.

9 0 tr
16 lec
Table 38: 100BASE-T1 Transceiver DC Characteristics
(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

12 e E
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

A# ing
VODIFF Absolute Peak Differential Output 100BASE-T1 mode -- -- 2.2 V

ND i H
Voltage1

a
VDIST Peak Distortion IEEE test mode 4 -- -- 15 mV

ER gh
1. Transmit power conforms to IEEE 802.3bw Transmit PSD mask.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
4.3.3 100BASE-TX Transceiver

Co
AL *
TI tlfs

Copied from FE PHY IP datasheet

yg
IEEE tests are typically based on templates and cannot simply be specified by a number. For an
EN 23

lo
exact description of the template and the test conditions, see the following specifications:

no
ID -jq

 10BASE-T: IEEE Standard 802.3 Clause 14

ch
NF jx

 100BASE-TX: ANSI/INCITS X3.263-1995 Standard

CO z1m

Te
Table 39: 100BASE-TX Transceiver DC Characteristics

ic
LL 8vd

(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

35 on
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

90 tr
VE jm

16 lec
VODIFF Absolute Peak Differential • 10BASE-T no cable -- 2.0 2.1 V
AR b

Output Voltage
M 9stk

• 10BASE-Te no cable

12 e E
1.54 1.75 1.96
• 10BASE-T cable 5851 -- -- mV

A# ing
f5

model
z4

• 100BASE-TX mode ND i H 0.95 1.0 1.05 V

zs

a
Overshoot2 100BASE-TX mode 0 -- 5% V
60

ER gh

Amplitude Symmetry 100BASE-TX mode 0.98x -- 1.02x V+/V-

o

ND an

(positive/ negative)
ih

, U Sh
vd

VIDIFF Peak Differential Input 10BASE-T mode 5852 -- -- mV

Voltage
2

AL *
4o

TI tlfs

Signal Detect Assertion 100BASE-TX mode 1000 4603 -- mV

m
MARVELL CONFIDENTIAL

peak-peak
EN 23

Signal Detect De-assertion 100BASE-TX mode 200 3604 -- mV

ID -jq
ou

peak-peak
NF jx

1. IEEE Standard 802.3-2008 Clause 14, Figure 14-9 shows the template for the “far-end” wave form. This template allows as little as
CO z1m

495 mV peak differential voltage at the far-end receiver.

2. The input test is actually a template test; IEEE Standard 802.3-2008 Clause 14, Figure 14-17 shows the template for the receive wave
LL 8vd

form.
3. The ANSI TP-PMD Specification requires that any received signal with peak-to-peak differential amplitude greater than 1000 mV should
VE jm

turn on signal detect (internal signal in 100BASE-TX mode). The device will accept signals typically with 460 mV peak-to-peak differential
amplitude.
AR b

4. The ANSI-PMD Specification requires that any received signal with peak-to-peak differential amplitude less than 200 mV should
M 9stk

de-assert signal detect (internal signal in 100BASE-TX mode). The device will reject signals typically with peak-to-peak differential
amplitude less than 360 mV.
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 57

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
4.3.4 SGMII
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
The SGMII specification is a de-facto standard proposed by Cisco. It uses a modified LVDS
specification based on the IEEE Standard 1596.3. For the exact definition of the terminology used in

9 0 tr
the following table, see the standard. The 88Q5050 device adds flexibility by allowing programmable

16 lec
output voltage swing and supply voltage option.

12 e E
Table 40: SGMII Output DC Characteristics

A# ing
(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

ND i H
S ym bo l P ar a m e te r 1 Min Ty p Max U ni t

a
VOH Output Voltage High -- -- 1600 mV

ER gh
VOL Output Voltage Low 700 -- -- mV

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
VRING Output Ringing -- -- 10 %

., L
, U Sh
2
|VOD| Output Voltage Swing (differential, peak) Programmable – see Table 41 mV

Co
AL *

peak
TI tlfs

y
VOffset Output Offset Voltage Variable – see Section 4.3.4.1 mV

g
(also called Common Mode Voltage)
EN 23

lo
no
ID -jq

RO Output Impedance (single-ended) 40 -- 60 

(50 termination)

ch
NF jx
CO z1m

Delta RO Mismatch in a pair -- -- 10 %

Te
Delta VOD Change in VOD between 0 and 1 -- -- 25 mV

ic
LL 8vd

35 on
Delta VOffset Change in VOffset between 0 and 1 -- -- 25 mV

90 tr
VE jm

IS+, IS- Output Current on Short to VSS -- -- 40 mA

16 lec
AR b

IS+- Output Current when TXP and TXN are -- -- 12 mA

M 9stk

12 e E
shorted
IX+, IX- Power-Off Leakage Current -- -- 10 A

A# ing
f5
z4

1. Parameters are measured with outputs AC connected with 100 differential load.
ND i H
2. Output amplitude is programmable by writing to SERDES register 26_1.2:0.
zs

a
60

ER gh

Table 41: Programmable SGMII Output Amplitude (SERDES Page 1 Register 26)
o

ND an
ih

, U Sh

B it s F ie l d D e s cr ip t i o n
2 vd

2:0 SGMII/Fiber Output Differential voltage peak measured.

AL *
4o

Amplitude1
TI tlfs

000: 14 mV
001: 112 mV
m
MARVELL CONFIDENTIAL

EN 23

010: 210 mV
011: 308 mV
ID -jq
ou

100: 406 mV
NF jx

101: 504 mV
CO z1m

110: 602 mV
111: 700 mV
LL 8vd

NOTE: Internal bias minus the differential peak voltage must be greater
than 700 mV.
VE jm

1. Cisco SGMII specification limits are |VOD| = 150 mV to 400 mV peak differential.
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 58 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
DC Electrical Characteristics

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 17: CML I/Os

ic
35 on
CML Outputs CML Inputs

9 0 tr
16 lec
Internal Bias1 Internal Bias1

12 e E
A# ing
50 ohm 50 ohm 50 ohm

ND i H
TXP

a
TXN RXP

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh

Co
AL *
TI tlfs

Internal Bias

y
Isink

g
EN 23

lo
no
ID -jq

50 ohm

ch
NF jx
CO z1m

Te
RXN

ic
LL 8vd

1. Internal bias is generated from the

35 on
AVDD supply and is typically 1.05V.

90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5

4.3.4.1 Common Mode Voltage (VOffset) Calculations

z4

ND i H
There are four different main configurations for the SGMII/fiber interface connections:
zs

a
 DC connection to an LVDS receiver
60

ER gh

 AC connection to an LVDS receiver

o

ND an
ih

 DC connection to an CML receiver

, U Sh
vd

 AC connection to an CML receiver

2

AL *

If AC coupling or DC coupling to an LVDS receiver is used, the DC output levels are determined by
4o

TI tlfs

the following:
m
MARVELL CONFIDENTIAL

 Internal bias. See Figure 17 for details. (If AVDD18 is used to generate the internal bias, the
EN 23

internal bias value will typically be 1.05V.)

ID -jq
ou

 The output voltage swing is programmed by register 26_1.2:0 (see Table 41).
NF jx

 VOffset = internal bias - single-ended peak-peak voltage swing. See Figure 18 for details.
CO z1m

If DC coupling is used with a CML receiver, the DC levels will be determined by a combination of the
MAC’s output structure and the input structure shown in the CML Inputs diagram in Figure 19.
LL 8vd

Assuming the same MAC CML voltage levels and structure, the common mode output levels will be
determined by:
VE jm

 VOffset = internal bias - single-ended peak-peak voltage swing/2. See Figure 19 for details.
AR b

If DC coupling is used, the output voltage DC levels are determined by the AC coupling
M 9stk


considerations above, plus the I/O buffer structure of the MAC.
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 59

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 18: AC Connections (CML or LVS Receiver) or DC Connection LVDS Receiver

ic
35 on
9 0 tr
CML Outputs

16 lec
Internal Bias1

12 e E
V = Internal Bias - Vpeak AC

A# ing
Coupling
50 ohm 50 ohm Cap.

ND i H
TXP V = VOffset

a
TXN

ER gh
(opposite
of TXP)

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh

Co
AL *
TI tlfs

I sink

yg
EN 23

lo
no
ID -jq

ch
NF jx
CO z1m

1. Internal bias is generated from the

Te
AVDD supply and is typically 1.05V.

ic
LL 8vd

35 on
90 tr
VE jm

Single-ended Voltage Details

16 lec
AR b
M 9stk

12 e E
(Internal Bias) - Vpeak

A# ing
f5
z4

Vpeak ND i H
zs

V = VOffset (i.e., common mode voltage) = (Internal Bias) - Vpeak-peak

a
TXP
60

ER gh
o

ND an
ih

, U Sh
2 vd

Vmin = (Internal Bias) - 3 × Vpeak

AL *
4o

TI tlfs

(Internal Bias) - Vpeak Vmin must be greater than 700 mV

m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m

TXN
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 60 Document Classification: Proprietary Information March 07, 2018

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
DC Electrical Characteristics

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 19: DC Connection to a CML Receiver

ic
35 on
CML Outputs CML Inputs

9 0 tr
16 lec
Internal Bias1
Internal Bias1

12 e E
V = Internal Bias
50 ohm

A# ing
50 ohm 50 ohm
TXP V = VOffset

ND i H
TXN RXP

a
ER gh
(opposite
of TXP) V = (Internal Bias) -

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Vpeak-peak

., L
, U Sh
Internal Bias

Co
AL *

I
TI tlfs

sink

y
50 ohm

g
EN 23

lo
no
ID -jq

RXN

ch
NF jx
CO z1m

Te
1. Internal bias is generated from the
AVDD supply and is typically 1.05V.

ic
LL 8vd

35 on
90 tr
VE jm

Single-ended Voltage Details

16 lec
AR b
M 9stk

12 e E
Internal
Bias

A# ing
f5
z4

Vpeak ND i H
zs

V = VOffset (i.e., common mode voltage) = (Internal Bias) - Vpeak

a
TXP
60

ER gh
o

ND an
ih

, U Sh
2 vd

Vmin = (Internal Bias) - Vpeak-peak (single ended)

AL *
4o

TI tlfs

Internal (Vmin must be greater than 700 mV)

m
MARVELL CONFIDENTIAL

Bias
EN 23
ID -jq
ou

NF jx
CO z1m

TXN
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 61

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Table 42: SGMII Input DC Characteristics

ic
(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

35 on
S ym bo l P ar a m e te r Min Ty p Max U ni t

9 0 tr
16 lec
VI Input Voltage Range a or b 675 -- 1725 mV

12 e E
VIDTH1 Input Differential Threshold -50 -- 50 mV
|RXP - RXN|

A# ing
VHYST2 Input Differential Hysteresis 25 -- -- mV

ND i H
RIN Receiver 100W Differential Input 80 -- 120 W
Impedance

a
ER gh
1. Receiver is at high level when VRXP - VRXN is greater than VIDTH and is at low level when VRXP - VRXN is less than

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
-VIDTH. A minimum hysteresis of VHYST is present between -VIDTH and +VIDTH as shown in Figure 20.

., L
, U Sh
2. A minimum hysteresis of VHYST is present between -VIDTH and +VIDTH as shown in Figure 20.

Co
AL *
TI tlfs

Figure 20: Input Differential Hysteresis

yg
EN 23

lo
Receiver High

no
ID -jq

ch
NF jx

-50 mV +50 mV
CO z1m

Te
ic
LL 8vd

VS_IN+ - VS_IN-

35 on
-VIDTH +VIDTH

90 tr
VE jm

16 lec
AR b

Receiver Low
M 9stk

12 e E
VHYST

A# ing
f5
z4

ND i H
4.3.5 Digital Pins
zs

a
60

ER gh

Table 43: DC Characteristics for Pins GPIO[4:0], INTn, MDC_CPU, MDC_PHY, MDIO_CPU, MDIO_
o

ND an
ih

PHY, RESETn, SPI_CS, SPI_SCLK, SPI_SIO[3:0], TCK, TDI, TDO, TEST, TMS, TRSTn
, U Sh
vd

(Sheet 1 of 2)
2

AL *

Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

4o

TI tlfs

1 • 1.8V Operation
VDDO Power Supply Voltage 1.71 1.8 1.89 V
m
MARVELL CONFIDENTIAL

EN 23

• 2.5V Operation 2.37 2.5 2.63 V

ID -jq
ou

• 3.3V Operation 3.14 3.3 3.46 V

NF jx

VIL Input Low Voltage -0.4 -- 0.3 × VDDO V

CO z1m

VIH Input High Voltage 0.7 × VDDO -- VDDO + 0.4 V

LL 8vd

VHYS Voltage Hysteresis 150 -- -- mV

VOL2 Output Low Voltage • 1.8V Operation 0 -- 0.2 V
VE jm

• 2.5V Operation 0 -- 0.4 V

AR b
M 9stk

• 3.3V Operation 0 -- 0.4 V

5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 62 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
DC Electrical Characteristics

ch
Te
Table 43: DC Characteristics for Pins GPIO[4:0], INTn, MDC_CPU, MDC_PHY, MDIO_CPU, MDIO_
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
PHY, RESETn, SPI_CS, SPI_SCLK, SPI_SIO[3:0], TCK, TDI, TDO, TEST, TMS, TRSTn

35 on
(Sheet 2 of 2)

9 0 tr
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

16 lec
2 • 1.8V Operation
VOH Output High Voltage VDDO - 0.2 -- VDDO V

12 e E
• 2.5V Operation VDDO - 0.4 -- VDDO V

A# ing
• 3.3V Operation VDDO - 0.4 -- VDDO V

ND i H
Pull-Up Strength (applicable VPAD = 0.5 × VDDO 10 -- 50 A
to pull-up pad only)

a
ER gh
Pull-Down Strength VPAD = 0.5 × VDDO 10 -- 50 A

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
(applicable to pull-down pad

., L
only)
, U Sh
Output Low Current1 • 1.8V Operation

Co
IOL 3 -- -- mA
AL *

@ 0.2V
TI tlfs

y
• 2.5V Operation 7 -- -- mA

g
EN 23

@ 0.4V

lo
no
ID -jq

• 3.3V Operation 7 -- -- mA
@ 0.4V

ch
NF jx

Output High Current1

CO z1m

IOH • 1.8V Operation 3 -- -- mA

Te
@ VDDO - 0.2V

ic
LL 8vd

• 2.5V Operation 7 -- -- mA

35 on
@ VDDO - 0.4V

90 tr
VE jm

• 3.3V Operation 7 -- -- mA

16 lec
@ VDDO - 0.4V
AR b
M 9stk

12 e E
CI Input Capacitance -- -- 5 pF
A

A# ing
IIN Input Leakage Current VDDO is ON, -- -- 2
f5

0V < VPAD < VDDO

z4

ND i H
zs

1. The characteristics for 2.5V and 1.8V only apply to MDC_CPU, MDC_PHY, MDIO_CPU, and MDIO_PHY. All other pins are always
a
supplied by 3.3V.
60

ER gh

2. The characteristics apply to GPIO[4:0], INTn, MDC_CPU, MDC_PHY, MDIO_CPU, MDIO_PHY, SPI_CS, SPI_SCLK, SPI_SIO[3:0], TDO.
o

ND an
ih

, U Sh
vd

Table 44: DC Characteristics for Pins P567_INCLK, P567_IND[3:0], P567_INDV, P8_INCLK, P8_
2

IND[3:0], P8_INDV
AL *
4o

TI tlfs

Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

m
MARVELL CONFIDENTIAL

EN 23

VDDO Power Supply Voltage • 1.8V Operation 1.71 1.8 1.89 V

ID -jq
ou

• 2.5V Operation 2.37 2.5 2.63 V

NF jx

• 3.3V Operation 3.14 3.3 3.46 V

CO z1m

VIL Input Low Voltage -0.4 -- 0.5 × VDDO V

-0.1
LL 8vd

VIH Input High Voltage 0.5 × VDDO -- VDDO + 0.4 V

VE jm

+ 0.1
AR b

VHYS Voltage Hysteresis 0 -- -- mV

M 9stk

CI Input Capacitance -- -- 5 pF
IIN Input Leakage Current VDDO is ON, -- -- 2 A
5
4f

0V < VPAD < VDDO

sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 63

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Table 45: DC Characteristics for Pins P567_OUTCLK, P567_OUTD[3:0], P567_OUTEN, P8_

ic
OUTCLK, P8_OUTD[3:0], P8_OUTEN (Sheet 1 of 2)

35 on
Symbol P a r a m e te r C o nd i tio n Min Ty p Max U ni t

9 0 tr
16 lec
VDDO Power Supply Voltage • 1.8V Operation 1.71 1.8 1.89 V

12 e E
• 2.5V Operation 2.37 2.5 2.63 V
• 3.3V Operation 3.14 3.3 3.46 V

A# ing
VIL Input Low Voltage • 1.8V Operation -0.4 -- 0.4 V

ND i H
• 2.5V Operation -0.4 -- 0.4 V

a
ER gh
• 3.3V Operation -0.4 -- 0.4 V

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
VIH Input High Voltage • 1.8V Operation 0.7 × VDDO -- VDDO + 0.4 V

., L
, U Sh
• 2.5V Operation 1.7 -- VDDO + 0.4 V

Co
• 3.3V Operation
AL *

2 -- VDDO + 0.4 V
TI tlfs

y
VHYS Voltage Hysteresis 150 -- -- mV

g
EN 23

lo
VOL Output Low Voltage • 1.8V Operation 0 -- 0.2 V

no
ID -jq

• 2.5V Operation 0 -- 0.4 V

ch
NF jx

• 3.3V Operation 0 -- 0.4 V

CO z1m

Te
VOH Output High Voltage • 1.8V Operation VDDO - 0.2 -- VDDO V

ic
LL 8vd

• 2.5V Operation VDDO - 0.4 -- VDDO V

35 on
• 3.3V Operation VDDO - 0.4 -- VDDO V

90 tr
VE jm

16 lec
Pull-Up Strength VPAD = 0.5 × VDDO 10 -- 50 A
AR b

(applicable to pull-up
M 9stk

12 e E
pad only)

A# ing
Pull-Down Strength VPAD = 0.5 × VDDO 10 -- 50 A
f5

(applicable to
z4

pull-down pad only)

ND i H
zs

a
CI Input Capacitance -- -- 5 pF
60

ER gh

IIN Input Leakage VDDO is ON, -- -- 2 A

o

ND an
ih

Current 0V < VPAD < VDDO

, U Sh
vd

IOL Output Low Current 1.8V Operation @ 0.4V,

2

ZP/ZN = 0000 -- -- -- mA
AL *
4o

TI tlfs

ZP/ZN = 0111 2 -- -- mA
m

ZP/ZN = 1111 6 -- -- mA
MARVELL CONFIDENTIAL

EN 23

2.5V Operation @0.4V,

ID -jq
ou

ZP/ZN = 0000 2 -- -- mA
ZP/ZN = 0111 6 -- -- mA
NF jx

ZP/ZN = 1111 9 -- -- mA
CO z1m

3.3V Operation @ 0.4V,

LL 8vd

ZP/ZN = 0000 2 -- -- mA
ZP/ZN = 0111 6 -- -- mA
VE jm

ZP/ZN = 1111 9 -- -- mA
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 64 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
DC Electrical Characteristics

ch
Te
Table 45: DC Characteristics for Pins P567_OUTCLK, P567_OUTD[3:0], P567_OUTEN, P8_
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
OUTCLK, P8_OUTD[3:0], P8_OUTEN (Sheet 2 of 2)

35 on
Symbol P a r a m e te r C o nd i tio n Min Ty p Max U ni t

9 0 tr
16 lec
IOH Output High Current 1.8V Operation @ VDDO - 0.4V,
ZP/ZN = 0000 -- -- -- mA

12 e E
ZP/ZN = 0111 2 -- -- mA
ZP/ZN = 1111 6 -- -- mA

A# ing
2.5V Operation @ VDDO - 0.4V,

ND i H
ZP/ZN = 0000 2 -- -- mA
ZP/ZN = 0111 6 -- -- mA

a
ER gh
ZP/ZN = 1111 9 -- -- mA

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
3.3V Operation @ VDDO - 0.4V,

., L
, U Sh ZP/ZN = 0000 2 -- -- mA
ZP/ZN = 0111 6 -- -- mA

Co
ZP/ZN = 1111 9 -- -- mA
AL *
TI tlfs

yg
EN 23

lo
no
ID -jq

Table 46: DC Characteristics for Pins C_LED[3:0]

ch
NF jx

Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

CO z1m

Te
VIL Input Low Voltage -0.4 -- 0.3 × VDDO V

ic
VIH Input High Voltage 0.7 × VDDO -- VDDO + 0.4 V
LL 8vd

35 on
VHYS Voltage Hysteresis 150 -- -- mV

90 tr
VE jm

16 lec
VOL Output Low Voltage 0 -- 0.4 V
AR b
M 9stk

VOH Output High Voltage VDDO - 0.4 -- VDDO V

12 e E
Pull-Up Strength (applicable VPAD = 0.5 × VDDO 10 -- 50 A

A# ing
f5

to pull-up pad only)

z4

CI Input Capacitance ND i H
-- -- 5 pF
zs

A
a
IIN Input Leakage Current VDDO is ON, -- -- 2
60

ER gh

0V < VPAD < VDDO

o

ND an

IOL Output Low Current @0.4V 71 -- -- mA

ih

, U Sh
vd

IOH Output High Current @VDDO - 0.4V 71 -- -- mA

2

AL *

1. Value per active LED

4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23

Table 47: DC Characteristics for Pins TRACECLK, TRACEDATA[3:0], TRACESWO

ID -jq
ou

Symbol P a r am et e r C on d it io n Min Ty p Max U ni t

NF jx

VDDO Power Supply Voltage 3.3V Operation 3.14 3.3 3.46 V

CO z1m

VIL Input Low Voltage 3.3V Operation -0.4 -- 0.4 V

LL 8vd

VIH Input High Voltage 3.3V Operation 2 -- VDDO + V

0.4
VE jm

VHYS Voltage Hysteresis 150 -- -- mV

AR b

VOL Output Low Voltage 3.3V Operation 0 -- 0.4 V

M 9stk

VOH Output High Voltage 3.3V Operation VDDO - 0.4 -- VDDO V

5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 65

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 47: DC Characteristics for Pins TRACECLK, TRACEDATA[3:0], TRACESWO
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
Symbol P a r am et e r C on d it io n Min Ty p Max U ni t

35 on
Pull-Up Strength VPAD = 0.5 × VDDO 10 -- 50 A

9 0 tr
16 lec
(applicable to pull-up
pad only)

12 e E
Pull-Down Strength VPAD = 0.5 × VDDO 10 -- 50 A
(applicable to pull-down

A# ing
pad only)

ND i H
CI Input Capacitance -- -- 5 pF

a
IIN Input Leakage Current VDDO is ON, -- -- 2 A

ER gh
0V < VPAD < VDDO

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
IOL Output Low Current 3.3V Operation @ 0.4V,

., L
, U Sh
ZP/ZN = 0000 1 -- -- mA

Co
ZP/ZN = 0111 5 -- -- mA
AL *

ZP/ZN = 1111 9 -- -- mA
TI tlfs

yg
IOH Output High Current 3.3V Operation @ VDDO - 0.4V,
EN 23

lo
ZP/ZN = 0000 1 -- -- mA

no
ID -jq

ZP/ZN = 0111 5 -- -- mA
ZP/ZN = 1111 9 -- -- mA

ch
NF jx
CO z1m

Te
Table 48: DC Characteristics for Pin R_LEDn[2:0]

ic
LL 8vd

35 on
Sy m b o l Parameter C o n di ti o n Min Ty pe Max Unit

90 tr
VE jm

VIL Input Low Voltage -0.4 -- 0.3 × VD V

16 lec
AR b

DO
M 9stk

12 e E
VIH Input High Voltage 0.7 × VDDO -- VDDO + V
0.4

A# ing
f5

VHYS Voltage Hysteresis 150 -- -- mV

z4

ND i H
VOL Output Low Voltage 0 -- 0.4 V
zs

a
60

ER gh

VOH Output High Voltage VDDO - 0.4 -- VDDO V

o

ND an

Pull-Up Strength VPAD = 0.5 × VDDO 10 -- 50 A

ih

(applicable to pull-up pad

, U Sh
vd

only)
2

AL *

CI Input Capacitance -- -- 5 pF
4o

TI tlfs

IIN Input Leakage Current VDDO is ON, -- -- 2 A

m
MARVELL CONFIDENTIAL

EN 23

0V < VPAD < VDDO

ID -jq
ou

IOL Output Low Current @0.4V 7 -- -- mA

NF jx

IOH Output High Current @VDDO - 0.4V 7 -- -- mA

CO z1m

Table 49: DC Characteristics for 5V Tolerant OC Pins TWSI_SCK, TWSI_SDA (Sheet 1 of 2)

LL 8vd

Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

VE jm

VIL Input Low Voltage -0.4 -- 0.7 V

AR b
M 9stk

VIH Input High Voltage 2.0 -- 5.5 V

VHYS Voltage Hysteresis 150 200 -- mV
5

VOL Output Low Voltage 0 -- 0.4 V

4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 66 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
Table 49: DC Characteristics for 5V Tolerant OC Pins TWSI_SCK, TWSI_SDA (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

35 on
IOL Output Low Current @ 0.4V 16 -- -- mA

9 0 tr
16 lec
CI Input Capacitance -- -- 5 pF

12 e E
IIN Input Leakage Current • VDDO is ON, -- -- 10 A
0V < VPAD <

A# ing
VDDO
• VDDO is OFF, A

ND i H
-- -- 10
0V < VPAD <

a
VDDO

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

4.3.6 ND an
Internal Resistors

., L
, U Sh

Co
Internal Resistors
AL *
TI tlfs

y
S ym bo l P ar a m e te r Min Ty p Max U ni t

g
EN 23

lo
RPull-Up Pull-Up Resistance 29.7 -- 181.5 k

no
ID -jq

RPull-Down Pull-Down Resistance 29.7 -- 181.5 k

ch
NF jx
CO z1m

Te
4.3.7 Low Power Signal Detect

ic
LL 8vd

35 on
Table 50: Low Power Signal Detect DC Characteristics
(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

90 tr
VE jm

16 lec
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t
AR b
M 9stk

12 e E
ISTANDBY Standby Current VBAT = 12V -- -- 50 A
IINH INH pin Source Current -- -- 50 A

A# ing
f5
z4

VINH INH pin Output High Voltage ND i H 1.4 -- 1.9 V

zs

a
60

ER gh
o

ND an
ih

4.4 AC Electrical Characteristics

, U Sh
2 vd

AL *

4.4.1 Main Clock

4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23

Table 51: Main Clock (XTAL_IN) AC Characteristics

(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)
ID -jq
ou

P ar a m e te r Min Ty p Max U ni t
NF jx
CO z1m

Clock Frequency 25 25 25 MHz

-100 +100
LL 8vd

ppm ppm
High Time 13 20 27 ns
VE jm

Low Time 13 20 27 ns
AR b
M 9stk

Rise Time (10% to 90%) -- -- 3 ns

Fall Time (90% to 10%) -- -- 3 ns
5

ps1
4f

Total Jitter -- -- 200

sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 67

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

1. Broadband peak-to-peak = 200 ps, Broadband rms = 3 ps, 12 kHz to 20 MHz rms = 1 ps.

ic
35 on
4.4.2 Power-On Reset

9 0 tr
16 lec
#

Table 52: Power-On Reset AC Characteristics

12 e E
(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

A# ing
S ym bo l P ar a m e te r Min Ty p Max U ni t

ND i H
TPU_RESET Valid power to RESETn de-asserted 10 -- -- ms

a
TSU_XTAL_IN Number of valid reference clock 10 -- -- clock

ER gh
cycles prior to RESETn de-asserted cycles

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
Figure 21: Power-On Reset Timing

Co
AL *
TI tlfs

T PU_RESET

yg
EN 23

lo
Power T SU_XTAL_IN

no
ID -jq

ch
NF jx
CO z1m

Te
XTAL

ic
LL 8vd

35 on
90 tr
VE jm

16 lec
RESETn
AR b
M 9stk

12 e E
4.4.3 100BASE-T1 Transceiver

A# ing
f5
z4

IEEE tests are typically based on templates and cannot simply be specified by a number. For an
ND i H
exact description of the template and the test conditions, see the IEEE Standard 802.3bw.
zs

a
#
60

ER gh

Table 53: 100BASE-T1 Transceiver AC Characteristics

o

(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)
ND an
ih

S ym bo l P ar a m e te r C o n d iti o n Min Ty p Max U ni t

, U Sh
vd

JTXOUT Transmit Jitter rms IEEE test mode 2 -- -- 50 ps

2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

4.4.4 100BASE-TX Transceiver

EN 23
ID -jq

Copied from FE PHY IP datasheet

ou

NF jx

IEEE tests are typically based on templates and cannot simply be specified by number. For an exact
CO z1m

description of the templates and the test conditions, see the following specifications:
 10BASE-T: IEEE Standard 802.3-2008 Clause 14
LL 8vd

 100BASE-TX: ANSI/INCITS X3.263-1995 Standard

#
VE jm

Table 54: 100BASE-TX Transceiver AC Characteristics (Sheet 1 of 2)

(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)
AR b
M 9stk

S ym bo l P ar a m e te r Min Ty p Max U ni t
TRISE Rise Time 3.0 4.0 5.0 ns
5
4f

TFALL Fall Time 3.0 4.0 5.0 ns

sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 68 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
Table 54: 100BASE-TX Transceiver AC Characteristics (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

35 on
S ym bo l P ar a m e te r Min Ty p Max U ni t

9 0 tr
16 lec
TRISE/TFALL Rise/Fall Time Symmetry 0 -- 0.5 ns
Symmetry

12 e E
DCD Duty Cycle Distortion 0 -- 0.51 ns,
peak-peak

A# ing
Transmit Jitter 0 -- 1.4 ns,

ND i H
peak-peak

a
ER gh
1. ANSI X3.263-1995 Standard, Figure 9-3

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
4.4.5 SGMII
, U Sh

Co
AL *

Table 55: SGMII Output AC Characteristics

TI tlfs

(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

yg
EN 23

S ym bo l P ar a m e te r Min Ty p Max U ni t

lo
no
ID -jq

TFALL VOD Fall Time (20% – 80%) 100 -- 200 ps

ch
NF jx

TRISE VOD Rise Time (20% – 80%) 100 -- 200 ps

CO z1m

Te
1
TSKEW1 Skew between two members of a -- -- 20 ps
differential pair

ic
LL 8vd

35 on
TOutputJitter Total Output Jitter Tolerance -- 127 -- ps
(Deterministic + 14 × rms Random)

90 tr
VE jm

16 lec
AR b

1. Skew measured at 50% of the transition.

M 9stk

12 e E
Figure 22: Serial Interface Rise and Fall Times

A# ing
f5
z4

ND i H
zs

a
60

ER gh

T X P /N
o

ND an

T R IS E T FALL
ih

, U Sh
vd

TT X P / N
2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23

Table 56: SGMII Input AC Characteristics

ID -jq
ou

(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)
NF jx

S ym bo l P ar a m e te r Min Ty p Max U ni t
CO z1m

TInputJitter Total Input Jitter Tolerance -- -- 599 ps

(Deterministic + 14 × rms Random)
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 69

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
4.4.6 MII
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
4.4.6.1 PHY Mode

9 0 tr
16 lec
In PHY mode, the
P[x]_INCLK pins are outputs

12 e E

 P[x]_OUTCLK pins are outputs

A# ing
Table 57: MII PHY Mode Input AC Characteristics Timing

ND i H
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

a
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

ER gh
TP_TX_CLK1 P[x]_INCLK Period • 10BASE mode -- 400 -- ns

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh • 100BASE mode -- 40 -- ns
TH_TX_CLK P[x]_INCLK High • 10BASE mode 160 200 240 ns

Co
AL *

• 100BASE mode
TI tlfs

16 20 24 ns

yg
TL_TX_CLK P[x]_INCLK Low • 10BASE mode 160 200 240 ns
EN 23

lo
• 100BASE mode 16 20 24 ns

no
ID -jq

TSU_TX MII Inputs (P[x]_IND[3:0], 15 -- -- ns

ch
NF jx

P[x]_INDV) valid prior to P[x]_INCLK

CO z1m

Te
going high

ic
THD_TX MII Inputs (P[x]_IND[3:0], 0 -- -- ns
LL 8vd

35 on
P[x]_INDV) valid after P[x]_INCLK

90 tr
going high
VE jm

16 lec
AR b

1. 2.5 MHz for 10 Mbps or 25 MHz for 100 Mbps.

M 9stk

12 e E
A# ing
Figure 23: MII PHY Mode Input Timing
f5
z4

ND i H
zs

TH _ T X _ C L K
a
60

ER gh
o

T
ND an

IN C L K L_TX _C LK
ih

, U Sh
2 vd

T P_ TX _C LK
AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23

IN P U T S
ID -jq
ou

NF jx

T H D _TX
CO z1m

T SU _TX
LL 8vd
VE jm

NOTE: IN C L K is th e c lo c k u s e d to c lo c k th e in p u t d a ta .
It is a n o u tp u t in th is m o d e .
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 70 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Table 58: MII PHY Mode Output AC Characteristics

ic
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

35 on
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

9 0 tr
16 lec
TP_RX_CLK1 P[x]_OUTCLK Period • 10BASE mode -- 400 -- ns

12 e E
• 100BASE mode -- 40 -- ns
TH_RX_CLK P[x]_OUTCLK High • 10BASE mode 160 200 240 ns

A# ing
• 100BASE mode 16 20 24 ns

ND i H
TL_RX_CLK P[x]_OUTCLK Low • 10BASE mode 160 200 240 ns

a
ER gh
• 100BASE mode 16 20 24 ns

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
TCQ_MAX P[x]_OUTCLK to outputs -- -- 25 ns

., L
(P[x]_OUTD[3:0], P[x]_OUTEN) valid
, U Sh

Co
TCQ_MIN P[x]_OUTCLK to outputs 10 -- -- ns
AL *

(P[x]_OUTD[3:0], P[x]_OUTEN)
TI tlfs

y
invalid

g
EN 23

lo
1. 2.5 MHz for 10 Mbps or 25 MHz for 100 Mbps.

no
ID -jq

ch
NF jx

Figure 24: MII PHY Mode Output Timing

CO z1m

Te
ic
TH _ R X _ C L K
LL 8vd

35 on
90 tr
VE jm

16 lec
O U TC LK L _R X_C LK
AR b
M 9stk

12 e E
T P _R X_C LK

A# ing
f5
z4

ND i H
zs

a
OUTPUTS
60

ER gh
o

ND an

T CQ_M AX T C Q _ M IN
ih

, U Sh
2 vd

O U T C L K is th e c lo c k u s e d to c lo c k th e o u tp u t d a ta .
AL *

NO TE:
4o

TI tlfs

It is a n o u tp u t in th is m o d e .
m
MARVELL CONFIDENTIAL

EN 23

4.4.6.2 MAC Mode

ID -jq
ou

NF jx

In MAC mode, the

CO z1m

 P[x]_INCLK pins are inputs

 P[x]_OUTCLK pins are inputs
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 71

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Table 59: MII MAC Mode Input AC Characteristics

ic
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

35 on
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

9 0 tr
16 lec
TSU_RX MII inputs (P[x]_IND[3:0], P[x]_INDV) With 10 pF load 10 -- -- ns
valid prior to P[x]_INCLK going high

12 e E
THD_RX MII inputs (P[x]_IND[3:0], P[x]_INDV) With 10 pF load 10 -- -- ns

A# ing
valid after P[x]_INCLK going high

ND i H
a
Figure 25: MII MAC Mode Input Timing

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh

Co
AL *

IN C L K
TI tlfs

yg
EN 23

lo
no
ID -jq

T H D _R X

ch
NF jx
CO z1m

Te
IN P U T S

ic
LL 8vd

35 on
T SU _R X

90 tr
VE jm

16 lec
AR b

NOTE: IN C L K is th e c lo c k u s e d to c lo c k th e in p u t d a ta .
M 9stk

12 e E
It is a n in p u t in th is m o d e .

A# ing
f5

Table 60: MII MAC Mode Output AC Characteristics

z4

ND i H
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
zs

a
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t
60

ER gh
o

TCQ_MAX P[x]_OUTCLK to outputs With 10 pF load -- -- 25 ns

ND an
ih

(P[x]_OUTD[3:0], P[x]_OUTEN) valid

, U Sh
vd

TCQ_MIN P[x]_OUTCLK to outputs With 10 pF load 0 -- -- ns

2

AL *

(P[x]_OUTD[3:0], P[x]_OUTEN)
4o

TI tlfs

invalid
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 72 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 26: MII MAC Mode Output Timing

ic
35 on
9 0 tr
16 lec
12 e E
O U TC LK

A# ing
ND i H
a
ER gh
OUTPUTS

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
T CQ_M AX T C Q _ M IN

Co
AL *
TI tlfs

y
NOTE: O U T C L K is th e c lo c k u s e d to c lo c k th e o u tp u t d a ta .

g
EN 23

lo
It is a n in p u t in th is m o d e .

no
ID -jq

ch
NF jx

4.4.7 RMII
CO z1m

Te
Table 61: RMII Input AC Characteristics, Using OUTCLK

ic
LL 8vd

35 on
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

90 tr
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t
VE jm

16 lec
period1
AR b

TP_TX_CLK P[x]_OUTCLK 100BASE mode -- 20 -- ns

M 9stk

12 e E
TH_TX_CLK P[x]_OUTCLK High 100BASE mode 8 10 12 ns

A# ing
TL_TX_CLK P[x]_OUTCLK Low 100BASE mode 8 10 12 ns
f5
z4

TSU_TX RMII inputs (P[x]_IND[1:0], P[x]_INDV) ND i H 4 -- -- ns

valid prior to P[x]_OUTCLK going high
zs

a
60

ER gh

THD_TX RMII inputs (P[x]_IND[1:0], P[x]_INDV) 2 -- -- ns

valid after P[x]_OUTCLK going high
o

ND an
ih

1. 50 MHz for 100 Mbps.

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 73

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 27: RMII Input Timing, Using OUTCLK

ic
35 on
TH _ T X _ C L K

9 0 tr
16 lec
12 e E
O U TC LK
T L_TX_C LK

A# ing
T P_ TX _C LK

ND i H
a
ER gh
IN P U T S

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
T H D _TX

Co
AL *

T SU _TX
TI tlfs

yg
EN 23

lo
NOTE: O U T C L K is th e c lo c k u s e d to c lo c k th e in p u t d a ta .

no
ID -jq

It is a n o u tp u t in th is m o d e .

ch
NF jx
CO z1m

Te
Table 62: RMII Output AC Characteristics, Using OUTCLK

ic
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
LL 8vd

35 on
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

90 tr
VE jm

TP_RX_CLK1 P[x]_OUTCLK Period 100BASE mode -- 20 -- ns

16 lec
AR b

TH_RX_CLK P[x]_OUTCLK High 100BASE mode 8 10 12 ns

M 9stk

12 e E
TL_RX_CLK P[x]_OUTCLK Low 100BASE mode 8 10 12 ns

A# ing
f5

TCQ_MAX P[x]_OUTCLK to outputs -- -- 16 ns

z4

(P[x]_OUTD[1:0], P[x]_OUTEN) valid ND i H

zs

TCQ_MIN P[x]_OUTCLK to outputs 2 -- -- ns

a
60

ER gh

(P[x]_OUTD[1:0], P[x]_OUTEN)
invalid
o

ND an
ih

1. 50 MHz for 100 Mbps.

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 74 Document Classification: Proprietary Information March 07, 2018

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 28: RMII Output Timing, Using OUTCLK

ic
35 on
TH _ R X _ C L K

9 0 tr
16 lec
T

12 e E
O U TCLK L_R X_C LK

A# ing
T P_R X_C LK

ND i H
a
ER gh
OUTPUTS

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
T CQ_M AX T C Q _ M IN

Co
AL *
TI tlfs

y
NOTE: O U T C L K is th e c lo c k u s e d to c lo c k th e o u tp u t d a ta .

g
EN 23

lo
It is a n o u tp u t in th is m o d e .

no
ID -jq

ch
NF jx

4.4.8 RGMII
CO z1m

Te
Table 63: RGMII AC Characteristics

ic
LL 8vd

(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

35 on
Also see Section 4.4.8.1, Output Timing With/Without Delay Control and Section 4.4.8.2, Input Timing

90 tr
VE jm

With/Without Delay Control.

16 lec
AR b

S ym bo l P ar a m e te r Min Ty p Max U ni t
M 9stk

12 e E
TskewT Data to Clock output Skew, at -500 0 500 ps

A# ing
Transmitter
f5
z4

TskewR Data to Clock input Skew, at Receiver ND i H 1.0 -- 2.6 ns

zs

TCYCLE Clock Cycle Duration 7.2 8.0 8.8 ns

a
60

ER gh

1
TCYCLE_ High Time for 1000BASE-T 3.6 4.0 4.4 ns
o

ND an

HIGH1000
ih

, U Sh

TRISE/TFALL Rise/Fall Time (20% – 80%) -- -- 0.75 ns

2 vd

1. Duty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet’s clock
AL *
4o

domain as long as minimum duty cycle is not violated and stretching occurs for no more than three TCYCLE of the
TI tlfs

lowest speed transitioned between.

m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 75

2 vd
4o
m
 ou
MARVELL CONFIDENTIAL
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
m
4o
2vd
ih
o60
zs

Page 76
z4
f5
M 9stk
AR b
VE jm
LL 8vd

Doc. No. MV-S111158-00 Rev. –

CO z1m
m NF jx
4o ID -jq
2
88Q5050
Datasheet

vd EN 23
ih

at Transmitter
at Transmitter

RX_CLK (RXC)
OUTCLK (TXC)
OUTCLK (TXC)

at Receiver
INCLK (RXC)
INDV (RX_CTL)
at Receiver
OUTEN (TX_CTL)

IND[7:4][3:0]
OUTD[7:4][3:0]

o6 TI tlfs
AL *
0z , U Sh
sz ND an
4f
5 ER gh
M 9stk a
AR b ND i H

INDV
OUTEN

IND[3:0]
VE jm A# ing
OUTD[3:0]

LL 8vd 12 e E

CONFIDENTIAL
CO z1m 16 lec
Figure 29: RGMII Multiplexing and Timing

9 0 tr
NF jx 35 on
ID -jq IND[7:4]
ic
EN 23 Te
OUTD[7:4]

Document Classification: Proprietary Information

TI tlfs ch
AL * no
, U Sh lo
ND an gy
Co
TskewT
TskewT

ER gh
a
ND i H
A# ing
12 e E
16 lec
90 tr
35 on
TskewR
TskewR

ic
Te

Copyright © 2018 Marvell

March 07, 2018
ch
no
lo
g y
Co
., L
ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technologyt Co., Ltd. * UNDER NDA# 121690
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
4.4.8.1 Output Timing With/Without Delay Control
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 64: Output (OUTCLK (TXC)) Timing when RGMII Tx Delay Control (Offset
0x01, Bit 14) = 0

9 0 tr
16 lec
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

12 e E
S ym bo l P ar a m e te r Min Ty p Max U ni t
Tskew RGMII Tx Delay Control (bit 14) = 0 -0.5 -- 0.5 ns

A# ing
ND i H
Figure 30: Output (OUTCLK (TXC)) Timing when RGMII Tx Delay Control (Bit 14) = 0

a
ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
O U T C L K (T X C )

., L
, U Sh

Co
AL *
TI tlfs

O U T D [3 : 0 ] ( T X D [3 : 0 ]) ,

y
O U T E N (T X _ C T L )

g
EN 23

lo
no
ID -jq

T skew T skew

ch
NF jx
CO z1m

Te
T skew T skew

ic
LL 8vd

35 on
Table 65: Output (OUTCLK (TXC)) Timing when RGMII Tx Delay Control (Offset

90 tr
VE jm

16 lec
0x01, Bit 14) = 1
AR b

(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
M 9stk

12 e E
S ym bo l P ar a m e te r Min Ty p Max U ni t

A# ing
f5

Tsetup RGMII Tx Delay Control (bit 14) = 1 1.2 -- -- ns

z4

Thold ND i H 1.0 -- -- ns
zs

a
60

ER gh

Figure 31: Output (OUTCLK (TXC)) Timing when RGMII Tx Delay Control (Bit 14) = 1
o

ND an
ih

, U Sh
vd

O U T C L K (T X C )
2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23

O U T D [3 :0 ] ( T X D [3 :0 ]) ,
ID -jq

O U T E N (T X _ C T L )
ou

NF jx
CO z1m

T h o ld T h o ld
LL 8vd

T s e tu p T s e tu p
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 77

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
4.4.8.2 Input Timing With/Without Delay Control
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 66: Input (INCLK (RXC)) Timing when RGMII Rx Delay Control (Offset 0x01,
Bit 15) = 0

9 0 tr
16 lec
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

12 e E
S ym bo l P ar a m e te r Min Ty p Max U ni t
Tsetup RGMII Rx Delay Control (bit 15) = 0 1.0 -- -- ns

A# ing
Thold 0.8 -- -- ns

ND i H
a
Figure 32: Input (INCLK (RXC)) Timing when RGMII Rx Delay Control (Bit 15) = 0

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
IN C L K ( R X C )

Co
AL *
TI tlfs

yg
IN D [ 3 : 0 ] ( R X D [3 : 0 ]) ,
EN 23

lo
IN D V (R X _ C T L )

no
ID -jq

ch
NF jx

T h o ld T h o ld
CO z1m

Te
T s e tu p T s e tu p

ic
LL 8vd

35 on
90 tr
VE jm

16 lec
Table 67: Input (INCLK (RXC)) Timing when RGMII Rx Delay Control (Offset 0x01,
AR b

Bit 15) = 1
M 9stk

12 e E
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

A# ing
f5

S ym bo l P ar a m e te r Min Ty p Max U ni t
z4

tsetup RGMII Rx Delay Control (bit 15) = 1 ND i H -0.9 -- -- ns

zs

a
thold 2.7 -- -- ns
60

ER gh
o

ND an
ih

Figure 33: Input (INCLK (RXC)) Timing when RGMII Rx Delay Control (Bit 15) = 1
, U Sh
2 vd

AL *
4o

IN C L K ( R X C )
TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

IN D [3 :0 ] ( R X D [3 :0 ]),
NF jx

IN D V (R X _ C T L )
CO z1m

T s e tu p T s e tu p
LL 8vd

T h o ld T
VE jm

h o ld
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 78 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
4.4.9 GMII
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 68: GMII Input AC Characteristics

9 0 tr
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

16 lec
S ym bo l P ar a m e te r Min Ty p Max U ni t

12 e E
TSU_GMII_INCLK GMII Setup Time 2.0 -- -- ns

A# ing
THD_GMII_INCLK GMII Hold Time 0 -- -- ns
1
TH_GMII_INCLK INCLK High 2.5 -- -- ns

ND i H
1
TL_GMII_INCLK INCLK Low 2.5 -- -- ns

a
ER gh
TP_GMII_INCLK INCLK Period 7.51 8.0 8.5 ns

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
1
FGMII_INCLK INCLK Frequency 125 - 100 ppm -- 125 + 100 ppm MHz

., L
, U Sh
TR_GMII_INCLK INCLK Rise Time -- -- 1.0 ns

Co
AL *

TF_GMII_INCLK INCLK Fall Time -- -- 1.0 ns

TI tlfs

yg
1. RX_CLK toggle rate is “don’t care” if link is down, or if not in 1000BASE-T mode.
EN 23

lo
no
ID -jq

Figure 34: GMII Input Timing

ch
NF jx
CO z1m

Te
TP_GMII_INCLK

ic
LL 8vd

TL_GMII_INCLK

35 on
TH_GMII_INCLK

90 tr
VE jm

16 lec
VIH_GMII (Min.)
AR b

INCLK
M 9stk

12 e E
VIL_GMII (Max.)
TF_GMII_INCLK TR_GMII_INCLK

A# ing
f5

VIH_GMII (Min.)
z4

IND[7:0]
ND i H
zs

INDV
a
VIL_GMII (Max.)
60

ER gh

THD_GMII_INCLK
o

ND an
ih

TSU_GMII_INCLK
, U Sh
2 vd

AL *
4o

TI tlfs

Table 69: GMII Output AC Characteristics (Sheet 1 of 2)

m
MARVELL CONFIDENTIAL

EN 23

(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
ID -jq

S ym bo l P ar a m e te r Min Ty p Max U ni t
ou

NF jx

TSU_GMII_GTX_CLK GMII Output to Clock 2.5 -- -- ns

CO z1m

THD_GMII_GTX_CLK GMII Clock to Output 0.5 -- -- ns

1
TH_GMII_GTX_CLK GTX_CLK High 2.5 -- 5.5 ns
LL 8vd

TL_GMII_GTX_CLK GTX_CLK Low 2.51 -- 5.5 ns

VE jm

TP_GMII_GTX_CLK GTX_CLK Period 7.51 8.0 -- ns

AR b
M 9stk

TR_GMII_GTX_CLK GTX_CLK Rise Time -- -- 1.0 ns

TF_GMII_GTX_CLK GTX_CLK Fall Time -- -- 1.0 ns
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 79

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 69: GMII Output AC Characteristics (Sheet 2 of 2)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

35 on
S ym bo l P ar a m e te r Min Ty p Max U ni t

9 0 tr
2

16 lec
TRSLEW_GMII_GTX_ GTX_CLK Rising Slew Rate 0.6 -- -- V/ns
CLK

12 e E
TFSLEW_ GMII_GTX_ GTX_CLK Falling Slew Rate 0.62 -- -- V/ns

A# ing
CLK

1. GTX CLK numbers not guaranteed during transition between 10/100/1000BASE-T operation.

ND i H
2. Instantaneous change during internal VIH_GMII (Min.) and VIL_GMII (Max.).

a
ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Figure 35: GMII Output Timing

., L
, U Sh
TP_GMII_GTX_CLK

Co
AL *
TI tlfs

y
TH_GMII_GTX_CLKTL_GMII_GTX_CLK

g
EN 23

lo
no
VOH_GMII (Min.)
ID -jq

GTX_CLK

ch
NF jx

VOL_GMII (Max.)
CO z1m

Te
TF_GMII_GTX_CLK TR_GMII_GTX_CLK

ic
VOH_GMII (Min.)
LL 8vd

35 on
OUTD[7:0]
OUTEN

90 tr
VOL_GMII (Max.)
VE jm

16 lec
THD_GMII_GTX_CLK
AR b
M 9stk

12 e E
TSU_GMII_GTX_CLK

A# ing
f5
z4

ND i H
4.4.10 SMI
zs

a
60

ER gh

4.4.10.1 SMI Clock – CPU Set (Slave)

o

ND an
ih

, U Sh

Table 70: SMI Clock AC Characteristics – CPU Set

vd

(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)
2

AL *
4o

TI tlfs

S ym bo l P ar a m e te r Min Ty p Max U ni t
m
MARVELL CONFIDENTIAL

TP MDC Period 50 -- -- ns
EN 23

(max. 20 MHz)
ID -jq
ou

TH MDC High Time 13 -- -- ns

NF jx

TL MDC Low Time 13 -- -- ns

CO z1m

TR MDC Rise Time -- -- 6 ns

LL 8vd

TF MDC Fall Time -- -- 6 ns

VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 80 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 36: SMI Clock Timing – CPU Set

ic
35 on
TP

9 0 tr
16 lec
TH TL

12 e E
A# ing
M D C

ND i H
a
TR TF

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
4.4.10.2 SMI Data – CPU Set (Slave)

Co
AL *

Table 71: SMI Data AC Characteristics – CPU Set

TI tlfs

y
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

g
EN 23

lo
S ym bo l P ar a m e te r Min Ty p Max U ni t

no
ID -jq

TDLY_MDIO MDC to MDIO (Output) Delay Time 0 -- 30 ns

ch
NF jx

TSU MDIO (Input) to MDC Setup Time 10 -- -- ns

CO z1m

Te
THD MDIO (Input) to MDC Hold Time 10 -- -- ns

ic
LL 8vd

35 on
Figure 37: SMI Data Timing – CPU Set

90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
M DC

A# ing
f5
z4

ND i H
zs

a
60

ER gh

M DIO (O utput)
o

ND an
ih

, U Sh
vd

T D LY _M D IO
2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

M DC
EN 23
ID -jq
ou

T HD
NF jx

T SU
CO z1m

M DIO (Input)
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 81

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
4.4.10.3 SMI – PHY Set (Master)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 72: SMI AC Characteristics – PHY Set

9 0 tr
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

16 lec
S ym bo l P ar a m e te r Min Ty p Max U ni t

12 e E
TP MDC Period 64 128 256 ns
(min. 3.90625 MHz, typ. 7.8125 MHz,

A# ing
max. 15.625 MHz)

ND i H
TH MDC High Time 20 -- -- ns

a
TL MDC Low Time 20 -- -- ns

ER gh
TR MDC Rise Time -- -- 6 ns

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
TF , U Sh MDC Fall Time -- -- 6 ns
TTX_SU MDIO Output Setup Time1 10 -- -- ns

Co
AL *

1
TTX_HD MDIO Output Hold Time 10 -- -- ns
TI tlfs

yg
TRX_SU MDIO Input Setup Time -- -- -- --
EN 23

lo
TRX_HD MDIO Input Hold Time -- -- -- --

no
ID -jq

2
TDLY_MDIO MDC to MDIO (Output) Delay Time 0 5 ns

ch
NF jx
CO z1m

Te
1. MDIO input setup and hold time is intentionally sampled with respect to the MDC falling edge.
2. MDIO data is intentionally clocked out on the falling edge of MDC.

ic
LL 8vd

35 on
Figure 38: SMI Output Timing – PHY Set

90 tr
VE jm

16 lec
AR b

TP
M 9stk

12 e E
TH TL

A# ing
f5
z4

ND i H
zs

MDC
a
60

ER gh
o

ND an

TR TF
ih

, U Sh
vd

TTX_HD
2

TTX_SU
AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23

MDIO (Output)
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 82 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 39: SMI Input Timing – PHY Set

ic
35 on
9 0 tr
16 lec
MDC

12 e E
A# ing
TRX_HD
TRX_SU

ND i H
a
MDIO (Input)

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh

Co
4.4.11 QSPI
AL *
TI tlfs

y
Table 73: QSPI AC Characteristics

g
EN 23

lo
(Over full range of values listed in the Recommended Operating Conditions unless otherwise

no
ID -jq

specified)

ch
NF jx

S ym bo l P ar a m e te r Min Ty p Max U ni t
CO z1m

Te
fQSPI Clock Frequency 19.23 -- 83.33 MHz

ic
D Duty Cycle -- 50 -- %
LL 8vd

35 on
90 tr
VE jm

4.4.12 TWSI

16 lec
AR b
M 9stk

12 e E
Table 74: TWSI AC Characteristics
(Over full range of values listed in the Recommended Operating Conditions unless otherwise

A# ing
f5

specified)
z4

S ym bo l P ar a m e te r
ND i H Min Ty p Max U ni t
zs

a
fSCK SCK Clock Frequency 0 -- 400 kHz
60

ER gh

THD;STA Start condition Hold Time 600 -- -- ns

o

ND an
ih

TLow Clock Low Period 1300 -- -- ns

, U Sh
vd

THigh Clock High Period 600 -- -- ns

2

AL *
4o

TSU;STA Setup Time for a repeated Start condition 600 -- -- ns

TI tlfs
m
MARVELL CONFIDENTIAL

THD;DAT Data Hold Time 01 -- -- ns

EN 23

TSU;DAT Data Setup Time 100 -- -- ns

ID -jq
ou

TR SDA/SCK Rise Time -- -- 300 ns

NF jx
CO z1m

TF SDA/SCK Fall Time1 -- -- 300 ns

TSU;STO Stop condition Setup Time 600 -- -- ns
LL 8vd

TBUF Bus Free Time 1300 -- -- ns

VE jm

1. A device must internally provide a hold time of at least 300 ns for the SDA signal (with respect to the VIH(min) of the
SCK signal) to bridge the undefined region of the falling edge of SCK.
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 83

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Figure 40: TWSI Timing

ic
35 on
TF THigh TR

9 0 tr
16 lec
TLow
SCK

12 e E
THD;DAT
TSU;STA TSU;DAT TSU;STO

A# ing
THD;STA

ND i H
SDA
TBUF

a
ER gh
TF
TR

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
4.4.13 EEPROM Interface

Co
AL *
TI tlfs

y
Table 75: EEPROM AC Characteristics

g
EN 23

lo
(Over full range of values listed in the Recommended Operating Conditions unless otherwise specified)

no
ID -jq

S ym bo l P ar a m e te r Min Ty p Max U ni t

ch
NF jx

TP EE_CLK Frequency -- 200 -- kHz

CO z1m

Te
TH EE_CLK High Time -- 2500 -- ns

ic
TL EE_CLK Low Time -- 2500 -- ns
LL 8vd

35 on
TIN EE_CLK Input Time 50 -- 1250 ns

90 tr
VE jm

16 lec
TOUT EE_CLK Output Time 0 -- 2500 ns
AR b
M 9stk

12 e E
Figure 41: EEPROM Interface Timing

A# ing
f5
z4

ND i H
zs

EE_CLK
a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs

EE_DIO
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

TIN/OUT
NF jx
CO z1m

TL TH
TP
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 84 Document Classification: Proprietary Information March 07, 2018

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Electrical Specifications

no
AC Electrical Characteristics

ch
Te
4.4.14 JTAG Interface
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Table 76: JTAG AC Characteristics

9 0 tr
(Over full range of values listed in the Recommended Operating Conditions unless otherwise

16 lec
specified)

12 e E
P ar a m e te r Min Ty p Max U ni t
Clock Frequency -- 25 -- MHz

A# ing
ND i H
4.4.15 Low Power Signal Detect

a
ER gh
Table 77: Low Power Signal Detect AC Characteristics

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
(Over full range of values listed in the Recommended Operating Conditions, unless otherwise specified)

., L
, U Sh
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

Co
AL *

TMDI, LAT Latency from MDI signals to INH assertion Normal link -- -- 2 s
TI tlfs

y
1
TWAKE, PW WAKE_IN pin Pulse Width to Wake-Up LPSD 10 -- 50 s

g
EN 23

lo
1. Default value.

no
ID -jq

ch
NF jx
CO z1m

Te
ic
LL 8vd

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 85

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Package Specifications

9 0 tr
16 lec
12 e E
5.1 Thermal Information

A# ing
Table 78: 128-Pin LQFP Package Thermal Information

ND i H
Sy m b o l Parameter C o n d iti o n Min Ty p Max U ni t

a
ER gh
JA Junction-to-Ambient Thermal JEDEC 3 in. × 4.5 in. 4-layer -- 17.7 -- °C/W
Resistance PCB with no air flow

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
JEDEC 3 in. × 4.5 in. 4-layer -- 15.9 -- °C/W
, U Sh
JA = (TJ - TA) / P
PCB with 1 m/sec air flow

Co
P = Total Power Dissipation
AL *

JEDEC 3 in. × 4.5 in. 4-layer -- 15 -- °C/W

TI tlfs

y
PCB with 2 m/sec air flow

g
EN 23

lo
JEDEC 3 in. × 4.5 in. 4-layer -- 14.3 -- °C/W

no
PCB with 3 m/sec air flow
ID -jq

JB

ch
Junction-to-Board Thermal JEDEC with no air flow -- 8.1 -- °C/W
NF jx

Resistance
CO z1m

Te
JB = (TJ - TB) / PBOTTOM

ic
LL 8vd

35 on
PBOTTOM = Power dissipation
from the bottom of the package

90 tr
VE jm

to the PCB surface

16 lec
AR b

JC Junction-to-Case Thermal JEDEC with no air flow -- 7.60 -- °C/W

M 9stk

12 e E
Resistance

A# ing
f5

JC = (TJ - TC) / PTOP

z4

PTOP = Power dissipation from ND i H

zs

the top of the package

a
60

ER gh

JB Junction-to-Board Thermal JEDEC 3 in. × 4.5 in. 4-layer -- 7.60 -- °C/W
Characteristics Parameter PCB with no air flow
o

ND an
ih

JEDEC 3 in. × 4.5 in. 4-layer -- 7.8 -- °C/W

, U Sh

JB = (TJ - TBOTTOM) / P

vd

PCB with 1 m/sec air flow

TBOTTOM = Temperature on the
2

AL *

JEDEC 3 in. × 4.5 in. 4-layer -- 7.9 -- °C/W

4o

bottom of the package

TI tlfs

PCB with 2 m/sec air flow

m
MARVELL CONFIDENTIAL

EN 23

JEDEC 3 in. × 4.5 in. 4-layer -- 7.8 -- °C/W

PCB with 3 m/sec air flow
ID -jq
ou

JT Junction-to-Top-Center JEDEC 3 in. × 4.5 in. 4-layer -- 0.36 -- °C/W

NF jx

Thermal Characterization PCB with no air flow

CO z1m

Parameter
JEDEC 3 in. × 4.5 in. 4-layer -- 0.57 -- °C/W
LL 8vd

PCB with 1 m/sec air flow

JT = (TJ - TTOP) / P
TTOP = Temperature on the top JEDEC 3 in. × 4.5 in. 4-layer -- 0.76 -- °C/W
VE jm

center of the package PCB with 2 m/sec air flow

AR b

JEDEC 3 in. × 4.5 in. 4-layer -- 0.89 -- °C/W

M 9stk

PCB with 3 m/sec air flow

5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 86 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 ou
MARVELL CONFIDENTIAL
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
m
4o
2vd
ih
o60
zs
z4
f5 5.2

March 07, 2018

M 9stk
AR b
VE jm

Copyright © 2018 Marvell

LL 8vd
CO z1m
m NF jx

E−PAD
4o ID -jq
2vd EN 23
ih TI tlfs
o6 AL *
0z , U Sh
sz ND an
4f
5
Figure 42: 128-Pin LQFP Package Drawing

ER gh
M 9stk a
AR b ND i H
Mechanical Drawing

VE jm A# ing
LL 8vd 12 e E

CONFIDENTIAL
CO z1m 16 lec
9 0 tr
NF jx 35 on
ID -jq ic
EN 23 Te

Document Classification: Proprietary Information

TI tlfs ch
AL * no
, U Sh lo
gy

Table 79 lists the dimensions of the 88Q5050 128-pin LQFP package.

ND an
ER gh Co
a
ND i H
A# ing
Figure 42 shows the mechanical drawing of the 88Q5050 128-pin LQFP package.

12 e E
16 lec
90 tr
35 on
ic
Te
Package Specifications

Doc. No. MV-S111158-00 Rev. –

Mechanical Drawing

Page 87
ch
no
lo
gy
Co
., L
ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technologyt Co., Ltd. * UNDER NDA# 121690
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

Table 79: 128-Pin LQFP Package Dimensions

ic
35 on
Symbol D i m e n s io n i n m m

9 0 tr
Min Nom Max

16 lec
A -- -- 1.60

12 e E
A1 0.05 -- 0.15

A# ing
A2 1.35 1.40 1.45
b 0.17 0.22 0.27

ND i H
b1 0.17 0.20 0.23

a
ER gh
c 0.09 -- 0.20

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
c1 0.09 -- 0.16

., L
, U Sh
D 21.90 22.00 22.10

Co
AL *

D1 19.90 20.00 20.10

TI tlfs

y
D2 7.80 8.00 8.20

g
EN 23

lo
E 15.90 16.00 16.10

no
ID -jq

E1 13.90 14.00 14.10

ch
NF jx

E2 7.80 8.00 8.20

CO z1m

Te
e 0.50 BSC

ic
LL 8vd

L 0.45 0.60 0.75

35 on
L1 1.00 REF

90 tr
VE jm

16 lec
R1 0.08 -- --
AR b
M 9stk

12 e E
R2 0.08 -- 0.20

A# ing
S 0.20 -- --
f5


z4

0° 3.5° 7° ND i H
zs

1 4° TYP
a
60

ER gh

2 12° TYP
o

ND an

3 12° TYP
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 88 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Part Order Numbering/Package Marking

no
Part Order Numbering

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Part Order Numbering/Package Marking

9 0 tr
16 lec
12 e E
6.1 Part Order Numbering

A# ing
Figure 43 shows the part order numbering scheme for the 88Q5050 device. Refer to Marvell Field
Application Engineers (FAEs) or representatives for further information when ordering parts.

ND i H
a
Figure 43: Sample Part Number

ER gh

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
88Q5050 –xx–LKJ2A000–xxxx

Co
AL *
TI tlfs

yg
Custom Code (optional)
EN 23

lo
no
ID -jq

Custom Code

ch
NF jx

Part Number
000 = Automotive Grade
CO z1m

Product Number

Te
ic
LL 8vd

35 on
Temperature Code

90 tr
VE jm

A= Automotive
Custom Code/

16 lec
AR b

Die Revision
M 9stk

12 e E
Environmental Code
2 = RoHS 6/6 + Halogen-free

A# ing
f5

(Green)
z4

ND i H
zs

a
60

ER gh
o

Package Code
ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq

Table 80: 88Q5050 Part Order Options

ou

NF jx

P a c k a g e Ty p e Part Order Number

CO z1m

128-pin LQFP 88Q5050-xx-LKJ2A000

(Automotive AEC-Q100 Grade 2, Green, RoHS 6/6 + halogen-free compliant package)
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 89

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
6.2 Package Marking
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Figure 44 shows a sample package marking and pin 1 location for the 88Q5050 device.

9 0 tr
Figure 44: Sample Package Marking and Pin 1 Location

16 lec
12 e E
A# ing
Marvell Logo

ND i H
Part Identifier, Package Code, Environmental

a
ER gh
Code
Country of Origin 88Q5050-LKJ2 88Q5050 = Part Identifier

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
(Contained in the Lot Number LKJ = Package Code

., L
, U Sh
mold ID or marked as YYWW xx@ 2= Environmental Code:
Country of Origin RoHS 6/6 + Halogen-free (Green)

Co
the last line on the
AL *

package.)
TI tlfs

yg
EN 23

lo
Pin 1 Location

no
ID -jq

Date Code, Custom Code, Assembly Plant Code

ch
NF jx

YYWW = Date Code (YY = Year, WW = Work Week)

CO z1m

xx = Custom Code/Die Revision

Te
@ = Assembly Plant Code

ic
LL 8vd

35 on
Note: The above drawing is not drawn to scale. Location of markings is approximate.

90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 90 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Acronyms and Abbreviations

no
ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Acronyms and Abbreviations

9 0 tr
16 lec
12 e E
AC Alternating Current

A# ing
ACK Acknowledgement

ND i H
ADC Analog-to-Digital Converter

a
AEC Automotive Electronics Council

ER gh
AGC Automatic Gain Control

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
AHB Advanced High-performance Bus
, U Sh
®

Co
ARM Advanced RISC Machine
AL *
TI tlfs

ARP Address Resolution Protocol

yg
ATU Address Translation Unit
EN 23

lo
no
ID -jq

AVB Audio Video Bridging

ch
NF jx
CO z1m

Te
BPDU Bridge Protocol Data Unit

ic
LL 8vd

35 on
CBS Committed Burst Size

90 tr
VE jm

CIR Committed Information Rate

16 lec
AR b

CML Current Mode Logic

M 9stk

12 e E
CPU Central Processing Unit

A# ing
f5

CRC Cyclic Redundancy Check

z4

CSMA/CD
ND i H
Carrier Sense Multiple Access / Collision Detection
zs

a
C-TAG Customer's Tag
60

ER gh

CTS Class Time Slot

o

ND an
ih

, U Sh
vd

DA Destination Address
2

AL *
4o

TI tlfs

DAC Digital-to-Analog Converter

m
MARVELL CONFIDENTIAL

DAP Debug Access Port

EN 23

DEI Drop Eligible Indicator

ID -jq
ou

DFE Decision Feedback Equalizer

NF jx
CO z1m

DHCP Dynamic Host Configuration Protocol

DME Differential Manchester Encoding
LL 8vd

DoS Denial of Service

VE jm

DPLL Digital Phase-Locked Loop

AR b

DPV Destination Port Vector

M 9stk

DSA Distributed Switching Architecture

5

DTCM Data Tightly Coupled Memory

4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 91

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
EBS Excess Burst Size

35 on
9 0 tr
ECC Error-Correction Code

16 lec
EEE Energy Efficient Ethernet

12 e E
EEPROM Electronically Erasable Programmable Read Only Memory

A# ing
eFUSE Electronic Fuse
EMD Egress Monitor Destination

ND i H
EMI Electromagnetic Interference

a
ER gh
EMS Egress Monitor Source

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
E-PAD Exposed Pad

., L
, U Sh

Co
AL *

FCS Frame Check Sequence

TI tlfs

y
FEFI Far-End Fault Indication

g
EN 23

lo
FFE Feed-Forward Equalizer

no
ID -jq

FID Filtering Information Database

ch
NF jx

FIFO First In First Out

CO z1m

Te
FIR Finite Impulse Response

ic
LL 8vd

FLP Fast Link Pulse

35 on
FPP Fast Page Programming

90 tr
VE jm

16 lec
FPri Frame Priority
AR b
M 9stk

12 e E
GARP Generic Attribute Registration Protocol

A# ing
f5

GMII Gigabit Media Independent Interface

z4

ND i H
zs

GPIO General Purpose Input/Output

a
60

ER gh

gPTP general Precision Time Protocol

o

ND an
ih

, U Sh
vd

Hi-Z High Impedance

2

AL *
4o

TI tlfs

IC Integrated Circuit
m
MARVELL CONFIDENTIAL

EN 23

ID Identifier
ID -jq
ou

IEEE Institute of Electrical and Electronics Engineers

NF jx

IFG Inter-Frame Gap

CO z1m

IGMP Internet Group Management Protocol

LL 8vd

IMD Ingress Monitor Destination

IMS Ingress Monitor Source
VE jm

I/O Input/Output
AR b
M 9stk

IP Internet Protocol
IPG Inter-Packet Gap
5
4f

IPTV Internet Protocol Television

sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 92 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Acronyms and Abbreviations

no
ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

IPv4 Internet Protocol version 4

ic
IPv6 Internet Protocol version 6

35 on
9 0 tr
IRL Ingress Rate Limiting

16 lec
ITCM Instruction Tightly Coupled Memory

12 e E
ITSM Isochronous Time Slot Metering

A# ing
JTAG Joint Test Action Group

ND i H
a
ER gh
LAC Link Aggregation Control

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
LAG Link Aggregation

., L
, U Sh
LAN Local Area Network

Co
AL *

LBU Low-speed Bus Unit

TI tlfs

y
LED Light Emitting Diode

g
EN 23

lo
LPI Low Power Idle

no
ID -jq

LPSD Low Power Signal Detect

ch
NF jx

LQFP Low-profile Quad Flat Package

CO z1m

Te
LVDS Low Voltage Differential Signaling

ic
LL 8vd

35 on
MAC Media Access Controller

90 tr
VE jm

16 lec
MDC Management Data Clock
AR b
M 9stk

12 e E
MDI Media Dependent Interface
MDIO Management Data Input/Output

A# ing
f5

MDIX Media Dependent Interface with Crossover

z4

ND i H
zs

MGMT Management
a
60

ER gh

MIB Management Information Base

o

ND an

MII Media Independent Interface

ih

, U Sh
vd

MLD Multicast Listener Discovery

2

MLT-3 Multiple Layer Transition 3

AL *
4o

TI tlfs

MP-SSRAM Multi-Port Synchronous SRAM

m
MARVELL CONFIDENTIAL

EN 23

MPU Memory Protection Unit

ID -jq
ou

MTU Maximum Transmission Unit

NF jx
CO z1m

NLP Normal Link Pulse

LL 8vd

NRL Non-Rate Limiting

NRZ Non-Return to Zero
VE jm

NRZI Non-Return to Zero Inverted

AR b
M 9stk

OABR OPEN Alliance BroadR-Reach®

5
4f

OAM Operations, Administration, and Maintenance

sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 93

2vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
PAV Port Association Vector

35 on
9 0 tr
PCL Policy Control List

16 lec
PCP Priority Code Point

12 e E
PCS Physical Coding Sublayer

A# ing
PECL Positive Emitter Coupled Logic
PFC Priority Flow Control

ND i H
PIRL Port Ingress Rate Limiter

a
ER gh
PLL Phase-Locked Loop

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
PMA Physical Media Attachment

., L
, U Sh
PMD Physical Media Dependent

Co
AL *

PPPoE Point-to-Point over Ethernet

TI tlfs

y
PPS Pulse Per Second

g
EN 23

lo
PPU PHY Polling Unit

no
ID -jq

PTP Precision Time Protocol

ch
NF jx

PVT Port VLAN Table

CO z1m

Te
ic
LL 8vd

QC Queue Controller

35 on
QoS Quality of Service

90 tr
VE jm

16 lec
QPri Queue Priority
AR b
M 9stk

12 e E
QSPI Quad Serial Peripheral Interface

A# ing
f5

PCB Printed Circuit Board

z4

ND i H
zs

a
60

ER gh

RAM Random Access Memory

o

ND an

RFC Request For Comments

ih

, U Sh
vd

RGMII Reduced Gigabit Media Independent Interface

2

RISC Reduced Instruction Set Computer

AL *
4o

TI tlfs

RMON Remote Monitoring

m
MARVELL CONFIDENTIAL

EN 23

RMU Remote Management Unit

ID -jq
ou

R/W Read/Write
NF jx

Rx Receive
CO z1m
LL 8vd

SA Source Address
SERDES Serializer/Deserializer
VE jm

SFD Start of Frame Delimiter

AR b
M 9stk

SGMII Serial Gigabit Media Independent Interface

SID State Information Database
5
4f

SMI Serial Management Interface

sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 94 Document Classification: Proprietary Information March 07, 2018

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Acronyms and Abbreviations

no
ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

SoC System-on-Chip

ic
SPI Serial Peripheral Interface

35 on
9 0 tr
SQE Signal Quality Error

16 lec
SRAM Static Random Access Memory

12 e E
SRP Stream Reservation Protocol

A# ing
SSRAM Synchronous SRAM
S-TAG Service Tag

ND i H
STP Spanning Tree Protocol

a
ER gh
STU SID Translation Unit

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an

., L
, U Sh
TAI Time Application Interface

Co
AL *

TAP Test Access Port

TI tlfs

y
TCAM Ternary Content Addressable Memory

g
EN 23

lo
TCP Transmission Control Protocol

no
ID -jq

TCP/IP Transmission Control Protocol/Internet Protocol

ch
NF jx

TDR Time Domain Reflectometry

CO z1m

Te
TOD, ToD Time of Day

ic
LL 8vd

TSM Time Slot Metering

35 on
TSN Transport block Sequence Number

90 tr
VE jm

16 lec
TWSI Two-Wire Serial Interface
AR b
M 9stk

12 e E
Tx Transmit

A# ing
f5

UDP User Datagram Protocol

z4

ND i H
zs

UTP Unshielded Twisted Pair

a
60

ER gh
o

ND an

VCT Virtual Cable Tester®

ih

, U Sh
vd

VID VLAN Identifier

2

VLAN Virtual LAN

AL *
4o

TI tlfs

VTU VLAN Translation Unit

m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

WAN Wide Area Network

NF jx

WoL Wake on LAN

CO z1m

WoF Wake on Frame

LL 8vd

xMII RGMII / RMII / MII

VE jm

XTAL Crystal
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 95

vd
2
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
Revision History

9 0 tr
16 lec
12 e E
Table 1: Revision History (Sheet 1 of 5)

A# ing
R e v i s io n Date Description

ND i H
Rev. -- February 14, 2018 Pre-release draft version

a
v0.15 Section 2, Signal Description

ER gh
• Section‚ LED and EEPROM Interface, on page 31: Table 15,

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
LED and EEPROM Interface, updated Pin Type columns.

., L
Section 4, Electrical Specifications, on page 55
, U Sh
• Updated tables 46, 47, 48, 49, 50 and 51.

Co
AL *
TI tlfs

Rev. – October 6, 2017 Section 6, Part Order Numbering/Package Marking

yg
v0.14 • Table 78, 88Q5050 Part order Options: Updated the Part
EN 23

lo
Order Number.

no
ID -jq

Rev. – June 27, 2017 Pre-release draft version

ch
NF jx

v0.13
CO z1m

Section 2, Signal Description

Te
• Table 18, Low-Power Signal Detect, on page 34: updated

ic
description of VLPF pin.
LL 8vd

35 on
• Table 19, Power and Ground, on page 35: updated
description of AVDD18 pin.

90 tr
VE jm

16 lec
Section 4, Electrical Specifications
AR b

• Table 50, Low Power Signal Detect DC Characteristics, on

M 9stk

12 e E
page 67: updated ISTANDBY.
• Table 35, Absolute Maximum Ratings, on page 55: updated

A# ing
f5

VDDA(18).
z4

• Section 4.3.5, Digital Pins, on page 62 updated values as

ND i H
detailed below.
zs

a
• Table 43, DC Characteristics for Pins GPIO[4:0], INTn,
60

ER gh

MDC_CPU, MDC_PHY, MDIO_CPU, MDIO_PHY, RESETn,

o

ND an

SPI_CS, SPI_SCLK, SPI_SIO[3:0], TCK, TDI, TDO, TEST,

ih

TMS, TRSTn, on page 62: updated VDDO, IOH, and IOL.

, U Sh
vd

• Table 44, DC Characteristics for Pins P567_INCLK, P567_

2

IND[3:0], P567_INDV, P8_INCLK, P8_IND[3:0], P8_INDV,

AL *
4o

TI tlfs

on page 63: updated VDDO.

m

• Table 45, DC Characteristics for Pins P567_OUTCLK,

MARVELL CONFIDENTIAL

EN 23

P567_OUTD[3:0], P567_OUTEN, P8_OUTCLK, P8_

OUTD[3:0], P8_OUTEN, on page 64: updated VDDO.
ID -jq
ou

NF jx

Rev. – May 10, 2017 Pre-release draft version

CO z1m

v0.12 Section 1, 88Q5050 Functional Description

• Section 1.1, Overview, on page 12: QSPI information
LL 8vd

updated.
Section 4, Electrical Specifications
VE jm

• Section 4.3.4, SGMII, on page 58 updated.

AR b

Appendix A, Acronyms and Abbreviations updated.

M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 96 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Revision History

no
ch
Te
Table 1: Revision History (Sheet 2 of 5)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
R e v i s io n Date Description

9 0 tr
Rev. – April 24, 2017 Pre-release draft version

16 lec
v0.11 Section 2, Signal Description

12 e E
• Table 9, SMI, on page 28: Resistor information for MDIO_
CPU and MDIO_PHY pins updated.

A# ing
• Table 20, Bootstrap Options, on page 37: Table introduction
extended; Default Pin Name column added; more details

ND i H
added to Functionality column.

a
• Section 2.3.2, Pin Connection Information, on page 39

ER gh
added.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
Section 4, Electrical Specifications

., L
• Table 37, Main Clock (XTAL_IN) DC Characteristics, on
, U Sh
page 56 updated.

Co
AL *

• Table 73, QSPI AC Characteristics, on page 83 updated.

TI tlfs

y
Appendix A, Acronyms and Abbreviations updated.

g
EN 23

lo
Rev. – February 14, 2017 Pre-release draft version

no
ID -jq

v0.10 Section 2, Signal Description

ch
NF jx

• Figure 9, 88Q5050 128-Pin LQFP Package (Top View), on

CO z1m

page 20: E-PAD added.

Te
• Table 19, Power and Ground, on page 35: E-PAD added.

ic
LL 8vd

Section 3, Device Physical Interfaces

35 on
• Figure 12, RMII MAC Interface Pins, on page 49 updated.

90 tr
VE jm

Section 4, Electrical Specifications

16 lec
• Section 4.4.2, Power-On Reset, on page 68 added.
AR b
M 9stk

12 e E
Section 5, Package Specifications
• Table 42, 128-Pin LQFP Package Drawing, on page 87:

A# ing
f5

E-PAD labeled.
z4

ND i H
zs

a
Rev. – December 15, 2016 Pre-release draft version
60

ER gh

v0.9 Section 1, 88Q5050 Functional Description

o

ND an

• Section 1.1, Overview, on page 12: General Features and

ih

Interfaces updated.
, U Sh
vd

• Figure 1, 88Q5050 Block Diagram, on page 14 updated.

2

AL *

• Section 1.2, Device Configuration, on page 14 added.

4o

TI tlfs

• Section 1.3, Application Cases, on page 16 updated.

m
MARVELL CONFIDENTIAL

• Section 1.4, Data Path and Control Paths, on page 18

EN 23

added.
ID -jq
ou

Section 2, Signal Description

• Figure 9, 88Q5050 128-Pin LQFP Package (Top View), on
NF jx

page 20: Colors updated.

CO z1m

• Table 11, TWSI, on page 30: Pin descriptions updated.

• Table 9, SMI, on page 28: Frequency information added to
LL 8vd

MDC_CPU description.
• Table 18, Low-Power Signal Detect, on page 34: Pin
VE jm

descriptions updated.
AR b

• Table 19, Power and Ground, on page 35: Pin descriptions

M 9stk

updated.
• Table 20, Bootstrap Options, on page 37: Notes updated.
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 97

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 1: Revision History (Sheet 3 of 5)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
R e v i s io n Date Description

9 0 tr
Rev. – December 15, 2016 Pre-release draft version

16 lec
v0.9 (Cont.) Section 4, Electrical Specifications

12 e E
(Cont.) • Section 4.1, Absolute Maximum Ratings, on page 55
updated.

A# ing
• Section 4.2, Recommended Operating Conditions,
on page 56 updated.

ND i H
• Section 4.3, DC Electrical Characteristics, on page 56: New

a
subsections added.

ER gh
• Table 45 on page 64: Maximum values for VIL updated.

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
• Section 4.4, AC Electrical Characteristics, on page 67: New

., L
, U Sh subsections added.
Section 5, Package Specifications

Co
AL *

• Section 5.1, Thermal Information, on page 86 added.

TI tlfs

• Table 79, 128-Pin LQFP Package Dimensions, on page 88:

yg
Values for D2 and E2 updated.
EN 23

lo
Appendix A, Acronyms and Abbreviations updated.

no
ID -jq

ch
Rev. – September 14, 2016 Pre-release draft version
NF jx

v0.8
CO z1m

Introduction added.

Te
Section 2, Signal Description

ic
LL 8vd

• Table 5, 100BASE-TX Interface (Port 6), on page 22:

35 on
Termination resistor information added.

90 tr
VE jm

Section 4, Electrical Specifications

16 lec
AR b

Section 4.3.5, Digital Pins, on page 62 updated.

M 9stk

12 e E
Rev. – August 10, 2016 Pre-release draft version

A# ing
f5

v0.7 Section 4, Electrical Specifications

z4

ND i H
• Section 4.3.5, Digital Pins, on page 62 added.
zs

• Section 4.3.6, Internal Resistors, on page 67 added.

a
60

ER gh

Section 5, Package Specifications

• Figure 42, 128-Pin LQFP Package Drawing, on page 87:
o

ND an
ih

E-PAD type changed back to chamfered.

, U Sh
vd

• Table 79, 128-Pin LQFP Package Dimensions, on page 88:

E-PAD dimensions updated.
2

AL *
4o

TI tlfs

Rev. – July 27, 2016 Pre-release draft version

m
MARVELL CONFIDENTIAL

v0.6
EN 23

Section 5, Package Specifications

• Figure 42, 128-Pin LQFP Package Drawing, on page 87:
ID -jq
ou

E-PAD type changed to non-chamfered.

NF jx

• Table 79, 128-Pin LQFP Package Dimensions, on page 88:

CO z1m

E-PAD dimensions added.

LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 98 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
Revision History

no
ch
Te
Table 1: Revision History (Sheet 4 of 5)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
R e v i s io n Date Description

9 0 tr
Rev. – July 26, 2016 Pre-release draft version

16 lec
v0.5 Section 2, Signal Description

12 e E
• Pin positions updated:
All pins rotated clockwise by one position (that is, pin 128 is

A# ing
now pin 127, pin 127 is now pin 126, …, and pin 1 is now
pin 128).

ND i H
Pins P7_S_TXN and P7_S_TXP swapped.

a
Section 3, Device Physical Interfaces added.

ER gh
Section 4, Electrical Specifications

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
• Section 4.1, Absolute Maximum Ratings, on page 55

., L
, U Sh
updated.

Co
• Table 36, Recommended Operating Conditions, on page 56
AL *

updated.
TI tlfs

yg
Rev. – July 6, 2016 Pre-release draft version
EN 23

lo
v0.4

no
Section 1, 88Q5050 Functional Description
ID -jq

• Table 1, Interface Combinations, on page 13 updated.

ch
NF jx

Section 2, Signal Description

CO z1m

Te
• Pin positions updated:
P6_RXP/N

ic
LL 8vd

P6_TXP/N

35 on
RSET

90 tr
VE jm

TSTPT

16 lec
• Pins renamed:
AR b
M 9stk

AVDD18 (pin 25) to S_AVDD18

12 e E
VBATF to VLPF

A# ing
VBATR to VLPR
f5

XTAL_1 to XTAL_IN
z4

ND i H
XTAL_2 to XTAL_OUT
zs

• Table 19, Power and Ground, on page 35: S_AVDD18 pin

a
60

ER gh

description added.
• Section 2.2.5, xMII (Port 5/6/7), on page 23: Editorial
o

ND an
ih

changes.
, U Sh

• Section 2.2.6, xMII/GMII (Port 8), on page 26: “GMII” added

vd

to section and table heading; editorial changes.

2

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Copyright © 2018 Marvell CONFIDENTIAL Doc. No. MV-S111158-00 Rev. –

ih

March 07, 2018 Document Classification: Proprietary Information Page 99

2 vd
4o
m
 Co

t Co., Ltd. * UNDER NDA# 121690

gy
lo
88Q5050

no
Datasheet

ch
Te
Table 1: Revision History (Sheet 5 of 5)
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED

ic
35 on
R e v i s io n Date Description

9 0 tr
Rev. – June 7, 2016 Pre-release draft version

16 lec
v0.3 Section 1, 88Q5050 Functional Description

12 e E
• Section 1.1, Overview, on page 12 updated.
Section 2, Signal Description

A# ing
• Several pin positions updated; pin descriptions updated

ND i H
accordingly.
• ADDRn[3] pin removed.

a
• Pins renamed:

ER gh
P1..5_WAKE to P1..5_WAKE_DIS

ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technology

ND an
P567_SEL_0_n to P567_SELn[0]

., L
P567_SEL_1 to P567_SEL[1]
, U Sh
P8_MODE_0 to P8_MODE[0]

Co
AL *

P8_MODE_1 to P8_MODE[1]
TI tlfs

P8_MODE_2_n to P8_MODEn[2]

yg
• Table 14, LED Port-to-PHY Mapping, on page 32 added.
EN 23

lo
• Table 19, Power and Ground, on page 35: VDDO_EFUSE

no
ID -jq

pin description updated.

• Table 20, Bootstrap Options, on page 37: ADDRn[x] pins

ch
NF jx

description updated.
CO z1m

Te
Rev. – May 4, 2016 Pre-release draft version

ic
LL 8vd

v0.2

35 on
90 tr
VE jm

16 lec
AR b
M 9stk

12 e E
A# ing
f5
z4

ND i H
zs

a
60

ER gh
o

ND an
ih

, U Sh
2 vd

AL *
4o

TI tlfs
m
MARVELL CONFIDENTIAL

EN 23
ID -jq
ou

NF jx
CO z1m
LL 8vd
VE jm
AR b
M 9stk
5
4f
sz
0z
o6

Doc. No. MV-S111158-00 Rev. – CONFIDENTIAL Copyright © 2018 Marvell

ih

Page 100 Document Classification: Proprietary Information March 07, 2018

2 vd
4o
m
 ou
MARVELL CONFIDENTIAL
0v - UNAUTHORIZED DISTRIBUTION OR USE STRICTLY PROHIBITED
m
4o
2
Contact Information

vd
ih
o60
zs
z4
f5
M 9stk
AR b
VE jm
LL 8vd
CO z1m
m NF jx
4o ID -jq
2vd EN 23
ih TI tlfs
o6 AL *
0z , U Sh
sz ND an
4f
5 ER gh
M 9stk a
AR b ND i H
VE jm A# ing
LL 8vd 12 e E
CO z1m 16 lec
9 0 tr
NF jx 35 on
ID -jq ic
EN 23 Te
TI tlfs ch
AL * no
, U Sh lo
ND an gy
ER gh Co
a
ND i H
A# ing
12 e E
16 lec
90 tr
35 on
ic
Te

5488 Marvell Lane

Tel: 1.408.222.2500
Santa Clara, CA 95054, USA
Marvell Semiconductor, Inc.

http://www.marvell.com
Fax: 1.408.988.8279

Marvell. Moving Forward Faster

ch
no
lo
gy
Co
., L
ou0vm4o2vdiho60zsz4f59stkbjm8vdz1mjx-jq23tlfs * Shanghai Hinge Electronic Technologyt Co., Ltd. * UNDER NDA# 121690