Efficient CAM cell design for

low power and low delay

V V Satyanarayana Satti Sridevi Sriadibhatla
School of Electronics Engineering School of Electronics Engineering
VIT University VIT University
Vellore, India Vellore, India
[email protected] [email protected]

Abstract—Content-addressable memory (CAM) is the hard- single operation. CAM compares table of stored data with the
ware based particular type of memory device utilized for low input search data and returns the matching address of lookup
power and high-speed application. CAMs are developed for data to the encoder. CAM architecture consists of an array
precise application without sacrificing their search speed, and
it is much faster than random accessmemory (RAM) in search of CAM cells, match lines, search lines, match line sense
application. CAM executes two essential functions storing and amplifier and an encoder is shown in Figure 1. CAM cell are
comparing. The additional circuitry during comparison process of two types ternary content addressable memory (TCAM) and
builds the size of CAM which expands fabrication cost. The new binary content addressable memory (BCAM).
hardware enhances the power consumption since each compari-
son of the circuitry is dynamic on each clock cycle accordingly.




To achieve low power design, some new implementations emulate   
the operation of CAM by utilizing different CAM cell designs 
in the CAM architecture. Therefore designing novel CAM cells   
for low power application in CAM architecture is a challenging 
task for the designer. This paper compares various CAM cell 
 
design at 180nm, 90nm and 45nm for power, delay and analysis  
is performed in cadence virtuoso tool. 
Index Terms—delay, precharge, power, XNOR cell, XOR cell.


 
I. I NTRODUCTION
 
One of the significant parameters in digital circuit design 

        
 
is power and delay. Power and delay of CAM cells play a
major role in designing many applications like image process-   
ing [1], network routers [2], data management [3] and data
compression [4]. Few types of research work on CAM cells Fig. 1. Basic CAM Architecture
have already been investigated on low power and delay [5-6].
Henceforth for better performance and low power applications, CAM cells are designed to store and search lookup table
there is a need to create efficient CAM cells. This work has data within a single clock cycle. BCAM cell uses single
been focused on reducing power and delay by using diverse SRAM circuit for bit storage (0 or 1), TCAM cell uses Two
proficiencies that have been gathered based on the previous SRAM cells to store ternary value dont care X other than 0 or
works. 1. In CAM for bit comparison, circuitry is based on the type
This Paper is organized as follows section II explains of application. Block diagram of basic BCAM, TCAM cell
about overview of CAM architecture, section III gives detail is shown in Figure.2, Figure.3. The bit comparison in CAM
description about basic CAM core cells with their encoding cell design is logically equivalent to XOR or XNOR of the
tables, section IV describes proposed design of TCAM cells stored bit and search bit. The transistors in the comparison
and their operation, section V shows the result of different circuitry are designed with typically minimum sized to
CAM cell design for power, delay in different technologies maintain high cell density. CAM operation is performed in
and section VI concludes. two stages precharge phase and evaluation phase. CAM cell
operation begins with loading the search input through search
II. OVERVIEW OF CAM ARCHITECTURE lines followed by pre-charging match line, once the match
CAM performs three basic operations reading, writing and line is pre-charge it temporarily disconnects match line from
comparing. CAM is intended to search his whole memory in a ground. Next, search data is broadcast through search line to
compare with the store data. While comparing stored bit and
the search bit if there is a match indicates match state then
978-1-5386-1716-8/17$31.00 © 2017 IEEE
 


match line isolated from the discharge discharge path
otherwise it indicates miss state then match line connected to 



ground.  

   





 
 
Fig. 4. NOR type BCAM cell structure

    

  TABLE I
E NCODING TABLE FOR BCAM NOR CELL

   D Dbar SL SLbar T1 T2 T3 T4 ML

  
 0 1 0 1 ON OFF OFF ON Match
1 0 0 1 OFF ON OFF ON Miss
0 1 1 0 ON OFF ON OFF Miss
1 0 1 0 OFF ON ON OFF Match
Fig. 2. Block Diagram of Basic BCAM

  B. NAND type BCAM cell

 NAND BCAM cell is shown in Figure.5. Bits stored in



 NAND BCAM cell is with the help of SRAM structure.
 
Comparison in NAND BCAM cell is performed by using
three transistors T1, TD1, TD2. NAND BCAM cell consumes
   less power because of low load capacitance to the match
 line but results from high delay because of their long pull
down paths [7]. The main purpose of CAM is to design the
 
architecture with low power consumption without degrading
 
 the performance. Therefore normally NOR type BCAM cell is
preferred when designing cells in CAM architecture because
of their low delay, even in the worst case NOR has a better
Fig. 3. Block Diagram of Basic TCAM
delay than NAND. Table II shows comparison table to explain
about match or miss for BCAM NAND.
III. BASIC CAM CORE CELLS
A. NOR type BCAM cell
NOR BCAM cell is shown in Figure.4. In this cell bits 0  
or 1 are stored with the help of SRAM structure in D and
Dbar . The comparison between the store bit and search bit is    
performed using four comparison transistors T1 through T4.
The transistors, T1/T3, and T2/T4 forms two separate pull-
down paths for the match line ML [7]. To operate the cell first 
 

precharge the match line this is initially in high. Then starts 
the evaluation phase, here search input is compared with the
stored bit. If there is a miss-match between the search bit and


store bit match line starts discharging to zero quickly because
of short pull-down paths. If there is a match then match line
retain the logic high as in precharge phase. The disadvantage
of BCAM NOR cell is power inefficient because pull down
transistors arrangement in this cell type contributes more drain  
capacitance to the match line. Table I shows encoding table
for BCAM NOR cell which give information about match or Fig. 5. NAND type BCAM cell structure
miss between search bit and a stored bit.
 TABLE II
E NCODING TABLE FOR BCAM NAND CELL
  
D Dbar SL SLbar T D1 T D2 T1 ML
0 1 0 1 ON OFF ON Match  
1 0 0 1 OFF OFF OFF Miss
0 1 1 0 OFF OFF OF Miss    
1 0 1 0 OFF ON ON Match


 

C. NOR type TCAM cell 
TCAM is encoded into two bits D and Dbar which need


not be complementary. These two bits are connected to pull
down path independently. Second SRAM is used in TCAM
NOR cell design to store a ternary value as shown in Figure.6.
TCAM NOR cell stores X value by setting D and Dbar to logic  
1 which forces the NOR cell to match by disconnecting both
pull down paths from the ground despite the inputs. Searching Fig. 7. NAND type TCAM cell structure
for an X in TCAM NOR cell is possible by setting SL and
SLbar to logic low [8]. For remaining combinations, it is as
TABLE IV
shown in Table III. E NCODING TABLE FOR TCAM NAND CELL
store
D Dbar N value SL SLbar T D1 T D2 T1 ML
0 1 0 0 0 1 ON OFF ON Match
1 0 0 1 0 1 OFF OFF OFF Miss
0 1 0 0 1 0 OFF OFF OFF Miss
 1 0 0 1 1 0 OFF ON ON Match
0 1 1 X 1 1 ON ON ON Match
1 0 1 X 1 1 ON ON ON Match

 
 
IV. PROPOSED CAM CELL
 
A. Early predict CAM cell
The aim of this CAM cell design is to terminate the match


 line that misses early in precharge phase. To achieve this basic
BCAM cell is modified with precharge controller [10] is shown
Fig. 6. NOR type TCAM cell structure in figure 8. My idea here is to use that precharge controller
in TCAM based early predict CAM cell is shown in Figure
9. Precharge controller here dynamically varies the precharge
TABLE III time to discard pre-charging of unnecessary match line to
E NCODING TABLE FOR TCAM NOR CELL full level. Prd is a precharge signal which varies dynamically
Store and Pr is a precharge signal which is fixed. When a bit is
Dbar SLbar T1 T2 T3 T4
D value SL ML
matched with the stored bit in the precharge phase, P rd is
0 1 0 0 1 ON OFF OFF ON Match
1 0 1 0 1 OFF ON OFF ON Miss same as pre-signal which makes match line high. When a bit
0
1
1
0
0
1
1
1
0
0
ON
OFF
OFF
ON
ON
ON
OFF
OFF
Miss
Match
is mismatched with the stored bit, P rd terminate the match line
1 1 X X X OFF ON ON OFF Match that is charging as soon as node Mp charges to the threshold
value. Thus precharge controllers in this CAM cell minimize
unnecessary charging of mismatched match line results in less
delay and reduce power.
D. NAND type TCAM cell
In TCAM NAND cell, for ternary storage, basic NAND B. Precharge free CAM cell
CAM cell is modified by adding a mask bit N is shown in Normally CAM operation begins with pre-charging then
Figure.7. Mask bit 1 allow setting the TCAM NAND cell by evaluation. It is observed that in precharge phase power
to store X, which forces mask transistor N ON, whatever wastage is more in CAM, because of short circuit current
the value of D. TCAM NAND cell allows a search for an and charge sharing problems and this occur when there is a
X by setting both differential search line pairs to logic 1 mismatch between the stored bit and search bit. To overcome
[9]. For the remaining combinations, it is shown as in Table IV. this problem BCAM cell is modified to avoid precharge phase
completely [11] is shown in Figure 10. Based on this idea
Proposed TCAM based precharge free CAM cell is shown in
  


Figure 11. Here both controls bit and pull down transistor
helps in avoiding the precharge phase. To operate the cell  
in precharge free, the control bit is set to null which makes
pull down transistor off. Depending on match and miss match
between stored bit and search bit match line remain high or
low.




  
  
  
  
 




 

Fig. 11. Precharge free TCAM cell structure

Fig. 8. Early Predict BCAM cell structure

V. RESULTS & DISCUSSION
In this paper, the analysis is performed on power and delay

 for different CAM cells at different technologies (180nm,
 
90nm, 45nm) using cadence virtuoso tool. Supply voltage 1V


 and operating frequency 100(MHz) is used for all the CAM
  cell structures. Table V to Table XII shows the different CAM
  cell outputs for the match power, mismatch power, and delay.
When compared to basic CAM cell structures, Proposed CAM
  cell structures have better improvements in power and delay
and their comparisons are clearly shown in Table V to Table

 XII.

Fig. 9. Early Predict TCAM cell structure TABLE V

A NALYSIS OF POWER AND DELAY FOR NOR BCAM

Technol Match Miss match Delay

  


Type of CAM ogy(nm) power(pW) power(pW) (pS)
45 164.3 283.4 44.80
NOR BCAM 90 356.9 534 47.72
180 1769 2660 109.3
 

TABLE VI
A NALYSIS OF POWER AND DELAY FOR NAND BCAM

Technol Match Miss match Delay

Type of CAM ogy(nm) power(pW) power(pW) (pS)
45 150 184.1 38.74
NAND BCAM 90 324 4220 36.52
 
180 1523 2515 77.25
  
 
TABLE VII
A NALYSIS OF POWER AND DELAY FOR NOR TCAM

Technol Match Miss match Delay

Type of CAM ogy(nm) power(pW) power(pW) (pS)
45 285.4 303.6 20.98
NOR TCAM 90 593.7 652.3 24.12
Fig. 10. Precharge free BCAM cell structure 180 2408 3102 78.04
 TABLE VIII [3] Jalaleddine, S.M., 1999. Associative memories and processors: The
A NALYSIS OF POWER AND DELAY FOR NAND TCAM exact match paradigm. Journal of King Saud University-Computer and
Information Sciences, 11, pp.45-67.
Technol Match Miss match Delay [4] Bremler-Barr, A. and Hendler, D., 2012. Space-efficient TCAM-based
Type of CAM ogy(nm) power(pW) power(pW) (pS) classification using gray coding. IEEE Transactions on Computers,
45 9534 9554 50.02 61(1), pp.18-30.
NAND TCAM 90 13020 16850 101.3 [5] Pagiamtzis, K. and Sheikholeslami, A., 2006. Content-addressable mem-
180 39170 39770 91.61 ory (CAM) circuits and architectures: A tutorial and survey. IEEE
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[6] Schultz, K.J., 1997. Content-addressable memory core cells A survey.
TABLE IX INTEGRATION, the VLSI journal, 23(2), pp.171-188.
A NALYSIS OF POWER AND DELAY FOR E ARLY P REDICT BCAM [7] Chang, Y.J. and Liao, Y.H., 2008. Hybrid-type CAM design for both
power and performance efficiency. IEEE Transactions on Very Large
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TABLE X [10] Kittur, H.M., 2017. Content Addressable MemoryEarly Predict and
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90 4338 1612 22.89
180 27140 49630 110.6

TABLE XI
A NALYSIS OF POWER AND DELAY FOR PRECHARGE FREE BCAM

Technol Match Miss match Delay

Type of CAM ogy(nm) power(pW) power(pW) (pS)
45 148.3 97.66 242.9
Precharge free BCAM 90 6249 254.5 59.2
180 1539 684.3 668.6

TABLE XII
A NALYSIS OF POWER AND DELAY FOR PRECHARGE FREE TCAM

Technol Match Miss match Delay

Type of CAM ogy(nm) power(pW) power(pW) (pS)
45 294.2 255.1 9.755
Precharge free TCAM 90 657.1 514.5 51.77
180 2190 1426 1.127

VI. CONCLUSION
In this paper, different CAM cell is analyzed for power
and delay using cadence virtuoso tool. Novel TCAM cells,
early predict and precharge free are proposed. When compared
to basic TCAM NOR and NAND cells novel TCAM cells
have better improvement in terms of power and delay which is
shown clearly in the Table section. In designing architectures
of CAM, novel CAM cells are useful to avoid the number
of comparison operation in order to reduce the power and to
improve performance.

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