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O Lander CHP 3 Test

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Ali Raza
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16 views2 pages

O Lander CHP 3 Test

Uploaded by

Ali Raza
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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Q1(a) Explain how the width of the data bus and system clock speed affect the performance

of a computer system.
Width of the data bus ................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

Clock speed ..............................................................................................................................

...................................................................................................................................................

...................................................................................................................................................

...............................................................................................................................................[6]
(b) Most computers use Universal Serial Bus (USB) ports to allow the attachment of devices.
Describe two benefits of using USB ports.

1 ................................................................................................................................................

...................................................................................................................................................

2 ................................................................................................................................................

...............................................................................................................................................[4]
(c) The table shows six stages in the von Neumann fetch-execute cycle.
Put the stages into the correct sequence by writing the numbers 1 to 6 in the right hand
column.

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1
2 (a) The diagram below shows a simplified form of processor architecture.

Name the three buses labelled A, B and C.

A ...............................................................................................................................................

B ...............................................................................................................................................

C ............................................................................................................................................... [6]

(b) State the role of each of the following special purpose registers used in a typical processor.

Program Counter ......................................................................................................................

...................................................................................................................................................

Memory Data Register ..............................................................................................................

...................................................................................................................................................

Current Instruction Register ......................................................................................................

...................................................................................................................................................

Memory Address Register ........................................................................................................

................................................................................................................................................... [8]

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