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Tessent Command Study Notes 5

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126 views

Tessent Command Study Notes 5

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electro123e
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Tessent Command Study Notes.

1. report_gates
Displays netlist information and simulation results for specified
gates, as well as simulation results for specific user-defined
ATPG functions. This command requires a flattened netlist
before use.

2. set_gate_report
Specifies the information displayed by the report_gates
command.

3. report_scan_volume
Shows the amount of scan data used by the pattern set,
including chain test patterns. Because pattern count is not a
good measure of EDT compression for different scan
configurations, this command gives an equivalent standard
measure of EDT and conventional ATPG, making it easier to
compare their results.

4. add_scan_chains
Assign names to pre-existing scan chains in the design.

5. create_module
 Create a new design module with no ports.

 After you create a module using this command, you can use
the set_current_design command to set the new module as
the top-level design for all subsequent commands and
provide the name of the new module.

 You can add a new port to the new module using the
create_port command, add an instance using the
create_instance command, and then connect the pins using
the create_connections command. Optionally, you can save

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the complete module to disk using the write_design
command.

 After creating a new module, the current design can be


redesigned to a different level using the set_current_design
command, and the module can be inserted using the
create_instance command.

6. create_port
 Creates a port on the specified design block.

By default, this command creates a port on the design module


of the current design. If the -on_module parameter is specified,
the command creates a port on the module specified by
obj_spec.

 This command returns a set of created port objects. If


port_name is bus, the command returns a set with a port
object for each bus bit, starting with the leftmost bit of the
bus and ending with the rightmost bit of the bus.

 If a tool already exists on the specified port and generates


an error, you can specify -silent to prevent the tool from
generating an error.

7. create_instance
Instantiate the module mod_spec in the design module of the
current design module. If the command succeeds, a collection
of newly created instances will be returned.

8. add_nonscan_instances
 Sets a custom is_non_scannable attribute on specified
design objects to exclude the objects from the scan
insertion process.

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 The tool does not perform scanability checks on non-scan
instances.

9. analyze_bus
Analyze the contention issues of specified bus gates.

If the bus passes the analysis, the tool displays a message


indicating that it passed. If the analysis aborts, the tool displays
a message indicating the tri-state drivers (TSDs) that the tool
identified when it aborted. If the bus analysis is aborted, the
tool displays two violating TSDs that were identified.

10.add_input_constraints
 Constrain PIs to specified values.

 inferred input constraints-some


input constraints are automatically applied to certain input
ports of the current design, depending on the current context
and the ICL port function. There are also some properties that
trigger the creation of input constraints.

 Constraints derived from ICL port functions


If an ICL description exists for the current design, then the
accompanying constraints are applied during the
set_current_design command (in all contexts except "patterns -
ijtag").

 Constraints derived from ICL module attributes


If the ICL module associated with the current design contains
the icl_module attributes "force_low_input_port_list" or
"forced_high_input_port_list", then all ports to which these
attributes are applied are correctly constrained, using
constraint types "C0" and "C1". Constraints are applied during
the execution of "set_current_design".

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 Constraints derived form
ports with port attributes set to "power" or "ground" are
correctly constrained using constraint types "CT1" and "CT0".
(set_current_design)

 Constraints on ports with ICL port function DataInPortAt


the end of the test_setup procedure, including iCall or iMerge
statements, all DataInPorts with ICL port function are
constrained to C0 or C1 according to the values ​ ​ last
assigned to them during IJTAG retargeting of iCall and iMerge
commands. This behavior is prevented if the port has the
icl_module attribute "tessent_no_input_constraints" set to on.

11.add_dft_control_points
Instructs the tool to assume the presence of DFT control logic
during pre-DFT DRC and to insert the control logic during DFT
insertion (as part of process_dft_specification).

12.write_design_import_script
Generates a script that can be processed by a synthesis tool to
synthesize the RTL design that has the DFT inserted.

13.report_power_metrics
Displays the power consumption metirc of the shift and capture
of the specified test patterns. Use this information to identify
test patterns that may cause chip failures due to power
consumption issues.

14.set_power_control
Enable low power ATPG and set the switching or capture
threshold. You can also run this command without parameters
to report the current power control settings.

4 Ashwani DFT
Using set_power_control to meet the power constraint will
affect the ATPG test pattern count and the tool running time
because calculating the toggle rate of each test pattern
requires additional time.

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