1 a.

8086 Internal Architecture

Architecture Diagram 4 Marks
Explanation 3 Marks

Features: It is a 16-bit μp, 8086 has a 20 bit address bus can access up to 2^20=1MB memory
locations (1 MB), It can support up to 64K I/O ports, It provides fourteen 16 -bit registers, It has
multiplexed address and data bus AD0- AD15 and A16 – A19, It requires single phase clock
with 33% duty cycle to provide internal timing,8086 is designed to operate in two modes,
Minimum and Maximum, It can prefetch up to 6 instruction bytes from memory and queues
them in order to speed up instruction execution. It requires +5V power supply,A 40 pin dual in
line package It is available in 3 versions based on the frequency of operation −
o 8086 → 5MHz
o 8086-2 → 8MHz
o (c)8086-1 → 10 MHz
Minimum and Maximum Modes:
The minimum mode is selected by applying logic 1 to the MN / MX input pin. This is a single
microprocessor configuration. The maximum mode is selected by applying logic 0 to the MN /
MX input pin. This is a multi micro processors configuration.8086 does not have a RAM or
ROM inside it. However, it has internal registers for storing intermediate and final results and
interfaces with memory located outside it through the System Bus. 2 Marks
Relevant Explanation about Registers, Pipelinig, Segmnetation, Bus Interface unit, Execution
Unit, Physical address calculation etc., 1 Marks
1 b. 8085 Pin Description
PIN Diagram 4 Marks
Explanation 3 Marks

The pins of a 8085 microprocessor can be classified into seven groups −

Address bus---A15-A8, it carries the most significant 8-bits of memory/IO address.
Data bus--AD7-AD0, it carries the least significant 8-bit address and data bus.
Control and status signals--These signals are used to identify the nature of operation. There are
3 control signal and 3 status signals. Three control signals are RD, WR & ALE.
RD − This signal indicates that the selected IO or memory device is to be read and is
ready for accepting data available on the data bus.
WR − this signal indicates that the data on the data bus is to be written into a selected
memory or IO location.
ALE − It is a positive going pulse generated when a new operation is started by the
microprocessor. When the pulse goes high, it indicates address. When the pulse goes
down it indicates data.
Three status signals are IO/M, S0 & S1.
IO/M--This signal is used to differentiate between IO and Memory operations, i.e. when it is
high indicates IO operation and when it is low then it indicates memory operation.
S1 & S0--These signals are used to identify the type of current operation.
Power supply--There are 2 power supply signals − VCC & VSS. VCC indicates +5v power
supply and VSS indicates ground signal.
Clock signals
There are 3 clock signals, i.e. X1, X2, CLK OUT.
X1, X2 − A crystal (RC, LC N/W) is connected at these two pins and is used to set
frequency of the internal clock generator. This frequency is internally divided by 2.
CLK OUT − this signal is used as the system clock for devices connected with the
microprocessor.
Interrupts & externally initiated signals
Interrupts are the signals generated by external devices to request the microprocessor to perform
a task. There are 5 interrupt signals, i.e. TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR. We will
discuss interrupts in detail in interrupts section.
INTA − It is an interrupt acknowledgment signal.
RESET IN − this signal is used to reset the microprocessor by setting the program
counter to zero.
 RESET OUT − this signal is used to reset all the connected devices when the
microprocessor is reset.
READY − this signal indicates that the device is ready to send or receive data. If
READY is low, then the CPU has to wait for READY to go high.
HOLD − this signal indicates that another master is requesting the use of the address and
data buses.
HLDA (HOLD Acknowledge) − It indicates that the CPU has received the HOLD
request and it will relinquish the bus in the next clock cycle. HLDA is set to low after the
HOLD signal is removed.
Serial I/O signals
There are 2 serial signals, i.e. SID and SOD and these signals are used for serial communication.
SOD (Serial output data line) − the output SOD is set/reset as specified by the SIM
instruction.
SID (Serial input data line) − the data on this line is loaded into accumulator whenever a
RIM instruction is executed. Relevant Explanation of 10 Pins----3Marks

2 a. Maximum mode 8086 Configuration

Diagram 4 Marks
Explanation 3 Marks

Maximum mode Configuration: In this we can connect more processors to 8086 (8087/8089).
8086 max mode is basically for implementation of allocation of global resources and passing bus
control to other coprocessor (i.e. second processor in the system), because two processors cannot
access system bus at same instant. All processors execute their own program.

When MN/ MX’ = 0 , 8086 works in max mode. Clock is provided by 8284 clock generator.
8288 bus controller- Address form the address bus is latched into 8282 8-bit latch. Three such
latches are required because address bus is 20 bit.
The ALE (Address latch enable) is connected to STB (Strobe) of the latch. The ALE for latch is
given by 8288 bus controller.
The data bus is operated through 8286 8-bit transceiver. Two such transceivers are required,
because data bus is 16-bit. The transceivers are enabled the DEN signal, while the direction of
data is controlled by the DT/R signal. DEN is connected to OE’ and DT/ R’ is connected to T.
Both DEN and DT/ R’ are given by 8288 bus controller.

Control signals for all operations are generated by decoding S’2, S’1 and S’0 using 8288 bus
controller.
 Bus request is done using RQ’ / GT’ lines interfaced with 8086. RQ0/GT0 has more
priority than RQ1/GT1.
 INTA’ is given by 8288, in response to an interrupt on INTR line of 8086.
 In max mode, the advanced write signals get enabled one T-state in advance as
compared to normal write signals. This gives slower devices more time to get ready to
accept the data; therefore it reduces the number of cycles.

 It derives the outputs ALE, DEN*, DT/R*, MWTC*, AMWC*, IORC*, IOWC* and
AIOWC*.
 IORC*, IOWC* are I/O read command and I/O write command signals respectively.

 INTA* pin is used to issue two interrupt acknowledge pulses to the interrupt controller
or to an interrupting device.
2 b.
Register Organization Names 4 Marks
Explanation 3 Marks
General-purpose registers are used to store temporary data within the microprocessor. There are
8 general-purpose registers in the 8086 microprocessor.

AX: This is the accumulator. It is of 16 bits and is divided into two 8-bit registers AH and AL to
also perform 8-bit instructions. It is generally used for arithmetical and logical instructions but in
8086 microprocessor it is not mandatory to have an accumulator as the destination operand.
BX: This is the base register. It is of 16 bits and is divided into two 8-bit registers BH and BL to
also perform 8-bit instructions. It is used to store the value of the offset.
CX: This is the counter register. It is of 16 bits and is divided into two 8-bit registers CH and CL
to also perform 8-bit instructions. It is used in looping and rotation.
DX: This is the data register. It is of 16 bits and is divided into two 8-bit registers DH and DL to
also perform 8-bit instructions. It is used in the multiplication and input/output port addressing.
SP: This is the stack pointer. It is of 16 bits. It points to the topmost item of the stack. If the stack
is empty the stack pointer will be (FFFE)H. Its offset address is relative to the stack segment.
BP – This is the base pointer. It is of 16 bits. It is primarily used in accessing parameters passed
by the stack. Its offset address is relative to the stack segment.
SI – This is the source index register. It is of 16 bits. It is used in the pointer addressing of data
and as a source in some string-related operations. Its offset is relative to the data segment.
DI – This is the destination index register. It is of 16 bits. It is used in the pointer addressing of
data and as a destination in some string-related operations. Its offset is relative to the extra
segment
3 a. ASSEMBLER DIRECTIVES
Assembler Directives list 4 Marks
Explanation of any 3-3 Marks
Assembler directives are the Instructions to the Assembler, linker and loader regarding the
program being executed are also called ‘pseudo instructions. Control the generation of machine
codes and organization of the program; but no machine codes are generated for assembler
directives.
They are used to
› specify the start and end of a program
› attach value to variables
› allocate storage locations to input/ output data
› define start and end of segments, procedures, macros etc..
ASSUME
Used to tell the assembler the name of the logical segment it should use for a specified segment.
You must tell the assembler that what to assume for any segment you use in the program.
Example
ASSUME: CODE
Tells the assembler that the instructions for the program are in segment named CODE.
DB – Defined Byte
Used to declare a byte type variable or to set aside one or more locations of type byte in memory.
Example
PRICES DB 49H, 98H, 29H:
Declare array of 3 bytes named PRICES and initialize 3 bytes as shown.
DD – Define Double Word
Used to declare a variable of type double word or to reserve a memory location which can be
accessed as double word.
DQ – Define Quadword
Used to tell the assembler to declare the variable as 4 words of storage in memory.
DT – Define Ten Bytes
Used to tell the assembler to declare the variable which is 10 bytes in length or reserve 10 bytes
of storage in memory.
DW – Define Word
Used to tell the assembler to define a variable type as word or reserve word in memory.
DUP: used to initialize several locations and to assign values to location
END – End the Program
To tell the assembler to stop fetching the instruction and end the program execution.
ENDP – it is used to end the procedure.
ENDS – used to end the segment.
EQU – EQUATE
Used to give name to some value or symbol.
EVEN – Align On Even Memory Address
Tells the assembler to increment the location counter to the next even address if it is not already
at an even address.
EXTRN
Used to tell the assembler that the name or labels following the directive are in some other
assembly module.
INCLUDE – include source code from file
Used to tell the assembler to insert a block of source code from the named file into the current
source module. This shortens the source code.
LABEL
Used to give the name to the current value in the location counter. The LABEL directive must be
followed by a term which specifies the type you want associated with that name.
LENGTH
Used to determine the number of items in some data such as string or array.
NAME
Used to give a specific name to a module when the programs consisting of several modules.
OFFSET
It is an operator which tells the assembler to determine the offset or displacement of named data
item or procedure from the start of the segment which contains it.

3 b. ALP-Search for a byte in set of 10 Numbers

ALP with directives, initialization, instructions-4 Marks
ALP Program, comments-3Marks
Assume cs: code, ds: data
mov ax,3000 Linking,Intialization steps
mov es,ax
mov di,6000 Destination
mov ax,25 Byte data
mov cx,0A Set of ten numbers String count
mov bx,cx
cld
REPNE SCASB
Dec di
Mov dx,di
Sub bx,cx
Dec bx
Hlt stop

4 a. Data Transfer Instruction Set 8086

Data Transfer Instructions list -5 Marks
Explanation with Example -2 Marks
DATA TRANSFER INSTRUCTIONS These instructions are used to transfer the data from the
source operand to the destination operand. Following are the list of instructions under this group
INSTRUCTION TO TRANSFER A WORD
MOV − Used to copy the byte or word from the provided source to the provided destination.
Ex: mov ax,bx
PUSH − Used to put a word at the top of the stack. Ex: Push ax
POP − Used to get a word from the top of the stack to the provided location. Ex: Pop ax
PUSHA − Used to put all the registers into the stack.
POPA − Used to get words from the stack to all registers.
XCHG − Used to exchange the data from two locations. EX: XCHG ax, bx
XLAT − Used to translate a byte in AL using a table in the memory.
INSTRUCTIONS FOR INPUT AND OUTPUT PORT TRANSFER
IN − Used to read a byte or word from the provided port to the accumulator.
OUT − Used to send out a byte or word from the accumulator to the provided port.
INSTRUCTIONS TO TRANSFER THE ADDRESS
LEA − Used to load the address of operand into the provided register.
LDS − Used to load DS register and other provided register from the memory
LES − Used to load ES register and other provided register from the memory.
INSTRUCTIONS TO TRANSFER FLAG REGISTERS
LAHF − Used to load AH with the low byte of the flag register.
SAHF − Used to store AH register to low byte of the flag register.
PUSHF − Used to copy the flag register at the top of the stack.
POPF − Used to copy a word at the top of the stack to the flag register.

4 b. ALP –Factorial of given number

ALP with directives, initialization, instructions-4 Marks
ALP Program, comments-3Marks
DATA SEGMENT
N DB 06H
FACT DW
DATA ENDS
CODE SEGMENT
ASSUME CS: CODE, DS: DATA
START:
MOV AX, DATA ; Initialization
MOV DS, AX
MOV AX, 1
MOV BL, N
MOV BH, 0
CALL FACTORIAL
MOV FACT, AX
MOV AH, 4CH
INT 21H
FACTORIAL PROC
CMP BX, 1
JE L1
PUSH BX
DEC BX
CALL FACTORIAL
POP BX
MUL BX
L1: RET
FACTORIAL ENDP
CODE ENDS
END START
5 a. 8255 PPI
Diagram 5 Marks
Explanation 2 Marks

8255 PROGRAMMMABLE PERIPHERAL INTERFACE --8255 is a general purpose

programmable I/O device designed to interface the CPU with its outside world such as ADC,
DAC, keyboard etc. We can program it according to the given condition. It can be used with
almost any microprocessor. It consists of three 8-bit bidirectional I/O ports i.e. PORT A, PORT
B and PORT C. We can assign different ports as input or output functions.
It consists of 40 pins and operates in +5V regulated power supply. Port C is further divided into
two 4-bit ports i.e. port C lower and port C upper and port C can work in either BSR (bit set rest)
mode or in mode 0 of input-output mode of 8255. Port B can work in either mode 0 or in mode 1
of input-output mode. Port A can work either in mode 0, mode 1 or mode 2 of input-output
mode. It has two control groups, control group A and control group B. Control group A consist
of port A and port C upper. Control group B consists of port C lower and port B. Depending
upon the value if CS’, A1 and A0 we can select different ports in different modes as input-output
function or BSR. This is done by writing a suitable word in control register (control word D0-
D7).

It stands for Chip Select. A LOW on this input selects the chip and enables the communication
between the 8255A and the CPU. It is connected to the decoded address, and A0 & A1 are
connected to the microprocessor address lines. Their result depends on the above conditions −
These input signals work with RD, WR, and one of the control signal.

Relevant Explanation of above –2 Marks

5 b. 8257 DMA Interface to 8086
Diagram—4 Marks
Explanation-3 Marks

DMA stands for Direct Memory Access. It is designed by Intel to transfer data at the fastest rate.
It allows the device to transfer the data directly to/from memory without any interference of the
CPU.Using a DMA controller, the device requests the CPU to hold its data, address and control
bus, so the device is free to transfer data directly to/from the memory. The DMA data transfer is
initiated only after receiving HLDA signal from the CPU.
Following is the sequence of operations performed by a DMA −
 Initially, when any device has to send data between the device and the memory, the
device has to send DMA request (DRQ) to DMA controller.
 The DMA controller sends Hold request (HRQ) to the CPU and waits for the CPU to
assert the HLDA.
 Then the microprocessor tri-states all the data bus, address bus, and control bus. The CPU
leaves the control over bus and acknowledges the HOLD request through HLDA signal.
 Now the CPU is in HOLD state and the DMA controller has to manage the operations
over buses between the CPU, memory, and I/O devices.

6 a. Interface of ADC with 8086 along with 8255 PPI

Interface Diagram-4 Marks
Explanation-3 Marks

SOC-Start of Conversion
EOC-End of Conversion
Signals in the real world are analog: light, sound, temperature, pressure, acceleration or other
phenomenon. So, real-world signals must be converted into digital, using a circuit called ADC
(Analog-to-Digital Converter), before they can be manipulated by digital equipment.
The time taken by the ADC from the active edge of SOC pulse till the active edge of EOC signal
is called as the conversion delay of the ADC.
General algorithm for ADC interfacing contains the following steps
1. Ensure the stability of analog input, applied to the ADC
2. Issue start of conversion SOC pulse to ADC
3. Read end of conversion EOC signal to mark the end of conversion process
4. Read digital data output of the ADC as equivalent digital output.
The analog to digital converter chips 0808 and 0809 are 8- bit CMOS, successive approximation
converters. It is fastest technique. The conversion delay is 100 µs at a clock frequency of 640
kHz, which is quite low as compared to other converters. This converter internally has a 3:8
analog multiplexer, so that at a time 8 different analog inputs can be connected to the chips. Out
of these 8 inputs only one can be selected for conversion by using 3 address lines A, B, C. The
CPU may drive these lines using output port lines in case of multichannel applications.

Relevant Explanation -3 Marks

6 b.Interrupt Service Routine and Interrupt table
ISR 3 Marks
Interrupt Table 3 Marks
Interrupt: An interrupt is a signal to the processor emitted by hardware or software indicating an
event that needs immediate attention. Whenever an interrupt occurs, the controller completes the
execution of the current instruction and starts the execution of an Interrupt Service
Routine (ISR) or Interrupt Handler. ISR tells the processor or controller what to do when the
interrupt occurs. The interrupts can be either hardware interrupts or software interrupts.
Sources of Interrupt
1. External signal/Hardware
2. Special Instruction in the program
3. Condition produced by instruction/Software
External signal/Hardware an 8086 can get interrupt from an external signal applied to the
nonmaskable interrupt (NMI) input pin; or the interrupt (INTR) input pin.
Special Instruction in the program
Interrupt Structure of 8086 supports a special instruction, INT to execute special program. At the
end of the interrupt service routine, execution is usually returned to the interrupted program.
Condition produced by instruction/Software
An 8086 is interrupted by some condition produced in the 8086 by the execution of an
instruction. For example divide by zero: Program execution will automatically be interrupted if
you attempt to divide an operand by zero.
At the end of each instruction cycle 8086 interrupts checks to see if there is any interrupt request.
If so, 8086 responds to the interrupt by performing series of actions
1. It decrements stack pointer by 2 and pushes the flag register on the stack..
2. It disables the INTR interrupt input by clearing the interrupt flag in the flag
3. It resets the trap flag in the flag register.
4. It decrements stack pointer by 2 and pushes the current code segment register contents on
the stack.
5. It decrements stack pointer by 2 and pushes the current instruction pointer contents on the
stack.
6. It does an indirect far jump at the start of the procedure by loading the CS and IP values
for the start of the interrupt service routine (ISR).

An IRET instruction at the end of the interrupt service procedure returns execution to the main
program.
Interrupt Vector Table 8086:
The 8086 gets the new values of CS and IP register from four memory addresses. When it
responds to an interrupt, the 8686 goes to memory locations to get the CS and IP values for the
start of the interrupt service routine. In an Interrupt Structure of 8086 system the first 1 Kbyte of
memory from 00000H to 003FFH is reserved for storing the starting addresses of interrupt
service routines. This block of memory is often called the Interrupt Vector Table in 8086 or
the interrupt pointer table. Since 4 bytes are required to store the CS and IP values for each
interrupt service procedure, the table can hold the starting addresses for 256 interrupt service
routines. Fig. 9.2 shows how the 256 interrupt pointers are arranged in the memory table.

Each interrupt type is given a number between 0 to 255 and the address of each interrupt js
found by multiplying the type by 4 e.g. for type 11, interrupt address is 11 x 4 = 4410= 0002CH

Only first five types have explicit definitions such as divide by zero and non maskable interrupt.
The next 27 interrupt types, from 5 to 31, are reserved by Intel for use in future microprocessors.
The upper 224 interrupt types, from 32 to 255, are available for user for hardware or software
interrupts.

7 a.
Definition 2 Marks
Features 3Marks
5 Interrupt sources 2 Marks
Microcontroller is a semiconductor IC that itself contains microprocessor, ports, timers,
counters, memory etc., on the same IC
Features
8051 microcontroller is designed by Intel in 1981.
It is an 8-bit microcontroller.
It is built with 40 pins DIP (dual inline package), 4kb of ROM storage and 128 bytes of RAM
storage, 2 16-bit timers.
It consists of are four parallel 8-bit ports, which are programmable as well as addressable as per
the requirement.
An on-chip crystal oscillator is integrated in the microcontroller having crystal frequency of 12
MHz
system bus connects all the support devices to the CPU. The system bus consists of an 8-bit data
bus, a 16-bit address bus and bus control signals. All other devices like program memory, ports,
data memory, serial interface, interrupt control, timers, and the CPU are all interfaced together
through the system bus.it having four register banks,64K bytes on-chip programmable memory
(ROM),128 user defined flags,16 bit timers,32 general purpose registers each of 8-bit 8051
microcontroller offers a number of special features such as ADC, UARTs, Op-amp, etc.

Interrupts are the events that temporarily suspend the main program, pass the control to the
external sources and execute their task. It then passes the control to the main program where it
had left off.8051 has 5 interrupt signals, i.e. INT0, TFO, INT1, TF1, RI/TI. Each interrupt can
be enabled or disabled by setting bits of the IE register and the whole interrupt system can be
disabled by clearing the EA bit of the same register.

7 b. Addressing modes of 8051

Addressing modes list 4 Marks
Explanation 3 Marks
In 8051 there are six types of addressing modes.
Immediate Addressing Mode
Register Addressing Mode
Direct Addressing Mode
Register Indirect Addressing Mode
Indexed Addressing Mode
Implied Addressing Mode
Immediate addressing mode
In this Immediate Addressing Mode, the data is provided in the instruction itself. The data is
provided immediately after the opcode.
MOVA, #0AFH;
In these instructions, the # symbol is used for immediate data.
Register addressing mode
In the register addressing mode the source or destination data should be present in a register (R0
to R7).
MOVA, R5;
Direct Addressing Mode
In the Direct Addressing Mode, the source or destination address is specified by using 8-bit data
in the instruction. Only the internal data memory can be used in this mode.
MOV 80H, R6;
Register indirect addressing Mode
In this mode, the source or destination address is given in the register. By using register indirect
addressing mode, the internal or external addresses can be accessed. The R0 and R1 are used for
8-bit addresses, and DPTR is used for 16-bit addresses, no other registers can be used for
addressing purposes.
MOV 0E5H, @R0;
In the instructions, the @ symbol is used for register indirect addressing.
Indexed addressing mode
In the indexed addressing mode, the source memory can only be accessed from program memory
only. The destination operand is always the register A. These are some examples of Indexed
addressing mode.
MOVCA, @A+PC
Implied Addressing Mode
In the implied addressing mode, there will be a single operand. These types of instruction can
work on specific registers only. These types of instructions are also known as register specific
instruction.
RLA;
SWAPA;
These are 1- byte instruction. The first one is used to rotate the A register content to the Left. The
second one is used to swap the nibbles in A.

8 a. Memory Organization 8051

Memory Organization Representation 4 Marks
Explanation 3 Marks

8051 Memory Organization The 8051 microcontroller's memory is divided into

1. Program Memory
2. Data Memory.
Program Memory (ROM) is used for permanent saving program being executed, while Data
Memory (RAM) is used for temporarily storing and keeping intermediate results and variables.
Program Memory (ROM) Program Memory (ROM) is used for permanent saving program
(CODE) being executed. The memory is read only. Depending on the settings made in compiler,
program memory may also used to store constant variables. The 8051 executes programs stored
in program memory only. Code memory type specifier is used to refer to program memory. 8051
memory organization allows external program memory to be added. How does the
microcontroller handle external memory depends on the pin EA logical state.
Up to 256 bytes of internal data memory are available depending on the 8051 derivative.
Locations available to the user occupy addressing space from 0 to 7Fh, i.e. first 128 registers and
this part of RAM is divided in several blocks. The first 128 bytes of internal data memory are
both directly and indirectly addressable. The upper 128 bytes of data memory (from 0x80 to
0xFF) can be addressed only indirectly. Since internal data memory is used for CALL stack also
and there is only 256 bytes splited over few different memory areas fine utilizing of this memory
is crucial for fast and compact code. Memory block in the range of 20h to 2Fh is bit-addressable,
which means that each bit being there has its own address from 0 to 7Fh
.

Access to external memory is slower than access to internal data memory. There may be up to
64K Bytes of external data memory. Several 8051 devices provide on-chip XRAM space that is
accessed with the same instructions as the traditional external data space. This XRAM space is
typically enabled via proper setting of SFR register and overlaps the external memory space.
Setting of that register must be manually done in code, before any access to external memory or
XRAM space is made.

8 b.
Calculations, Directives, Instructions, program flow 4 Marks
ALP 3 Marks
To toggle all the bits of port 1 for every 200ms, we need to use a timer interrupt to generate an
interrupt every 200ms. In the interrupt service routine (ISR), we can toggle all the bits of port 1.
Here are the calculations needed:
1. Crystal frequency: 11.0592MHz
2. Machine cycle frequency: Crystal frequency/12 = 921.6kHz
3. Timer 0 mode: 16-bit timer mode
4. Timer 0 initial value: 65536 - (200ms * Machine cycle frequency) = 65536 - (200ms *
921.6kHz) = 65536 - 184320 = 47016 (decimal)
5. Timer 0 reload value: Same as initial value (47016 decimal)
6. Timer 0 interrupt frequency: Machine cycle frequency / Timer 0 reload value = 921.6kHz
/ 47016 = 19.6Hz
 Org 0h; Set the origin to 00H
Mov P1,#00H;Initialize port 1 to 0
Mov Tmod,#01H;set timer0 to 16 bit mode
Mov TH0, Highbyte (47016) set timer0 to high value;
Mov TL0, lowerbyte (47016) set timer0 to high value;
SetB TR0; start Timer0
SetB EA; Enable global Interrupts Main
SJMP Main; loop timer0 forever Timer0_ISR
CPL P1; Toggle all bits of port1
RETI; Return from Interrupt

9 a. ADC Interfacing with 8051

Interface Diagram 5 Marks
Explanation 2 Marks
The data we process in a microcontroller normally deals with digital signals. But there may a situation
where we have to deal with external inputs such as analog signals. All most all the input signals from
physical sensors are of analog signals. In such cases, we can interface the microcontroller with an external
device such as an ADC0808 to convert the analog signal to a digital signal. Because microcontrollers can
only understand 0 and 1.

Steps to follow
1. Start
2. Select the channel using Address pins.
3. A Low – High transition on ALE to latch in the address.
4. A Low – High transition on Start to reset the ADC’s SAR.
5. A High – Low transition on ALE.
6. A High – Low transition on start to start the conversion.
7. Wait for End of cycle (EOC) pin to become high.
8. Make Output Enable pin High.
9. Take Data from the ADC’s output
10. Make Output Enable pin Low.
11. Stop
9 b. Programming the 8051 to receive data serially
Steps and Relevant Explanation 7 marks
In programming the 8051 to receive character bytes serially, the following steps must be taken.
1. The TMOD register is loaded with the value 20H, indicating the use of Timer 1 in mode2 to
set the baud rate.
2. TH1 is loaded with one of the values in Table(2) to set the baud rate.
3. The SCON register is loaded with the value 50H, indicating serial mode 1, where 8-bit data is
framed with start and stop bits and receive enable is turned on.
4. TR1 is set to 1 to start Timer 1.
5. RI is cleared with the “CLR RI” instruction.
6. The RI flag bit is monitored with the use of the instruction “JNB RI, xx” to see if an entire
character has been received yet.
7. When RI is raised, SBUF has the byte. Its contents are moved into safe place.
8. To receive the next character, go to Step 5.

10 a.
TCON Register format 3 Marks
SCON Register Format 3 Marks
Explanation 1 Mark
TCON (Timer Control register) TCON is an 8-bit register. Its bits are used for generating
interrupts internal or external. The most important bits of the timer TR and TF are also in it.

TR (timer run) and TF (timer overflow) bits which we use in almost all over timer applications
are in it.
TF1 Timer 1 Overflow flag. Set when timer overflows. Clear by software
TR1 set to enable Timer 1
TF0 Timer 0 Overflow flag. Set when timer overflows. Clear by software
TR0 Set to enable Timer 0
IEI Interrupt flag for interrupt 1
ITI Set for negative edge trigger for interrupt 1, clear for level trigger
IE0 Interrupt flag for interrupt 0
IT0 Set for negative edge trigger for interrupt 0, clear for level trigger
SCON (Serial Control) it’s an 8 bit register, Used for serial data communication. It is bit
addressable.

SM0, SM1 and SM2 are used to specify the serial connection mode. There are five different
modes four are shown above in the diagram. The fifth one is when we make SM2=1 which is 8-
bit transfer mode. The most common mode is mode 1.
REN is Receive Enable, when REN=1 it allows the 8051 to receive and transfer data . If you
want 8051 to both transfer and receive data, REN must be set to ‘1’. when REN=0 it means
receiver is disabled.
TB8 and RB8 is used for serial modes 2 and 3.
TI and RI are important bits. TI is Transmit Interrupt flag, When 8051 micro controller finishs
the transfer of 8-bit character, it raises the TI flag to indicate that it is ready to transfer another
byte. RI is Receive Interrupt flag, When 8051 receive data via RxD pin(Port1 pin 0), it get rid of
the start and stop bits and places the byte in the SBUF. Then it raises the RI flag to indicate that a
byte has been received and should be picked up before it is lost.

10 b. Interfacing 7 Segment Display to 8051

Diagram-5 Marks
Explanation-2Marks

Seven segment displays are used to indicate numerical information. Seven segments display can
display digits from 0 to 9 and even we can display few characters like A, b, C, H, E, e, F, etc.
These are very popular and have many more applications. This system displays the digits from 0
to 9 continuously with a predefined delay. In the process, seven segment displays internally
consist of 8 LEDs. In these LEDs, 7 LEDs are used to indicate the digits 0 to 9 and single LED is
used for indicating decimal point. Generally seven segments are two types, one is common
cathode and the other is common anode. In common cathode, all the cathodes of LEDs are tied
together and labeled as com. and the anode are left alone. In common anode, seven segment
display all the anodes are tied together and cathodes are left freely. Below figure shows the
internal connections of seven segment Display.