Module-2

Interfacing Devices &

Introduction to 8086
By
Dr. Venkata Sridhar .TM.Tech, PhD, FIETE

Assistant Professor
Dept. of ETC, IIIT-Bhubaneswar.
 Syllabus : Module-2
Interfacing: Programmable peripheral interface 8255, ADC, DAC, Relay and
Stepper Motor interfacing.

Special Purpose Programmable Peripheral Devices and Their Interfacing:

Programmable Interrupt Controller 8259A, Programmable Communication
Interface 8251 USART, Programmable Interval Timer 8253/54 and Introduction
to DMA Controller: DMA Transfers and Operations.

Introduction to 8086 Microprocessor: Architecture, Register Organization,

Physical Memory Organizations

2
By T.VenkataSridhar, ETC
 Interfacing Devices
8255 PPI Programmable Peripheral Interface

8251 USART Universal Synchronous Asynchronous

Receiver and Transmitter

8259 PIC programmable Interrupt Controller

8257 DMA Direct Memory Access Controller

8253 PIT programmable Interval Timer

3
8279 KDC Keyboard and Display Controller
By T.VenkataSridhar, ETC
 8255- PPI
Features:
It is a programmable device.

It has 24 I/O programmable pins like PA,PB,PC

(3-8 pins).

T T L compatible.

Improved dc driving capability

4 By T.VenkataSridhar, ETC
 Block Diagram

5 By T.VenkataSridhar, ETC
 Pin Diagram

6 By T.VenkataSridhar, ETC
 Function of pins:
Data bus(D -D ):These are 8-bit bi-directional
0 7
buses, connected to 8085 data bus for
transferring data.

CS: This is Active Low signal. When it is low,

then data is transfer from 8085.

Read: This is Active Low signal, when it is Low

read operation will be start.

Write: This is Active Low signal, when it is Low

Write operation will be start.
7 By T.VenkataSridhar, ETC
 Address (A0-A1):This is used to select the ports. like
this

A1 A0 Select

0 0 PA

0 1 PB

1 0 PC

1 1 Control Word Reg.

8 By T.VenkataSridhar, ETC
  RESET: This is used to reset the device. That
means clear control registers.

 PA -PA :It is the 8-bit bi-directional I/O pins

0 7
used to send the data to peripheral or
or to receive the data from peripheral.

 PB -PB :Similar to PA
0 7

 PC -PC :This is also 8-bit bidirectional I/O

0 7
pins. These lines are divided into two groups.
1. PC0 to PC3(Lower Groups)
2. PC4 to PC7 (Higher groups)
These two groups working in separately using
4 data’s.
9 By T.VenkataSridhar, ETC
 Operation modes (2)
(1) BIT SET/RESET MODE:
The PORT C can be Set or Reset by sending OUT
instruction to the CONTROL registers.
(2) I/O MODES: (Mode 0, Mode1 and Mode 2)
MODE 0 (Simple input / Output):
In this mode , port A, port B and port C is used as
individually (Simply).
Features:
Outputs are latched , Inputs are buffered not
latched.
Ports do not have Handshake or interrupt
10 capability. By T.VenkataSridhar, ETC
 MODE 1 :(Input/output with Hand shake)
In this mode, input or output is transferred by hand
shaking Signals.

DATA BUS
STB
Computer Printer
ACK
Busy

Handshaking signals is used to transfer data

between whose data transfer is not same.

11 By T.VenkataSridhar, ETC
 MODE 2: Strobe bi-directional I/O data transfer:
 This mode allows bidirectional data transfer over a single 8-bit data bus using
handshake signals.
 This feature is possible only Group A
 Port A is working as 8-biy bidirectional.
 PC3-PC7 is used for handshaking purpose.
 The data is sent by CPU through this port , when the peripheral request it.

 Mode 0
 Basic I/O
 Mode 1
 Strobe I/O
 Mode 2
 Bi-Dir Bus

12 By T.VenkataSridhar, ETC
 CONTROL WORD FORMATS:
1. In the INPUT mode , When RESET is High all 24 pins (3-ports)
be a input mode.
2. i.e all flip flops are cleared, and the interrupts are rest.
3. This condition is maintained even after RESET goes low.
4. This can be avoided by writing single control word to the
control registers , when required

FOR BIT SET/RESET MODE:

13
 CWR FOR I/O MODE:

14 By T.VenkataSridhar, ETC
 Strobed mode

Or
Or
8085(2)
8085(1)

15 By T.VenkataSridhar, ETC
 8255 Interfacings

Or
8085
System

16 By T.VenkataSridhar, ETC
 8255 Interfacings contd..

17 By T.VenkataSridhar, ETC
 8255 Interfacings contd..

18 By T.VenkataSridhar, ETC
 Relays understanding
A relay is an electrically operated switch. Many relays use
an electromagnet to mechanically operate a switch, but other operating
principles are also used, such as solid-state relays. Relays are used
where it is necessary to control a circuit by a separate low-power
signal, or where several circuits must be controlled by one signal.

19 By T.VenkataSridhar, ETC
 Interfacing a relay with 8085 via 8255 to run High load device

Execute a
Program to
enable or
energise
the coil.

20 By T.VenkataSridhar, ETC
 Stepper Motor Interfacing

21 By T.VenkataSridhar, ETC
22 By T.VenkataSridhar, ETC
 Interfacing Analog to Digital Data
Converters

• In most of the cases, the PIO 8255 is used for interfacing the
analog to digital converters with microprocessor.
• The analog to digital converters is treaded as an input device by
the microprocessor / controller , that sends an initialising signal to
the ADC to start the analogy to digital data conversation process.
The start of conversation signal is a pulse of a specific duration.
• The process of analog to digital conversion is a slow process, and
the microprocessor has to wait for the digital data till the
conversion is over. After the conversion is over, the ADC sends end
of conversion EOC signal to inform the microprocessor that the
conversion is over and the result is ready at the output buffer of the
ADC. These tasks of issuing an SOC pulse to ADC, reading EOC
signal from the ADC and reading the digital output of the ADC are
23
carried out by the CPU using 8255 I/O ports. By T.VenkataSridhar, ETC
 • The time taken by the ADC from the active edge of SOC pulse till
the active edge of EOC signal is called as the conversion delay of
the ADC.
• It may range any where from a few microseconds in case of fast
ADC to even a few hundred milliseconds in case of slow ADCs.
• The available ADC in the market use different conversion
techniques for conversion of analog signal to digitals. Successive
approximation techniques and dual slope integration techniques are
the most popular techniques used in the integrated ADC chip.

General algorithm for ADC interfacing contains the following steps:

1. Ensure the stability of analog input, applied to the ADC.
2. Issue start of conversion pulse to ADC
3. Read end of conversion signal to mark the end of conversion
processes.
4. Read digital data output of the ADC as equivalent digital output.
24 By T.VenkataSridhar, ETC
 ADC 0808/0809 :
• The analog to digital converter chips 0808 and 0809 are 8- bit
CMOS, successive approximation converters. This technique is one of
the fast techniques for analog to digital conversion. The conversion
delay is 100μs at a clock frequency of 640 KHz, which is quite low as
compared to other converters. These converters do not need any
external zero or full scale adjustments as they are already taken care of
by internal circuits. These converters internally have a 3:8 analog
multiplexer so that at a time eight different analog conversion by using
address lines - ADD A, ADD B, ADD C. Using these address inputs,
multichannel data acquisition system can be designed using a single
ADC. The CPU may drive these lines using output port lines in case of
multichannel applications. In case of single input applications, these
may be hardwired to select the proper input.
• There are unipolar analog to digital converters, i.e. they are able to
convert only positive analog input voltage to their digital equivalent.
These chips do no contain any internal sample and hold circuit.
25 By T.VenkataSridhar, ETC
26 By T.VenkataSridhar, ETC
27 By T.VenkataSridhar, ETC
 -

Read the digital data

Select the desired address

Try to develop
different programs
with 8085/86/51

Or 8085
28 By T.VenkataSridhar, ETC
 Interfacing Digital To Analog Converters
• INTERFACING DIGITAL TO ANALOG CONVERTERS: The
digital to analog converters convert binary number into their
equivalent voltages. The DAC find applications in areas like
digitally controlled gains, motors speed controls, programmable
gain amplifiers etc.

• AD 7523 8-bit Multiplying DAC : This is a 16 pin DIP,

multiplying digital to analog converter, containing R-2R ladder
for D-A conversion along with single pole double thrown NMOS
switches to connect the digital inputs to the ladder.

• The pin diagram of AD7523 is shown in fig the supply range is

from +5V to +15V, while Vref may be any where between -10V to
+10V. The maximum analog output voltage will be any where
between -10V to +10V, when all the digital inputs are at logic high
29
state.
By T.VenkataSridhar, ETC
 • Usually a zener is connected between OUT1 and OUT2 to save
the DAC from negative transients. An operational amplifier is used
as a current to voltage converter at the output of AD to convert the
current out put of AD to a proportional output voltage.
30 By T.VenkataSridhar, ETC
 • It also offers additional drive capability to the DAC output. An
external feedback resistor acts to control the gain. One may not
connect any external feedback resistor, if no gain control is required.

31 By T.VenkataSridhar, ETC
 8251- USART

32 By T.VenkataSridhar, ETC
33 By T.VenkataSridhar, ETC
34 By T.VenkataSridhar, ETC
35 By T.VenkataSridhar, ETC
 RS-232C
 A widely accepted interface standard originally developed to foster data
communication on public telephone network through a modem
(modulatordemodulator). This has been adapted to the communication of
terminals (PCs) directly to computer.

Fig: Null mode connection

36 By T.VenkataSridhar, ETC
  The 8251 USART (Universal Synchronous Asynchronous
Receiver Transmitter) is capable of implementing either an
asynchronous or synchronous serial data communication.

 As a peripheral device of a microcomputer system, the

8251 receives parallel data from the CPU and transmits serial data
after conversion.

 This device also receives serial data from the outside and
transmits parallel data to the CPU after conversion.

37 By T.VenkataSridhar, ETC
 Block diagram of 8251

38 By T.VenkataSridhar, ETC
39 By T.VenkataSridhar M.Tech,MIETE
40 By T.VenkataSridhar, ETC
41 By T.VenkataSridhar, ETC
 Control Registers:  MI-Mode Instruction Reg.
 CI-Command “ “.
 Status Reg.

42 By T.VenkataSridhar, ETC
43 By T.VenkataSridhar, ETC
44 By T.VenkataSridhar, ETC
45 By T.VenkataSridhar, ETC
 Fig: Interfacing with 8085.
46 By T.VenkataSridhar M.Tech,MIETE
47 By T.VenkataSridhar M.Tech,MIETE
 8086

48 By T.VenkataSridhar, ETC
 8259 – Programmable Interrupt Controller
* Topics beyond syllabus starts.. SKIP

49 Internal Architecture of the 8259A By T.VenkataSridhar, ETC

 Command Words:  ICW(4)
 OCW(3)

50 By T.VenkataSridhar, ETC
51
 Initialization Command Word (ICW1, ICW2)

52 By T.VenkataSridhar, ETC
 ICW 3, ICW4

53 By T.VenkataSridhar, ETC
54 By T.VenkataSridhar, ETC
 Interfacing with Processor - 8085

55 By T.VenkataSridhar, ETC
 Interfacing with - 8086

56 By T.VenkataSridhar, ETC
 8257 – Direct Memory Access Controller

57 By T.VenkataSridhar, ETC
58 By T.VenkataSridhar M.Tech,MIETE
By T.VenkataSridhar, ETC
 Pin-diagram of DMA-8237

59 By T.VenkataSridhar M.Tech,MIETE
By T.VenkataSridhar, ETC
 Control Registers of DMA-8237
 CAR (Current Address Register): holds the 16-bit memory address
used for the DMA transfer (one for each channel), either
incremented or decremented during the operation
 CWCR (Current Word Count Register): Programs a channel for the
number of bytes (up to 64K) transferred during a DMA operation
 BA (Base Address) and WC (Word Count): Used when auto-
initialization is selected for a channel, to reload the CAR and CWCR
when DMA is complete.
 CR (Command Register): Programs the operation of the controller

60
By T.VenkataSridhar, ETC
MR (Mode Register): Programs the mode of
operation for a channel (one for each channel).

 RR (Request Register): Used to

request DMA transfer via
software (memory-to-memory
61
transfers)
By T.VenkataSridhar, ETC
 MR (Mask Register):

 SR (Status Register): Shows the status of each DMA channel

62 By T.VenkataSridhar, ETC
 Programming the 8237
First program the address and count registers first:
1. Clear the F/L flip-flop with a clear F/L command
2. Disable the channel
3. Program the LSB and then MSB of the address
4. Program the LSB and then MSB of the count
select the mode of operation
Enable channel
Example(with 8086)
 Design the 8237/57 decoding circuit and the 8237/57
address line connections so that the 8237/57 is in the
address range 70h-7Fh.
 Write a program that starts a block memory-to-memory
DMA transfer from memory locations 10000H-13FFFH to
63
14000H-17FFFH using channel 0 as source and channel
By T.VenkataSridhar, ETC
 8237 Programming Example

CLEAR_FF EQU 7CH ;F/L CLEAR VALUE

CH0_A EQU 70H ;CHANNEL 0 ADDRESS
CH1_A EQU 72H ;CHANNEL 1 ADDRESS
CH1_C EQU 73H ;CHANNEL 1 COUNT
MODE EQU 7BH ;MODE
CR EQU 78H ;COMMAND REGISTER
MASKS EQU 7FH ;MASKS
REQ EQU 79H ;REQUEST REGISTER
STATUS EQU 78H ;STATUS REGISTER
;ES = segment of source and destination
;SI = source address
;DI = destination address
;CX = count
DMA PROC FAR
MOV AL, 0
OUT CLEAR_FF, AL ;CLEAR F/L FF
MOV AX, ES ;PROGRAM SOURCE ADDRESS
SHL AX, 4 ;SHIFT LEFT SEGMENT
ADD AX, SI ;ADD SOURCE OFFSET
OUT CH0_A, AL ;CHANNEL 0 ADDRESS PROGRAMMING LSB FIRST
MOV AL, AH ;ONLY AL ALLOWED IN IN/OUT INSTRUCTIONS
OUT CH0_A, AL ;CHANNEL 0 ADDRESS PROGRAMMING MSB LAST

64 By T.VenkataSridhar, ETC
 EXAMPLE (CONTINUED)

MOV AX, ES ;PROGRAM DESTINATION ADDRESS

SHL AX, 4;SHIFT LEFT SEGMENT
ADD AX, DI ;ADD DESTINATION OFFSET
OUT CH1_A, AL ;CHANNEL 1 ADDRESS PROGRAMMING LSB FIRST
MOV AL, AH ;ONLY AL ALLOWED IN IN/OUT INSTRUCTIONS
OUT CH1_A, AL ;CHANNEL 1 ADDRESS PROGRAMMING MSB FIRST
MOV AX, CX ;PROGRAM COUNT
DEC AX ;ADJUST COUNT
OUT CH1_C, AL ;MOVE TO CHANNEL 1 COUNT
MOV AL, AH
OUT CH1_C, AL

MOV AL, 88H ;PROGRAM MODE

OUT MODE, AL

MOV AL,1 ;MEMORY-TO-MEMORY TRANSFER

OUT CR, AL

MOV AL, 0EH ;UNMASK CHANNEL 0

OUT MASKS, AL

MOV AL, 4;START DMA TRANSFER BY SETTING REQUEST BIT FOR CHANNEL 2
OUT REQ, AL

65 By T.VenkataSridhar, ETC
66
 8253 - Programmable Interval Timer
 PIT
(programmable
Interval Timer),
used to bring
down the
frequency
Three
to the
counters
desired level.
inside
8253/8254. Each
works
independently
and is
programmed
separately to
divide the input
 There are 4by
frequency porta
address
number needed
from 1
for a
to 65536. single
8253/8254,
given by A0, A1,
67
and CS. By T.VenkataSridhar, ETC
68 By T.VenkataSridhar, ETC
69 By T.VenkataSridhar, ETC
70 By T.VenkataSridhar, ETC
71 By T.VenkataSridhar, ETC
72 By T.VenkataSridhar, ETC
 8279 – Keyboard & Display Controller
 Intel's 8279 is a general purpose keyboard display controller
that simultaneously drives the display of a system and interfaces
a keyboard with the CPU, leaving it free for its routine task.

 The keyboard/display interface scans the keyboard to identify

if any key has been pressed and sends the code of the pressed
key to the CPU. It also transmits the data received from the CPU,
to the display device.

 Both of these functions are performed by the controller in

repetitive fashion without involving the CPU. The keyboard is
interfaced either in the interrupt or the polled mode.
73
By T.VenkataSridhar, ETC
8279 Internal Architecture

74
By T.VenkataSridhar, ETC
8279 Pin Diagram

75 8279 Pin Configuration(a) and Logic Diagram(b)

By T.VenkataSridhar, ETC
8279 Pin Description
DBo-DB7 These are bidirectional data bus lines. The data and command words to and from
the CPU are transferred on these lines.
CLK This is a clock input used to generate internal timings required by 8279.
RESET This pin is used to reset 8279. A high on this line resets 8279. After resetting 8279,
its in sixteen 8-bit display, left entry encoded scan, 2-key lock out mode. The clock
prescaler is set to 31.
CS’ Chip Select: A low on this line enables 8279 for normal read or write operations.
Otherwise, this pin should remain high.
Ao A high on the Ao line indicates the transfer of a command or status information. A low
on this line indicates the transfer of data. This is used to select one of the internal registers
of 8279.
RD’, WR’ (Input/Output) READ/WRITE input pins enable the data buffes to receive or
send data over the data bus.
IRQ This interrupt output line goes high when there is data in the FIFO sensor RAM. The
interrupt line goes low with each FIFO RAM read operation. However, if the FIFO RAM
further contains any key-code entry to be read by the CPU, this pin again goes high to
generate an interrupt to the CPU.

76
By T.VenkataSridhar, ETC
8279 Pin Description Conti…
Vss, Vcc These are the ground and power supply lines for the circuit.
SLo-SL3-Scan Lines These lines are used to scan the keyboard matrix and display digits.
These lines can be programmed as encoded or decoded, using the mode control register.
RLo-RL7-Return Lines These are the input lines which are connected to one terminal of
keys, while the other terminal of the keys are connected to the decoded scan lines. These
are normally high, but pulled low when a key is pressed.
SHIFT The status of the shift input line is stored along with each key code in FIFO in
the scanned keyboard mode. Till it is pulled low with. a key closure it is pulled up
internally to keep it high.
CNTL/STB-CONTROL/STROBED I/P Mode In the keyboard mode, this line is
used as a control input and stored in FIFO on a key closure. The line is a strobe line
that enters the data into FIFO RAM, in the strobed input mode. It has an internal pull
up. The line is pulled down with a key closure.
BD-Blank Display This output pin is used to blank the display during digit switching or
by a blanking command.
OUTAo - OUTA3 and OUTBo-OUTB3 These are the output ports for two 16 x 4 (or
one 16 x 8) internal display refresh registers. The data from these-lines is synchronized
with the scan lines to scan the display and keyboard. The two 4-bit ports may also be
77 used as one 8-bit port.
By T.VenkataSridhar, ETC
Modes of Operation of 8279
The modes of operation of 8279 are:
(i) Input (Keyboard) modes
(ii) Output (Display) modes
 Input (Keyboard) Modes 8279 provides three input modes which are:

1. Scanned Keyboard Mode This mode allows a key matrix to be interfaced using
either encoded or decoded scans. In the encoded scan, an 8 x 8 keyboard or in decoded
scan, a 4 x 8 keyboard can be interfaced. The code of key pressed with SHIFT and
CONTROL status is stored into the FIFO RAM.

2. Scanned Sensor Matrix In this mode, a sensor array can be interfaced with 8279
using either encoded or decoded scans. With encoded scan 8 x 8 sensor matrix or with
decoded scan 4 x 8 sensor matrix can be interfaced. The sensor codes are stored in the
CPU addressable sensor RAM.

3. Strobed input In this mode, if the control line goes low, the data on return lines, is
stored in the FIFO byte by byte.

78
By T.VenkataSridhar, ETC
Modes of Operation of 8279
 Output (Display) Modes 8279 provides two output modes for selecting the display
options. These are:

1. Display Scan In this mode, 8279 provides 8 or 16 character multiplexed displays

those can be organized as dual 4-bit or single 8-bit display units.

2. Display Entry (right entry or left entry mode) 8279 allows options for data entry
on the displays. The display data is entered for display either from the right side or
from the left side.

Command Words of 8279

command words or status words are written or read with Ao = 1 and CS = 0 to or from
8279. The various commands available in 8279 are.

(a) Keyboard Display Mode Set

The format of the command word to select different modes of operation of 8279 is
given below with its bit definitions.

79
By T.VenkataSridhar, ETC
80
By T.VenkataSridhar, ETC
 (b) Programmable Clock The clock for operation of 8279 is obtained by dividing the
external clock input signal by a programmable constant called prescaler,

PPPPP is a 5-bit binary constant. The input frequency is divided by a decimal constant
ranging from 2 to 31, decided by the bits of an internal prescaler, PPPPP.

(c) Read FIFO/Sensor RAM The format of this command is given as shown below:

x - don't care
AI - Auto Increment flag
AAA - Address pointer to 8 bit FIFO RAM
This word is written to set up 8279 for reading FIFO/sensor RAM. In scanned
keyboard mode, AI and AAA bits are of no use. The 8279 will automatically drive data bus
for each subsequent read, in the same sequence, in which the data was entered. In sensor
matrix mode, the bits AAA select one of the 8 rows of RAM. If AI flag is set, each
successive read will be from the subsequent RAM location.
81
By T.VenkataSridhar, ETC
 (d) Read Display RAM This command enables a programmer to read the display RAM
data.

The CPU writes this command word to 8279 to prepare it for display RAM read operation.

AI is auto increment flag and

AAAA, the 4-bit address, points to the 16-byte display RAM that is to be read.

If AI = 1, the address will be automatically, incremented after each read or write to the
display RAM. The same address counter is used for reading and writing.

(e) Write Display RAM

AI - Auto Increment flag

AAAA - 4-bit address for 16-bit display RAM to be written
Other details of this command are similar to the 'Read Display RAM Command'.
82
By T.VenkataSridhar, ETC
(f) Display Write Inhibit/Blanking

The IW (Inhibit Write flag) bits are used to mask the individual nibble as shown in
the above command.
The output lines are divided into two nibbles (OUTAo-OUTA3 and OUTBo-
OUTB3 ), those can be masked by setting the corresponding IW bit to 1.
Once a nibble is masked by setting the corresponding IW bit to 1, the entry to
display RAM does not affect the nibble even though it may change the unmasked nibble.
The blank display bit flags (BL) are used for blanking A and B nibbles. Here D0 and D2
corresponds to OUTBo-OUTB3 while D1 and D3 corresponds to OUTAo-OUTA3 for
blanking and masking respectively.
(g) Clear Display RAM

The CD2, CD1, CDo is a selectable blanking code to clear all the rows of the display
RAM as given below. The characters A and B represent the output nibbles
83
By T.VenkataSridhar, ETC
End Interrupt/Error Mode Set

For the sensor matrix mode, this command lowers the IRQ line and enables further
writing into the RAM. Otherwise, if a change in sensor value is detected, IRQ goes high
that inhibits writing in the sensor RAM.

Key-code and Status Data Formats

This section briefly describes the formats of the key-code/sensor data in their
respective modes of operation and the FIFO Status Word formats of 8279.

84
By T.VenkataSridhar, ETC
 Key-code Data Formats : After a valid key closure, the key code is entered as a byte code
into the FIFO RAM, in the following format, in scanned keyboard mode. The data format
of the key-code in scanned keyboard mode is given below. The key-code format contains
3-bit contents of the internal row counter, 3-bit contents of the column counter and status
of the SHIFT and CNTL keys.

In the sensor matrix mode, the data from the return lines is directly entered into
an appropriate row of sensor RAM, that identifies the row of the sensor that changed its
status.
The SHIFT and CNTL keys are ignored in this mode. RL bits represent the
return lines. Rn represents the sensor RAM row number that is equal to the row number of
the sensor array in which the status change was detected.

85 By T.VenkataSridhar, ETC
 FIFO status word
 The FIFO status word is used in keyboard and strobed input mode to indicate the error.
 Overrun error occurs, when an already full FIFO is attempted an entry. Underrun
error occurs when an empty FIFO read is attempted.
 FIFO status word also has a bit to show the unavailability of FIFO RAM because of
the ongoing clearing operation
 In sensor matrix mode, a bit is reserved to show that at least one sensor closure
indication is stored in the RAM. The SIB bit shows the simultaneous multiple closure
error in special error mode.
 The status word contains FIFO status, error and display unavailable signals.

86
By T.VenkataSridhar, ETC
 Interfacing and Programming 8279
Problem 1.
Interface keyboard and display controller 8279 with 8086 at address 0080H. Write an ALP
to set up 8279 in scanned keyboard mode with encoded scan, N-key rollover mode. Use a
16-character display in right entry display format. Then clear the display RAM with zeros.
Read the FIFO for key closure. If any key is closed, store it's code to register CL. Then
write the byte 55 to all the displays, and return to DOS. The clock input to 8279 is 2 MHz,
operate it at 100 kHz.

Solution
Specifications
 The 8279 is interfaced with lower byte of the data bus, i.e. Do-D7 Hence the Ao input
of 8279 is connected with address line A1.
 The data register of 8279 is to be addressed as 0080H, i.e. Ao = 0. As already
discussed, the data is either read from or written to this address (Ao = 0). For addressing
the command or status word Ao input of 8279 should be 1 (the address line A1 of 8086
should be 1), i.e. the address of the command word should be 0082H.
 Figure below shows the interfacing schematic.
 The next step is to write all the required command words for this problem.
87
By T.VenkataSridhar, ETC
88
By T.VenkataSridhar, ETC
89
By T.VenkataSridhar, ETC
 Interfacing Hardware

90
By T.VenkataSridhar, ETC
Program
Program below gives the ALP required to initialize the 8279 as required.

91
By T.VenkataSridhar, ETC
 * Topics beyond syllabus Ends..

92
By T.VenkataSridhar, ETC
 End of Interfacing Devices

Any Doubts ???

93
By T.VenkataSridhar, ETC
 Intel’s 8086
Introduction to 8086 Microprocessor: Architecture, Register
Organization, Physical Memory Organizations.

94
By T.VenkataSridhar, ETC
 8086 Overview
 It was the first 16-bit processor having 16-bit ALU, 16-bit registers, internal
data bus, and 16-bit external data bus resulting in faster processing.

 It is available in 3 versions based on the frequency of operation

8086 → 5MHz
8086-2 → 8MHz
8086-1 → 10 MHz
 It uses two stages of pipelining, i.e. Fetch Stage and Execute Stage,
which improves performance.

 Fetch stage can pre-fetch up to 6 bytes of instructions and stores them in

the queue.

 Execute stage executes these instructions.

 It has 256 vectored interrupts.

95  It consists of 29,000 transistors.

By T.VenkataSridhar, ETC
Architecture of 8086

AX
BX
CX
DX

96
By T.VenkataSridhar, ETC
Register Organisation

General Purpose Registers AX, BX, CX, DX.

Special Purpose Registers IP,SP, BP, SI, DI.

Segment Registers CS, DS, ES, SS.

Flag Register
X X X X X X X

Memory Organisation:

Non overlapped segmentation

Overlapped segmentation

97 End of Module-2 By T.VenkataSridhar, ETC

 Further Refer
Microprocessors and Peripherals
by
Douglas. V. Hall
And
Advanced Microprocessors and Peripherals
by
KM Bhurchandi & AK Ray

www.intel.com
98
By T.VenkataSridhar, ETC