Weeks 12 and 13

Interrupt Interface of the 8088 and

8086 Microprocessors
INTERRUPT INTERFACE
Interrupts provide a mechanism for quickly changing program environment.
The section of the program which the control is passed: Interrupt Service Routine,
ex: For printers it is the printer driver.
8088 and 8086 interrupts:
P
R
9 External Hardware Interrupts
I
O 9 Nonmaskable Interrupt
R
I 9 Software Interrupts
T
Y 9 Internal Interrupts
9 Reset
High

Lower priority interrupts need to wait for the higher priority interrupts to be completed
2
8088/8086 Interrupts
• An interrupt is an external event which informs the CPU that a
device needs service
• In the 8088 & 8086 there are are a total of 256 interrupts (or
interrupt types)
– INT 00
– INT 01
– …
– INT FF
• When an interrupt is executed, the microprocessor automatically
saves the flags register (FR), the instruction pointer (IP) and the
code segment register (CS) on the stack and goes to a fixed
memory location.
• In 80x86, the memory location to which an interrupt goes is always
four times the value of the interrupt number
• INT 03h goes to 000Ch

3
Interrupt Service Routine
• For every interrupt, there must be a program associated with it
• This program is called an Interrupt Service Routine (ISR)
• It is also called an interrupt handler
• When an interrupt occurs, CPU runs the interrupt handler but where
is the handler?
– In the interrupt Vector Table (IVT)

INT Number Physical Address Contains

INT 00 00000h IP0:CS0

INT 01 00004h IP1:CS1

INT 02 00008h IP2:CS2

. . .
. . .
. . .
INT FF 003FCh IP255:CS255
4
Interrupt Vector Table

• Interrupt vector table consists of 256 entries each

containing 4 bytes.
• Each entry contains the offset and the segment address of
the interrupt vector each 2 bytes long.
• Table starts at the memory address 00000H.
• First 32 vectors are spared for various microprocessor
operations.
• The rest 224 vectors are user definable.
• The lower the vector number, the higher the priority.

5
 Interrupt Vector Table

•Contains 256 address pointers

First 1 K (vectors)
memory
•These pointers identify the
starting location of their service
routines in program memory.
•Held as firmware or loaded as
system initialization

6
Examples

For example: vector 50: CS and IP?

Physical Address 200 = (4 x 50) = 200 = 11001000 =
C8H
000C8 contains IP: and 000CA contains CS information

• INT 12h (or vector 12)

• The physical address 30h (4 x 12 = 48 = 30h)
contains
0030h and 0031h contain IP of the ISR
0032h and 0033h contain CS of the ISR

7
Interrupt Instructions

8
 Differences between INT and CALL

™A CALL FAR instruction can jump any location within the

1 MB address range but INT nn goes to a fixed memory location
in the Interrupt Vector Table to get the address of the interrupt
service routine
™A CALL FAR instruction is used by the programmer in the
sequence of instruction in the program but externally activated
hardware interrupt can come at any time
™A CALL FAR cannot be masked but INT nn in hardware can be
blocked.
™A CALL FAR saves CS:IP but INT nn saves Flags and CS:IP
™At the end of the subroutine RET is used
whereas for Interrupt routine IRET should be the last statement
9
Interrupt Mechanisms, Types, and Priority

INTERRUPT TYPES SHOWN WITH DECREASING

PRIORITY ORDER
1.Reset
2.Internal interrupts and exceptions
3.Software interrupt
4.Nonmaskable interrupt
5.Hardware interrupt

All the interrupts are serviced on priority basis. The higher priority
interrupt is served first and an active lower priority interrupt service is
interrupted by a higher priority one. Lower priority interrupts will have to
wait until their turns come.
The section of program to which the control is passed called
Interrupt-service routine (ISR)

10
Interrupt instructions

• Interrupt enable flag (IF) causes external interrupts to be enabled.

• INT n initiates a vectored call of a subroutine.
• INTO instruction should be used after each arithmethic instruction
where there is a possibility of an overflow.
• HLT waits for an interrupt to occur.
• WAIT waits for TEST input to go high.

11
 The Operation of Real Mode Interrupt

1. The contents of the FLAG REGİSTERS are pushed onto the stack
2. Both the interrupt (IF) and (TF) flags are cleared. This disables the
INTR pin and the trap or single-step feature. (Depending on the
nature of the interrupt, a programmer can unmask the INTR pin by
the STI instruction)
3. The contents of the code segment register (CS) is pushed onto the
stack.
4. The contents of the instruction pointer (IP) is pushed onto the stack.
5. The interrupt vector contents are fetched, and then placed into both
IP and CS so that the next instruction executes at the interrupt
service procedure addressed by the interrupt vector.
6. While returning from the interrupt-service routine by the instruction
IRET, flags return to their state prior to the interrupt and and
operation restarts at the prior IP address.

12
INT 00 (divide error)

MOV AL,92
SUB CL, CL
DIV CL ; 92/0 undefined

; Also invoked if the quotient is too large to fit into the assigned register
MOV AX,0FFFh
MOV BL,2
DIV BL

; WRITE A DIVIDE ERROR ISR

Prompt db ‘Division by zero attempted$’
Diverr: PUSH DX
Mov ah,09h
Mov dx, offset prompt
int 21h
POP DX
13
INT 01 (Single Step)

ÀIn executing a sequence of instructions, there is often a need to

examine the contents of the CPU’s registers and system
memory.
ÀThis is done by executing one instruction at a time and then
inspecting the registers and memory
ÀThis is called the tracing or the single stepping
ÀTF must be set (D8 of the flag register)

PUSHF
POP AX
OR AX,0000000100000000B
PUSH AX
POPF
14
Other Interrupts
• INT 02h
– Intel has set aside INT 02h for the NMI interrupt
– There is an NMI pin on the CPU
– If the NMI pin is activated by a H signal, the CPU jumps to
00008H to fetch the CS:IP of the ISR associated with NMI
• INT 03h (breakpoint)
• INT 04H (signed number overflow) or INTO
– If OF=0 goes to 00010h to get the address of the ISR
– Otherwise, it is equivalent to NOP
• Example: Use debug dump command to see the IVT
– D 0000:0000 0013

15
External Hardware Interrupt Interface
Minimum Mode

9The interrupt circuitry must identify

which of the pending interrupts has
the highest priority.
9Then passes its type number to the
MPU
9The MPU samples the INTR at the
last clock period of each instruction
execution cycle. Its active high level
must be maintained.
9When recognized INTRA
generated.

16
External hardware-interrupt Interface
• Minimum mode hardware-interrupt interface:
– 8088 samples INTR input during the last clock period of each
instruction execution cycle. INTR is a level triggered input;
therefore logic 1 input must be maintained there until it is
sampled. Moreover, it must be removed before it is sampled next
time. Otherwise, the same Interrupt Service is repeated twice.
– INTA goes to 0 in the first interrupt bus cycle to acknowledge
the interrupt after it was decided to respond to the interrupt.
– It goes to 0 again the second bus cycle too, to request for the
interrupt type number from the external device.
– The interrupt type number is read by the processor and the
corresponding int. CS and IP numbers are again read from the
memory.

17
External hardware-interrupt Sequence

18
Resident Programs
• Usually non-resident program is a file, loaded from disk by DOS.
Termination of such program is the passing control back to DOS.
DOS frees all memory, allocated for and by this program, and stays
idle to execute next program.
• Resident program passes control to DOS at the end of its execution,
but leaves itself in memory whole or partially.
• Such way of program termination was called TSR - Terminate-and-
Stay-Resident. So resident programs often called by this
abbreviations - TSR.
• For example, TSR can watch keypresses to get passwords, INT 13h
sectors operations to substitute info, INT 21h to watch and dispatch
file operations and so on.
• TSR stays in memory to have some control over the processes.
Usually, TSRs takes INTerrupt vectors to its code, so, when interrupt
occurs, vector directs execution to TSR code.

19
 Storing an Interrupt Vector in the Vector Table

In order to install an interrupt vector – sometimes called a hook – the

assembler must address absolute memory

INT 21h

Initialization
AH = 25h Terminate and stay resident
Read the current vector
AL = interrupt AH = 31h
AH = 35h
type number AL = 00
AL = interrupt type
DS:DX = address DX = number of paragraphs
number
of new interrupt to reserve for the program
ES:BX = address
procedure
stored at vector

20
A virus!

21
Example-storing Interrupt Vector

22
Example-storing Interrupt Vector

23
 Interrupt Sequence

¾The interrupt sequence

begins when external device
requests service by
activating one of the
interrupt inputs.
¾The external device
evaluates the priority of this
interrupt
¾INTR Æ 1
¾80x86 checks for the
INTR at the last T state of
the instruction
¾Check for IF before
granting INTA 24
 Interrupt Sequence

¾80x86 initiates the INTA

bus cycle. During T1 of the
first bus cycle ALE is sent
and bus is at Z state and
stays high for the bus cycle.
¾LOCK is provided in
maxmode operation
¾During the second
interrupt acknowledge bus
cycle, external circuitry
gates one of the interrupts
20ÆFF onto data bus lines
¾Must be valid during T3
and T4 of second bus cycle25
 Interrupt Sequence

¾DT/R and DEN are at

logic zero and IO/M is at 1.
¾Next save the contents of
the flag register
™Two word read
¾TF and IF are cleared
operations are performed. ¾CS and IP are pushed
™The type number is
internally multiplied by 4
™The contents in this ¾Upon return by IRET
location is fetched and
loaded into IP
¾CS and IP are popped
™Then type number * 4 + ¾Flags are popped
2 content is loaded into
CS
26
Interrupt Example
• An interrupting device interrupts the microprocessor each time the
interrupt request input has a transition from 0 to 1.
• 74LS244 creates the interrupt type number 60H as a response to
INTA
• Assume:
– CS=DS=1000H
– SS=4000H
– Main program offset is 200H
– Count (counts the number of interrupts) offset is 100H
– Interrupt-service routine code segment is 2000H
– Interrupt-service routine code offset is 1000H
– Stack has an offset of 500H to the current stack segment
– Make a map of the memory space organisation
– Write a main program and a service routine to count the number of
positive interrupt transitions.

27
Interrupt Example

Interrupts the microprocessor each time the interrupt request signal has a
transition from 0Æ 1. The corresponding interrupt number generated by
the hardware in response to INTA is 60H
28
Memory organization

29
Program

30
Using hardware interrupt
Using Tri-state buffers to Input vector

Cheapest Way (FF applied)

31
Interrupt circuits

32
Description
• 8255 is decoded at 0500h, 0502h, 0504h, and 0506h
• 8255 is operated at Mode 1 (strobed input) B0 CONTROL WORD
• Whenever a key is typed , the INTR output (PC3) becomes a logic 1
and requests an interrupt thru the INTR pin on the microprocessor
• The INTR remains high until the ASCII data are read form port A.
• In other words, every time a key is typed the 8255 requests a type
40h interrupt thru the INTR pin
• The DAV signal from the keyboard causes data to be latched into
port A and causes INTR to become a logic 1
• Data are input from the keyboard and then stored in the FIFO (first
in first out) buffer
• FIFO in our example is 256 bytes
• The procedure first checks to see whether the FIFO is full.
• A full condition is indicated when the input pointer (INP) is one byte
below the output pointer (OUTP)

33
Remembering Mode 1 with Interrupts this time

34
Example: “Read from the Keyboard routine” into FIFO

; interrupt service routine to read a key from the keyboard

PORTA EQU 500h
CNTR EQU 506h
FIFO DB 256 DUP (?)
INP DW ? ; SET AS OFFSET FIFO IN MAIN PROG
OUTP DW ? ; SET AS OFFSET FIFO IN MAIN PROG
KEY: PROC FAR ;USES AX BX DI DX
MOV BX, INP
MOV DI, OUTP
INC BL
CMP BX, DI ;test for queue full
JE FULL ; if queue is full
DEC BL
MOV DX, PORTA
IN AL,DX ; read the key
MOV [BX], AL
INC WORD PTR INP
JMP DONE
FULL: MOV AL,8 ;DISABLE THE INTERRUPT
MOV DX, CNTR
OUT DX,AL
DONE: IRET
KEY ENDP

35
Example contd: “Read from the FIFO into AH”
READ: PROC FAR USES BX DI DX
EMPTY: MOV BX, INP
MOV DI, OUTP
CMP BX,DI
JE EMPTY
MOV AH, CS:DI
MOV AL,9 ; enable 8255 intEa
MOV DX, CNTR
OUT DX,AL
INC BYTE PTR CS:OUTP
RET
READ : ENDP

36
Multiple Interrupts - Another Interrupt Structure

37
Multiple Interrupts - Interrupt Structures

¾This drawing can

accommodate up to 7
interrupts.
¾If any of the IR inputs
becomes a logic 0, then the
output of the NAND gate
goes to logic 1 and requests
an interrupt through the
INTR input.
¾The PRIORITY among the
interrupts is resolved using
software techniques.
Ex: IR1 and IR0 active
creates FCH (252). At this
location IR0 can be placed to
resolve.
38
Operation

• If any of the IR inputs becomes a logic 0, then the output

of the NAND gate goes to logic 1 and requests an interrupt
through the INTR input
• Single interrupt request
• What if IR0 and IR1 are active at the same time?
• The interrupt vector is generated is FCh
• If the IR0 input is to have higher priority, the vector
address for IR0 is stored at vector location FCh
• The entire top half of the vector table and its 128
interrupt vectors must be used to accommodate all
possible conditions
• This seems wasteful but it may be cost effective in
simple systems
39
Multiple Interrupts Using Priority Encoder

Or you may use a

priority encoder!

40
8255 Programmable Interrupt Controller
 8259 Programmable Interrupt Controller

•The 8259 programmable interrupt controller (PIC) adds eight

vectored priority encoded interrupts to the microprocessor.
•This controller can be expanded to accept up to 64 interrupt
requests. This requires a master 8259 and eight 8259 slaves.
•Vector an Interrupt request anywhere in the memory map.
•Resolve eight levels of interrupt priorities in a variety of modes,
such as fully nested mode, automatic rotation mode, and specific
rotation mode.
•Mask each of the interrupt request individually
•Read the status of the pending interrupts, in-service interrupts
and masked interrupts.

42
Block Diagram

43
82C59A Programmable Interrupt Controller
• Block diagram of 82C59A includes 8 blocks
– 8259 is treated by the host processor as a peripheral device.
– 8259 is configured by the host pocessor to select functions.
– Data bus buffer and read-write logic: are used to configure the
internal registers of the chip.
• A0 address selects different command words within the 8259

44
 82C59A Programmable Interrupt Controller
– Control Logic INT and INTA¯ ared used as the handshaking interface.
• INT output connects to the INTR pin of the master and is connected to a
master IR pin on a slave. INTA¯ is sent as a reply.
• In a system with master and slaves, only the master INTA ¯ signal is
connected.
– Interrupt Registers and Priority Resolver: Interrupt inputs IR0 to IR7
can be configured as either level-sensitive or edge-triggered inputs.
Edge-triggered inputs become active on 0 to 1 transitions.
1. Interrupt request register (IRR): is used to indicate all interrupt
levels requesting service.
2. In service register (ISR): is used to store all interrupt levels which are
currently being serviced.
3. Interrupt mask register (IMR): is used to enable or mask out the
individual interrupt inputs through bits M0 to M7. 0= enable, 1=
masked out.
4. Priority resolver: This block determines the priorities of the bits set in
the IRR. The highest priority is selected and strobed into the
corresponding bit of the ISR during the INTA¯ sequence.
– The priority resolver examines these 3 registers and determines
whether INT should be sent to the MPU
45
82C59A Programmable Interrupt Controller

– Cascade-buffer comparator: Sends the address of the

selected chip to the slaves in the master mode and
decodes the status indicated by the master to find own
address to respond.
– Cascade interface CAS0-CAS2 and SP¯/EN¯:
• Cascade interface CAS0-CAS2 carry the address of the slave to be
serviced.
• SP¯/EN¯ :=1 selects the chip as the master in cascade mode
:=0 selects the chip as the slave in cascade mode
:in single mode it becomes the enable output for
the data transiver

46
 Interrupt Sequence

1) One or more of the INTERRUPT REQUEST lines (IR0 - IR7) are

raised high, setting the corresponding IRR bit(s).
2) The 82C59A evaluates those requests in the priority resolver with
the IMR and ISR, resolves the priority and sends an interrupt (INT)
to the CPU, if appropriate.
3) The CPU acknowledges the lNT and responds with first INTA pulse.
4) During this INTA pulse, the appropriate ISR bit is set and the
corresponding bit in the IRR is reset (to remove request). The
82C59A does not drive the data bus during the first INTA pulse.
5) The 80C86/88/286 CPU will initiate a second INTA pulse. The
82C59A outputs the 8-bit pointer onto the data bus to be read by the
CPU.
6) This completes the interrupt cycle. In the Automatic End of
Interrupt (AEOI) mode, the ISR bit is reset at the end of the second
INTA pulse. Otherwise, the ISR bit remains set until an appropriate
End of Interrupt (EOI) command is issued at the end of the interrupt
subroutine.
47
8259 System Bus

48
Content of the Interrupt Vector Byte

49
Two controllers wired in cascade

On the PC, the controller is

operated
in the fully nested mode

Lowest numbered IRQ input

has highest priority

Interrupts of a lower priority

will not be acknowledged
until the higher priority interrupts
have been serviced

50
 Fully Nested Mode
• It prioritizes the IR inputs such that IR0 has highest priority and IR7
has lowest priority
• This priority structure extends to interrupts currently in service as
well as simultaneous interrupt requests
• For example, if an interrupt on IR3 is being serviced (IS3 = 1) and a
request occurs on IR2, the controller will issue an interrupt request
because IR2 has higher priority.
• But if an IR4 is received (or any interrupt higher than IR2), the
controller will not issue the request
• Note however that the IR2 request will not be acknowledged unless
the processor has set IF within the IR3 service routine
• In all operating modes, the IS bit corresponding to the active routine
must be reset to allow other lower priority interrupts to be
acknowledged
• This can be done by outputting manually a special nonspecific EOI
instruction to the controller just before IRET
• Alternatively, the controller can be programmed to perform this
nonspecific EOI automatically when the second INTA pulse occurs
51
Interrupt Process Fully Nested Mode

52
 End of Interrupt
¾The In Service (IS) bit can be reset automatically following the trailing edge
of the last in sequence INTA pulse (when AEOI bit in ICW4 is 1) or by a
command word that must be issued to the 8259 before returning from a service
routine (EOI command).
¾An EOI command must be issued twice in the Cascade mode, once for the
master and once for the corresponding slave.
¾There are two forms of (non-automatic) EOI command:
9Specific: When there is a mode which may disturb the fully nested
structure, the 8259 may not determine the last level acknowledged. In
this case a specific EOI must be issued, which includes the IS level to
be reset. (OCW2)
9Non Specific: When a Non Specific EOI issued the 8259 will
automatically reset the highest IS bit of those that are set, since in the
fully nested mode the highest level was necessarily the last level
acknowledged and serviced. (preserve the nested structure)
™A non Specific EOI can be also issued at OCW2.
53
Initialization Sequence
Two types of command words are
provided to program the 8259:
1) The initialization command words
(ICW)
2) The operational command words
(OCW)

• Writing ICW1, clears ISR and

IMR
• Also Special Masked mode SMM
in OCW3, IRR in OCW3 and EOI
in OCW2 are cleared to logic 0.
• Fully Nested Mode is entered.
• ICW3 and ICW4 are optional
• It is not possible to modify just one
ICW. Whole ICW sequence must
be repeated
54
 ICW1

What value should be written to ICW1 in order to configure the

8259 so that ICW4 needed, the system is going to use multiple
8259s and its inputs are level sensitive?

00011001b = 19h

55
ICW2

What should be programmed into register ICW2 if type number output

on the bus is to range from F0h to F7h

11110000b = F0h

Suppose IR6 is set to generate the value of 6E. Generate the addresses for
the other interrupts.
IR7 = 6F IR3 = 6B
IR6 = 6E IR2 = 6A
IR5 = 6D IR1 = 69
IR4 = 6C IR0 = 68 56
Master Slave Configuration

57
Master Slave Configuration

9When slave signals the master that an interrupt is active the master determines
whether or not its priority is higher than that of any already active interrupt.
9If the new interrupt is of higher priority the master controller switches INTR to
logic 1
58
 Master Slave Configuration

9This signals MPU that external device needs to be serviced. If IF is set. As the first INTA is
sent out the master is signaled to output the 3 bit cascade code of the slave device whose whose
interrupt request is being acknowledged on the CAS bus. All slaves read this code and compare
internally
9The slave corresponding to the code is signaled to output the type number of its highest
priority active interrupt on the data bus during the second INTA cycle. 59
ICW3

Q) Suppose we have two slaves connected to a master

using IR0 and IR1.
A) The master is programmed with an ICW3 of 03h,
one slave is programmed with an ICW3 of 00h and
the other with an ICW3 of 01h.
60
Example Master-Slave

aAny requests on interrupt lines INT7

through INT14 will cause IR6 to be
activated on the MASTER.
aThe MASTER will then examine the bit 6
in its ICW3 to see if it is set.
aIf so it will output the cascade number of
the SLAVE on CAS0 through CAS2.
aThese cascade bits are received by the
SLAVE device which examines its ICW3 to
see if there is a match..
aThe programmer must have programmed
110 into the SLAVE’S ICW3. If there is a
match between the cascade number and
ICW3, the SLAVE device will output the
appropriate vector number during the
second INTA pulse.

61
 ICW4

AEOI mode requires no

commands. During the second
INTA the ISR bit is reset. The
major drawback with this mode
is that the ISR doesn’t have info
on which IR is served. Thus any
IR with any priority can now
Interrupt service routine.

BUF when 1 selects buffer mode. The SP/EN pin becomes an output for the data
buffers.
When 0, the SP/EN pin becomes the input for the (MASTER/SLAVE)
functionality

M/S is used to set the function of the 8259 when operated in buffered mode.
If M/S is set the 8259 will function as the MASTER.
If cleared will function as SLAVE. 62
Masks and Other Mode selection

•Interrupt Masks
•Each Interrupt request can be masked individually
by the IMR programmed through OCW1. Each bit in
the IMR masks one interrupt channel if it is set (1).
Bit 0 masks IR0, Bit 1 masks IR1 and so forth,
Masking an IR channel does not affect the other
channels operation.

63
Special Fully Nested Mode
– Used in the case of a large system where cascading
is used, and the priority has to be conserved within
each slave.
– This mode is similar to the normal nested mode with
the following:
• When an interrupt request from a certain slave is in service
this slave is not locked out from the master’s priority logic
and further interrupt requests from higher priority IR’s within
the slave will be recognized by the master and will initiate
interrupts to the processor.
• When exiting the ISR the software has to check whether the
interrupt is the only interrupt that is serviced from the SLAVE.
This is done by sending an EOI command and check the In
service register in the SLAVE. If it is the only one, a non
specific EOI has to be sent to the MASTER, if it is not empty
no action performed.
64
Automatic Rotation

–Several interrupt sources all of equal priority

–When the EOI is issued the IS bit is reset and then assigned
the lowest priority
–The priority of of other inputs rotate accordingly

65
 Automatic Rotation

interrupt requests
arrive on IR4 and IR6

EOI command always resets

the highest ISR bit (bit of
highest priority)
Use automatic rotating
mode to clear the IS bit as soon
as it is acknowledged

66
Specific Rotation

• The programmer can change priorities by

programming the bottom priority and thus
fixing all other priorities
(for ex: if IR5 is programmed as the bottom
priority device, then IR6 will have the highest
one)
• The set priority command is issued in OCW2
where R=1, SL=1, L0-L2 is the binary priority
level code of the bottom priority device)

67
OCW1 - OCW2
OCW1 is used to access the contents of the IMR. A READ operation can be performed
to the IMR to determine the present setting of the mask. Write operations can be
performed to mask or unmask certain bits.

Controller will not confuse OCW2 with ICW1 since D4 = 1

68
Example
ISR PROC FAR
…
MOV AL, 00100000b
OUT 20h, AL
IRET
ISR ENDP

What should be OCW1 if interrupt inputs IR0 through IR3 are to be masked
and IR4 through IR7 are to be unmasked?

D3D2D1D0 = 1111
D7..D4 = 0
Î 00001111 = 0F

What should be OCW2; if priority scheme rotate on non specific EOI issued
101 00000 (since it doesn’t have to be specific on certain bit

69
OCW3

Permits reading of the contents of the ISR or IRR registers through software

70
 Example
Normally when an IR is acknowledged and EOI is not issued, lower priority
interrupts will be inhibited.
So the SPECIAL MASK MODE, when a mask bit is set in OCW1, it
inhibits further interrupts at that level and end enables from all other levels,
that are not masked.

MOV AL, 00010000b ; mask IRQ4

OUT 21h, AL ; OCW1 (IMR)
MOV AL, 01101000b ; special mask mode
OUT 20h, AL ; OCW3

; by masking itself and selecting the special mask mode

interrupts on IRQ5 thru IRQ7 will now be accepted by the
controller as well as IRQ0 thru IRQ3

71
IR7
• Controller does not remember interrupt requests that are not
acknowledged
• If an interrupt is requested but no IR bit is found during INTA that is
IR is removed before acknowledged, then controller will default to
an IR7
• If the IR7 input is used for a legitimate device, the service routine
should read the IS register and test to be sure that bit 7 is high
ISR7 PROC FAR
MOV AL, 00001011b
OUT 20h, AL
IN AL, 20h
TEST AL, 80h ; IS7 set
JZ FALSE
; process interrupt here
FALSE: IRET
ISR7 ENDP
72
 Example

Analyze the circuit

and write an
appropriate main
program and a service
routine that counts as
a decimal number the
positive edges of the
clock signal applied
to IR0
Use type number 72

73
Example
• A0 not used
• Two I/O addresses are FF00h and FF02h
• FF00h: ICW1,
• FF02h: ICW2, ICW3, ICW4, OCW1
• ICW1 = 00010011b = 13h
• type number 72 will be used
– ICW2 = 01001000b = 48h
• ICW3 not needed
• nonbuffered and auto EOI
– ICW4 = 03h
• mask all other interrupts but IR0
– OCW1 = 11111110b = FEh

74
Main program and ISR
CLI
START: MOV AX, 0
MOV ES, AX
MOV AX, 100h
MOV DS, AX
MOV AX, 0FF0h; stack
MOV SS, AX
MOV SP, 100h
; interrupt install
MOV AX, OFFSET SRV72
MOV [ES:120h], AX
MOV AX, SEG SRV72
MOV [ES:122h]. AX

75
Example contd
; initialization
; service routine
MOV DX, 0FF00h
SRV72: PUSH AX
MOV AL, 13h
MOV AL, [COUNT]
OUT DX, AL
INC AL
MOV DX, 0FF02h
DAA
MOV AL, 48h
MOV [COUNT], AL
OUT DX, AL
POP AX
MOV AL, 03h
IRET
OUT DX, AL
MOV AL, 0FEh
OUT DX, AL
STI
; wait for interrupt
HERE: JMP HERE

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