Scholars' Mine

Doctoral Dissertations Student Theses and Dissertations

Fall 2018

Advanced topologies of high-voltage-gain DC-DC boost

converters for renewable energy applications
Ahmad Alzahrani

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Department: Electrical and Computer Engineering

Recommended Citation
Alzahrani, Ahmad, "Advanced topologies of high-voltage-gain DC-DC boost converters for renewable
energy applications" (2018). Doctoral Dissertations. 2716.
https://scholarsmine.mst.edu/doctoral_dissertations/2716

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ADVANCED TOPOLOGIES OF HIGH-VOLTAGE-GAIN DC-DC BOOST
CONVERTERS FOR RENEWABLE ENERGY APPLICATIONS

by

AHMAD SAEED Y. ALZAHRANI

A DISSERTATION

Presented to the Graduate Faculty of the

MISSOURI UNIVERSITY OF SCIENCE AND TECHNOLOGY

In Partial Fulfillment of the Requirements for the Degree

DOCTOR OF PHILOSOPHY

in

ELECTRICAL ENGINEERING

2018

Approved by

Mehdi Ferdowsi, Advisor

Jonathan Kimball
Pourya Shamsi
Donald Wunsch
Ali Rownaghi
 Copyright 2018
AHMAD SAEED Y. ALZAHRANI
All Rights Reserved
 iii

PUBLICATION DISSERTATION OPTION

This dissertation consists of the following four articles which have been submitted
for publication, or will be submitted for publication as follows:

Paper I: Pages 14-51 are submitted to IEEE ACCESS.

Paper II: Pages 52-85 are submitted IEEE transactions on Power Electronics.

Paper III: Pages 86-119 are submitted to IEEE Journal of Emerging and
Selected Topics in Power Electronics.

Paper IV: Pages 120-143 are submitted to IEEE Transactions on Industrial

Electronics
 iv

ABSTRACT

This dissertation proposes several advanced power electronic converters that are
suitable for integrating low-voltage dc input sources, such as photovoltaic (PV) solar panels,
to a high voltage dc bus in a 200 − 960 V dc distribution system. The proposed converters
operate in the continuous conduction mode (CCM) and offer desirable features such as low-
voltage stresses on components, continuous input currents, and the ability to integrate several
independent dc input sources. First, a family of scalable interleaved boost converters with
voltage multiplier cells (VMC) is introduced. Several possible combinations of Dickson
and Cockcroft-Walton VMCs are demonstrated and compared in terms of the voltage gain,
number of components, and input current sharing. This dissertation also presents a novel
VMC structure called Bi-fold Dickson. The novel VMC offers equal current sharing between
phases regardless of the number of stages, voltage ripple cancellation at each stage, and
does not require an output diode. A family of high-voltage-gain multilevel boost converters
is presented, with detailed example of the hybrid flyback and three-level boost converter.
In this family, the effective frequency seen by the magnetic element is multiple times
the switching frequency, and therefore smaller magnetic devices can be used. Theory of
operations, steady-state analysis, component selections, simulation, and efficiency analysis
are included for each proposed converter. The operation of the proposed converters was
further verified with 80 − 200 W hardware prototypes.
 v

ACKNOWLEDGMENTS

I would like to express my deepest and sincerest gratitude to my advisor, Dr. Mehdi
Ferdowsi for his outstanding guidance, leadership, understanding and patience throughout
my Ph.D. research, without him this dissertation would not have been completed. His vivid
demonstrations of power electronics and professional guidance helped me to come up with
ideas and organize my thoughts.
I would like to thank to Dr. Pourya Shamsi, Dr. Donald Wunsch, Dr. Ali Rownaghi
and Dr. Jonathan Kimball for their invaluable support, academic guidance and for kindly
agreeing to be on my committee. I would like to thank Dr. Kimball for tips and tricks he
taught me about PCBs and giving me the opportunity to mentor NSF REU students.
I would like to thank my colleagues and lab mates and Md. Rashidulzzaman, Tamal
Paul and Haidar Almubarak for helping me during my research time. Special thanks to the
ECE front office Carol, Jony, and Erin for helping me. I would like also to thank staff of the
graduate studies and the library for providing me with advices and assistance.
I would like to thank Najran University, Saudi Arabian Cultural Mission, and Min-
istry of Education in Saudi Arabia for the opportunity to pursue my graduate degrees and
for the support.
Finally, I am indebted to my family for their unconditional love and support through-
out all aspects of my life.
 vi

TABLE OF CONTENTS

Page

PUBLICATION DISSERTATION OPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v

LIST OF ILLUSTRATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xi

LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xvii

SECTION

1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.1. OVERVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

1.2. LITERATURE REVIEW . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.1. Conventional Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

1.2.2. Cascaded and Stacked Boost Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2.3. Three-level Boost Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.2.4. Isolated Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.2.5. Switched Capacitors and Hybrid Boost Converters. . . . . . . . . . . . . . . . . . . . 9

1.2.6. Interleaved Boost Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.3. RESEARCH CONTRIBUTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

PAPER

I. A FAMILY OF NON-ISOLATED INTERLEAVED BOOST CONVERTERS

WITH VOLTAGE MULTIPLIER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
 vii

ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2. THEORY OF OPERATION AND GENERAL STRUCTURE OF THE

PROPOSED FAMILY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.1. INTERLEAVED BOOST STAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2.2. VOLTAGE MULTIPLIER STAGE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.3. TOPOLOGIES OF A TWO-PHASE INTERLEAVED BOOST

CONVERTER WITH VMCS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

2.4. POSSIBLE MODIFICATIONS TO THE TOPOLOGIES . . . . . . . . . . . . 28

2.4.1. Convert a Floating Output Converter to Grounded Output . 28

2.4.2. Modification to Make the Converter Isolated . . . . . . . . . . . . . . . 29

2.4.3. Connecting Two Different VMCs to Obtain the Overall

Nonuniform Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3. MODES OF OPERATION AND STEADY-STATE ANALYSIS OF AN

EXAMPLE CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.1. MODE 1: BOTH MOSFETS ARE ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2. MODE 2: S1 IS ON AND S2 IS OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.3. MODE 3: S1 IS OFF AND S2 IS ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

3.4. STEADY-STATE VOLTAGE GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33

4. COMPONENT SELECTIONS AND EFFICIENCY ANALYSIS . . . . . . . . . . . . 34

4.1. INDUCTOR SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

4.2. ACTIVE SWITCHES SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.3. DIODE SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37

4.4. CAPACITOR SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

5. POWER LOSSES AND EFFICIENCY ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

6. SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

7. EXPERIMENTAL IMPLEMENTATION AND RESULTS . . . . . . . . . . . . . . . . . . . 40

8. CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
 viii

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

II. HIGH-VOLTAGE-GAIN DC-DC STEP-UP CONVERTER WITH BI-FOLD

DICKSON VOLTAGE MULTIPLIER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52

1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

2. CONSTRUCTION OF BI-FOLD DICKSON SC/VMCS. . . . . . . . . . . . . . . . . . . . . . 57

3. THE PROPOSED TOPOLOGY INTRODUCTION AND THEORY OF

OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

4. MODE ANALYSIS AND STEADY STATE VOLTAGE GAIN. . . . . . . . . . . . . . . 59

4.1. MODE 1 (T0 − T1 ) AND (T2 − T3 ) : BOTH Q1 AND Q2 ARE ON . . 59

4.2. MODE 2 (T1 − T2 ): Q1 IS ON AND Q2 IS OFF . . . . . . . . . . . . . . . . . . . . . . 59

4.3. MODE 3 (T3 − T4 ) : Q1 IS OFF AND Q2 IS ON . . . . . . . . . . . . . . . . . . . . . . 62

5. DISCONTINOUS CONDUCTION MODE AND BOUNDARY CON-

DUCTION MODE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1. DCM OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

5.1.1. Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1.2. Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1.3. Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1.4. Mode 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1.5. Mode 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

5.1.6. Steady-state Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

5.2. BOUNDARY CONDUCTION MODE (BCM) . . . . . . . . . . . . . . . . . . . . . . . . 69

6. COMPONENTS SELECTION AND EFFICIENCY CALCULATIONS . . . . . 70

6.1. INDUCTOR SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

6.2. ACTIVE SWITCH SELECTION. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

6.3. DIODE SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

6.4. CAPACITORS SELECTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

 ix

6.5. EFFICIENCY ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73

7. SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75

8. EXPERIMENTAL IMPLEMENTATION AND RESULTS . . . . . . . . . . . . . . . . . . . 77

9. CONCLUSION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

III. A FAMILY OF HIGH-VOLTAGE-GAIN MULTILEVEL BOOST CONVERT-

ERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87

2. PROPOSED FAMILY OF MULTILEVEL BOOST CONVERTER WITH

HIGH GAIN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.1. INTERLEAVING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89

2.2. HIGH GAIN CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

3. EXAMPLE CONVERTER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

3.1. THEORY OF OPERATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

4. COMPONENT SELECTIONS AND EFFICIENCY ANALYSIS . . . . . . . . . . . . 100

4.1. ACTIVE SWITCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100

4.2. DIODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.3. CAPACITORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101

4.4. COUPLED INDUCTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

4.5. THE LOSS ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5. SIMULATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.1. PHOTOVOLTAIC SOURCE SIMULATION. . . . . . . . . . . . . . . . . . . . . . . . . . 106

5.2. MPPT CONTROL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

6. EXPERIMENTAL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

7. CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
 x

IV. A FAMILY OF INTERLEAVED STEP-UP TOPOLOGIES USING SINGLE-

SWITCH MULTISTAGE BOOST CONVERTERS AND VOLTAGE MULTI-
PLIER CELLS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

ABSTRACT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120

1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121

2. THEORY OF OPERATION AND STEADY-STATE ANALYSIS . . . . . . . . . . . . 123

2.1. MODE 1: BOTH ACTIVE SWITCHES ARE ON . . . . . . . . . . . . . . . . . . . . 124

2.2. MODE 2: Q1 IS ON AND Q2 IS OFF . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

2.3. MODE 3: Q1 IS OFF AND Q2 IS ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129

2.4. STEADY-STATE ANALYSIS AND STATIC VOLTAGE GAIN . . . . . 130

3. COMPONENTS SELECTION AND EFFICIENCY ANALYSIS . . . . . . . . . . . . 132

3.1. ACTIVE SWITCHES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3.2. DIODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

3.3. INDUCTORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

3.4. CAPACITORS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

3.5. EFFICIENCY ANALYSIS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

4. EXPERIMENTAL IMPLEMENTATION AND RESULTS . . . . . . . . . . . . . . . . . . . 136

5. CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140

SECTION

2. SUMMARY AND CONCLUSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

REFERENCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

VITA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
 xi

LIST OF ILLUSTRATIONS

Figure Page

SECTION

1.1. The conventional boost converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

1.2. The efficiency and gain of the conventional boost converter considering the
conduction loss of the inductor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

1.3. Cascaded conventional boost converter (a) two stage (b) m stages . . . . . . . . . . . . . . . . 6

1.4. Single-switch multistage boost converter (a) two stages (b) three stages . . . . . . . . . . 6

1.5. Stacked boost converter a) Quadratic b) Quartic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

1.6. Three level boost converter a) schematic b) equivalent circuit to mode 1 where
both active switches are ON c) equivalent circuit to mode 2 d) equivalent
circuit to mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

1.7. Examples of isolated Dc-dc topologies converter a) two-switch flyback con-

verter b) two-switch forward converter c) Voltage-fed half-bridge converter d)
dual active bridge converter e) Full-bridge converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

1.8. Example of common switched capacitor circuits a) Cascaded voltage doubler

b) Fibonacci SC c) Dickson SC d) Series parallel SC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

1.9. Hybrid boost converter with a) Cockcroft-walton VMC b) Dickson VMC . . . . . . . 10

1.10. Interleaved boost converter with coupled inductors and voltage multipliers . . . . . . 11

PAPER I

1. General structure of the proposed family: (a) with output diode and capacitor
(b) with LC filter output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

2. Reduction of energy storage at multiple phases. In case of two phases, the

required energy storage is reduced by 50%. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

3. The normalized current ripples with respect to a single phase boost converter. . . 21

4. Interleaved boost stage with output waveforms: (a) two phases (b) three phases. 21

5. The switching pattern for the two-phase interleaved boost converter. The active
switches are driven by two out of phase signals, and the converter operates in
three modes of operation in the CCM. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
 xii

6. The switching pattern for a three-phase interleaved boost converter. The

converter is driven by three signals with a phase shift of 120◦ , and the converter
operates at four modes of operation in the CCM.. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

7. Two main voltage multiplier cells: (a) Dickson VMC (b) Cockcroft-Walton VMC. 23

8. Various topologies belong to the interleaved boost converter with voltage

multiplier cells (group A-D). The output is filtered using an output diode and
a capacitor filter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

9. Various topologies belong to the interleaved boost converter with voltage

multiplier cells (group E-H): with an output diode and a capacitor filter. . . . . . . . . . 25

10. Using an output LC filter instead of a diode-capacitor for the same groups
aforementioned. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

11. Modification to convert a floating output converter to a grounded output converter. 28

12. Group A and F can be converted to have a grounded output. Both have an
ideal voltage gain of M = N+1 N
1−d , which is 1−d less than the ones with floating
outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

13. The presented family can be modified by adding an isolation device to meet
the isolation requirement and improve the voltage gain. . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

14. Example of nonuniform topologies. The converter features two different types
of VMCs, a cell from group F and Cockcroft-Walton VMC. . . . . . . . . . . . . . . . . . . . . . . 30

15. Example converter; an interleaved boost stage with a 3 level VMC . . . . . . . . . . . . . . . 32

16. Modes of operation of the example converter; (a) mode 1 (b) mode 2 (c) mode 3 32

17. The example converter can convert the voltage from two independent power
sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

18. Simulation waveforms of voltages and currents across semiconductor switches

and inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

19. Simulation waveforms of the capacitors’ voltage and the output voltage in the
steady-state . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

20. Simulation of the capacitors’ currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

21. Simulation waveforms of the diodes’ currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

22. Efficiency analysis of the example converter; the actual losses (left) and the
loss breakdown (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

23. The hardware prototype and the experimental setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

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24. Experimental results of the voltage across the active switches and the diodes . . . . 45

25. Experimental results of the voltage across the capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . 45

26. Experimental results of the input current, inductor currents, active switches
and diode currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46

27. Experimental results of the capacitors’ currents and the output current . . . . . . . . . . . 46

PAPER II

1. Application of a high-gain DC-DC converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

2. The construction of a bi-fold Dickson cell. The BD cell is constructed using

two conventional Dickson cells, and one of the cells is rotated by 180◦ . Then,
they are connected so that a single VMC stage consists of two complementary
switches and two capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

3. Implementation of a bi-fold Dickson switched capacitor (left) and a bi-fold

voltage multiplier cell (right) with N = 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

4. Several examples of using bi-fold Dickson VMC in various power electronics

topologies. The VMC can be used in (a) a voltage-fed circuit, (b) a current fed
circuit, (c-d) AC rectification circuits, and (d-e) interleaved high-voltage-gain
DC-DC circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

5. Interleaved boost converter with Dickson voltage multiplier a) N = 1 and

Vin = 1−d b) N = 2 and Vin = 1−d c) Interleaved boost converter with a
Vo 2 Vo 4

Greinacher VMC, which has the same gain as (b). d) The proposed converter
with N = 3 and a gain of VVino = 1−d 6
. The analysis, simualtion, and experiment
are based on this topology. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

6. Switching pattern of two-phase boost converter. The phase shift between the
active switches’ duty cycles yields three modes of operation. . . . . . . . . . . . . . . . . . . . . 61

7. Modes of operation: (a) Mode 1, both Q1 and Q2 are ON; (b) Mode 2: Q1 is
ON and Q2 is OFF; (c) Mode 3: Q1 is OFF and Q2 is ON; . . . . . . . . . . . . . . . . . . . . . . . . 61

8. Interleaved boost stage waveforms. Voltage and currents of the active switches
(left) and voltage and currents of the inductors (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

9. Voltage stress on the diodes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

10. Voltage gain vs. the duty cycle at different numbers of VMC stages. . . . . . . . . . . . . 65

11. Waveforms of the DCM mode of operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

12. DCM modes: a) mode 4, when i L2 hits the zero b) mode 5, when i L1 hits the zero 67

13. The gain of the converter at τ = 1.25 × 10−3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

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14. The boundary between CCM and DCM τBCM at different numbers of bi-fold
VMC cells. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

15. Voltages and currents of active switches (left) and inductors (right) . . . . . . . . . . . . . . 76

16. Voltage and current stress through diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

17. Voltage and current stress on capacitors. The voltage ripples are partially
canceled. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

18. The hardware prototype of the proposed converter (left) and the thermal image
of the proposed converter operating at 100 W (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

19. Inductor currents and smooth pre-filtered input current (left) and active switches
currents (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

20. Voltage stress across active switches and diodes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79

21. Capacitor voltages and AC voltage ripples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

22. Loss (left) and loss distribution (right) of the converter as a function of the load. 80

23. Diode currents (upper waveforms) and capacitor currents (lower waveforms) . . . . 81

24. Efficiency of the converter at different loads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

PAPER III

1. Interleaving types: a) is vertical interleaving using three or multilevel struc-

tures, b) interleaving by paralleling two converters and c) mixing both tech-
niques to increase the effective frequency of the magnetic element and reduce
the conduction power loss of the inductor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

2. Multilevel boost converter topologies: (a) TLB (b) Four-level boost converter,
(c) Floating interleaved TLB, (d) Interleaved TLB and (e) Interleaved four
level boost converter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

3. Multilevel boost converter topologies with high coupled inductors cell: (a)
TLB with coupled inductors and (b) Four-level boost converter with coupled
inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

4. Multilevel boost converter topologies with high switched-inductor cell: (a)

TLB with switched-inductor cell and (b) Four-level boost converter with
switched-inductor cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5. Multilevel boost converter topologies with high switched-inductor cell: (a)

TLB with switched-inductor cell and (b) Four-level boost converter with
switched-inductor cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
 xv

6. Hybrid multilevel with flyback converter: (a) Hybrid TLB with flyback, (b)
Hybrid interleaved TLB with flyback and (c) hybrid four-level boost with flyback 94

7. The switching pattern of the example converter. The two active switches have
the same duty cycle, and they are 180o out of phase. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

8. Modes of operation: a) mode 1: Q1 and Q2 are ON, b) mode 2: Q1 is ON and

Q2 is OFF and c) mode 3: Q1 is OFF and Q2 is ON . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96

9. Gain of the converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

10. Voltage gain of the converters listed in Table. 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

11. Voltage stress across switched (left) and current passing through switches (right) 104

12. Input, output and capacitors waveforms. The voltage waveforms (left) and
current waveforms (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

13. Simulated loss breakdown at 80 W . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105

14. The I-V curve (top) and P-V curve (bottom) at the standard conditions. The
maximum power point is about 136W, and the fill factor is about 0.574. . . . . . . . . 107

15. Temperature’s effect on the I-V and P-V curves. As the temperature increases,
the output power of the PV is reduced. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

16. Irradiance’s effect on the output of the PV panel. The figure shows that there
is a strong correlation between the current of the PV panel and the irradiance
level. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108

17. MPPT algorithm used to control the proposed converter . . . . . . . . . . . . . . . . . . . . . . . . . . 110

18. Effect of step size on the performance of the algorithm a) small step size b)
large step size c) adaptive with ∆D
i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111

19. The simulated results of the converter with MPPT: a) Performance of the
controller b) Solar irradiance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

20. Hardware prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

21. The voltage stress across the active switches (left) and the voltage stress across
the diodes (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

22. The voltage across the capacitors (left) and the ac components across the
capacitors voltage (right). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113

23. Experimental results of the output voltage and the voltage ripple across the
output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114

24. Input current and active switch currents (left) and diodes currents (right) . . . . . . . . 114
 xvi

25. Efficiency of the proposed converter. Comparison between simulated and

experimental efficiency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

PAPER IV

1. The general structure of the proposed converter a) both phases have a multistage
boost converter and fed by a single source b) phases have different numbers
of stages and are fed by a single source c) both phases have the same number
of cascaded boost stages but they are fed by two independent sources d) each
phase has different number of stages and they are fed by two independent
voltage sources.) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124

2. Multistage boost converters a) Quadratic cell with grounded capacitor, b)

Cubic cell with grounded capacitors, c) Quadratic cell with floating capacitor,
and d) Cubic cell with floating capacitors. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

3. Different variations of the proposed converter (a) Schematic of the proposed

converter with 3 stages (cubic) and no VMC, (b) another interleaved cubic
boost converter with one stage of cross capacitor VMC, and (c) interleaved
cubic boost converter with one Cockcroft-Walton cell. . . . . . . . . . . . . . . . . . . . . . . . . . . . 126

4. Schematic of the proposed converter with k boost stages and N voltage mutli-
2N
plier cells. The voltage gain is (1−d) k . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

5. Schematic of the proposed converter with 3 stages (cubic) and 3 voltage

mutliplier cells (tripler) and implemented using MOSFETs instead of diodes
to reduce the conduction loss. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

6. Schematic of the proposed converter with k = 2 and N = 2 . . . . . . . . . . . . . . . . . . . . . . . 128

7. Equivalent circuits to a) mode 1: both active switches are ON, b) mode 2: Q1

is ON and Q2 is OFF, and c) mode 3: Q1 is OFF and Q2 is ON . . . . . . . . . . . . . . . . . . . 128

8. The voltage gain of the proposed converter with different numbers of boost
stages k and voltage multiplier cells N . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131

9. Hardware prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

10. Voltage waveforms of the active switches and the diodes. . . . . . . . . . . . . . . . . . . . . . . . . . 137

11. Voltage waveforms of the capacitors, the output load and the ac components
of the output voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138

12. Current passing through the active switches, inductors and diodes D11 -D23 . . . . . 138

13. Currents waveforms of the VMC diodes, VMC capacitors and Ca1 and Ca2 . . . . . 139

14. The efficiency of the hardware prototype and the simulated efficiency . . . . . . . . . . . 139
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LIST OF TABLES

Table Page

SECTION

1.1. Common design goals in dc-dc converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2

PAPER I

1. Comparison of different interleaved DC-DC converters . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

2. Output voltage at different cases of the input current and duty cycles . . . . . . . . . . . . . 35

3. List of Parameters used in simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

4. List of Components used for the hardware prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44

PAPER II

1. Output voltage at different cases. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

2. Comparison between Different Topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

3. List of parameters used in the simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4. Component Listing for the Hardware Prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

PAPER III

1. Comparison between different converters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

2. List of parameters used in the simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

3. Characteristics of PVL-136 solar panel . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

4. The parameter extraction of PV L − 136 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107

5. Component Listing for the Hardware Prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112

PAPER IV

1. Output voltage at different cases when the number of stages are even. . . . . . . . . . . . . 131

2. Comparison between different topologies . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132

3. Diode average and RMS currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133

 xviii

4. Inductor peak and RMS currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134

5. Efficiency analysis for components . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135

6. Component Listing for the Hardware Prototype . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

 SECTION

1. INTRODUCTION

1.1. OVERVIEW

The use of high-voltage-gain power converters was limited in the past to a few
applications such as supplying power to plasma display panels and integrating batteries to
an uninterruptible power supply [1, 2]. Today, high-voltage-gain converters are being used
in a wide variety of applications such as radar systems, dc distribution systems, renewable
energy harvesting, and data centers. Integrating renewable energy into the electric power
grid encourages the use of high-voltage-gain converters to boost the voltage of the renewable
energy sources to be suitable for integration to a 400 V dc distribution system. The use of
dc distribution has several advantages over the use of an ac distribution system regarding
the number of conversion units, price, and power quality. Therefore, using a high-voltage-
gain dc-dc converter, one can convert the unregulated low-output voltage of a solar panel
to a regulated high-voltage output. Also, the high-voltage-gain converter can extract the
maximum power. Several topologies can be used as a high-voltage-gain converter system.
However, there is not yet a preferred step-up topology for all applications.
The design goals of power electronic converters vary from application to application,
but the most common goals are maximum performance, high power density, or minimum
cost. To achieve better performance of the converter, one needs to operate the converter
at a suitable frequency, where the switching and core losses are lowest. Also, the passive
components should be large enough to reduce the voltage and current ripples. However,
decreasing the switching frequency limits the bandwidth of the controller and increases
the size of the passive components. High power density of the converter can be achieved
 2

Table 1.1. Common design goals in dc-dc converters

Design goal Techniques used Challenges

Maximum - Low switching frequency to reduce the switching loss - Low bandwidth for control

performance - Sizable passive component to reduce the voltage and current ripples - Low power density

Maximum - High switching frequency - Thermal constraints

power density - Topologies with small magnetic elements or switched capacitor techniques - Electromagnetic interference

- Low cost components, usually old and Less-efficient components - Performance

Minimum cost
- Simplest topologies - Efficiency

by either increasing the switching frequency so that passive components are minimized,
or finding topologies that require no or very little magnetic storage, such as switched
capacitors or resonant switched capacitors. The heat dissipation in the semiconductors and
electromagnetic interference are the main hurdles in designing a converter with a very high
power density. The total cost of a power converter can be reduced simply by using low-cost
components or by designing topologies that require a low count of components. However,
obtaining good performance and high efficiency with spending less money is very difficult
to achieve. Table 1.1 summarizes the techniques used for the common goal and challenges
associated with it.
The common design goals can be even more difficult to achieve in designing high-
voltage-gain step-up converters because of the drawbacks of the existing topologies, such
as the high voltage stress across components and insufficient voltage gain. Topologies
with high voltage stress across components require components with a high voltage rating,
which have higher conduction and switching losses. The ideal topology for a high-voltage-
gain conversion system would be a topology with a low number of components, high
efficiency, low cost, high voltage gain, low weight, small size, high power density, easy
integration capability, and high reliability. Practically, the ideal topology is not possible
nowadays for several reasons, such as the limitation of operating frequency due to the
 3

losses incurred in the magnetic cores [3, 4] and the high cost of the efficient components
and new technologies [5, 6]. In renewable energy applications, the dc-dc topologies need
to have specific features, such as drawing continuous and smooth input current and the
ability to integrate several different types of power sources. Interleaved high-voltage-gain
converters can be fed by several independent voltage sources and have high ac components
due to interleaving on the input current, which makes them filtered out easily, and obtain an
accurate measurement of the input current to perform maximum power point tracking.

1.2. LITERATURE REVIEW

1.2.1. Conventional Boost Converter. The conventional boost converter is the

simplest step-up dc-dc topology. It has only four power-stage elements: an inductor, a
low-side MOSFET, a diode, and an output capacitor, as shown in Figure 1.1 [7–9]. The
ideal voltage gain of the converter is given by

Vo 1
= (1.1)
Vin 1 − d

where d is the duty cycle, which is the percent of ON time to the switching time period.
The conventional boost converter, in theory, can provide a high voltage gain at an extremely
high duty cycle, but practically speaking, it cannot be used as a high-voltage-gain converter
because of several reasons. First, working with extremely high duty cycles compromises
the efficiency and increases the voltage stress across components. Figure 1.2 shows that
voltage gain and efficiency versus the duty cycles considering only the conduction loss of the
inductor, which is normalized to the output power. The high voltage gain is limited to duties
higher than 0.9 and with low efficiency. Considering other conduction losses of the switches,
the voltage gain is significantly reduced and the efficiency is severely compromised. The
output diode has to block the output voltage, and in high power applications, it may suffer
 4

L D

Q +
Co vo R
Vin _

Figure 1.1. The conventional boost converter

from the reverse recovery phenomena. Another disadvantage is that the magnetic element
that ensures continuous conduction mode would be massive, which increases the weight of
the converter and decreases the power density. [7]
1.2.2. Cascaded and Stacked Boost Converters. Cascading two or more con-
ventional boost converters increases the voltage gain without operation at extremely high
duty cycle [10, 11]. Figure 1.3(a) shows a two-stage cascaded boost converter, which is a
quadratic boost converter with voltage gain given by

Vo 1
Gainideal = = (1.2)
Vin (1 − d)2

The efficiency of a converter with two cascaded boost converters is given by

ηoverall2 = η1 η2 (1.3)

More conventional boost converter can be cascaded [12], as shown in Figure 1.3(b), and the
voltage gain of the cascaded converter is given by

Vo 1
Gainideal = = (1.4)
Vin (1 − d)m
 5

Efficiency of the conventional boost converter

D
The voltage gain of the conventional boost converter

Figure 1.2. The efficiency and gain of the conventional boost converter considering the
conduction loss of the inductor.

where m is the number of the cascaded converters. The overall efficiency of m stages can
be given by
m
Ö
ηoverallm = ηn (1.5)
n=1

The drawback of cascading two or more boost converters is that the power is being processed
twice, which might compromise the overall efficiency. Another disadvantage is the voltage
stress across the active switch and diode of the output stage, which is still as high as the ones
in the conventional boost converter. Single-switch cascaded converter has the same gain
as the cascaded boost converter but with a reduced number of active switches, as shown in
Figure 1.4. Using single switch leads to fewer gate driver circuitry components and lower
overall cost. However, the stages cannot be independently controlled as in the cascaded
boost converter [2, 13–15].
 6

iL L1 D1 L2 D2 Io
_
+ vL +
Q1 C1 Q2 Vo
C2 R
Vin _

(a)
iL Io

+
1st stage 2nd stage mth stage Vo
R
Vin _

(b)
Figure 1.3. Cascaded conventional boost converter (a) two stage (b) m stages

D2

iL L1 D1 L2 Do Io
_ _
+ vL1 + vL2
+
Q1 Co Vo
Vin C1 R
_

(a)
D2 L3

iL L1 D1 L2 D3 Do Io
_
+ vL +
Q1 Co Vo R
Vin C1 C2
_

(b)

Figure 1.4. Single-switch multistage boost converter (a) two stages (b) three stages
 7

+
C4 L4 D7
output stage
D5 D6
Intermediate stage +
C3 L3
D3 D4

+ +
C2 D3 C2 L2 RL
L2
D1 D2 D1 D2
RL
+ +
C1 L1 C1 L1

Vin Q Vin Q

(a) (b)
Figure 1.5. Stacked boost converter a) Quadratic b) Quartic

Stacking two or more converters means that the output voltage equals the sum of
converters output. Several stacked converters are introduced in the literature to increase
the voltage gain [16–19]. Figure 1.5 shows an example of a stacked converter [20]. The
example converter has gain of
Vo 1
= (1.6)
Vin (1 − d)n

where n is the number of series capacitors. The drawbacks of this type of converter is the
voltage balance across the output capacitors if they have large numbers.
1.2.3. Three-level Boost Converter. Three-level boost was first introduced to mit-
igate the voltage stress across the output diode of the conventional boost converter and
reduce the size of magnetic elements by increasing the effective frequency [21]. The three-
level boost converter consists of an inductor, two active switches, two diodes, two output
capacitors and a floating output, as shown in Figure 1.6(a). The converter has three modes
of operation as shown in Figure 1.6(b-d), and their sequence control depends on the voltage
balance between the output capacitors [22–25]. By defining the duty cycle with respect
 8

iL L D1 Io iL L D1 Io
+ vL _ + vL _
Q1 C1 + Q1 C1 +
+ +

R Vo R Vo
Vin + _ Vin + _
Q2 C2 Q2 C2

D2 D2
(a) (b)
iL L D1 Io iL L D1 Io
_ _
+ vL + vL
Q1 Q1 +
C1 + + C1 +

R Vo R Vo
Vin + _ Vin + _
Q2 C2 Q2 C2

D2 D2
(c) (d)

Figure 1.6. Three level boost converter a) schematic b) equivalent circuit to mode 1 where
both active switches are ON c) equivalent circuit to mode 2 d) equivalent circuit to mode 3

to the switching frequency, the voltage gain of this converter is the same as the one of the
conventional boost converter. Still this converter is impracticable to use for applications
that necessitate high-voltage-gain converters because of the insufficient voltage gain.
1.2.4. Isolated Converters. Isolated converters can be used to increase the voltage
by increasing the turns ratio of the transformer or the coupled inductor [26–28]. Isolated
converters can be categorized based on the symmetry of the magnetic cycle of isolation de-
vice in the B-H loop [28]. Converters with an asymmetrical magnetic cycle, such as flyback
and forward converters, where the magnetic operating point of the isolation device remains
in the same quadrant. Converters with symmetrical magnetic cycles include the half-bridge
converter, dual active bridge converter, full-bridge converter, and push-pull converter. Fig-
ure 1.7 shows the circuit diagram of some conventional isolated converters, which can be
found in the literature [7, 8]. Isolated converters are required in applications where safety
is crucial, such as medical devices. However, in other applications, non-isolated dc-dc
topologies are more suitable because non-isolated converters have higher power density,
 9

D1
Q2 Q2
Do Q2
D3 Do Co
C2
D2 D2 Lo
N1 N2 Co RL N1 N2 D4 Co RL
Vin D1 Vin D1 Vin
C1 Q1
R
Q1 Q1 D2

(a) (b) (c)

D1
Q1 Q3 Q5 Q7
Q1 Q3 Co
+
N1 N2 Co R Ls
Vin Vin
Q2 Q4 Q6 Q8 Q2 Q4
R D2

(d) (e)

Figure 1.7. Examples of isolated Dc-dc topologies converter a) two-switch flyback converter
b) two-switch forward converter c) Voltage-fed half-bridge converter d) dual active bridge
converter e) Full-bridge converter

smaller size, and lower weight than the isolated ones. The voltage stress across switches in
the isolated converters due to the spikes instigated by the leakage inductance. Therefore,
energy circulation circuits are necessary.
1.2.5. Switched Capacitors and Hybrid Boost Converters. Switched capacitors
(SCs) mainly consist of active switches and capacitors, and they can boost the voltage by
charging and discharging capacitors. SC circuits do not use magnetic storage elements
to transfer energy and therefore would significantly increase the power density and reduce
the size and weight of the converter. Moreover, the SC circuit can be fabricated into an
integrated chip (IC) and used in portable low-power electronics. Figure 1.8 shows examples
of the most common SC circuits [29–32]. The disadvantage of using SC circuits is the
regulation and the inherent losses. This type of circuit suffers from the discontinuity of
the input currents and usually has a fixed output without the ability to increase the voltage
using the pulse width modulation signal. Although several papers presented SC converters
to have a variable output voltage, such as in [33, 34], the resolution of the conversion ratio
is still limited.
 10

Q1

Q2 +
C1
Q2 Q1 Q1 Q1 Q2

Q2 +
Vin Q1 C3 Q2 C2 Q2 C2
Q2 R
+ + Co
C2 Co R
Q1 Q1 Q1
Vin

(a) (b)
+

C3
+
C1 Q1 Q1
Q2 Q1
Q2

Vin Q5 Q6 Q7 Q8 Q9 Q2 +
+ C1 Q2 C1 + +
vC1
+ vCo Co R _ vC2 C2 vo R
_ _ _
C2 Vin Q1 Q1
Q4 Q3 +
C4

(c) (d)

Figure 1.8. Example of common switched capacitor circuits a) Cascaded voltage doubler
b) Fibonacci SC c) Dickson SC d) Series parallel SC

L1 C2 C4 C2 C4
L1
+ + + +
iL _
+ vL1 iL + vL1 _
Q1 D1 D2 D3 D4 D5 Q1 D1 D2 D3 D4 D5

Vin + + + Vin

+
+

+
C1 C3 C5 R C1 C3 C5 R

Boost converter Cockcroft-Walton voltage multiplier Boost converter Dickson voltage multiplier
(a) (b)

Figure 1.9. Hybrid boost converter with a) Cockcroft-walton VMC b) Dickson VMC

Hybrid boost converters combine the switched capacitor or voltage multiplier cell
with the CBC to increase the overall voltage gain, reduce the voltage stress across the
switches, and reduce the critical inductance. A typical configuration of hybrid boost
converters is shown in Figure 1.9, where the CBC is attached to Cockcroft-Walton or
Dickson VMC. Although the voltage gain of the converter is high, the efficiency of such
converter is compromised by the conduction losses in the high-current loop, which is the
loop that contains the inductor and the active switch.
1.2.6. Interleaved Boost Converters. The interleaving technique connects two or
more conventional boost converters on parallel, and switches them with a phase shift between
phases [35, 35–37]. The current will be shared among phases, and therefore the current
 11

N12 N23 C2

+
*

N11
Q1 D1 D2 Do

+
+
Vin C1 Co Vo R
* ─
N21 Q2
*
N22 N13

Figure 1.10. Interleaved boost converter with coupled inductors and voltage multipliers

stress is reduced as well as the conduction losses in the active switches and the magnetic
elements. Interleaving two conventional boost converters increases the frequency of the
input current and makes it easier to be filtered [38]. The voltage stress across the output
diode, however, is still the same as in the conventional boost converter [39]. The voltage
gain of the interleaved boost converter can be increased using VMC, coupled inductors, or
both, such as in [40–42]. Figure 1.10 shows a two-phase interleaved boost converter with
coupled inductors and VMCs. Using both VMC and coupled inductors, the voltage gain
becomes a function of the turns ratio, VMC stages, and the duty cycles, which makes the
converter scalable and has a wide range of output voltage. However, using coupled inductors
might require energy circulation circuits and snubbers to reduce the voltage spikes across
the switches.
The research in this dissertation is motivated by the drawbacks of the aforementioned
topologies. Therefore, several topologies are presented to improve the existing topologies
and attain desirable features, such as low voltage stresses and low voltage and current
ripples.
 12

1.3. RESEARCH CONTRIBUTION

This dissertation presents several novel DC-DC converter topologies suitable for
renewable energy applications.
Paper I introduces a family of an interleaved high-voltage-gain boost converters with
extended voltage multiplier cells. This group of converters has the capability of converting
low input voltages (12 − 48 V) to high output voltages, such as 380/400 V DC bus. The
general structure of the family consists of two stages: an interleaved boost stage and voltage
multiplier cells. Either a single or multiple independent voltage sources can feed the
interleaved boost stage, and each source can be controlled independently. The presented
converters are compared, and the way of extending the voltage multiplier cells is illustrated.
An example converter is provided, and its theory of operation and steady-state analysis is
included. Then, the analysis results are verified by simulation and experimental results.
Paper II introduces an interleaved voltage multiplier with bi-fold Dickson voltage
multiplier cells. The proposed converter in this paper also consists of two stages. However,
the proposed topology has an enhanced VMC, which has two diodes and two capacitors per
stage. The implementation bi-fold Dickson VMC and its derivation from original Dickson
VMCs are illustrated, and their applicable use in various topologies are explained. The
main advantage of the converter is the low voltage stress on all components; even the output
capacitors share the output voltage equally. Another advantage is that the input current is
shared between inductors equally regardless of the number of stages. Modes of operation
and steady-state analysis are illustrated. The converter analysis is verified by simulation
and A 200 − W hardware prototype.
Paper III Introduces a hybrid flyback and multilevel boost converters to be used as
a high voltage gain DC-DC converter. The proposed converter has advantages of vertical
interleaving, which can multiply the effective frequency seen by the magnetic element and
therefore reduce the size and magnetic storage requirement. The converter uses a flyback
transformer to increase the voltage gain by increasing the transformer turns ratio. The
 13

converter has improvements over the conventional boost converter regarding the voltage
stress across active switches and the effective frequency across the magnetic element. The
proposed converter is an enhancement over the three-level boost converter for the voltage
gain and over the fly-boost converter in terms of the required magnetic storage to operate in
the continuous conduction mode.
Paper IV presents an interleaved switched-inductor boost converter with VMC. The
proposed converter utilizes the self-lift cells to increase the voltage gain and reduce the
inductors’ currents so that the size of the inductors are reduced and the conduction power
loss is also reduced. Few self-lift cells, both extended and basic, and some VMC can
be used with the proposed converter. An example converter is illustrated with two basic
self-lift cells with Cockcroft-Walton VMC cells.
 14

PAPER

I. A FAMILY OF NON-ISOLATED INTERLEAVED BOOST CONVERTERS

WITH VOLTAGE MULTIPLIER CELLS

Ahmad Alzahrani, Pourya Shamsi, and Mehdi Ferdowsi

Departement of Electrical and Computer Engineering
Missouri University of Science and Technology
{asakw9, shamsip, ferdowsi}@mst.edu

ABSTRACT

In this paper, a family of non-isolated interleaved high-voltage-gain DC-DC con-

verters is presented. This family can be used in a wide variety of applications, such as in a
photovoltaic systems interface to a high voltage DC distribution bus in a microgrid and an
X-ray system power supply. The general structure of this family is illustrated and consists of
two stages: an interleaved boost stage and a voltage multiplier stage. The interleaved boost
stage is a two-phase boost converter, and it converts the input DC voltage to an AC square
waveform. Moreover, using the interleaved boost stage increases the frequency of the AC
components so that it can be easily filtered with smaller capacitors and, therefore, makes
the input current smoother than the one from the conventional boost converter. The voltage
multiplier cell (VMC) can be a Dickson cell, Cockcroft-Walton (CW), or a combination
of the two. The VMC stage rectifies the square-shaped voltage waveform coming from
the interleaved boost stage and converts it to a high DC voltage. Several combinations of
VMCs and how they can be extended are illustrated, and the difference between them is
 15

summarized so that designers can be able to select the appropriate topology for their appli-
cations. An example of this converter family is illustrated with detailed modes of operation,
a steady-state analysis, and an efficiency analysis. The example converter was simulated to
convert 20 VDC to 400 VDC , and a 200 W hardware prototype was implemented to verify the
analysis and simulation. The results show that the example has a peak efficiency of 97% of
this family of converters and can be very suitable for interfacing renewable energy sources
to a 400 VDC DC distribution system.
Keywords: Interleaved, boost, Step-up, High-gain, DC-DC, Renewable, Microgrid, PV,
DC distribution, VMC, Modular

1. INTRODUCTION

The total power generation from renewable energy sources has been increasing
rapidly and is predicted to increase threefold in the near future [1, 2]. The transition from
using conventional and depletable energy sources in electricity generation to renewable
and sustainable sources requires adaptable power infrastructure and high-efficiency power
electronic converters. The power electronics play an indispensable role in renewable energy
sources’ integration to the main electric grid. Using highly efficient power converters
could help customers save energy and therefore increase the economic benefits [3, 4]. The
renewable energy market necessitates not only efficient, but also versatile and multipurpose,
converters. Recently, the idea of integrating a low voltage PV panel to a 400 V DC
distribution bus became a research interest due to the advantage of the DC distribution bus
over AC. The DC distribution system has less conversion units and better efficiency, power
quality, and performance than the AC distribution systems [5–9]. Integration of a single PV
panel to a 400 V DC distribution system requires a high-gain DC-DC converter [10].
Several topologies found in the literature can be used as high-gain DC-DC convert-
ers [11–22]. However, there is no superior solution for all applications. The most common
topology used to step up the input voltage is the conventional boost converter, which is the
 16

most straightforward step-up converter [23]. However, the conventional boost converter
would not have enough voltage gain for integrating renewable energy sources to a 400 V,
but if it were to have enough voltage gain, it would be only when operating at a higher
duty cycle, which might lead to the appearance of reverse recovery phenomena and low
overall efficiency, especially if the inductor DC equivalent resistance is high. Moreover, the
required inductance to stay in the continuous conduction mode is very large, and therefore,
the converter requires large and bulky magnetics [24, 25].
Cascaded boost converters were introduced to replace the conventional boost con-
verter. Such solutions increase the overall voltage gain and allow each converter to operate
at a lower duty cycle [26]. However, cascading two or more converters at least doubles
the power being processed, and that might compromise the efficiency as well. Moreover,
controlling cascaded converters requires that the output impedance of a converter be lower
than the input impedance of the following converter to ensure stability [27]. That might
lead to complications in the design and control. Stacking two or more converters helps by
sharing the power among different converters and allows the use of lower current rating
devices [28]. However, the overall voltage gain is still the same as the voltage gain of the
conventional boost converter.
Several converters can achieve higher voltage by incorporating either coupled in-
ductors or transformers [29, 30]. Such topologies increase the voltage gain by increasing
the turn ratio. However, several issues can arise. First, the leakage inductance can cause
some voltage spikes across switching devices, and that might require some voltage clamp
circuits. Second, incorporating such devices reduces the power density of the converter
and increases the weight. Furthermore, the semiconductor materials will improve rapidly,
while magnetic materials will not. Therefore, with the increase of switching frequency,
the magnetic-based components might become the most significant culprits for power loss
inside the converter. Thus, this paper introduces a family of converters that can have a
high-voltage-gain ratio, continuous current, low stress across both active and passive de-
 17

vices, and high power density. The proposed family consists of two stages: an interleaved
boost stage and voltage multiplier cells. The interleaved boost stage reduces the variation of
the input current so that it is easy to obtain more accurate measurements of the PV current
to track the maximum power. The voltage multiplier cells increase the voltage gain and
reduce the voltage stresses across switching devices. Moreover, the converter can achieve a
high-voltage-gain ratio while operating at a lower duty cycle. The proposed family requires
the lower value of critical inductance to keep the converter operating in the continuous
conduction mode (CCM). The rest of the paper is structured as follows: Section 2 provides
the theory of operation and the general structure of the proposed family. Section 3 presents
different variations of the converter belonging to the proposed family. In Section 4, an
example of the proposed converter is given and analyzed. In Section 5 and 6, the simula-
tion and experimental results of the example converter are provided, respectively. Finally,
conclusions and future work are described in Section 7.

2. THEORY OF OPERATION AND GENERAL STRUCTURE OF THE

PROPOSED FAMILY

The general structure of the proposed family is shown in Figure 1, which consists of
an interleaved boost stage followed by a voltage multiplier cell, and then it is either filtered
using an output diode and capacitor capacitor as in Figure 1(a) or using an LC filter as
shown in Figure 1(b). By using an output diode and a capacitor filter, the output of VMC
1
is further increased by 1−d but the output current is discontinuous. On the contrary, when
using an LC filter, the output voltage of the VMC is not increased, but the output current
is continuous if the inductor is large enough to operate in the CCM mode. Several papers
present members belonging to the proposed family [31–37]. However, no information about
extending the VMC cells or the interleaved boost phases has been reported. The following
sections present details about each stage of the proposed family.
 18

IL1, IL2 Vwz Vo

Iin Do
D1
x w
L1 L2 +
+ iL1 iL2
Vin _ Vxy C1 C2 Co Vo Rload
S1 S2 _
D2
y z

Interleaved boost stage Voltage multiplier

(a)
IL1, IL2 Vwz Vo
Iin
Lo
D1
x w
L1 L2 +
+ iL1 iL2
Vin _ Vxy C1 C2 Co Vo Rload
S1 S2
_
D2
y z
Interleaved boost stage Voltage multiplier
(b)

Figure 1. General structure of the proposed family: (a) with output diode and capacitor (b)
with LC filter output

2.1. INTERLEAVED BOOST STAGE

The IBC stage consists of two or more phases. Each phase consists of an inductor
and a low-side active switch. Since the IBC stage is a current source, the active switches can
be closed simultaneously with no need for a dead time insertion circuit as in the voltage-fed
converters. A phase shift between the active switches is vital to reduce the current ripples
from the input current and therefore reduce the size of the input filter. A recommended
phase shift between active switches can be given by

360◦
Shi f t = (1)
φ

where φ is the number of interleaved phases, which is a positive integer greater than or
equal to two. To ensure the continuity of the input current and to prevent a voltage-second
imbalance in the inductors, the minimum duty cycle is given by

φ−1
D≥ . (2)
φ
 19

90
80

Energy storage
reduction (%)
70
60
50
40
30
20
10
0
1 2 3 4 5 6 7
Number of phases

Figure 2. Reduction of energy storage at multiple phases. In case of two phases, the required
energy storage is reduced by 50%.

Besides reducing the current ripples, the interleaved boost stage reduces the magnetic
storage. In the case of two-phase, and assuming the inductors share the input current
equally, the reduction in the magnetic element is half as follows:

I 2

2
1
+ 12 L 2I


E2 L
= 2 2
1
× 100 = 50%. (3)
E1 2 LI
2

The reduction for Eφ is given by κ as

1
κ(%) = (1 − ) × 100. (4)
φ

Figure 2 shows the percentage of the reduction of a different number of phases. The
reduction becomes insignificant as the number of phases increases. The reduction of the
magnetic volume ζ does not follow (4) as illustrated in [38]. Instead, one should compare
the volume reduction as follows:

V olumen=1 − φV olumen=φ
ζ= × 100 (5)
V olumen=1
 20

where V olumen=1 is the volume of the magnetic element in a single phase converter and
V olumen=φ is the volume of the magnetic element of a multiphase converter with φ phases.
Another advantage of interleaving is that the total conduction loss in the inductors and the
active switching devices is reduced if the current is shared equally between the phases as
follows:

IL2 × RDC
PLtot al = , (6)
φ
2
IS,rms × RON
PS,condtot al = . (7)
φ

The input current ripples depend on the number of interleaved phases and the duty cycle.
Figure 3 shows the relationship between the number of stages and the normalized input
ripples. Increasing the number of phases reduces the ripples and allows ripple cancellation
to occur at multiple duty cycle values. Two phases can have one point of ripple cancellation
at the 0.5 duty cycle; while in three phases the ripple cancellation occurs at two points: the
0.25 and 0.75 duty cycles. For more phases, the duty cycle values where ripple cancellation
can occur are given by

1 2 φ−1
d∆v=0 = [ , , ..., ] (8)
φ φ φ

Figures 4(a) and (b) show the schematic and output waveforms of the interleaved
boost stage for two and three phases, respectively. The switching waveforms and modes
of operations are shown in Figure 5 for two phases and Figure 6 for three phases. More
phases can be used, such as in [39], but three or more phases will not have a uniform pattern
of connections to the VMC, and the permutation of variation of the topologies is large.
Therefore, the number of phases is limited to two in this paper.
 21

2 phases
0.8
3 phases
Current Ripple 4 phases
0.6

0.4

0.2

0
0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
Duty (D)

Figure 3. The normalized current ripples with respect to a single phase boost converter.
+-

+-

Vin Vin

L1 L2 L1 L2 L3

iL1 iL2 iL1 iL2 iL3

x x
y y

z
S1 S2 S1 S2 S3

Vin
Vxy 1 d
0
Vin Vin
Vxy 1 d 1 d
Vin
0
Vyz 1 d
Vin 0
1 d Vin
Vin 1 d
Vxz 1 d
0
Vin
1 d

(a) (b)

Figure 4. Interleaved boost stage with output waveforms: (a) two phases (b) three phases.
 22

Mode 1 Mode 2 Mode 1 Mode 3 Mode 1

Mode
1
Q1
d1Ts Mode
2

180° t
Ts Mode
1
Q2
d2Ts
Mode
3
t
t0 t1 t2 t3 t4

Figure 5. The switching pattern for the two-phase interleaved boost converter. The active
switches are driven by two out of phase signals, and the converter operates in three modes
of operation in the CCM.

Mode
Mode 3

Mode 4
Mode 1
Mode 2
Mode 1

Mode 1

Mode 1
Mode 2

Mode
Ts 2

Q1 d1Ts
Mode
1
120° t

Mode
Q2 d2Ts 3

120° t
Mode
1

Q3 d3Ts
Mode
4
t0 t1 t2 t3 t4 t5 t0 t1 t2 t

Figure 6. The switching pattern for a three-phase interleaved boost converter. The converter
is driven by three signals with a phase shift of 120◦ , and the converter operates at four modes
of operation in the CCM.
 23

C4
+
C2
+

D1 D2 D3 D4
A
C1
+
B
C3
+

(a)
C2 C4
+ +

D1 D2 D3 D4
A
C1 C3
+ +
B
(b)
Figure 7. Two main voltage multiplier cells: (a) Dickson VMC (b) Cockcroft-Walton VMC.

2.2. VOLTAGE MULTIPLIER STAGE

The voltage multiplier stage rectifies the modified squared waveform that comes
from the interleaved boost stage and boosts the voltage to a higher level. The VMC stage
consists of capacitors and diodes. The two main extendable VMCs are the Dickson VMC
and Cockcroft-Walton VMC, as shown in Figure 7. The main difference between these
VMCs is the way capacitors are connected. In the Dickson VMC, all negative sides of
the even capacitors are connected to phase a, and all negative sides of the odd capacitors
are connected to phase b. In the Cockcroft-Walton VMC, each negative side of the odd
capacitor is connected to the positive side of the previous odd capacitor, and each negative
side of the even capacitor is connected to the positive side of the previous even capacitor.
Various combinations are derived out of these two VMCs, as in [40–45] .
 24

+
+

-
Vin
-

-
Vin Vin

L1 L2 L1 L2 L1 L2

iL2 D1 D3 D5 Do
Group A

iL1
iL1 iL2 D1 Do iL1 iL2 D1 D3 Do

+ + + + + + +
+ + + + + +
C1 C2 C3 C4 C5 C6 Co R
+ +
C1 C2 Co R C1 C2 C3 C4 Co R

D2 D4 D6
S1 S2
D2 D2 D4
S1 S2 S1 S2
3 5 7
M M M
1 d 1 d 1 d

+-
+-

+-
Vin Vin Vin

L1 L2 L1 L2 L1 L2

iL1 iL2 C1 C3 C5 Do
iL1 iL2 C1 Do iL1 iL2 C1 C3 Do + + +
Group B

+ + +

+
D1 D2 D3 D4 D5 D6 Co R
D1 D2 +
Co R D1 D2 D 3 D4 Co R
+
+ + +

+ + + C2 C4 C6
S1 S2
C2 C2 C4
S1 S2 S1 S2

M
3 5 7
M M
1 d 1 d 1 d

+-
+-

+-

Vin Vin Vin

L1 L2 L1 L2 L1 L2
Group C

C1 Do C1 C3 Do iL1 C1 C3 C5 Do
iL1 iL2 iL1 iL2 iL2 + + +
+ + +

D3 D1 D2 D3 D4 D 5 D6 Co R
D1 D2 Co R D1 D2 D4 Co R +
+ +

+ + +
+ + +
C2 C4 C6
C2 C2 C4 S1 S2
S1 S2 S1 S2

3 7
M M
5
M
1 d 1 d 1 d
+
-

+
-

Vin
+

Vin
-

Vin
L1 L2
Group D

L1 L2
D1 D2 Do L1 L2
D1 D2 D3 Do
iL1 iL2 D1 D2 D3 D4 Do
iL1 iL2
iL1 iL2
+ +
+ + +
C1 C2 + + + +
C1 C2 C3
C1 C2 C3 C4
+
+ + +
Co vo Co vo R + +

_ Co vo R
_
S1 S2 _
S1 S2 S1 S2

3 5
M M
4 M
1 d 1 d 1 d

Figure 8. Various topologies belong to the interleaved boost converter with voltage mul-
tiplier cells (group A-D). The output is filtered using an output diode and a capacitor
filter.
 25

Vin

+
-
Vin
+-

Vin

+-
C2 C2 C2 C4
L1 L2 L1 L2
+ L1 L2 +
+ +
Group E

iL1 iL2 D1 D2 Do Do iL1 iL2 D1 D2 D3 D4 Do

iL1 iL2 D1 D2 D3

+ + + +
+ + + + + +
+
Co vo R
Co vo R Co vo R
C1 _ C3 C1 C3 _
C1 _
S1 S2 S1 S2 S1 S2

3 4 5
M M M
1 d 1 d 1 d

+-
Vin
+-

+-

Vin Vin
L1 L2
L1 L2 L1 L2 D1a D2a D3a Do
iL1 iL2
D1a Do D1a D2a Do
iL1 iL2 iL1 iL2
Group F

+ + +
C1a C2a C3a
+ +
C1a C1a + C3b
+
+
+ + Co vo R
+ +
vo vo _
Cout R Co R
S1 S2
_ _
S1 S2 S1 S2 C1b + C2b + C3b +
+ +
C1b C1b + C3a
D1b D2b D3b
D1b 3 D1b D2b 5 7
M M M
1 d 1 d 1 d
Vin

+-
Vin Vin
+-

+
-

C2a C4a
C2a

+
L1 L2
L1 L2 C2a L1 L2
+

D1a D2a D3a D4a Do

+ D1a D2a D3a Do iL1 iL2
iL1 iL2 iL1 iL2
Group G

D1a D2a Do C3a

C3a

+
+

C1a
+

C1a C1a
+
+ + +
+ +
Co vo R
Co vo R Co vo R
C1b C1b _
+

C1b _ _ C3b
S1 S2
S1 S2 S1 S2 C3b

D1b D2b D1b D2b D3b D1b D2b D3b D4b

C2b C4b
3 C2b 5 7
+ C2b
M M M
1 d 1 d 1 d
Vin Vin Vin
+-

+-

+-

L1 L2 L1 L2 L1 L2
C2a C2a
iL1 iL1 iL1
Group H

iL2 iL2 + iL2 +

D1a Do D1a D2a Do D1a D2a D3a Do

+ +
C1a C1a C1a + C3a
+ + + + +
+ +
Co vo R Co vo R Co vo R
+ +
_ C1b _ C1b _
+

S1 S2 C1b S1 S2 C3b S1 S2 C3b

+ +

D1b D2b D1b D2b D3b D1b D2b D3b D4b

C2b +
+ + +

4 6
M C2b
M
5 C2b C4b M
1 d 1 d 1 d

Figure 9. Various topologies belong to the interleaved boost converter with voltage multi-
plier cells (group E-H): with an output diode and a capacitor filter.
 26

+
-
Vin
Vin

+
-
L1 L2 C2 C4
L1 L2

Group E
+ +
iL2 D1 D3 D5 Lo
Group A

iL1
iL1 iL2 D1 D2 D3 D4 Lo

+ + + + + + +
C1 C2 C3 C4 C5 C6 Co R
+ +
+ +
Co vo R
C1 C3 _
D2 D4 D6 S1 S2
S1 S2
+-

Vin

+-
Vin
L1 L2
L1 L2
iL1 iL2 C1 C3 C5 Lo Lo
+ + + D1a D2a D3a
Group B

iL1 iL2

Group F
+ + +
C1a C2a C3a
+
D1 D2 D3 D4 D 5 D6 Co R
+
+
+ + + Co vo R
_
C2 C4 C6 S1
S1 S2 S2
+ + +
C1b C2b C3b

D1b D2b D3b

+-

Vin Vin
+-

C2a C4a
Group G

L1 L2 L1 L2 +

D1a D2a D3a D4a Lo

Group C

iL1 C1 C3 C5 Lo iL1 iL2

iL2 + + +
C3a
+

C1a
D 1 D2 D3 D4 D5 D6 Co R
+ +
+
Co vo R
+ + + C1b _
S1 S2 C3b
C2 C4 C6
S1 S2
D1b D2b D3b D4b

C2b C4b

Vin
+-
+
-

Vin
L1 L2
Group D

L1 L2 C2a
Group H

iL1 iL2 +
D1 D2 D3 D4 Lo
iL1 iL2 D1a D2a D3a Lo

+ + + +
C1a + C3a
C1 C2 C3 C4 +
+ +
Co vo R
+ + +
C1b _
Co vo R
S1 S2 C3b
_ +
S1 S2
D1b D2b D3b D4b

+ +

C2b C4b

Figure 10. Using an output LC filter instead of a diode-capacitor for the same groups
aforementioned.
 27

2.3. TOPOLOGIES OF A TWO-PHASE INTERLEAVED BOOST CONVERTER

WITH VMCS

Figures 8 and 9 show different interleaved boost converters with different VMCs
and a diode capacitor filter. Figure 10 shows the same groups, but with an LC output filter
instead of a diode-capacitor filter. Group A uses cross capacitor VMC cells. This group is
analyzed in [46]. Group B and C have cross diode VMC cells, and similar work is presented
in [47]. The cells can start in the inverting cells, as in group B, or non-inverting VMC stage,
as in group C. To extend the VMC in these two groups, each cell must be followed by a cell
with the opposite polarity. For example, the first stage in group B is positive (the diodes are
upward), so it must be followed by a negative cell (diodes are downward), and vice versa.
The polarity of the output voltage depends on the polarity of the last cell. Group D has
Dickson VMC [10], and group E consists of Cockcroft-Walton [48]. Group F contains the
example converter and will be analyzed in this paper. Group G has two CW chains, and
it can have either the same or a different number of cells on each chain. Finally, Group
H uses Dickson cells on one phase and Cockcroft-walton VMC on the other phase with
either the same or a different number VMC stages. Several interleaved boost converters
with VMCs belonging to this family can be found in the literature such as [49], where the
Dickson VMC is modified to have lower voltage stress across capacitors without changing
the overall voltage gain.
The main difference between these groups is how internal capacitors are charged and
discharged. Some other differences including the load connection type (floating, inverted,
or grounded), the stress on the capacitors and diodes, and the number of components in each
VMC stage. The VMC structure affects the sharing of the input current between phases in
the interleaved boost stage. That is, in converters that have an output diode, if there is a
single diode in each stage, then the current sharing can be equal if the number of stages is
even. However, if there is an output diode and each stage of the VMC has two diodes, then
 28

Do1

L1 L2 VMC
+ iL1 iL2
Vin _ (Group A and
S1 S2 group F) Do2
+
Co Vo Rload
_

Figure 11. Modification to convert a floating output converter to a grounded output con-
verter.

there will never be equal current sharing between the inductors. In converters where an LC
filter is used, there will not be equal current sharing between phases. Table 1 summarizes
the differences between the VMCs and illustrates this.

2.4. POSSIBLE MODIFICATIONS TO THE TOPOLOGIES

The presented family can be modified to obtain specific features such as isolation,
where a transformer can be inserted between the interleaved boost stage and the VMC stage,
or to convert a topology with a floating output to a grounded output.
2.4.1. Convert a Floating Output Converter to Grounded Output. Groups A
and F have a floating output, where the output has a different reference point than the
input. In voltage control mode, a differential sensor is required for the feedback loop.
Designers can convert floating outputs to grounded outputs by adding a diode to the VMC,
and connecting the output to the ground, as shown in Figure 11. Although the voltage stress
across the components in the grounded output converter are still the same as the ones in the
floating output converter, the voltage gain is significantly reduced. Figure 12 shows group
A and F with the grounded output.
 29

Vin

+
-
Vin

-
L1 L2
L1 L2

iL1 iL2 D1 D3 Do1 D1a D2a Do1

iL1 iL2
+ +
C1a C3b
+ + + +
C1 C2 C3 C4
+
+
Do2 vo
Do2 Co R
_
D2 D4
S1 S2 +
Co R S1 S2
+ +
C1b C3a

D1b D2b

(a) (b)

Figure 12. Group A and F can be converted to have a grounded output. Both have an ideal
voltage gain of M = N+1 N
1−d , which is 1−d less than the ones with floating outputs.

Do
D1
L1 L2 +
+ iL1 iL2 Isolation
Vin _ C1 C2 Co Vo Rload
S1 S2 _
D2

Interleaved boost stage N1:N2 Voltage multiplier

Figure 13. The presented family can be modified by adding an isolation device to meet the
isolation requirement and improve the voltage gain.

2.4.2. Modification to Make the Converter Isolated. This family can easily be
a family of isolated converters by adding a transformer or coupled inductors between the
interleaved boost stage and the VMC stage, as shown in Figure 13. After adding the isolation
device with an N1 : N2 turns ratio, the voltage gain can be calculated as

N2
Misolated = Mnonisolated × (9)
N1
 30

+
-
Vin

L1 L2 C3 C5
+ +

iL1 iL2 D1 D3 D4 D5 Do

+ + C4 +
C1 C2 Co R

D2
S1 S2

Figure 14. Example of nonuniform topologies. The converter features two different types
of VMCs, a cell from group F and Cockcroft-Walton VMC.

2.4.3. Connecting Two Different VMCs to Obtain the Overall Nonuniform Con-
verter. Extra possible combinations of different voltage multiplier cells can be derived, e.g.,
but will be unable to expand one or both VMCs. The analysis of nonuniform converters is
performed on a case by case basis. Figure 14 shows an example of nonuniform combina-
tions. The converter consists of one cell from group F followed by Cockcroft-Walton cells.

3. MODES OF OPERATION AND STEADY-STATE ANALYSIS OF AN

EXAMPLE CONVERTER

This section presents a detailed analysis of the circuit, shown in Figure 15. The
converter is driven by two 180◦ out phase signals, as shown in Figure 6. The equivalent
circuit of the three modes is shown in Figure 16 (a-c). The analysis was performed with
several assumptions: 1) All components are ideal; 2) The capacitors are large enough that
 31

Table 1. Comparison of different interleaved DC-DC converters

With output diode and capacitor filter (Figures. 8 and 9) With LC filter (Figure 10)
hI L1 i hI L1 i
Group Output Diodes/stage Caps/stage Ideal voltage gain hI L2 i Ideal voltage gain hI L2 i

N−1+d

N even


2N+1 N 2N

 N+1−d
A Floating 2 2 1−d N+1 1−d
N−d

N odd


 N+d

  
 −(2N+1)  −(2N)  N+1−d
N even N even N even

 
 


 1−d N+1

 1−d 
 N−1+d
B Floating/ inverting 2 2 N
2N+1 2N N+d
  
N odd N odd N odd

 
 

 1−d  1−d  N−d
  
  
 −(2N+1)  −(2N)  N−d
N odd N odd N odd

 
 


 1−d N

 1−d 
 N+d
C Floating/ inverting 2 2 N+1
2N+1 2N N+d−1
  
N even N even N even

 
 

 1−d  1−d  N+1−d
  
 
N N+1−2d
 
N even N odd

 

N+1

 N+2 N+1−d

 N+1
D Grounded 1 1 1−d 1−d
N
 
 1 N odd N even

 

 N+2(1−d)
 
 
N N+1−2d
 
 N+2 N even N odd

 

N+1
 N+1−d

 N+1
E Grounded 1 1 1−d 1−d
N
 
 1 N odd N even

 

 N+2(1−d)
 
2N+1 N 2N N+d
F Floating 2 2 1−d N+1 1−d N−d

2N+1 N 2N N+d
G Floating 2 2 1−d N+1 1−d N−d

Nup + Ndn even


 1
2 max(Nup ,Ndn )
 
Nup + Ndn odd
 
1/V MCdn 1/V MCdn
 
Nup +Ndn
 

 1−d  

Nup −(1−d)
H Floating 1 Nup > Ndn


1−d 
Ndn +(1−d)
Nup +Ndn Nup + Ndn odd


Nup + Ndn even
 
1/V MCdn 1/V MCdn

 

 1−d 
Nup +(1−d)
Nup < Ndn
  
 

 

  Ndn −(1−d)

ripples can be neglected; 3) The converter is operating in the steady-state condition; 4) The
duty cycles of the active switches are symmetrical; and 5) The converter is fed by a single
voltage source.

3.1. MODE 1: BOTH MOSFETS ARE ON

In this mode, both inductors draw energy from the source, and all diodes are in
reverse biased mode. The output load is fed by the output capacitor. The voltage across the
inductors is given by
v L1 = v L2 = Vin . (10)
 32

+-
Vin

L1 L2
D1a D2a D3a Do
iL1 iL2
+ + +
C1a C2a C3a

Co vo R
_
S1 S2
+ + +
C1b C2b C3b

D1b D2b D3b

Figure 15. Example converter; an interleaved boost stage with a 3 level VMC
+-

Vin

L1 L2
D1a D2a D3a Do
iL1 iL2
+ + +
C1a C2a C3a

Co vo R
_
S1 S2
+ + +
C1b C2b C3b

D1b D2b D3b

(a)
+-

Vin

L1 L2
D1a D2a D3a Do
iL1 iL2
+ + +
C1a C2a C3a

Co vo R
_
S1 S2
+ + +
C1b C2b C3b

D1b D2b D3b

(b)
+-

Vin

L1 L2
D1a D2a D3a Do
iL1 iL2
+ + +
C1a C2a C3a

Co vo R
_
S1 S2
+ + +
C1b C2b C3b

D1b D2b D3b

(c)

Figure 16. Modes of operation of the example converter; (a) mode 1 (b) mode 2 (c) mode 3
 33

3.2. MODE 2: S1 IS ON AND S2 IS OFF

In this mode L1 still draws energy from the source, L2 discharges into the VMC
capacitors, and all diodes are in reverse biased mode. The voltage across the inductors is
given by
v L1 = Vin, (11)

v L2 = Vin − VC1a = Vin − VC1b = Vin + VC2a − VC3a = Vin + VC2b − VC3b . (12)

3.3. MODE 3: S1 IS OFF AND S2 IS ON

In this mode L1 discharges into the VMC capacitors, L2 draws energy from the
source, and all diodes are in reverse biased mode. The voltage across the inductors is given
by

v L1 = Vin + VC1a − VC2a = Vin + VC1b − VC2b = Vin + VC3a + VC3b − Vo, (13)

v L2 = Vin . (14)

3.4. STEADY-STATE VOLTAGE GAIN

Steady state equations can be derived from the state equations by a voltage-second
balance on the inductors. The average voltage across the inductors is given by

v L1 = v L2 = 0 (15)

The voltage across each first-stage capacitor is given by

Vin
VC1a = VC1b = . (16)
1−D
 34

The voltage of each second-stage capacitor is given by

2Vin
VC2a = VC2b = . (17)
1−D

Each third-stage capacitor’s voltage is given by

3Vin
VC3a = VC3b = . (18)
1−D

Therefore, the output voltage transfer function is given by

Vo 7
M= = . (19)
Vin 1 − D

For N number of VMC stages, the transfer function is given by

2N + 1
M= . (20)
1−D

The previous analysis was for a converter that is being fed by a single source, and
equal duty cycles were assumed. The proposed converter is capable of being fed by two
independent voltage sources, e.g., different PV panels, as shown in Figure 17. Also, it can
operate at different duty ratios, which is suitable for tracking the maximum power point for
each PV panel. The Table 2 summarizes the voltage gain in cases with two different sources
and asymmetrical duty cycles.

4. COMPONENT SELECTIONS AND EFFICIENCY ANALYSIS

This section presents details about the design and component selections of the
example converter.
 35

Table 2. Output voltage at different cases of the input current and duty cycles

Case the output voltage

NVin1 (N+1)Vin2
d1 , d2 and Vin1 , Vin2 1−d1 + 1−d2

(N+1)
d1 , d2 and Vin1 = Vin2 N
Vin ( 1−d1
+ 1−d2 )

d1 = d2 and Vin1 , Vin2 1

1−d (NVin1 + (N + 1)Vin2 )
(2N+1)Vin
d1 = d2 and Vin1 = Vin2 1−d

Vin2

Vin1 L1 L2
D1a D2a D3a Do
iL1 iL2
+ + +
C1a C2a C3a

Co vo R
_
S1 S2
+ + +
C1b C2b C3b

D1b D2b D3b

Figure 17. The example converter can convert the voltage from two independent power
sources.
 36

4.1. INDUCTOR SELECTION

The critical inductance that ensures CCM operation is given by

Rd(1 − d)2
L1crit = , (21)
N(2N + 1) fs

Rd(1 − d)2
L2crit = . (22)
(N + 1)(2N + 1) fs

However, to select an inductor based on the percentage of the ripple, one should follow

Vin d
L1 = , (23)
∆i L1 fs

Vin d
L2 = . (24)
∆i L2 fs

The average current passing through inductors L1 and L2 is as follows:

Vo N
IL1,avg = , (25)
R (1 − d)

Vo N + 1
IL2,avg = . (26)
R (1 − d)

The peak currents can be calculated as follows:

Vo N dVin
IL1,pk = + , (27)
R (1 − d) L fs

Vo N + 1 dVin
IL2,pk = + . (28)
R (1 − d) L fs

The RMS currents are given by

v
u
t !2
2
Vo N dVin
IL1,r ms = + √ , (29)
R(1 − d) 2 3L fs
 37
v
u
t !2
2
Vo (N + 1) dVin
IL2,r ms = + √ . (30)
R(1 − d) 2 3L fs

4.2. ACTIVE SWITCHES SELECTION

The voltage stress across MOSFETs can be calculated by

Vin
VS1 = VS2 = (31)
1−d

and the average current passing through the MOSFETs is given by

 
Vo dN
IS1,avg = +N +1 , (32)
R 1−d

Vo d(N + 1)
 
IS2,avg = +N . (33)
R 1−d

The root mean square value of the switch current is given by

r   2  2
(2N+1)Vin (2d−1)
IS1r ms = Vo
R
dN
1−d +N +1 + 2L fs , (34)

r  2  2
d(N+1) (2N+1)Vin (2d−1)
IS2,r ms = Vo
R 1−d +N + 2L fs . (35)

4.3. DIODE SELECTION

The voltage stress across the diodes is a function of the number of stages. The
voltage stress is reduced as the number of stages increases, and that comes at the cost of
efficiency. The voltage stress is given by

2Vo
VD = . (36)
(2N + 1)
 38

The average current passing through each diode can be calculated by

ID N ,avg = Io (37)

and the RMS value of the diodes can be calculated as

r
1
ID,rms = Io . (38)
1−d

4.4. CAPACITOR SELECTION

The capacitor is selected based on the tolerated voltage ripple, and it can be calculated
using the following equation
Io (1 − d)
C= . (39)
f ∆v

The RMS value of the current passing through the output capacitor is given by

s
d
ICo,r ms = Io (40)
(1 − d)

and the RMS current of the other capacitors can be calculated by

s
d
ICn,r ms = Io (1 + ) (41)
(1 − d)

5. POWER LOSSES AND EFFICIENCY ANALYSIS

The power losses in the inductors are given by

PL = IL21,r ms DCR1 + IL22,r ms DCR2 (42)

 39

where DCR1 and DCR2 are the DC resistance. The power losses in the active switches can
be divided into two parts: switching loss and conduction loss. The switching loss can be
calculated using the following equation:

1
PSW = 2( × IL,avg × VS × (tOFF + tON ) fs
2
1
+ × fs × Coss × VS2 ). (43)
2

The conduction loss part is given by

PS,conduction = Is21,r ms R1 (on) + IS22,r ms R2 (on) (44)

where R1 (on) and R2 (on) are the drain-source resistance of S1 and S2 . The power loss in
the diodes can be calculated by

N
Õ N
Õ
PD = IDavg × VF + IDr ms × r f (45)
i=1 i=1

where VF is the forward voltage of the diode, and r f is the bulk resisor. The power loss in
the capacitors due to the equivalent series resistance (ESR) is given by

PC,total = N IC2n,r ms E SRn + IC2o,r ms E SRo . (46)

The total loss is given by

Ploss = PD,total + PC,total + PS,conduction + PSW + PL (47)

The overall efficiency of the converter is given by

Po
η% = × 100. (48)
Ploss + Po
 40

6. SIMULATION

The example converter was simulated in PLECS/MATLAB, with a maximum time

step of 10−7 s and tolerance of 10−3 . The parameters used in the simulation are listed in
Table 3. The major waveforms are plotted in Figure 18. The voltage stress across the active
switches is 57 V. The average current on L1 and L2 is 4.28 A and 5.7 A, respectively.
The maximum voltage across the diodes is 114 V. The average and effective values of the
current passing through each diode are 0.5 A and 0.84 A. The voltage across the capacitors
is shown in Figure 19. The currents passing through the diodes and capacitors are shown in
Figure 20 and Figure 21, respectively. The first-stage capacitors C1 A and C1B have a voltage
of 57 V, the second-stage capacitors have a voltage of 114 V, and the third-stage capacitors
have a voltage of 171 V. The RMS current of the output capacitor is 0.68 A, while the other
capacitors have an RMS current of 1.18 A. The efficiency analysis was performed using the
loss equations of the components and the rating from the datasheets of the components used
for implementing the hardware prototype. The approximate loss breakdown and breakdown
percentage as a function of the output load is depicted in Figure 22. The total loss at 200 W
is about 4.98 W. The major source of loss is the conduction loss in the diodes, which counts
for about 68%. The conduction loss in the MOSFETs is about 13%, and the switching loss
is about 7% of the total loss. The conduction loss in the inductors counts for about 11%,
and the total loss caused by the ESR of the capacitors is less than 1%.

7. EXPERIMENTAL IMPLEMENTATION AND RESULTS

A 200 W hardware prototype was implemented and tested to further verify the
operation of the example converter. The components used to construct the hardware
prototype are listed in Table 4, and the experimental setup is shown in Figure 23. The
converter was designed for a nominal duty cycle of 0.65 and increased to roughly 0.657
to compensate for the gain reduction caused by the diodes’ forward voltage and losses in
 41

Active switches voltage S1 S2

60
40
20
0
Active swtiches current S1 S2
15
10
5
0
Inductor voltage L1 L2
20
0
-20
-40
Inductor current L1 L2
6

Diodes voltage D1a , D3a , D2b

100

Diodes voltage D3b , D1b , D2a , Do

100

0
2.0000 2.0001 2.0002 2.0003 2.0004 2.0005 × 1e-1
Time [s]

Figure 18. Simulation waveforms of voltages and currents across semiconductor switches
and inductors

420
VCo
380

340

300
Voltage [V]

260

220

180 VC3A VC3B

140 VC2A VC2B

100
VC1A VC1B
60
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
Time [s]

Figure 19. Simulation waveforms of the capacitors’ voltage and the output voltage in the
steady-state
 42

C1A ,C1B,C3A,C3B C2A ,C2B

Current [A]
2

-2
Co

Current [A]
1

2.0000 2.0001 2.0002 2.0003 × 1e-1

Time [s]

Figure 20. Simulation of the capacitors’ currents

D1A , D1B D2A , D2B

2.0

1.5
Current [A]

1.0

0.5

0.0
D3A , D3B Do
2.5
2.0
Current [A]

1.5
1.0
0.5
0.0
2.00000 2.00005 2.00010 2.00015 2.00020 × 1e-1
Time [s]

Figure 21. Simulation waveforms of the diodes’ currents

Table 3. List of Parameters used in simulation

Parameter Value
Input voltage 20 V
Output voltage 400 V
Load resistance 800 Ω
Ideal duty cycle 0.65
Switching frequency 100 kHz
Inductors 100 µH
Capacitors 10 µF
 43

MOSFETs Conduction MOSFETs Switching Diodes Inductors Capacitors

5 100
4.5 90
4 80
3.5 70

Percentage [%]
Power loss [W]

3 60
2.5 50
2 40
1.5 30
1 20
0.5 10
0 0
0 20 40 60 80 100 120 140 160 180 200 0 20 40 60 80 100 120 140 160 180 200
Power [W] Power [W]

Figure 22. Efficiency analysis of the example converter; the actual losses (left) and the loss
breakdown (right)

wires. The AFG3052C signal generator was used to generate gate signals with a switching
frequency of 50 kHz. The converter is fed by 20 V, where N5700 power supply is used, and
the output load is implemented using ceramic resistors with various values. The voltage
stress across the active switches and diodes are shown in Figure 24, which supports the
simulation results as the voltage across the active switches equals 57 V, and the maximum
voltage stress across the diodes equals 124 V. The voltage across the capacitors is shown
in Figure 25. The voltage across each capacitor in the first stage equals 57 V, in the second
stage equals 133 V, and in the third stage equals 200 V. The output voltage equals 400 V.
The current waveforms of inductors, switches, and capacitors were acquired at ≈ 100 W,
as shown in Figure 26 and 27. The peak efficiency of the converter is about 97% at 160 W
and about 96.3% at 200 W.
 44

Auxiliary Oscilloscope
supply
Measurement devices

The proposed
Signal generator VDC converter
Ceramic
The load resistors
The hardware
prototype
Signal generator

Figure 23. The hardware prototype and the experimental setup

Table 4. List of Components used for the hardware prototype

Item Designation Rating Part No.

Inductor L1, L2 100 µH, DCR = 25 mΩ, 60B104C

C1A, C2A
Capacitor C1B C2B 10 µF B32674D3106K
C3AC3B

Capacitor Co 22 µF B32774D4226K000
150 V, 37 A
MOSFET Q 1, Q 2 IPA105N15N3
Rds(on) = 10.525 mΩ
D1A, D2A 250V, 40A
Diode MBR40250G
D1B, D2B VF = 0.86 V, trr = 35 ns
L100J100E, L225J50RE
load Rload multiple values
L225J250E,L225J500E
 45

VS1 (50 V/div) VS1 (50 V/div)

VS2 (50 V/div) VD3a (100 V/div)

VD1a (100 V/div) VD1b (100 V/div)

VD2a (100 V/div) VD2b (100 V/div)

VS1 (50 V/div)

VD3b (100 V/div)

VDo (100 V/div)

Figure 24. Experimental results of the voltage across the active switches and the diodes

Vin (25 V/div) VC1B (50 V/div)

VC1A (50 V/div) VC2B (100 V/div)

VC3B (100 V/div)

VC2a (100 V/div)
VCo (250 V/div)
VC3a (250 V/div)

Figure 25. Experimental results of the voltage across the capacitors

 46

Gate signal S1 VS1 (50 V/div)

IS1(5 A/div)
IL1 (2 A/div)

IL2 (2 A/div)
IS2 (5 A/div)
Iin (2 A/div)
ID1a (2 A/div)

VS1 (50 V/div) VS1 (50 V/div)

ID2a (2 A/div) ID2b (2 A/div)

ID3a (2 A/div) ID3b (2 A/div)

ID1b (2 A/div) IDo (2 A/div)

Figure 26. Experimental results of the input current, inductor currents, active switches and
diode currents

VS1 (50 V/div) VS1 (50 V/div)

IC1A = IC1B (2 A/div)

ICo (2 A/div)

IC2A =IC2B (2 A/div)

Io (2 A/div)

IC3A =IC3B (2 A/div)

Figure 27. Experimental results of the capacitors’ currents and the output current
 47

8. CONCLUSION

In this paper, the family of an interleaved boost converter with voltage multiplier
cells was presented. The general structure of the family consists of two sections: an
interleaved boost stage and voltage multiplier cells. The structure comes in two configu-
rations. Configuration 1’s output is filtered using an output diode and a capacitor filter,
where configuration 2’s output is filtered using an LC filter. The difference between the two
configurations was explained, and a comparison between the various family members was
presented. An example of this family was given with a detailed steady-state analysis and
component selection, which was evinced by simulation. A 200-W hardware prototype was
implemented to further verify the analysis and the simulation. The converter is capable of
drawing power from both a single or dual independent input voltage and with the same or
different duty cycles of the active switches. These cases were summarized and compared.
The family has good features besides the high-voltage gain. The input current ripple has
twice frequency of the one in the conventional boost converter, which reduces the filter
requirements and increases the accuracy of the current sensing for better tracking of MPPT.
Although the converter is efficient, the efficiency can be further increased by either replacing
the diodes with better ones or with active switches, with a trade-off of the complexity.

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 52

II. HIGH-VOLTAGE-GAIN DC-DC STEP-UP CONVERTER WITH BI-FOLD

DICKSON VOLTAGE MULTIPLIER CELLS

Ahmad Alzahrani, Pourya Shamsi, and Mehdi Ferdowsi

Departement of Electrical and Computer Engineering
Missouri University of Science and Technology
{asakw9, shamsip, ferdowsi}@mst.edu

ABSTRACT

This paper presents an interleaved boost converter with a bi-fold Dickson voltage
multiplier suitable for interfacing low-voltage renewable energy sources to high-voltage
distribution buses and other applications that require a high-voltage-gain conversion ratio.
The proposed converter was constructed from two stages: an interleaved boost stage, which
contains two inductors operated by two low-side active switches, and a voltage multiplier
cell (VMC) stage, which mainly consists of diodes and capacitors to increase the overall
voltage gain. The proposed converter offers a high-voltage-gain ratio with low voltage
stress on the semiconductor switches as well as the passive components. This allows the
selection of efficient and compact components. Moreover, the required inductance that
ensures operation in the continuous conduction mode (CCM) is lower than the one in the
conventional interleaved boost converter. The distinction of the proposed converter is that
the inductors’ currents are equal, regardless of the number of VMCs. Equal sharing of
interleaved boost-stage currents reduces the conduction loss in the active switches as well
as the inductors and thus improves the overall efficiency, as the conduction power loss is a
quadratic function. In this paper, the theory of operation and steady-state analysis of the
proposed converter are illustrated and verified by simulation results. A 200 W hardware
prototype was implemented to convert a 20 V to a 400 V DC load and validate both the
theory and the simulation.
 53

Keywords: High-Gain, bi-fold Dickson, DC-DC, VMC, Renewable, PV, Solar, MPPT

1. INTRODUCTION

Step-up DC-DC converters with high-voltage-gain ratios were only used in a limited
number of applications, such as radar and X-ray systems. Currently, they are being used in
a wide variety of applications such as photovoltaic (PV) panels’ interface to a microgrid or
a DC distribution bus, as shown in Figure 1(a), or power distribution unit (PDU) to power
data centers and supercomputers [1], as shown in Figure 1(b). Both applications deploy a
400 VDC distribution system due to its advantage over an AC distribution system in terms
of the number of conversion units, size, cost, and immunity against load disturbances and
ground faults [2–6]. Most PV panels have an output voltage range between 15 and 45 V [7],
which is very low. Integrating a PV panel to a 400 VDC is a challenging task and necessitates
a high-voltage-gain step-up converter.
The conventional boost converter (CBC) requires operation at very high duty cycles
to obtain a high-voltage-gain ratio. In practice, the gain of the CBC is limited by the
conduction losses, and obtaining a high-voltage-gain ratio is not feasible. Not only that,
but the CBC also suffers from the voltage stress and reverse recovery phenomenon at high
voltages [8] and requires a large inductor to operate in the CCM. Derived topologies from
the CBC, such as cascaded boost converters, can achieve a higher voltage and operate
at low duty cycles [9, 10]. However, they suffer from low efficiency due to the power
being processed multiple times and require complicated control and extra effort to ensure
stability [11, 12]. The three-level boost converter is derived from the series-input series-
output multiphase boost converter. The stress on the switches and inductance requirement is
reduced. However, it still has the same gain as the CBC [13–15]. The single-switch quadratic
boost converter has a simple structure and does not suffer from instability like the cascaded
boost converter. However, the voltage and current stress across the switches are high, and
the inductor that ensures the CCM operation is large. Using isolated topologies such as
 54

forward, flyback, or full-bridge converters, the high-voltage-gain ratio at can be achieved

lower duty cycles by increasing the turns ratio of the transformer [16–18]. However, such
devices suffer from parasitic leakage inductance, which significantly increases the voltage
stress on the active switches and can cause damage unless additional auxiliary is used [19].
Isolated converters generally have low power density, higher cost, and lower efficiency than
non-isolated converters [20–22].
Using VMC with the CBC increases the voltage gain and improves the performance,
as the total indirect power is reduced [23, 24]. Nevertheless, the inductor size is still
relatively substantial to obtain a smooth input current. Therefore, topologies such as those
found in [25, 26] use VMCs with an interleaved boost stage to reduce the magnetic storage
requirement and obtain a smoother input current. The stress on the internal components
depends on the VMC connections and the number of cells (e.g., the modified Dickson cell
has lower voltage stress across the components than the original Dickson cell). This paper
presents a high-gain interleaved DC-DC converter that is an improved version of [25, 26].
The features of the proposed converter can be summarized as follows: 1- The converter has
a high-voltage-gain ratio that is sufficient for the integration of renewable energy sources to
a high voltage DC bus. 2- The voltage stresses across active switches, diodes, and passive
components are low, and that allows the selection of components whose cost, efficiency, and
compactness are balanced. 3- The input current is shared equally between the two phases,
regardless of the number of VMC stages. Therefore, the conduction loss of the interleaved
boost stage and the thermal dissipation requirement are reduced. 4- The converter has two
capacitors at each stage, in which voltage ripple cancellation is achieved. 5- The input
current is continuous and has low ripple due to the interleaving. Hence, continuity of the
input current reduces the filter requirement and allows accurate current measurement for
maximum power point tracking (MPPT). 6- The converter does not need an output diode
or an LC filter to rectify or regulate the output voltage such as in [25, 26]. Each stage can
produce a constant DC voltage.
 55

Figure 1. Application of a high-gain DC-DC converter

The rest of this paper is structured as follows. First, the construction of the bi-fold
Dickson cell and the Dickson voltage multiplier is presented and explained in Section 2.
The theory of operation and a comparison to similar converters is illustrated in Section
3. The analysis of CCM modes and steady-state voltage gain formulas are derived in
Section 4. Section 5 presents the operation of the converter in the discontinuous conduction
mode and the boundary conduction mode The component selections and their power loss
models are derived in Section 6, and the simulation results are presented in Section 7. The
implementation of the hardware prototype and the experimental results are explained in
Section 8. Finally, conclusions and future work are presented in Section 9.
 56

S S S S S S
C S C C S C C S C C S C C S C CS C
chain 1 ϕ1 ϕ2 ϕ1 ϕ2 ϕ1 ϕ2 ϕ1 ϕ2 connected
ϕ1 ϕ2 ϕ1 ϕ2
two Dickson chains
ϕ1 ϕ2 ϕ1 ϕ2
S S
C S C C S C S C C S C S C S C S C S C S C
flipped S
chain 2 ϕ1 ϕ2 ϕ1 ϕ2

Figure 2. The construction of a bi-fold Dickson cell. The BD cell is constructed using two
conventional Dickson cells, and one of the cells is rotated by 180◦ . Then, they are connected
so that a single VMC stage consists of two complementary switches and two capacitors.

A C A C
D D C D D
Q C Q̅ C Q C Q̅ C C C C

ϕ2 ϕ2

ϕ1 ϕ1
C C C C C C C C
Q̅ Q Q̅ Q D D D D
B D B D

Stage 1 Stage 2 Stage 3 Stage 4 Stage 1 Stage 2 Stage 3 Stage 4

Figure 3. Implementation of a bi-fold Dickson switched capacitor (left) and a bi-fold voltage
multiplier cell (right) with N = 4.

L
A C A C A C
Q1 Q3 Q1 Q3
bi-fold ϕ2 bi-fold
ϕ2 ϕ2 bi-fold R
Dickson Dickson
ϕ1 Dickson
R R
Vin ϕ1 Vin ϕ1
Q2 Q4 VMC Q2 Q4 VMC VMC
B D B D B D

(a) (b) (c)

A C A C A
T1 C
Q1 Q1
1:N L1 L1
ϕ2 bi-fold ϕ2 bi-fold ϕ2 bi-fold
Vin R Dickson R
Dickson Dickson R
ϕ1 ϕ1 VMC ϕ1 VMC
VMC Vin Vin
L2 Q2 D L2 Q2
B D D
B B

(d) (e) (f)

Figure 4. Several examples of using bi-fold Dickson VMC in various power electronics
topologies. The VMC can be used in (a) a voltage-fed circuit, (b) a current fed circuit, (c-d)
AC rectification circuits, and (d-e) interleaved high-voltage-gain DC-DC circuits.
 57

2. CONSTRUCTION OF BI-FOLD DICKSON SC/VMCS

The conventional Dickson charge pump or voltage multiplier is shown in Figure 2.

The circuit takes a DC input voltage and converts it to high-level voltage by charging and
discharging internal capacitors. It has been utilized in a variety of applications, including
nonvolatile memories, RF antenna switched controllers [27], and recently it was used for
ultra step-up voltage ratio converters [26]. The challenge with a Dickson voltage multiplier
is that the stress across the capacitors increases as the number of stages increases. Although
multiple capacitors can be connected in a series to satisfy the voltage rating, voltage
mismatches between capacitors might appear. One way to remove the mismatches is by
connecting a resistance in parallel with the capacitors. That makes the resistance dissipate
the excessive power. However, this method might not work in high power applications
because of the high power dissipation and thermal limitations. Therefore, this paper
introduces a bi-fold Dickson voltage multiplier to reduce the voltage stresses on both
semiconductors and capacitors. The construction of the bi-fold Dickson cell is shown in
Figure 2. The cell is constructed by using two traditional Dickson cells and rotating one
by 180◦ . Then, the capacitors of the upper cell are connected to the capacitors of the lower
cell. That is, phase φ1 of the upper cell is connected to φ1 in the lower cell, and likewise for
the capacitors connected to phase φ2 . The proposed cell consists of multiple stages; each
stage has two complementary switches and two capacitors. Either active switches or diodes
can be used to implement the switches in the proposed cell, as shown in Figure 3. This
can be seen as a trade-off between efficiency, cost, and control complexity. If the switches
were implemented using diodes, the forward voltage of the diodes would compromise the
overall efficiency. However, with using diodes, the converter has spontaneous split-phase
control [28]. The diodes remain reverse-biased until the voltage mismatches between the
capacitors are gone. Therefore, no current spikes are present. Alternately, if the switches
are implemented using active switches, the efficiency can be significantly improved, but
complex control is needed. That is, the switches must be delayed to prevent temporary
 58

KVL violations that cause current spikes. In addition to the control, the circuit requires a
large number of gate-driving circuits with level shifting and isolation components to drive
the floating switches. In this paper, the proposed converter is implemented using only
diodes. Figure 4 shows the use of the cell in different power circuits. The cell can be used
in a voltage-fed DC-DC converter [29] or current-fed DC-DC converter [30], as shown in
Figure 4(a,b), respectively. Also, it can be used in AC rectification circuits as in a typical
60 Hz AC source, in both isolated and non-isolated topologies as shown in Figure 4(c,d),
or a high-frequency AC system (e.g., the 20 kHz Space Station power distribution system
proposed by NASA) [31]. In this paper, the cell is used with an interleaved boost stage, as
shown in Figure 4(e,f), to convert low-voltage DC sources to higher DC voltages.

3. THE PROPOSED TOPOLOGY INTRODUCTION AND THEORY OF

OPERATION

The proposed converter consists of an interleaved boost stage and a bi-fold Dickson
multiplier cell stage. The interleaved stage consists of two inductors connected to the input
source and switched by two low-side active switches. The function of the interleaved boost
stage is to store energy and release it to the bi-fold Dickson VMC capacitors. Figures 5(a),
(b), and (d) show the interleaved boost converter with a different number of bi-fold Dickson
VMCs. Note that the proposed converter with N = 2, shown in Figure 5(b), is similar to
the interleaved boost converter with the Greinacher VMC that was proposed in [32], shown
in Figure 5(c). The only difference is that the Greinacher cell is not extensible. Each stage
contains two diodes and two capacitors, as shown in Figure 5(d). The proposed converter
has three modes of operations: mode 1, where both switches are ON; mode 2, where switch
1 is ON and switch 2 is OFF; and mode 3, where switch 1 is OFF and switch 2 is ON. The
switching patterns can be seen in Figure 6. There is a 180◦ phase shift between the active
switches’ gate signals. This topology, unlike [25], can work with both active switches open
and without violating voltage second balance across input inductors. However, opening both
 59

active switches creates several drawbacks to the interleaved topology, such as a reduction in
the voltage gain and an imbalance between capacitor voltage. Therefore, it is not beneficial to
use this topology for a duty cycle less than 50%. To conduct the analysis, a few assumptions
are considered: 1) All components of the proposed converter are ideal; 2) The capacitors
are large enough that the voltage ripples can be neglected; 3) The converter operates in the
steady state; 4) The duty cycles are symmetrical and greater than 50%, and the converter is
fed by a single voltage source. Nonetheless, the voltage gain ratio of the proposed converter
will be summarized for cases where the duty cycles are asymmetrical and for cases where
the converter is fed by two independent voltage sources.

4. MODE ANALYSIS AND STEADY STATE VOLTAGE GAIN

4.1. MODE 1 (T0 − T1 ) AND (T2 − T3 ) : BOTH Q1 AND Q2 ARE ON

In this mode, both active switches are conducting and allowing the source to transfer
energy to both inductors. All diodes are reverse-biased, and they are OFF. The equivalent
circuit of this mode is shown in Figure 7(a). The last-stage capacitors, C3A and C3B keep
the energy level to the output load. The state equations of this mode are given by

di L1
L1 = v L1 = Vin (1)
dt

di L2
L2 = v L2 = Vin (2)
dt

4.2. MODE 2 (T1 − T2 ): Q1 IS ON AND Q2 IS OFF

In this mode, Q1 is still ON, and L1 keeps drawing energy from the source. Alter-
nately, Q2 is turned OFF, and the energy in L2 is released to the VMC stage. Diodes D1B ,
D2 A , and D3B are forward-biased and ON, while diodes D1 A ,D2B , and D3 A are reverse-biased
 60

L1 D1A
iL1
_
+ vL 1 +
iL2 L2
_
vC 1A C1A
iin + vL 2
_

+
vo R
_
Vin
Q2 Q1 +
vC 1B C1B
_

D1B

(a)
L1 D1A D2A L1 D1A D2A
iL1 iL1
_ _
+ vL + + vL +
L2
1
+ L2
1
+
iL2 vC iL2 vC
_ 1A C1A vC C2A _ 1A C1A vC C2A
iin + vL 2
_ _
2A
iin + vL 2
_ _
2A

+ +
vo R vo R
_ _
Vin Vin
Q2 Q1 + Q2 Q1 +
+ +
vC 1B C1B vC C2B
vC 1B C1B vC C2B
_ _
2B _ _
2B

D1B D2B D1B D2B

(b) (c)

L1 D1A D2A D3A

iL1
_
+ vL +
L2
1
+ +
iL2 vC
_ 1A C1A vC C2A vC C3A
iin + vL 2
_ _
2A
_
3A

+
vo R
_
Vin
Q2 Q1 + + +
vC 1B C1B vC C2B vC C3B
_ _
2B
_
3B

D1B D2B D3B

(d)

Figure 5. Interleaved boost converter with Dickson voltage multiplier a) N = 1 and VVino = 1−d
2

b) N = 2 and VVino = 1−d

4
c) Interleaved boost converter with a Greinacher VMC, which has
the same gain as (b). d) The proposed converter with N = 3 and a gain of VVino = 1−d 6
. The
analysis, simualtion, and experiment are based on this topology.
 61

Mode-I Mode-II Mode-I Mode-III Mode-I

Ts
Q1
d1Ts

180° t
Ts
Q2
d2Ts

t
t0 t1 t2 t3 t4

Figure 6. Switching pattern of two-phase boost converter. The phase shift between the
active switches’ duty cycles yields three modes of operation.

L1 D1A D2A D3A

iL1
_
+ vL +
L2
1
+ +
iL2 vC
_ 1A C1A vC C2A vC C3A
iin + vL 2
_ _
2A
_
3A

+
Vin vo R
_

Q2 Q1 + + +
vC 1B C1B vC C2B vC C3B
_ _
2B
_
3B

D1B D2B D3B

(a)
iL1 L1 D1A D2A D3A
_
+ vL1 + +
L2 +
iL2 vC
_ 1A C1A vC C2A vC C3A
+ vL _ _
2A
_
3A
iin 2

+
Vin vo R
_

Q2 Q1 + + +
vC 1B C1B vC C2B vC C3B
_ _
2B
_
3B

D1B D2B D3B

(b)
iL1 L1 D1A D2A D3A
_
+ vL +
L2
1
+ +
iL2 vC
_ 1A C1A vC C2A vC3A C3A
+ vL _ _
2A
_
iin 2

+
Vin vo R
_

Q2 Q1 + + +
vC 1B C1B vC C2B vC C3B
_ _
2B
_
3B

D1B D2B D3B

(c)

Figure 7. Modes of operation: (a) Mode 1, both Q1 and Q2 are ON; (b) Mode 2: Q1 is ON
and Q2 is OFF; (c) Mode 3: Q1 is OFF and Q2 is ON;
 62

Vin
____ 1
Vg1
1-D t
VQ1 0
0 t 1
Vin
____ Vg2
0 t
1-D
VQ2 VL1 Vin
0 t 0 t

IL1+IL2 Vin -VC1A

IL1 VL2 Vin
IQ1 IL1 IL1 t
0

0 t Vin -VC1B
IL1+IL2
Vin _______
____ Vin-VC1B ____
Vin Vin-VC1A
_______
IL2 IL2 IL2 L2 L2 L1 L1
IQ2 IL2
IL1 t
0 t 0

Figure 8. Interleaved boost stage waveforms. Voltage and currents of the active switches
(left) and voltage and currents of the inductors (right)

Vo Vo
____ Vo
____ ____
VD1A 2N N 2N
VD2B
VD3A 0 t
Vo Vo
____ Vo
VD1B ____ ____
2N N 2N
VD2A
VD3B t
0

Figure 9. Voltage stress on the diodes

and do not conduct. Inductor L1 is still being charged by the input voltage. Inductor L2 and
the input voltage charge capacitors C1B , C2 A , and C3B . The equivalent circuit of this mode
is shown in Figure 7(b), and the inductor voltages and capacitor currents are governed by

di L1
L1 = v L1 = Vin (3)
dt

di L2
L2 = v L2 = Vin − Vc1B = Vin + Vc2B − Vc3B = Vin + Vc1A − Vc2A (4)
dt

4.3. MODE 3 (T3 − T4 ) : Q1 IS OFF AND Q2 IS ON

After mode 2, the converter operates in mode 1, and then it switches to mode 3.
Mode 3 is the opposite of mode 2. In this mode, switch Q1 is turned OFF, and switch
Q2 is still ON. The equivalent circuit is shown in Figure 7(c). Diodes D1 A ,D2B , and D3 A
 63

are forward-biased. Diodes D1B , D2 A , and D3B are reverse-biased, and they are OFF. The
inductor L1 transfers its energy to the VMC stage, while L2 starts drawing power from the
source. The state equations are given by

di L1
L1 = v L1 = Vin − Vc1A = Vin + Vc2A − Vc3A = Vin + Vc1B − Vc2B (5)
dt

To find the voltage transfer function, one can apply the voltage second balance to the inductor
voltages. So, the average value of the voltage across the inductors L1 and L2 are given by

∫ dT ∫ T
hv L1 i = Vin dt + (Vin − VC1 A )dt = 0 (6)
0 dT

∫ dT ∫ T
hv L2 i = Vin dt + (Vin − VC1B )dt = 0 (7)
0 dT

From previous equations, the capacitor voltage can be obtained. The first-stage
capacitor voltage is given by

Vin
VC1 A = VC1B = (8)
1−d

The relationship between the second-stage capacitor voltage and the first-stage capacitor
voltage can be given by

2Vin
VC2A = VC2B = Vc1A + Vc1B = (9)
1−d

The third-stage capacitor voltage is given by

3Vin
Vc3A = Vc3B = Vc2A + Vc2B − Vc1B = (10)
1−d
 64

The output voltage is the sum of the voltages across the last-stage capacitors. Therefore,
the voltage gain ratio for the proposed converter with a three-stage VMC is given by

Vo 6
= (11)
Vin 1 − d

One can generalize the equations for the N th stage converter. The capacitor voltages in each
stage are given by
NVin
VcN A = VcN B = (12)
1−d

The output voltage for the N th stage converter is given by

2NVin
Vo = VcN A + VcN B = (13)
1−d

Therefore, the voltage gain ratio is given by

Vo 2N
= (14)
Vin 1 − d

Equation 14 is an ideal gain at d1 = d2 and a single input Vin . However, the converter can
work with asymmetrical duty cycle ratios and also with two independent power sources.
Table 1 summarizes the output voltage gain at different duties as well as with two different
independent input voltage sources.

Table 1. Output voltage at different cases

Case the output voltage

Vin Vin2
d1 , d2 and Vin1 , Vin2 N( 1−d11 + 1−d2 )

d1 , d2 and Vin1 = Vin2 1

NVin ( 1−d1
+ 1
1−d2 )

d1 = d2 and Vin1 , Vin2 N

1−d (Vin1 + Vin2 )
2NVin
d1 = d2 and Vin1 = Vin2 1−d
 65

100
N=1
90 N=2
N=3
80 N=4
70 N=5

Gain
60
50
40
30
20
10
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
Duty

Figure 10. Voltage gain vs. the duty cycle at different numbers of VMC stages.

Increasing the number of VMC stages increases the voltage-gain ratio, as shown
in Figure 10. However, practical voltage gain might be reduced due to the nonidealities.
The proposed converter can be compared to various interleaved topologies, such as the
interleaved boost converter with a Dickson voltage multiplier that was proposed in [26].
The circuit in [26] suffers from high voltage stress on its capacitors as the number of stages
increases, and that might be challenging in high power applications. The modified Dickson
voltage multiplier that was proposed in [25] is an improved version of the converter in [26].
The circuit connects the output ground to the first stage of the Dickson VMC, and therefore
some of the internal capacitors have reduced voltage stress. However, the output capacitor
still has high voltage stress. Another drawback of the aforementioned converters is that
there is an uneven current share between the inductors when the converter has an even
number of VMC stages. Table 2 shows a comparison summary of the proposed converter
with the converters presented in [26] and [25]. The proposed converter has the lowest
maximum stress and the highest voltage-gain ratio. The active switch voltage stress is also
the lowest. The voltage stress across diodes is equal to the converter proposed in [25].
Both the converter presented in [25] and the proposed converter have a floating output
feature, which requires a differential voltage sensor for voltage feedback. Nevertheless, the
grounded output load is not necessary to interface the PV panels, where the control circuit
goal is to extract the maximum power.
 66

Table 2. Comparison between Different Topologies

Interleaved with the Interleaved with the Proposed

Topology
conventional Dickson [26] modified Dickson [25] Converter
N+1 N+1 2N
Static Gain 1−D 1−D 1−D
Maximum stress Vo Vo Vo
on Switches N 2 2N
Maximum stress 2Vo Vo Vo
on Diodes N+1 N N
Maximum stress Vo
Vo Vo 2
on Capacitors
Equal inductors Only with Only with Equal regardless of
current sharing odd number of stages odd number of stages number of stages
Output connection grounded floating floating

1
Vin
____ Vg1
Vin t
VQ1 1-D 0
0 t 1
Vg2
Vin
____ t
1-D Vin 0
VQ2 VL1 Vin
0 t 0 t

IL1+IL2 Vin -VC1A

IL1 VL2 Vin
IQ1 IL1 IL1 t
0

0 t Vin -VC1B
IL1+IL2
IL1 t
IL2 IL2 IL2
IQ2 IL2
t 0 t
0

Figure 11. Waveforms of the DCM mode of operation

5. DISCONTINOUS CONDUCTION MODE AND BOUNDARY CONDUCTION

MODE

5.1. DCM OPERATION

In DCM mode, the converter has five modes of operation. Three of these modes are
similar to the one for a converter operating in CCM mode. The other two are mode 4 and
mode 5. Mode 4 occurs after mode 2, where IL1 is zero, and mode 5 occurs after mode 3,
where IL2 is zero. The sequence of the modes is mode 1, mode 2, mode 4, mode 1, mode
3, mode 5, and then it repeats. The waveforms of the interleaved boost stage operating in
DCM mode are shown in Figure 11
 67

L1 D1A D2A D3A

iL1
_
+ vL +
L2
1
+ +
iL2 vC
_ 1A C1A vC C2A vC C3A
+ vL _ _
2A 3A
iin 2
_

+
Vin vo R
_

Q2 Q1 + + +
vC1B C1B vC2B C2B vC C3B
_ _ _
3B

D1B D2B D3B

(a)
L1 D1A D2A D3A
iL1
_
+ vL +
L2
1 + +
iL2 vC1A
_ C1A vC2A C2A vC C3A
iin + vL 2
_ _ _
3A

+
Vin vo R
_

Q2 Q1 + + +
vC 1B C1B vC C2B vC C3B
_ _
2B
_
3B

D1B D2B D3B

(b)

Figure 12. DCM modes: a) mode 4, when i L2 hits the zero b) mode 5, when i L1 hits the zero

5.1.1. Mode 1. same as mode 1 in CCM

5.1.2. Mode 2. same as mode 2 in CCM
5.1.3. Mode 3. same as mode 3 in CCM.
5.1.4. Mode 4. During this mode, Q1 is OFF and Q2 is ON. The inductor L2 is still
being charged from the input source. The inductor L1 discharged all of its stored energy to
the VMC stages, and the current is zero. The zero current is not enough to force the diodes
to become forward-biased. Therefore all diodes are reversed-biased. The equivalent circuit
of this mode is shown in Figure 12(a).
5.1.5. Mode 5. In this mode, Q1 is ON and Q2 is OFF. The input source is charging
L1 . The L2 discharged its energy to the VMC stage, and the IL2 is zero. All diodes are
reversed=biased, and the output is fed by the last stage capacitors. The equivalent circuit of
this mode is shown in Figure 12(b).
 68

5.1.6. Steady-state Analysis. . The voltage gain and voltage across capacitors can
be obtained by applying the voltage second balance across the inductors. The voltage of the
first capacitors is calculated by

r !
1 d2
V1a = V1b = 1+ 1+ × Vin (15)
2 9τ

L× fs
where τ = R The output of the second and third stage output capacitors are given by

r !
d2
VC2a = VC2b = 1 + 1+ × Vin (16)
9τ

r !
3 d2
VC3a = VC3b = 1+ 1+ × Vin (17)
2 9τ

The output voltage equals the sum of the voltage across the last stage’s capacitors, which
can be calculated by r !
d2
Vo = 3 1 + 1+ × Vin (18)
9τ

Previous equations can be generalized for a converter with N number of stages. The
nth stage capacitor voltage is given by

s !
n 4d 2
VCna = VCnb = 1+ 1+ × Vin (19)
2 τ × (2N)2

where n is a positive integer. The voltage gain is given by

s !
4d 2
Vo = N 1 + 1+ × Vin (20)
τ × (2N)2

Figure 13 shows the voltage gain of the proposed converter in the DCM mode at τ =
1.25 × 10−3 . The voltage gain in DCM is higher than in CCM. However, that comes at the
cost of increasing the current ripples across the components.
 69

35
N=1
N=2

Voltage Gain
30 N=3
N=4
25
N=5

20

15
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95 1
D

Figure 13. The gain of the converter at τ = 1.25 × 10−3

5.2. BOUNDARY CONDUCTION MODE (BCM)

The converter is operating in BCM if the average value of the inductor current is
equal to the inductor current ripple. In BCM, one can obtain the τBCM by equating the
voltage gain of the CCM to the voltage gain of the DCM, as follows

s !
2N 4d 2
= N 1+ 1+ (21)
1−d τ × (2N)2

The time constant of the inductor is calculated by

d(1 − d)2
τBCM = (22)
4N 2

The time constant is plotted versus the duty cycle at different numbers of VMC stages, as
shown in Figure 14. CCM mode occurs when τ is more than τBCM .
 70

0.04
0.035 N=1
N=2
N=3
0.03 N=4
N=5
0.025
 BCM 0.02
0.015
0.01
0.005
0 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1
D

Figure 14. The boundary between CCM and DCM τBCM at different numbers of bi-fold
VMC cells.

6. COMPONENTS SELECTION AND EFFICIENCY CALCULATIONS

6.1. INDUCTOR SELECTION

The average value of inductor currents is dependent on the load current and the
number of VMC stages. The average value of the input current can be found with the
following equation:
2N Io
Iin = (23)
1−d

The input current is equally shared between inductors and can be calculated by

Iin N Io
IL1,avg = IL2,avg = = (24)
2 1−d

The critical inductance that is required to ensure the converter operates in CCM mode is
calculated by
Vin d(1 − d)
L1,crit = L2,crit = (25)
2N Io fs
 71

Inductors are normally designed based on the desired value of the inductor current ripple.
The equations for L1 and L2 selection are

Vin d
L1 = (26)
∆i L1 fs

Vin d
L2 = (27)
∆i L2 fs

The peak value of the inductor current is obtained by

N Io Vin d
IL1,pk = + (28)
1 − d 2L1 fs

N Io Vin d
IL2,pk = + (29)
1 − d 2L2 fs

The RMS current of the inductors is given by

s
 N I 2  V d 2
o in
IL1,RMS = + √ (30)
1−d 2 3L1 fs

s
 N I 2  V d 2
o in
IL2,RMS = + √ (31)
1−d 2 3L2 fs

6.2. ACTIVE SWITCH SELECTION

The active switches are implemented using MOSFETs due to their ability to operate
at high switching frequencies. To select MOSFETs for this topology, the maximum stresses
on the switches need to be calculated. The voltage stress on the MOSFETs depends on the
number of stages. The stresses on the active switches are given by

Vo Vin
VQ1 = VQ2 = = (32)
2N 1 − d
 72

The maximum current that passes through the switches is given by

2N Io Vin d
IS,pk = + (33)
1 − D 2L fs

The average currents passing through the active switches are given by

2N Io Vin d
IQ1,pk = IQ2,pk = + (34)
1 − d 2L fs

N Io
IQ1,avg = IQ2,avg = (35)
1−d

The RMS value is approximated by the following equation:

N Io d
IQ1,r ms = IQ2,r ms = p (36)
(1 − d)3

6.3. DIODE SELECTION

One of the advantages of this topology is that the voltage stresses across the diode
also depend on the number of stages. The more stages, the less voltage stress on the diodes.
The maximum voltage that the diodes have to block is calculated by

Vo
VD Nmax = (37)
N

The total average currents of the diode are given by

Vo
ID N A = ID NB = (38)
R

The RMS current is given by

r
Vo 1
ID N A ,rms = ID NB ,rms = (39)
R 1−d
 73

6.4. CAPACITORS SELECTION

The capacitors selection is determined by the maximum current and voltage rating.
The maximum voltage stress across the capacitors is already calculated in. Equally impor-
tant, the maximum allowed voltage ripple and frequency determine the minimum required
capacitance. Both capacitors in each VMC stage have to be equal to ensure equal current
sharing operation [33]. The output capacitor selection depends on the allowed voltage rip-
ples. Both output capacitors have to be equal, and they are selected based on the following
equation:

Io (1 − D)Ts
C= (40)
∆VC1

The RMS current of the capacitors can be given by

r
d
IC3A,r ms = IC3B,r ms = Io (41)
1−d
r !
d
IC1A,r ms = IC1B,r ms = Io 1 + (42)
1−d
r !
d
IC2A,r ms = IC2B,r ms = Io 1 + (43)
1−d

6.5. EFFICIENCY ANALYSIS

The conduction loss in the DC resistance of the inductor (RL ) is given by

φ
Õ
PL = IL2i,r ms × RLi (44)
i=1
 74

In cases of φ = 2, L1 = L2 , and RL1 = RL2 , the conduction power loss in the inductors can
be given by
N 2 Vo2 d 2Vin2
PLt ot = 2RL [ + √ ] (45)
(1 − d)2 R2 (2 3L fs )2

The total switching loss in both MOSFETs is calculated by

f Vin
PQ1SW = PQ2SW = (N Io (Ton + To f f ) + Coss Vin ) (46)
2(1 − d)2

where Coss is the output capacitance of the MOSFETs, and Ton and To f f are the turn on and
turn off times [34]. The conduction loss in the MOSFET is given by

PQ1con + PQ2con = IQ1,r ms RON1 + IQ2,r ms RON2 (47)

The conduction power loss of the diode can be calculated by

N
Õ N
Õ
PD = IDavg × VF + IDr ms × r f (48)
i=1 i=1

The power loss through a capacitor is given by

PC = IC2r ms E SR (49)

The total power loss is given by

φ
Õ φ
Õ
PLoss = PLtot + PQi,SW + PQi,cond
i=1 i=1
2N
Õ 2N
Õ
+ PDn + PCn (50)
n=1 n=1
 75

The efficiency of the converter is given by

η (%) = PLtot +
Íφ
P +
Íφ
1
P + 2N PDn + 2N PCn
Í Í × 100 (51)
i=1 Qi,SW i=1 Qi,cond n=1 n=1
1+ Vin ×Iin

More detailed information about the efficiency of the proposed converter is presented in
Section 7.

7. SIMULATION

The proposed converter was simulated using the PLECS block set in the MAT-
LAB/SIMULINK software, with the variable-step continuous solver (ode23), a maximum
time step of 10−7 s, and a tolerance of 10−5 . The component parameters used in this sim-
ulation are listed in Table 2. To avoid singular loops and errors, small parasitic elements
are included in the simulation. The voltage and current waveforms of the switches and
the inductors are shown in Figure 15. The maximum stress on active switches Q1 and
Q2 is 66.6 V, and the average and peak values of the switch currents are 5 A and 6.3 A,
respectively. Similarly, the average current of each inductor is 5 A, and the RMS current
is ' 5.1 A. The inductor currents are interleaved, and that can increase the frequency of
the input current ripple currents so that these ripples can be easily filtered out with smaller
capacitors than the CBC. Figure 16 shows the diodes’ voltage and current waveforms. The
maximum voltage stress on the diodes is 133.3 V, the average current is 0.5 A, and the
RMS current is 0.91 A. Figure 17 shows the waveforms of the voltage and the current of
the capacitors. The voltage across each of the output capacitors is ' 200 V, and the RMS
current is 1.26 A. The second stage capacitors have 133 V, and the RMS current is 0.76 A.
The first-stage capacitors have 57 V, and the RMS current is 0.76 A. The figure also shows
the capacitors’ voltage ripple cancellation at each stage.
 76

Table 3. List of parameters used in the simulation

Parameter Value
Input voltage 20 V
Output voltage 400 V
Load resistance 800 Ω
Ideal duty cycle 0.7
Switching frequency 100 kHz
Inductors 100 µH
Capacitors 10 µF
Q1 voltage L1 voltage
Voltage [V]

Voltage [V]
60 20
40 0
20 -20
0 -40
-60
Q2 voltage L2 voltage
Voltage [V]

Voltage [V]
60 20
40 0
20 -20
0 -40
-60
Q1 current L1 current
6
Current [A]

Current [A]
10
5
5
0 4
Q2 current L2 current
6
Current [A]

Current [A]
10
5
5
0 4
6.000 6.001 6.002 6.003 × 1e-2 6.0000 6.0010 6.0020 × 1e-2
Time [s] Time [s]

Figure 15. Voltages and currents of active switches (left) and inductors (right)
Q1 Voltage Q2 Voltage D1A Current D1B Current
80
Voltage [V]

Current [A]

60 2
40
20 0
0
D1A , D2B, D3A Voltage D2A Current D2B Current
150
Voltage [V]

Current [A]

6
100
4
50 2
0 0
D1B, D2A, D3B Voltage D3A Current D3B Current
150
4
Voltage [V]

Current [A]

100
2
50
0 0
6.0000 6.0010 6.0020 × 1e-2 6.000 6.001 6.002 6.003 × 1e-2
Time [s] Time [s]

Figure 16. Voltage and current stress through diodes

C1A Voltage C1B Voltage C1A Current C1B Current
Current [A]

2
Voltage [V]

67 0
-2
66 -4
-6
C2A Voltage C2B Voltage C2A Current C2B Current
Current [A]

133.5 5
Voltage [V]

133.0
0
132.5
132.0
C3A Voltage C3B Voltage C3A Current C3B Current
199.5
Current [A]
Voltage [V]

2
199.0
0
198.5
6.000 6.001 6.002 6.003 × 1e-2 6.000 6.001 6.002 6.003 × 1e-2
Time [s] Time [s]

Figure 17. Voltage and current stress on capacitors. The voltage ripples are partially
canceled.
 77

Table 4. Component Listing for the Hardware Prototype

Item Designation Rating Part No.
Inductor L1, L2 100 µH, DCR = 25 mΩ, 60B104C
C1A, C2A
Capacitor C1B C2B 10 µF EXH2E106HRPT
C3A, C3B
150 V, 37 A
MOSFET Q 1, Q 2 IPA105N15N3
Rds(on) = 10.525 mΩ
D1A, D2A 250V, 40A
Diode MBR40250G
D1B, D2B VF = 0.86 V, trr = 35 ns
L100J100E, L225J50RE
load Rload multiple values
L225J250E,L225J500E

8. EXPERIMENTAL IMPLEMENTATION AND RESULTS

A 200 W hardware prototype was implemented experimentally to verify the analysis

and simulation presented in the previous sections. Figure 18 shows the annotated prototype
board of the proposed converter. The converter was designed for a nominal converter
ratio 400
20 = 20 and a duty cycle of 0.7. The switching frequency was 50 kHz. The
components used to implement the prototype are listed in Table 4. The active switches
were implemented using MOSFETs IPA105N15N3 for their low on-resistance, low gate
capacitance, and low switching power loss. Schottky diodes MBR40250G were selected
to implement the blocking diodes of the VMC because of their fast recovery time as well
as their relatively low forward voltage. Film capacitors were selected to implement the
blocking and output capacitors, which have a low equivalent series resistance and a high
voltage rating. The converter was fed by the N5766A DC power supply to power a 200 W
load, which was implemented using a combination of ceramic resistors. Figure 18 shows the
thermal image of the converter operating at 100 W, and it shows that the active switches are
the only part that is heating up. Figure 19 shows the inductors and active switch currents at
80 W. Each inductor current has an average value of 2 A and a peak current of ' 2.1 A. They
are shifted 180◦ , and that doubles the input current ripple frequency as shown. Figure 20
shows the voltage stress across Q1 and Q2 , as well as the diodes; the stresses across the
active switches are 66 V, and the maximum voltage on the diodes is 133 V.
 78

D1A -C3A

C1A - C3A

C1B - C3B
D1B -C3B

Figure 18. The hardware prototype of the proposed converter (left) and the thermal image
of the proposed converter operating at 100 W (right)

The capacitor voltages, stage voltage, and voltage ripples are shown in Figure 21.
The stage 1 capacitor voltage is 66.67 V each. The stage 2 capacitor voltage is 133.34 V
each. The output stage capacitors have 200 V of stress each, and the output voltage is 400 V.
Figure 22 shows the breakdown of the component loss, excluding the inductor core
loss. The breakdown percentage of the losses at 100 W is as follows: the first major loss
source are the diodes with about 57% of the total loss; the second major loss source are
the active switches. They are the culprit for 30.5% of the total loss due to the conduction
and switching loss. The capacitors and inductors conduction losses account of 0.6% and
11.3%, respectively. The loss breakdown assumed the conduction patterns of the diodes
are equal, which in practice can be slightly different. Therefore, the diodes’ conduction
loss is overestimated, and it is lower in experimentation. The overall efficiency is shown in
Figure 24. The converter has a dimension of 3.98” L × 3.35” W, with a height of 1.38 in.
The power density of the converter is roughly 21.7 W/in3 . The inductors and film capacitor
take dominant real estate of the PCB. The power density could be more than 45 W/in3
if multilayer ceramic capacitors were used instead of film capacitors, with, of course, a
significant increase in the total cost.
 79

Iin= 4 A (2A/Div)
IQ1 (5 A/Div)

IL1=2A (2A/Div) IL2=2A (2A/Div)

IQ2 (5A/Div)

Figure 19. Inductor currents and smooth pre-filtered input current (left) and active switches
currents (right)

Gate signal 1 10 V (20 V/div)

T = 20 µs
Gate signal 1 10 V (20 V/div)

VD1A = 133.3 V (100 V/div)

Gate signal 2 10 V (20 V/div)

VD2A = 133.3 V (100 V/div)

VQ1 = 66 V (100 V/div)

VQ2 = 66 V (100 V/div) VD3A = 133.3 V (100 V/div)

Gate signal 1 10 V (20 V/div)

VD1B = 66.6 V (100 V/div)

VD2B = 133.3 V (100 V/div)

VD3B = 133.3 V (100 V/div)

Figure 20. Voltage stress across active switches and diodes

 80

Gate signal 1 10 V (20 V/div) Gate signal 1 10 V (20 V/div)

VC1A+VC1B = 133.3 V (250 V/div) ΔVC1A (1 V/div) ΔVC1B = (1 V/div)

VC2A+VC2B = 266.66 V (100 V/div)

Δ(VC1A + VC1B ) = (2.5 V/div)

Vo=VC3A+VC3B = 400 V (100 V/div)

Gate signal 1 10 V (20 V/div) Gate signal 1 10 V (20 V/div)

ΔVC3A (0.5 V/div) ΔVC3B (0.5 V/div)

ΔVC2A (1 V/div) ΔVC2B = (1 V/div)

Δ(VC3A + VC3B ) (2.5 V/div)

Δ(VC2A + VC2B ) = (2.5 V/div)

Figure 21. Capacitor voltages and AC voltage ripples

MOSFETs conduction loss MOSFETs switching loss Diodes Inductors Capacitors

0.6%
14 100
11.3%
90
12
80
Loss breakdown percentage %
Component power loss [W]

10 70

60
8 57.6%
50

6 40

30
4
20 13.7%
2
10
16.8%
0 0
0 50 100 150 200 250 300 350 400 0 50 100 150 200 250 300 350 400
Load power [W] Load power [W]

Figure 22. Loss (left) and loss distribution (right) of the converter as a function of the load.
 81

ID1A (2 A/div) ID1B (2 A/div)

ID2A (5 A/div) ID2B (5 A/div)

ID3A (2 A/div) ID3B (2 A/div)

IC1A (2 A/div) IC1B (2 A/div)

-IC2A (2 A/div) IC2B (2 A/div)

IC3A (2 A/div) IC3B (2 A/div)

Figure 23. Diode currents (upper waveforms) and capacitor currents (lower waveforms)

98

96
Efficiency (%)

94

92

90

88
60 80 100 120 140 160 180 200
Power (W)

Figure 24. Efficiency of the converter at different loads

 82

9. CONCLUSION

This paper has presented a high-voltage-gain DC-DC step-up converter to interface

renewable energy sources to a higher voltage DC bus, such as a 20 V input source to a
400 VDC . The converter employs a bi-fold Dickson VMC with an interleaved boost stage to
obtain a high voltage gain. Several features make the converter desirable, such as low voltage
stress across components, modularity, and the continuity of the input current. The converter
balances the capacitor voltages and features equal current sharing among phases, which
improves the conduction losses on both inductors and MOSFETs. Additionally, the proposed
converter is capable of converting power from either a single or two independent PV panels.
An analysis of the converter and the selection of the components are discussed in detail
and supported by the simulation results. A 200-W hardware prototype was implemented to
validate the analysis and the simulation.

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 86

III. A FAMILY OF HIGH-VOLTAGE-GAIN MULTILEVEL BOOST

CONVERTERS

Ahmad Alzahrani, Pourya Shamsi, and Mehdi Ferdowsi

Departement of Electrical and Computer Engineering
Missouri University of Science and Technology
{asakw9, shamsip, ferdowsi}@mst.edu

ABSTRACT

This paper presents various topologies based on multilevel boost converters, with
a focus on those derived from three-level boost converters (TLB). The TLB is a common
dc-dc step-up topology and is widely used in various applications, such as power factor cor-
rection (PFC) and voltage regulation. Using such topology in applications that require high
voltage gain is a challenge because of the insufficient voltage gain. The proposed family
utilizes several different techniques to increase the voltage gain of the TLB. These tech-
niques include using coupled inductors, switched inductor cells, or a flyback transformer.
An example converter of TLB with a flyback transformer is fully illustrated with modes
of operation, a steady-state analysis and component selection. The converter simulated to
proof the theory and analysis , which is used to convert a 20 V to 200 V. The converter
was also simulated to extract power from three PVL-136 photovoltaic (PV) panels using an
MPPT algorithm. An 80 W hardware prototype was implemented in the lab to validate the
simulation and the analysis.

Keywords: High-Gain, three-Level, dc-dc, boost, self-left, coupled inductor, flyback,

MPPT, solar, PV
 87

1. INTRODUCTION

Power electronics converters have an indispensable role in integrating renewable

energy sources to the electric power grid. As more renewable energy sources are used, more
efficient components and converters are desirable. Renewable energy sources, in general,
suffer from low voltage output and high dependence on weather conditions. Photovoltaics
energy also has one more issue, which is shading. Shading can reduce the output power
of the solar panel and possibly even create hot spots, which might lead to damage in the
solar cell itself. The stochastic nature of the PV output leads to a variable maximum
power point and variable input voltage, which necessitates a maximum power point tracker
(MPPT) [1–3]. Connecting several panels in series increases the overall voltage and power.
However, voltage mismatches between cells leads to a reduction of efficiency and output
power. Connecting solar panels in parallel increases the total current, but the voltage is still
as that of a single cell [4–6].
In this case, a step up converter with a high-voltage-gain ratio is needed. The CBC
can achieve high gain at high duty cycles, in theory. In reality, achieving high gain with
the CBC is impracticable because of the conduction losses and the nonidealities [7, 8].
Also using the CBC to operate in the continuous conduction mode (CCM) requires bulky
magnetics and high rating switching devices [9–11]. The voltage gain can be increased by
cascading several CBCs. Each stage operates at a lower value duty ratio, and the overall
voltage gain is high. However, cascading two or more CBCs means processing the power
two times or more, which might reduce the performance of the converter and complicate the
control design [12, 13]. Similarly, stacking several CBCs can share the power and reduce
the current rating, but there is no improvement in the voltage gain. A hybrid flyback-boost
converter utilizes the flyback transformer to increase the voltage gain of the CBC [13].
The voltage gain of the converter is a function of the transformer turns ratio. However,
using a transformer would increase the weight and volume of the converter and decrease
the power density. The TLB converter was introduced to reduce the voltage stress of the
 88

semiconductors, and reduce the size of the magnetic elements by increasing the effective
frequency. The drawback of the TLB converter is the low voltage gain, which is not sufficient
for renewable energy sources that have low voltage. The conventional isolated converters
such as flyback, forward and push-pull draw a discontinuous current from the input source,
which make them not suitable for use in renewable energy applications [14, 15].
Flying capacitor voltage multiplying converters can achieve high gain with low
voltage stress across the components and operate in the CCM with minimal inductance due
to the high effective frequency. The effective frequency value is a multiple of the switching
frequency, which is based on the number of stages [16–18]. However, the minimum duty
cycle and the phase shift is a function of the stages. That is, the greater the FCML level, the
higher the duty cycle that is required, and that limits the range of the operating duty cycle.
The narrow range of the duty cycle can be a disadvantage in cases with MPPT control and
load matching.
The voltage gain can be increased by using a transformer or a coupled inductor,
either an isolated or integrated one [19–21]. Therefore, the voltage gain becomes a function
of the turns ratio, and as gain requirement increased, so does the turns ratio requirement.
However, the leakage inductance causes voltage spikes on the active switches and requires
clamping circuits. Furthermore, employing magnetic elements with a higher turns ratio
increases the weight of the converter and reduces the power density, especially at a low
frequency. Recently, several papers introduce interleaved boost converters with switched-
capacitor circuits [22, 23]. The switched-capacitor circuit has a high power density, and the
interleaved part can minimize the magnetic storage requirement. However, using switched-
capacitor requires very complicated driving circuitry, and complicated control to remove
the mismatches between the capacitors.
This paper presents a family a high-voltage-gain step-up dc-dc converter based
on multilevel boost converter to integrate solar panels with low output voltage, typically
12 − 45 Vdc , to a dc distribution bus in a dc microgrid (200 − 960 Vdc ). To implement a
 89

converter with a high-gain conversion ratio, coupled-inductors and voltage multiplier cells
were incorporated to increase the voltage gain of the converter. The proposed converter
is better than paralleling or cascading boost converters in terms of efficiency and voltage
stress across components. The main advantage is that the effective frequency is seen by
the magnetic is higher than the switching frequency, which allow reduction in the magnetic
size.
The rest of the paper is structured as follows: Section 2 presents different variations
of converters belonging to the proposed family with an explanation of the technique used to
enhance the voltage gain. In Section 3, an example of the proposed converter is given and
analyzed. The component selections and efficiency analysis is presented in Section 4. In
Section 5 and 6, simulation and experimental results of the example converter are provided,
respectively. Finally, conclusions and future work are described in Section 7.

2. PROPOSED FAMILY OF MULTILEVEL BOOST CONVERTER WITH HIGH

GAIN

2.1. INTERLEAVING

Although the interleaving techniques increase the frequency of the AC components

of the input current, the frequency of the AC components of the inductor current is still the
same as the switching frequency, which might not be a good trade-off for increasing the
number of elements. Topologies, such as flying capacitor multilevel converters (FCMC) and
multilevel converter families, tend to increase the effective frequency of the inductor voltage
using vertical interleaving. That is, the effective frequency usually equals the switching
frequency multiplied by the number of levels. Increasing the effective frequency that is
seen by the inductors reduces the critical inductances that ensure the continuous flow of
the inductor current and allow designers to select magnetic components with a smaller
volume and build high power density converters. At high power, the advantage of vertical
 90

vL2
vL iL2 D2
L D1 Io L2
Q1
Q1
_
+ vL

+
iL
iL Q1 C1 + vL1 D1
iL1
Q1
R Vo L1 +
Vin iin
Q2 C2 _ Q2
Q2 Q2 C RL Vo
Vin _

D2

L2 iL2
_
+ vL2

Interleaving L1 iL1
_
+ vL1
iin Q1

Vertical
Vin Interleaving

QN

Figure 1. Interleaving types: a) is vertical interleaving using three or multilevel structures,

b) interleaving by paralleling two converters and c) mixing both techniques to increase the
effective frequency of the magnetic element and reduce the conduction power loss of the
inductor

interleaving might not be useful because the magnetic element has to process is a huge
amount of energy, and it is difficult to design a small and efficient magnetic element. If that
is the case, one can combine both the vertical interleaving and the conventional interleaving
to increase the performance of the converter, as shown in Figure 1. However, this paper
only explores converters with vertical interleaving, specifically those based on the TLB
converter.
 91

2.2. HIGH GAIN CELLS

Figure 2 shows a family of multilevel boost converters. The number of levels does
not improve the voltage gain; it only increases the effective frequency across the magnetic
elements and reduces the voltage stress. The voltage gain from the TLB converter is not
high enough for boosting low-voltage input sources 10 times or more. Therefore, several
techniques can be used to improve the voltage gain. First one is to use the coupled inductors
to increase the voltage. The voltage gain becomes a function of the turns ratio, and increasing
the turns ratio would increase the voltage gain. Figure 3(a) shows the TLB converter with the
coupled inductors, which is fully analyzed in [24]. The coupled inductors can be used with
a four-level boost converter, as shown in 3(b). Another way to improve the voltage gain is to
use a switched inductor cell [25–28] to replace the input inductor, such as in Figure 4 and 5.
The inductors in the switched-inductor cells charge in parallel from the input source and
discharge in series. The current rating of the inductors is reduced, and the overall voltage
gain of the converter is improved. However, the main disadvantage of previous high gain
techniques is that they use the diode in the high current loop, the loop that contains the input
source and the active switches. Putting a diode in the high current loop can compromise
the efficiency of the converter because of the high conduction loss of the diode. Also,
a bigger heat dissipation element is required. The voltage gain can be increased without
placing a diode in the high current loop. That is, a flyback transformer can be utilized to
increase the voltage gain, as shown in Figure 6. The converter has lower voltage stress and
a higher effective frequency across the magnetic element than the integrated flyback-CBC
converter [29]. Table 1 shows a comparison between different types of converters.
 92

L D1
iin
_
+ vL _
vD1 +
Q1 +
C1 vC1
L D1 _
iin
_ _ + +
+ vL vD1 +
+
Q2 Q4 C2 vC2
Q1 C1 _ R Vo
vC1 +
_ Vin _
R Vo
Vin + +
Q2 C2 vC2
_ Q3 Q5 C3 vC3
_ _
D2 D2
_ _
+ vD2 + vD2

(a) (b)
L L D1
iin D1 iin
_ _
+ vL _ + vL _
vD1 + vD1 +
+ Q1 +
Q1 C1 C1
vC1 vC1
_
D2 _

_ + +
vD2 + +
Q2 C2 vC2 Qn+1
R R Vo
_ Vo
Vin D3 V _
_ in
_
+ vD3 + +
Qn
Q3 C3 vC3 Q2n-1 Cn vCn
_
_
D4 Dn-1
_ _
+ vD4 + vDn-1

(c) (d)

Figure 2. Multilevel boost converter topologies: (a) TLB (b) Four-level boost converter, (c)
Floating interleaved TLB, (d) Interleaved TLB and (e) Interleaved four level boost converter.

D4

iin D3 D1
D4 N1 N2 _
vD1 +
Q1 +
C1 vC1
iin D3 D1 D2 _

N1 N2 _
vD2 + + +
Q1 + Q2 C2 vC2
C1 + _ R Vo
vCo1
_ Vin D3 _
R Vo _
Vin + + vD3 +
Q2 _ Q3
C2 vCo2 C3 vC3
_ _
D4
_
D2 + vD4
(a) (b)

Figure 3. Multilevel boost converter topologies with high coupled inductors cell: (a) TLB
with coupled inductors and (b) Four-level boost converter with coupled inductors
 93

D3

L1 D2 L2 D4
_
D3 D1 vD4 +
Q1 +
C1 vC1
D2 L2 _
L1 D4 iin
_ + +
D1 vD4 +
+
Q2 Q4 C2 vC2
Q1 C1 _ R Vo
iin vC1 + Vin
_ _
R Vo
Vin + +
Q2 C2 vC2
_ Q3 Q5 C3 vC3
_ _
D5 D5
_ _
+ vD5 + vD5

(a) (b)

Figure 4. Multilevel boost converter topologies with high switched-inductor cell: (a) TLB
with switched-inductor cell and (b) Four-level boost converter with switched-inductor cell

D1 L2

L1 Ca D2 D3

D1 L2
Q1 +
C1 vC1
L1 Ca D2 D3 iin _

+ +
+
Q2 Q4 C2 vC2
Q1 C1 _ R Vo
iin vC1 + Vin
_ _
R Vo
Vin + +
Q2 C2 vC2
_ Q3 Q5 C3 vC3
_ _
D4 D4

(a) (b)

Figure 5. Multilevel boost converter topologies with high switched-inductor cell: (a) TLB
with switched-inductor cell and (b) Four-level boost converter with switched-inductor cell
 94

D3

+
N2 C4 vC4
_

D3 iin D1
_
+ N1 vD1 +
N2 C3 vC3 Q1 +
_ C1 vC1
_ +
iin D1
N1 + + R Vo
Q2 Q4 C2 vC2
Q1 + _
C1 vC1
R Vo _
Vin
_ _
+ +
Vin Q3 Q5 C3 vC3
Q2 C2 vC2
_ _
D4
_
+ vD4
D2
(a) (b)

Figure 6. Hybrid multilevel with flyback converter: (a) Hybrid TLB with flyback, (b)
Hybrid interleaved TLB with flyback and (c) hybrid four-level boost with flyback

Table 1. Comparison between different converters

Converter Figure 2(a) Figure 6(a) Figure 4(a) Figure 5(a) Figure 3(a)

N2
1 N1 (2d−1)+2 2d 2 N2 1
Voltage gain 1−d 2(1−d) 1−d 1−d N1 1−d

Number of capacitors 2 3 2 3 2

Number of diodes 2 3 5 4 4

number of inductors 1 − 2 2 −

number of Coupled inductors − 1 − − 1

 95

Mode-I Mode-II Mode-I Mode-III Mode-I

Ts

Q1
dTs

180° t
Ts
Q2
dTs

t
t0 t1 t2 t3 t4

Figure 7. The switching pattern of the example converter. The two active switches have the
same duty cycle, and they are 180o out of phase.

3. EXAMPLE CONVERTER

3.1. THEORY OF OPERATION

This section presents an example of the high-voltage-gain TLB. The converter

utilizes the flyback transformer to increase the voltage gain of TLB. The output voltage
equals the sum of the voltage across C1 ,C2 , and C3 . The converter is switched by an isolated
half-bridge. The switches of the half-bridge are not complementary, but rather they are
180o out of phase, as shown in Figure 7. The analysis of this converter is made with a few
assumptions: 1) The converter operates in the steady-state, and the voltage is shared equally
between C1 and C2 ; 2) All capacitors are big and the voltage ripples are neglected; 3) All
components are ideals.
With respect to these assumptions, the converter has three modes of operation, as
shown in Figure 8. During mode 1, both active switches are ON, and all the diodes are
reverse-biased and they are OFF. The magnetizing inductor is charged by the input source.
All capacitor are discharging to the output load. The equivalent circuit in this mode is
 96

D3
_
vD3 + +
N2 C3 vC3
_

iin D1
N1 _ +
vD1 +
Lm Q1 + R
C1 vC1 Vo
_ _

Vin +
Q2 C2 vC2
_
D2
_
+ vD2
(a)
D3
_
vD3 + +
N2 C3 vC3
_

iin D1
N1 _ +
vD1 +
Lm Q1 + R
C1 vC1 Vo
_ _

Vin +
Q2 C2 vC2
_
D2
_
+ vD2
(b)
D3
_ +
vD3 +
N2 C3 vC3
_

iin D1
N1 _ +
vD1 +
Lm Q1 + R
C1 vC1 Vo
_ _

Vin +
Q2 C2 vC2
_
D2
_
+ vD2
(c)

Figure 8. Modes of operation: a) mode 1: Q1 and Q2 are ON, b) mode 2: Q1 is ON and Q2

is OFF and c) mode 3: Q1 is OFF and Q2 is ON
 97

shown in Figure 8 (a). The state equations are given by

VLm = Vin (1)

Vo = VC1 + VC2 + VC3 (2)

Vo
IC1 = IC2 = IC3 = − (3)
R

In mode 2, switch Q1 is ON and Q2 is OFF. Diodes D2 and D3 are forward-biased

and conducting. Diode D1 is reverse-biased and blocking. The equivalent circuit of this
mode is shown in Figure 8 (b), and it is represented by the following equations.

Vin + VC1 − Vo
VLm = Vin − VC2 =   (4)
1 + NN21

Vo
IC1 = − (5)
R

Vo
IC 2 = IQ1 − (6)
R

 
N2
IQ1 = Iin − IS (7)
N1

Vo
IC3 = IS − (8)
R
 98

In mode 3, switch Q1 is OFF and Q2 is ON. The diode D2 is reverse-biased and

blocking. The other diodes are forward-biased and conducting. Figure 8 (c) shows the
equivalent circuit of this mode. The state equations of this mode are given by

Vin + VC2 − Vo
VLm = Vin − VC1 =   (9)
1 + NN21

Vo
IC1 = IQ2 − (10)
R
 
N2
IQ2 = Iin − IS (11)
N1
Vo
IC2 = − (12)
R
Vo
IC3 = IS − (13)
R

By applying volt-second balance, one can obtain the steady state equations across the output
capacitors, as follows:
0.5 Vin
VC1 = VC2 = (14)
1−d
N2
N1 (2d − 1)
VC3 = × Vin (15)
2(1 − d)

The ideal voltage gain of the proposed converter is given by

Vo
N2
N1 (2d − 1) + 2
M= = (16)
Vin 2(1 − d)

The gain is a function of the duty and turns ratio. Figure 9 shows the gain of the proposed
converter. Also, the gain is compared to the converter listed in Table 1, as shown in Figure 10
 99

Figure 9. Gain of the converter

40

35

30 Fig. 2(a)
Fig. 3(a)
25 Fig. 4(a)
Voltage gain

Fig. 5(a)
Fig. 6(a)
20

15

10

0
0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95
duty ratio

Figure 10. Voltage gain of the converters listed in Table. 1

 100

4. COMPONENT SELECTIONS AND EFFICIENCY ANALYSIS

This section present design information of the example converter and component
selections.

4.1. ACTIVE SWITCHES

The voltage stress across the active switches is the same as that of the TLB converter,
which is half of the CBC. The voltage stress can be calculated by

0.5Vin
VQ1 = VQ2 = (17)
1−d

The average current of the MOSFETs is given by

N1 (2d − 1) + 2d
N2
IQ1,avg = IQ2,avg = Iin × (18)
N1 (2d − 1) + 2
N2

where Ii n can be obtained using the following equation

N2
N1 (2d − 1) + 2
Iin,avg = Io × (19)
2(1 − d)

The peak values of the active switches and the peak value of the input current are
the same, and they are equal to

Vin (2d − 1)
Iin,pk = IQ1,pk = IQ2,pk = Iin,avg + (20)
2 fs Lm

The rms current is approximated by

s
N2 N2 N2
N1 (2d−1)+2d N1 (2d−1)+2 N1 (2d−1)+2 Vin (2d−1) 2
IQ1,r ms = (Io N2 2(1−d) )2 + Io 2(1−d) fs Lm + ( V√in (2d−1) ) (21)
N1 (2d−1)+2
3 fs Lm

and IQ1,r ms = IQ2,r ms if the voltage across C2 and C1 is equal.

 101

4.2. DIODES

The voltage stress of the diodes D1 and D2 can be calculated using

0.5Vin
VD1 = VD2 = (22)
1−d

the stress on the output diode D3 is given by

0.5 NN12 Vin

VD3 = (23)
1−d

The average current for all the diodes is equal and given by

ID1,avg = ID2,avg = ID3,avg = Io (24)

However, the RMS current values are different for D3 than they are for D1 and D2 . The
RMS current is approximated by

Io
ID1,r ms = ID2,r ms = √ (25)
1−d

Io
ID3,r ms = p (26)
2(1 − d)

4.3. CAPACITORS

The capacitors’ voltages were already mentioned in the steady-state section, and,
based on that, the voltage rating of the capacitors is selected. The capacitance is selected
based on the tolerated voltage ripple of the output voltage. The capacitance can be calculated
by
d
C = Io (27)
∆v × fs
 102

Note that the frequency seen by C3 is twice that of the switching frequency. Hence, the
required capacitance is reduced to half. The effective values of the capacitor currents are
approximated by r
d
IC1,r ms = IC2,r ms = Io (28)
1−d
s
2d − 1
IC3,r ms = Io (29)
2(1 − d)

4.4. COUPLED INDUCTORS

The turns ratio of the coupled inductors can be calculated using

Vo
N2 Vin (1 − d) − 1
=2× (30)
N1 2d − 1

Note that d is higher than 0.5. The magnetizing inductance can be designed based on the
tolerated current ripple which is given by

Vin (2d − 1)
Lm = (31)
2∆i fs

where ∆i is the tolerated current ripple, which is usually 20 − 30% of the average current.

4.5. THE LOSS ANALYSIS

The losses of the converter can be divided by the losses in each component. The
losses in the coupled inductor are given by

 β
dVin
PL = 2
× Rdc + KFe
Iin,rms (core volume) (32)
| {z } 2 fs N1 Ac
| {z }
copper loss
core loss
 103

where Rdc is the dc resistance of the copper wire. The parameters KFe and β are
related to the core loss and determined from the manufacturer’s datasheet [30]. N1 is the
number of primary turns, and Ac is the cross section area of the core. The loss in both
MOSFETs is given by

2
PQ,total = 2 (IQ,r ms Ron ) + IQ,avg VQ (to f f + ton ) fs + Coss VQ 2 fs (33)
| {z } | {z } | {z }
conduction loss overlap loss loss caused by
Coss discharge

where Rds (on) is the on-state resistance of the MOSFET, ton and to f f are the turn-ON
and turn-OFF times, respectively, and the Coss is the output capacitance of the MOSFET.
Diode conduction loss is given by

PD = VF × Io + Q R ×Vr × fs (34)
| {z } | {z }
conduction rever se recover y loss

where VF is the forward voltage of the diode, Q R is the reverse recovery charge,
and Vr is the maximum reverse voltage. The losses caused by the capacitors’ equivalent
series resistance (ESR) is not significant compared to the aforementioned losses. The losses
caused by E SR are given by
PC = IC,rms
2
E SR (35)

The loss distribution and efficiency analysis are given in the next sections.

5. SIMULATION

The proposed converter was simulated using Simulink with PLECS blockset. The
parameters used in the simulation are listed in Table 2, and small parasitic elements were
included to help the solver avoid singular loops. The voltages and currents for the switches
are shown in Figure 11. The maximum voltage stress across the active switches is 56 V,
and that is also the maximum voltage across diodes D1 and D2 . However, diode D3 has to
 104

Q1 voltage Q1 current
60 6
40 4

[A]
[V]
20 2
0 0
Q2 voltage Q2 current
60 6
40 4

[A]
[V]

20 2
0 0
D1 D1
60 3
40 2

[A]
20 1
[V]

0 0
D2 D2
60 3
40 2

[A]
20 1
[V]

0 0
D3 D3
150
100 1.0
[V]

[A]
50 0.5
0 0.0
2.900000 2.900010 2.900020 2.900030 2.900000 2.900010 2.900020 2.900030
Time [s] Time [s]

Figure 11. Voltage stress across switched (left) and current passing through switches (right)

block approximately 150 V. The average and rms values of each MOSFET current is 3.87 A
and ' 4.43 A, respectively The average and rms values of diodes D1 and D2 ’s current is
0.41 A and ' 0.98 A, respectively, and the average and rms values of the D3 is 0.41 A and
' 0.69 A.
Figure 12 shows the voltage and current of the input source, capacitors and output
load. The voltage across capacitors C1 ,C2 and C3 are ' 55 V, ' 55 V, and ' 95 V,
respectively. The output voltage is about 206 V. The effective value of the current is
roughly 0.89 A for IC1 and IC2 . The effective value of IC3 is 0.5543 A. The loss breakdown
at 80 W is depicted in Figure 13, where the major loss comes from the diodes at about 46%.
The active switches, coupled inductors, and capacitors account for about 29%, 24%, and
1%, respectively. The converter efficiency can be improved by selecting diodes with fast
reverse recovery and low forward voltage and coupled inductors with dc resistance.
 105

Vin Iin
25 10

[A]
[V]

20 5

15 0
VC1 IC1
60
2

[A]
[V]

55 1
0
50
VC2 IC2
60
2

[A]
[V]

55 1
0
50
VC3 IC3
100 1.0
0.5
[V]

[A]
95
0.0
90 -0.5
× 1e-1 ICo
250
VCo
[V]

[A]
200 4.15

150 4.10
2.90000 2.90010 2.90020 2.90030 2.900000 2.900010 2.900020 2.900030
Time [s] Time [s]

Figure 12. Input, output and capacitors waveforms. The voltage waveforms (left) and
current waveforms (right)

Diodes
MOSFETs
Coupled inductors
Capacitors

Figure 13. Simulated loss breakdown at 80 W

 106

Table 2. List of parameters used in the simulation

Parameter Value
Turns ratio 2.7
Lm 500 µH
Vin 20 V
Vo 200 V
Load R 500 Ω
Duty cycle 0.82
fs 100 kHz
Capacitors 30 µF

5.1. PHOTOVOLTAIC SOURCE SIMULATION

The PV module (Uni-solar PVL-136) used in this simulation is made of a triple-

junction amorphous silicon (3 − a − Si) material. The nominal efficiency of the module is
roughly 6.26 %, and the area of the module is about 2.16 m2 . The electrical characteristics
of the PV panel are given in Table 3 [31]. The simulation of a PV panel requires the
identification of several PV parameters, such as the series resistance Rs , parallel resistance
Rsh , ideality factor n, saturation current Is and photocurrent Iph . One can extract the
parameters of a single diode model using different methods, such as in [32]. Table. 4 lists
the extracted parameters using various approaches. The IV and PV characteristic curves
at the 1000 W/m2 and 25◦C are shown in Figure 14. The fill factor of the module is
0.574. Plotting the I-V and P-V curves at different temperature values and irradiance levels
illustrates how the output power of the PV panel is affected. Figure 15 shows the effect of
the temperature on the output power. The PV panel has a lower open circuit Voc at a higher
temperature. The output power is also reduced as the temperature is increased. Figure 16
illustrates the correlation between the irradiance and the output power. The output power
of the PV increases as the solar irradiance increases [35].
 107

Table 3. Characteristics of PVL-136 solar panel

Parameter Value Parameter Value

Voc 46.2 T empv %/C −0.38
Isc 5.1 T empi %/C 0.100
Vmpp 33.0 T empv %/C −0.309
Impp 4.1 T empi %/C 0.100
Maximum power 135.312 T emp p %/C −0.209
Ns 22 Fill factor 0.574

Table 4. The parameter extraction of PV L − 136

Conventional [33] [32] NREL [34]

Is 2.076 1.447 2.2377
Iph 5.1 5.66 5.2256
Rs 1.7277 1.8493 1.9114
Rsh 60.1 in f 48.34
n 3.737 3.893 3.45

6 Uni-solar PVL-136
Current (A)

(Voc) (Isc)
4 236W
mpp=(33V) (4.13A)
2
136W
00 5 10 15 20 25 30 35 40 45 50
Voltage (V)
150
Power (W)

100
mpp=(33V) (4.13A)
50 136W
0 0 5 10 15 20 25 30 35 40 45 50
Voltage (V)

Figure 14. The I-V curve (top) and P-V curve (bottom) at the standard conditions. The
maximum power point is about 136W, and the fill factor is about 0.574.
 108

Uni-solar PVL-136
6

Current (A)
4
25 o C
2 o
45 C
0
0 5 10 15 20 25 30 35 40 45 50
Voltage (V)
150
25 o C
Power (W)

100
45 o C
50

0
0 5 10 15 20 25 30 35 40 45 50
Voltage (V)

Figure 15. Temperature’s effect on the I-V and P-V curves. As the temperature increases,
the output power of the PV is reduced.

Module type: Uni-solar PVL-136

6 1 kW/m2
Current (A)

4 0.5 kW/m 2
2 0.1 kW/m 2
0
0 5 10 15 20 25 30 35 40 45 50
Voltage (V)
150 1 kW/m 2
Power (W)

100 0.5 kW/m 2

50 0.1 kW/m 2
0
0 5 10 15 20 25 30 35 40 45 50
Voltage (V)

Figure 16. Irradiance’s effect on the output of the PV panel. The figure shows that there is
a strong correlation between the current of the PV panel and the irradiance level.
 109

5.2. MPPT CONTROL

The PV panel operates at the maximum power (MPP) if the load resistance matches
the PV resistance of the maximum power point (Rmpp ). Often the load resistance does not
match the PV, and that results in a power decrease. Therefore, a maximum power point
tracker (MPPT) is needed to ensure that the PV panel produces the maximum point at any
solar irradiance level. Although there are plenty of MPPT algorithms and techniques [36–
40], perturb and observe (P&O) is the simplest and most widely used. The flow chart of
P&O is shown in Figure 17. The challenge with such an algorithm is the size of the step of
the duty. A large step size can reach the vicinity of MPP faster but mightcause the tracker
to zigzag, resulting in an inablity to reach the true MPP. Small step sizes can reacher closer
operation points near the true MPP but take more time to reach the MPP, and in the case of
local and global maxima, the converter might get stuck in a local maxima. Several solutions
suggest the adaptive or variable step size [41], in which the step size can be large if the
converter operates far from the MPP and small once it operates near the MPP. However,
in rapid changes of the solar irradiance level, the controller might not perform correctly.
Figure 18 shows the effect of the step size on the algorithm performance. The converter
was simulated to interface three parallel-connected solar panels. The simulation results are
shown in Figure 19. The controller can extract the maximum power output of the PV system
and perform well in cases where there is a huge dip in the solar irradiance.

6. EXPERIMENTAL

This section presents the implementation of the hardware prototype and the experi-
mental results of the example converter. An 80 W hardware prototype, shown in Figure 20,
was implemented to verify the analysis and simulation. The components used to implement
the hardware are listed in Table 5. The voltage stress across components, capacitor voltages,
and output voltages are depicted in Figures. 21, 22, and 22, respectively. The output voltage
 110

Sense Vpv(k) and Ipv(k)

ΔP=Vpk(k)Ipv(k) - Vpk(k-1)Ipv(k-1)
ΔV=Vpk(k)- Vpk(k-1)

NO ΔP>0 YES

NO ΔV > 0 YES NO ΔV > 0 YES

D(k)=D(k-1)-ΔD D(k)=D(k-1)+ΔD D(k)=D(k-1)-ΔD

Return

Figure 17. MPPT algorithm used to control the proposed converter

is about 200 V. The voltage stress across the active switches is low although it is slightly
different from the analysis. The difference is caused by the voltage balance across the output
capacitors. This is inherited from the TLB topology, and several successful attempts to
remove the imbalance between capacitors have been published, such as in [42, 43]. The
output voltage is not effected by the imbalance across the output capacitors. The output
voltage and its ac components are shown in Figure 23, and the currents passing through
the switching devices are shown in Figure 24. The efficiency of the hardware prototype is
compared to the the simulation, as shown in Figure 25. The peak efficiency of the converter
is around 95%.

7. CONCLUSIONS

A family of high-voltage-gain multilevel boost converter was presented. The main

advantage of the proposed family is the higher effective frequency across the magnetic
elements, without increasing the switching frequency, which leads to a weight and size
 111

Oscillating around the MPP

MPP

Power [W]
16 17 18

Voltage [V] Vmpp Voc

(a)
Oscillating far from the MPP
MPP
Power [W]

Voltage [V] Vmpp Voc

(b)
Reaching the MPP
MPP
Power [W]

5 6

Vmpp Voc
Voltage [V]
(c)
Figure 18. Effect of step size on the performance of the algorithm a) small step size b) large
step size c) adaptive with ∆Di
 112

Figure 19. The simulated results of the converter with MPPT: a) Performance of the
controller b) Solar irradiance

Figure 20. Hardware prototype

Table 5. Component Listing for the Hardware Prototype

Item Designation Rating Part No.

Coupled inductors N2
N1 = 2.7 200 µH, ET D 49, turns ratio= 2.7
C1, C2
Capacitor 10 µF B32674D3106K
C3
150 V, 37 A
MOSFET Q 1, Q 2 IPA105N15N3
Rds(on) = 10.525 mΩ
D1, D2 250V, 40A
Diode MBR40250G
D3 VF = 0.86 V, trr = 35 ns
 113

T = 20 µs
Gate signal 1 10 V (20/div) Gate signal 1 10 V (20/div)

VD3 (250/div)
Gate signal 2 10 V (10/div)

VQ1 (100/div) VD1 (100/div)

VQ2 (100/div) VD2 (100/div)

Figure 21. The voltage stress across the active switches (left) and the voltage stress across
the diodes (right)

Gate signal 1 10 V (10/div) Gate signal 1 10 V (10/div)

VC3
VC3

VC1
VC1
VC2
VC2

Figure 22. The voltage across the capacitors (left) and the ac components across the
capacitors voltage (right)
 114

Gate signal 1 10 V (10/div)

Vo = 200 V (100/div)

ΔVo < 0.99 V (5/div)

Figure 23. Experimental results of the output voltage and the voltage ripple across the
output voltage

Gate signal 1 10 V (10/div) Gate signal 1 10 V (10/div)

Iin ID3

ID1
IQ1

IQ2 ID2

Figure 24. Input current and active switch currents (left) and diodes currents (right)
 115

100
Simulation
Experimental

Efficiency [%]
95

90

85
10 20 30 40 50 60 70 80 90 100
Output power [W]

Figure 25. Efficiency of the proposed converter. Comparison between simulated and
experimental efficiency

reduction of the magnetic elements. Although the input current is not a triangular waveform
in this family, it is not discontinuous and has high-frequency ac components that can be
easily filtered. An example converter of TLB with a flyback transformer was analyzed,
designed and simulated. The converter was simulated to interface three parallel-connected
solar panels, and details about MPPT control were presented. An 80 W hardware prototype
was implemented to validate the design and simulation.

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 120

IV. A FAMILY OF INTERLEAVED STEP-UP TOPOLOGIES USING

SINGLE-SWITCH MULTISTAGE BOOST CONVERTERS AND VOLTAGE
MULTIPLIER CELLS

Ahmad Alzahrani, Pourya Shamsi, and Mehdi Ferdowsi

Departement of Electrical and Computer Engineering
Missouri University of Science and Technology
{asakw9, shamsip, ferdowsi}@mst.edu

ABSTRACT

This paper presents an interleaved step-up dc-dc converter with single-switch mul-
tistage boost converters and voltage multiplier cells (VMC) to convert input sources that
have low output voltage, such as renewable energy sources, to a high-voltage dc bus. The
proposed converter features low voltage stress across the components, equal current sharing
among all phases, and a smooth input current. Moreover, the proposed converter has a
modular structure in both the VMC and the boost stage. That is, the VMC can have N
number of cells, and the boost stage can have k number of stages. The k can be different
in each phase, which allows the designers to integrate two independent renewable energy
sources that have different output voltages. The converter was analyzed, and details about
the design are included. An 80 W hardware prototype was implemented to validate the
theory of operation and analysis.

Keywords: DC-DC, Interleaved, High-Gain, Multilevel, Quadratic, PV, Renewable, Power

electronics, Voltage multiplier cells
 121

1. INTRODUCTION

The high-voltage-gain dc-dc step-up converters have become more popular in recent
years due to the progress in power and energy fields and the emergence and development
of technologies and applications, such as dc microgrids and dc distribution systems [1–5].
The dc distribution system was found to be an enhanced alternative to the ac distribution
system due to the low number of conversions, protections against grounding faults, high
power quality, and cost. More importantly, the dc distribution is suitable for integrating
renewable energy sources [6–12]. However, most of the renewable energy sources have
low output voltage, which needs to be boosted by about 15 − 25 times. The most common
topology used for stepping up the voltage is the conventional boost converter, which has
a simple structure and a low number of components. However, the voltage gain of the
conventional boost converter can only be high at extreme duty cycles [13, 14]. Operating at
extremely high duty cycles increases the voltage stress across the components and requires
a large inductance in order to make the converter draw a continuous input current. With
consideration of the conduction and the switching loss, the voltage gain is significantly
reduced. Such drawbacks sparked the research for a topology with high-voltage-gain
conversion ratio.
One way to increase the voltage gain is by cascading multiple conventional boost
converters, where the output voltage is increased exponentially. Cascading two conventional
boost converters allows both stages to operate at a low duty cycle [15–17]. Therefore, the
voltage stress on the first stage components is low. However, the stress on the second stage
output diode still has to block the output voltage. The quadratic converter can be simplified
by using only a single active switch. The output diode of such a converter suffers from
high voltage stress, and the input current has high current ripples [18–20]. The voltage
stress across the components is reduced in the three-level boost converter, and the size of
the converter is decreased due to the increase of the effective frequency across the inductor.
The three-level boost has the same gain as the boost converter, which is not sufficient
 122

for renewable energy applications [21, 22]. Switched capacitor circuits are capable of
increasing the voltage gain by increasing the number of switching cells. Several advantages
can be obtained: high power density, low EMI, the capability of being fabricated into IC
chips. The drawbacks are the inherent losses, a high number of active switches that require
isolation circuitry and gate drivers. Moreover, the output voltage is fixed and cannot be
regulated. Several topologies utilize the transformer or a coupled inductor’s turns ratio to
increase the voltage gain as in [23–27]. Utilizing the transformer can meet the requirement
of isolation and safety and can provide multiple outputs. However, the power density is
significantly reduced, and the weight of the converter is increased. Also, the stress on the
active switches caused by the parasitic leakage inductance can cause damage to the switches
unless an extra auxiliary circuit is implemented to recycle the energy. Similar to using a
transformer, using an integrated coupled inductor improves the voltage gain but without
providing isolation, such as a hybrid flyback-boost, interleaved with coupled inductors, or
quadratic boost converter with coupled inductors. Such topologies suffer from leakage
inductance as well and require extra circuits for circulating the energy and reducing the
voltage stress across the switches [28–30].
This paper introduces an interleaved single-switch multistage boost converter with
voltage multiplier cells. The converter features low voltage stress on components and high
voltage gain, allows the user to get the most ripple cancellation that interleaving offers, has
the capability to integrate different voltage sources, and can match a wide range of loads.
Each phase of the interleaved multistage can have either the same or a different number of
boost stages than the other phases. This can be very useful for integrating sources with a
significant difference in their output voltage. The VMC stage uses a bi-fold Dickson that
has a symmetrical structure and low voltage stress across the components. Incorporating
two symmetrical phases with the same duty cycle yields equal current sharing between the
phases and a very smooth input current.
The rest of this paper is structured as follows. First, the theory of operation and steady-state
 123

analysis of each mode is presented in Section 2. The components selection and design
procedure are presented in Section 3, and the implementation of the hardware prototype
and experimental results are explained in Section 4. Finally, conclusions and future work
are presented in Section 5.

2. THEORY OF OPERATION AND STEADY-STATE ANALYSIS

The general structure of the proposed converter is shown in Figure 1. The converter
consists of two single-switched multistage boost converter cells. These cells are 180◦ out of
phase, and they are independent of each other, which means each cell can have a different
number of the boost stages, as shown in Figure 1 (b) and (d). Two independent voltage
sources can feed the proposed converter instead of one, which is an essential quality to
interface multiple renewable energy sources. The single switch multistage boost converter
allows the converter to achieve higher converter gain with no need to add extra active
switches and can come in different topologies, as shown in Figure 2. The second stage
of the converter consists of voltage multiplier cells to increase the voltage and reduce the
voltage stress across the diodes. Numerous VMCs can be used with this converter as
in [31–33]. Example converters of the proposed family are shown in Figure 3. In this paper,
Bi-fold Dickson VMC is used for the proposed converter, which features lower stress across
the diodes and capacitors. Therefore, the voltage gain can be increased in three ways: by
increasing the number of VMC cells, by increasing the duty cycle, or by increasing the
number of boost stages. The Figure 4 shows the proposed converter with k boost stages
and N number of VMC cells. The converter can replace all diodes with active switches to
improve the efficiency in case of very high power applications, as shown in Figure 5. The
following analysis and experimentation are based on the converter with k = 2 and N = 2,
as shown in Figure 6. The analysis of the proposed converter was performed on several
assumptions: 1) All components are ideal 2) All capacitors are large so that the voltage is
constant 3) The duty cycles are symmetrical 4) The converter operates in the steady state.
 124

Multi stage
boost Vin2 Multi stage
converter boost
Voltage converter Voltage
+ +
Multi stage multiplier multiplier vo R
vo R
Vin
boost cell _ Vin1 Multi stage cell _

converter boost
converter
(a) (c)

Multi stage Vin2 Multi stage

boost boost
converter converter Voltage
Voltage +
+ Vin1 Single multiplier R
single multiplier vo R
vo
stage boost cell _
stage boost cell _
Vin converter
converter
(b) (d)

Figure 1. The general structure of the proposed converter a) both phases have a multistage
boost converter and fed by a single source b) phases have different numbers of stages and
are fed by a single source c) both phases have the same number of cascaded boost stages
but they are fed by two independent sources d) each phase has different number of stages
and they are fed by two independent voltage sources.)

The switching pattern of the proposed converter can be seen in Figure 7. The converter has
three modes of operations and the sequence of the mode is that the mode 1 always comes
between mode 2 and 3.

2.1. MODE 1: BOTH ACTIVE SWITCHES ARE ON

In this mode, diodes Da1 and Da3 are forward-biased, and they are ON, which allows
the voltage source to charge the inductors L1 and L3 , respectively. Diodes Da2 and Da4
are reversed biased, and they are OFF. Inductors L2 and L4 are being charged by capacitors
Ca1 and Ca2 , respectively. All diodes in the VMC stage are reversed biased, and they are
OFF. The load is separated from the source, and it is fed by capacitors C2A and C2B . the
equivalent circuit for this mode is illustrated in Figure 7 (a). The inductor voltages are given
by
 125

Da4 L3

Da2 L2 Da3
D2

L1 D1 L2 L1 Da1

+ + Q
C1 + Q1
Ca1 vCa1 Ca2 vCa2
1

_ _

(a) (b)
D2 D2 D4

L1 D1 L2 L1 D1 L2 D3 L3

C1 C1 C2
+ Q1 + + Q1

(c) (d)

Figure 2. Multistage boost converters a) Quadratic cell with grounded capacitor, b) Cubic
cell with grounded capacitors, c) Quadratic cell with floating capacitor, and d) Cubic cell
with floating capacitors

di L1
L1 = Vin (1)
dt
di L2
L2 = VC a1 (2)
dt

di L3
L3 = Vin (3)
dt

di L4
L4 = VC a2 (4)
dt

and the output voltage is given by

Vo = VC2A + VC2B (5)

 126

Da4 L3 Db1

Da2 L2 Da3

L1 Da1
+
Co vo R
_
+ + Q
1
Ca1 vCa1 Ca2 vCa2
_ _

_ _
Vin Ca3 vCa3 Ca4 vCa4
+ + Q2
L4 Da5

Da6 L5 Da7

Da8 L6 Db2

(a)
Da4 L3

Da2 L2 Da3

L1 Da1 D1 Do
+ +
+ + vC1 C1 vC2 C2
Q1 _ _
Ca1 vCa1 Ca2 vCa2
_ _
Vin +
Co vo R
_ _ _

Ca3 vCa3 Ca4 vCa4

+ + Q2
Da5 D2
L4

Da6 L5 Da7

Da8 L6

(b)
Da4 L3

Da2 L2 Da3

L1 Da1

+ + Q1 C2
R
Ca1 vCa1 Ca2 vCa2 Do
_ _
Vin ─ Vo + D1
_ _
Co
Ca3 vCa3 Ca4 vCa4
+ + Q2
L4 Da5

Da6 L5 Da7

Da8 L6

(c)

Figure 3. Different variations of the proposed converter (a) Schematic of the proposed
converter with 3 stages (cubic) and no VMC, (b) another interleaved cubic boost converter
with one stage of cross capacitor VMC, and (c) interleaved cubic boost converter with one
Cockcroft-Walton cell.
 127

Lk Lk

Da2 L2 Lk-1

L1 Da1 D1A D2A D3A D3A

+ + + +
+ vC1A C1A vC2A C2A vC3A C3A vC3A C3A
+ + + Q1 _ _ _ _
vCa1 vCak
_ _ +
Vin vo R
_
_ _

vCa(k+1) vCa2k + + + +
+ + + + Q2 vC1B C1B vC2B vC3B vCNB
_ C2B C3B CNB
Lk+1 Da(k+1) _ _ _

Da(2k-1) D1B D2B D3B DNB

Da(k+2) Lk+2

Da2k L2k

Figure 4. Schematic of the proposed converter with k boost stages and N voltage mutliplier
2N
cells. The voltage gain is (1−d) k

L3
Q4

L2
Q2 Q3

L1 +
+ +
Q1 + + Q1 Q1 vC1A Q1 vC2A C Q1 vC3A C3A
C1A 2A _
C1 C2 _ _
+
vo R
_

Vin
C3 C4 + + +
+ + Q2
vC1B C1B vC2B C2B vC3B C3B
L4 _ _ _

Q5 Q1 Q1 Q1
L5

Q6 Q7 L6

Q8

Figure 5. Schematic of the proposed converter with 3 stages (cubic) and 3 voltage mutliplier
cells (tripler) and implemented using MOSFETs instead of diodes to reduce the conduction
loss.
 128

Da2 L2

L1 Da1 D1A D2A

+ +
+ vC1A C1A vC2A C2A
Q1 _ _
vCa1 Ca1
_ +
Vin
vo R
_ _

vCa2 Ca2 + +
+ Q1 vC1B C1B vC2B C2B
L3 Da3 _ _

Da4 L4 D1B D2B

Figure 6. Schematic of the proposed converter with k = 2 and N = 2

Da2 L2

L1 Da1 D1A D2A

+ + + +
vC1A C1A vC2A C2A
+ Q1 _ _
Ca1
+
Vin
vo R
_

Ca2 + + +
+ Q2 +
vC1B C1B vC2B C2B
L3 Da3 _ _

Da4 L5 D1B D2B

(a)
Da2 L2

L1 Da1 D1A D2A

+ + + +
vC1A C1A vC2A C2A
+ Q1 _ _
Ca1
+
Vin
vo R
_

Ca2 + + +
+ Q2 +
vC1B C1B vC2B C2B
L3 Da3 _ _

Da4 L4 D1B D2B

(b)
Da2 L2

L1 Da1 D1A D2A

+ + + +
vC1A C1A vC2A C2A
+ Q1 _ _
Ca1
+
Vin
vo R
_

Ca2 + + +
+ Q2 +
vC1B C1B vC2B C2B
L3 Da3 _ _

Da4 L4 D1B D2B

(c)

Figure 7. Equivalent circuits to a) mode 1: both active switches are ON, b) mode 2: Q1 is
ON and Q2 is OFF, and c) mode 3: Q1 is OFF and Q2 is ON
 129

2.2. MODE 2: Q1 IS ON AND Q2 IS OFF

In this mode, inductor L1 is still being charged by the input source, while L2 is
being charged by Ca1 . Inductors L3 and L4 are discharging to the VMC stage. Diodes D1A
and D2B are reversed biased, and diodes D1B and D2A are forward biased. The energy in
capacitors C1A and C2B is being discharged, and capacitors C1B and C2A are being charged.
The equivalent circuit of this mode is shown in Figure 7 (b). The state equations are given
by

di L1
L1 = Vin (6)
dt
di L2
L2 = VC a1 (7)
dt

di L3
L3 = Vin − VCa2 (8)
dt

di L4
L4 = VCa2 − VC1B = VCa2 + VC1A − VC2A (9)
dt

2.3. MODE 3: Q1 IS OFF AND Q2 IS ON

In this mode, L1 and L2 are being discharged to the VMC stage. Diodes D1B and
D2A are reversed biased. Diodes D1A and D2B are also reversed biased, and they are OFF.
Opposite from mode 2, capacitors C1B and C2A are being discharged, while C1B and C2B
are being charged. The equivalent circuit to this mode is shown in Figure 7(c). The voltage
across the inductors is given by

di L1
L1 = Vin − VC1a (10)
dt
di L2
L2 = VCa1 − VC1A = VCa1 + VC1B − VC2B (11)
dt
 130

di L3
L3 = Vin (12)
dt

di L4
L4 = VC a2 (13)
dt

2.4. STEADY-STATE ANALYSIS AND STATIC VOLTAGE GAIN

By applying voltage-second balance to the inductors, the voltage across the capac-
itors and the output voltage, as well as the voltage gain of the converter, can be obtained.
The capacitor voltages are given by

Vin
VCa1 = VCa1 = (14)
1−d

Vin
VC1A = VC1B = (15)
(1 − d)2

2Vin
VC2A = VC2B = (16)
(1 − d)2

And the output voltage gain is given by

4Vin
Vo = (17)
(1 − d)2

The output voltage gain of the proposed converter with k boost converter stages and
N VMC cells is given by

2N
M= (18)
(1 − d) k
 131

N=1, k=2
35
N=3, k=2 N=2, k=2
30
N=3, k=1
25

Voltage gain
20
N=2, k=1
15

10 N=1, k=1
5

0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9 0.95

duty

Figure 8. The voltage gain of the proposed converter with different numbers of boost stages
k and voltage multiplier cells N

The converter can be fed by two independent voltage sources, and each phase can
operate at a different duty cycle. Table 1 shows the output voltage for these cases.

Table 1. Output voltage at different cases when the number of stages are even

Case the output voltage

d1 , d2 and Vin1 , Vin2 N

V
(1−d1 )2 in1
+ N
V
(1−d2 )2 in2

d1 , d2 and Vin1 = Vin2 NVin ( (1−d1 2 + 1

(1−d2 )2
)
1)

d1 = d2 and Vin1 , Vin2 N

(V
(1−d)2 in1
+ Vin2 )

d1 = d2 and Vin1 = Vin2 2N

V
(1−d)2 in

The converter is compared to other topologies in terms of the voltage gain and
number of components, as shown in Table 2
 132

Table 2. Comparison between different topologies

Quadratic cascaded Cascaded three-level Interleaved boost Interleaved quadratic Proposed Converter
Topology
boost converter [34] boost converter (two stages) [35] with the Dickson VMC with N = 5 [32] boost converter [36] with N = 2, k = 2

1 1 6 1 4
Static voltage gain (1−d)2 (1−d)2 1−D (1−D)2 (1−D)2

Maximum stress Vo Vo Vo
Vo 2 N Vo 2
on switches or diodes
Maximum voltage Vo Vo
Vo 2 Vo Vo 2
on capacitors
Number of
2 4 6 3 6
capacitors
Number of
2 4 6 6 8
diodes
Number of
1 2 2 4 4
inductors
Number of floating
− 2 − − −
active switches
Number of grounded
2 2 2 2 2
active switches

3. COMPONENTS SELECTION AND EFFICIENCY ANALYSIS

3.1. ACTIVE SWITCHES

The voltage stress across the MOSFETs are given by

1 Vo
VQ1 = VQ2 = Vin 2
= (19)
(1 − d) 2N

and the maximum current passing through the active switches is given by

 
NVo 3 − 2d Vin 1 − d 1 d
IS1,pk = − + − (20)
R (1 − d)2 2 fs L1 L2 (1 − d)L4

 
NVo 3 − 2d Vin 1 − d 1 d
IS2,pk = − + − (21)
R (1 − d)2 2 fs L3 L4 (1 − d)L2

The rms currents can be approximated using the following equation

s
NVo 4 1
IS1,rms = IS2,rms = 2
+ (22)
R (1 − d) (1 − d)4
 133

Table 3. Diode average and RMS currents

Current Average RMS

q
ID1A, ID1B , ID2A , ID2B Vo
R
Vo
R
1
1−d
√
I D a1 , I D a3 Vo dN
R (1−d)2
Vo N
R (1−d)2 d

Vo (N)
√
I D a2 , I D a4 R (1−d)
Vo N
R (1−d)2 1−d

3.2. DIODES

The maximum voltage stress across the diodes is given by

d
VDa1 = VDa3 = Vin (23)
(1 − d)2

1
VDa2 = VDa4 = Vin (24)
1−d

1
VD1A = VD2A = VD1B = VD2B = 2Vin (25)
(1 − d)2

The average current and the RMS current passing through the diodes are shown in Table. 3.

3.3. INDUCTORS

The input current is given by

Vo 2N
Iin = (26)
R (1 − d)2

the average current passing through inductors L1 and L3 is given by

Vo N
IL1 = IL3 = (27)
R (1 − d)2
 134

Table 4. Inductor peak and RMS currents

Current Peak RMS

r 2  2
I L1 Vo N
R (1−d)2 + Vin d
2L1 fs
Vo N
R (1−d)2 + √Vin d
2 3L1 fs
r 2  2
I L2 Vo N
R 1−d + Vin d
2(1−d)L2 fs
Vo N
R (1−d) + √ Vin d
2 3(1−d)L2 fs
r 2  2
I L3 Vo N
R (1−d)2 + Vin d
2L3 fs
Vo N
R (1−d)2 + √Vin d
2 3L3 fs
r 2  2
I L4 Vo N
R 1−d + Vin d
2(1−d)L4 fs
Vo N
R (1−d) + √ Vin d
2 3(1−d)L4 fs

the average current passing through inductors L2 and L4 is given by

Vo N
I L2 = I L4 = (28)
R (1 − d)

The operation of the proposed converter in the CCM requires minimum inductance. The
minimum inductance for L1 and L3 can be calculated using

Vin d(1 − d)2

L1,crit = L3,crit = (29)
2N Io fs

the critical inductance for L2 and L4

Vin d(1 − d)
L2,crit = L4,crit = (30)
2N Io fs

The peak and rms values of inductor currents are listed in Table 4
 135

3.4. CAPACITORS

The voltage across the capacitors is already calculated in. The capacitor values
are chosen based on the allowed ripples on the voltage. The output capacitance can be
caluclaced by
Vo (1 − d)Ts
C= (31)
R ∆VC

The RMS current of the output, and the first stage capacitors are given, respectively, by

r
d
IC2A,r ms = IC2B,r ms = Io (32)
1−d
r !
d
IC1A,r ms = IC1B,r ms = Io 1 + (33)
1−d

3.5. EFFICIENCY ANALYSIS

The efficiency of the proposed converter is mainly affected by the diodes, inductors
and active switches. Table 5 lists all the equations used for calculating the losses of the
converter. The simulated efficiency is compared to the experimental in Section 4.

Table 5. Efficiency analysis for components

Components Equation Variables

Inductors RL is the dc
IL2r ms × RL
conduction loss resistance of the inductor
Inductors a, b, and c obtained using
a(∆B)b fsc
core loss curve fitting from material datasheet
fs Coss is mosfet output capacitor
2 Coss × VS2 +
MOSFETs fs is switching frequency
switching loss Ton and Ton are the
fs
× NVo Vs
× (tOFF + tON ) on and off time of the mosfet
2 R(1−d)2

MOSFETs Ron is the conduction

IS2r ms × Ron
conduction loss resistance of the MOSFET
Diode V f is the forward
V f ∗ IDavg
conduction loss voltage of the diode
Capacitor E SR is the equivalent
IC2r ms × E SR
ESR loss series resistance of the capacitor
 136

Table 6. Component Listing for the Hardware Prototype

Item Designation Rating Part No.

Inductor L1 − L4 100 µH, DCR = 25 mΩ, 60B104C

C1A, C2A
Capacitor 10 µF EXH2E106HRPT
C1B C2B

Capacitor Ca1, Ca2 10 µF B32674D3106K

150 V, 37 A
MOSFET Q 1, Q 2 IPA105N15N3
Rds(on) = 10.525 mΩ
D1A, D2A 250V, 40A
Diode MBR40250G
D1B, D2B VF = 0.86 V, trr = 35 ns

4. EXPERIMENTAL IMPLEMENTATION AND RESULTS

An 80 W hardware prototype was implemented and tested in the laboratory to verify

the operation and the analysis of the converter. Figure 9 shows the hardware prototype,
which was implemented using the components listed in Table. 6. The N5700 was used to
supply power at 10 V to the prototype, and the output load was implemented using a mix of
ceramic resistors. The duty cycle was set to be around 0.6, and that made the output equal to
250 V. The measurements and waveforms were taken at 80 V. Figure 10 shows the voltage
waveforms across the switches. The active switches have a maximum voltage stress of 62 V.
The maximum voltage stress across the diodes in the interleaved single-switch multistage is
about 38 V for Da1 and Da3 and about 63 V for Da2 and Da4 . The maximum voltage stress
across the VMC diodes is 125 V. The voltage across the capacitors, depicted in Figure 11,
is 25 V for C1 and C2 , 63 V for C1A and C1B and 125 V for C2A and C2B . The output voltage
is about 250 V with ac components of less than 2%. Other waveforms such as the current of
the switches and passive components are shown in Figure 12 and Figure 13. The efficiency
of the converter was simulated and experimentally measured, as shown in Figure 14. As
mentioned before, the efficiency can be further increased by selecting efficient diodes with
low forward voltage for the interleaved boost stage or by replacing the diodes with efficient
ones or MOSFETs.
 137

VMC

Interleaved single-switch boost stage

Figure 9. Hardware prototype

S2 (10 V/Div)
S1 (10 V/Div)

S2 (10 V/Div) VDa1 (50 V/Div)

Q1 (100 V/Div) VDa2 (50 V/Div)

Q2 (100 V/Div) VDa3 (50 V/Div)

S2 (10 V/Div) S2 (10 V/Div)

VDa4 (100 V/Div) VD1B (250 V/Div)

VD1B (250 V/Div)

VD1A (250 V/Div)

VD2A (250 V/Div)

Figure 10. Voltage waveforms of the active switches and the diodes.
 138

S2 (10 V/Div) S2 (10 V/Div)

VC1 (50 V/Div)

VC2A (100 V/Div)

VC1B (50 V/Div)

VC2 (50 V/Div)
VC2B (100 V/Div)
VC1A (50 V/Div)

S2 (10 V/Div)

VCo (250 V/Div)

ΔVCo (5 V/Div)

Figure 11. Voltage waveforms of the capacitors, the output load and the ac components of
the output voltage.

S2 (10 V/Div) S2 (10 V/Div)

Iin= 8.4 A (2 A/Div)

IL4=1.7 A (2 A/Div) IL3= 1.7 A (2 A/Div)

IQ1 (10 A/Div)

IL1=4.2 A (2 A/Div) IL2=4.2 A (2 A/Div)

S2 (10 V/Div) S2 (10 V/Div)

IQ2 (10 A/Div) IDa2 (5 A/Div)

IDa1 (5 A/Div)
IDa4 (5 A/Div)

IDa3 (5 A/Div) ID1A (2 A/Div)

Figure 12. Current passing through the active switches, inductors and diodes D11 -D23
 139

S2 (10 V/Div) S2 (10 V/Div)

ID2A (2 A/Div) ICa1 (5 A/Div)

ID1B (2 A/Div) ICa2 (5 A/Div)

ID2B (2 A/Div) IC1A (2 A/Div)

S2 (10 V/Div)

IC2A (2 A/Div)

IC1B (2 A/Div)

IC2B (2 A/Div)

Figure 13. Currents waveforms of the VMC diodes, VMC capacitors and Ca1 and Ca2

96
Simulation
95
Experiment
Efficiency [%]

94

93

92

91

90
0 10 20 30 40 50 60 70 80
Power [w]

Figure 14. The efficiency of the hardware prototype and the simulated efficiency
 140

5. CONCLUSIONS

This paper presents a non-isolated interleaved multistage boost converter with VMC.
The converter has a high voltage and low voltage stresses across the components. Converting
a 10V to a 250 V can be achieved by the quadratic boost stage and a 2-cell VMC when
operating at a 0.6 duty ratio. The converter is capable of converting power from a single
source or two independent sources. The input is shared among the two phases equally, and
since the converter operates at 0.6 the current ripple cancellation is higher than the other
interleaved boost converters. The analysis of this converter was explained and validated by
simulation and experimental prototype. The converter is very suitable for integrating PV
panels to higher voltage DC buses.

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 144

SECTION

2. SUMMARY AND CONCLUSIONS

This dissertation has presented several advanced high-voltage-gain dc-dc step-up

topologies suitable for renewable energy sources integration to a high voltage dc distribution
bus. First, a family of interleaved boost converters with VMCs was presented. The family
consists of two stages: an interleaved boost stage and a VMC stage, which mainly consist
of diodes and capacitors and are expendable. The output of the VMC can be filtered
by an output diode and output capacitors or by an LC filter. Many group combinations
are presented and compared in terms of the voltage gain, output-input connection, input
current sharing among inductors, and the number of capacitors and diodes per stage. An
example converter to efficiently convert a 20 V to a 400 V was designed and verified by
simulation and experimental results. The second paper has presented a novel VMC and
connected it to an interleaved boost converter with no need of an output diode or LC filter.
Therefore, the output is fed by two capacitors and the voltage is rectified at each VMC
stage. The proposed converter features a have high voltage gain, equal current sharing,
low voltage stress across components, and better ripple cancellation across capacitors. The
proposed converter was analyzed, and the design process was explained. A 200 W hardware
prototype was implemented to convert 20 V input to 400 V output. The converter has a peak
efficiency of 96% and maximum voltage stress across components less than 135 V. The third
paper presents a hybrid fly-multilevel boost converter. The converter utilizes the multilevel
structure to increase the effective frequency across the magnetic device, which is a flyback
transformer. The proposed hybrid multilevel boost converters have most required features
for renewable energy applications, such as low stress across components, high voltage
gain, drawing continuous current, and small magnetic elements. The converter modes
 145

of operation and steady-state analysis are presented and verified by simulation. Further
verification was ensured by implementing a hardware prototype of an example converter
to convert 20 V to 200 V for 100 W output load power. Paper four presents an interleaved
multistage boost converter with VMC. In this topology, each phase of the interleaved stage
can have the same or a different number of boost stages, and all phases share the VMC. The
theory of operation, the steady-state analysis is presented for example converter, which has
an interleaved quadratic boost stage with two-stage VMC. The converter was analyzed and
verified by simulation results. A hardware prototype was implemented to convert 10 V to
250 V and 200 W to prove the operation and further verify the simulation results. Future
work includes experimentation of large PV side surfaced and more panels to demonstrate
the benefit of the proposed structures over the flat regular solar PV panels and closed-
loop analysis and control of the proposed converters. Different control schemes have to
be further studied, and further details about MPPT extraction algorithms under different
weather conditions are required to reveal the operation of the proposed converters further.
 146

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VITA

Ahmad Saeed Y. Alzahrani was born in Albaha, KSA. He received the B.S. degree
from the Department of Electrical Engineering, Umm Al-Qura University, Makkah, KSA,
in 2009, and the M.S. degree from the Department of Electrical and Computer Engineering,
University of Denver, Denver, CO, USA, in 2013. He received his the Ph.D. degree in
electrical engineering with the Missouri University of Science and Technology, Rolla, MO,
USA, in December 2018. Following the completion of his Ph.D., he worked as an assistant
professor in the Electrical Engineering Department at Najran University.