UNIT-4

Synthesis of Combinational
& Sequential Logic
 Contents
• Introduction to synthesis
• Synthesis of combinational logic
• Synthesis of sequential logic with latches
• Synthesis of three state devices and bus interfaces
• Synthesis of sequential logic with flip flops
• Synthesis of explicit machines
• Registered logic
 Introduction to Synthesis
• Synthesis: A gate level realization of the described functionality
• The critical steps of Synthesis tool include
- Detect and eliminate redundant logic
- Detect combinational feedback loops
- Exploit don’t-care conditions
- Detect unused states
- Detect and collapse equivalent states
- Make state assignments and
- Synthesize optimal, multilevel realizations of logic subject to constraints on
area and/or speed in a physical technology
 Introduction to Synthesis
• Models of circuit can be classified according to three levels of
abstraction
- Architectural: operations that must be executed by circuit to
transform a sequence of inputs into a specified sequence of
outputs, but doesn’t associate the operations with specific clock
cycles.

- Logical: describes a set of variables and a set of Boolean functions

that the circuit must implement.

- Physical: final layout level of abstraction

 Types of Synthesis
• Synthesis creates a sequence of transformations between views of
circuit,
- from higher level of abstraction to a lower one, with each step
leading to more detailed description of physical reality

• The different types of Synthesis include

-Logical synthesis
-RTL synthesis
-High level synthesis
 Y-chart representing Synthesis
• Y-Chart representation of
Verilog constructs for
Synthesis in three views
of circuit
 Logic Synthesis:
Synthesis tool organization
• It generates a structural view form a logic level view of a circuit
Multi level combinational logic
 Circuit before decomposition
• A Boolean expression,

F = abc + abd + a’c’d’ + b’c’d’

Circuit after decomposition
 Directed Cyclic Graph (DAG)
• A DAG representing the set of functions F, G, and H, which is to be
decomposed in terms of new nodes X and Y, with
Eg: Directed Cyclic Graph (DAG) before &
after extraction
 Eg: DAG of a function before factoring
• The function represented by
DAG is described by the Boolean
equation:
F= ac + ad + bc + bd + e
 The DAG of the factored form of a function
• The factored form of F is, F = (a+b)(c+d) + e, having fewer no. of
literals
Eg: DAG of a function before (a) and after (b)
substitution
•G = a + b
F=a+b+c

• After substitution,
F has the form:
F=G+c
Eg: DAG of a function before (a) and after (b)
elimination of an internal node
• A DAG representing the function
F before and function G is
eliminated from it, where before
elimination
F = Ga + G’b
G=c+d
And after elimination:
F = ac + ad + bc’d’
 RTL Synthesis
• It begins with an architecture and converts language-based RTL
statements into a set of Boolean equations that can be optimized by a
logic synthesis tool.

• The RTL description represents either FSM or a more general sequential

machine that makes register transfers within boundaries of predefined
clock cycle.
• RTL descriptions in Verilog use language operators and make synchronous
concurrent assignments to register variables (Non blocking assignments).
• Broad scope of use
• The synthesis engine must minimize and optimally encode the state of RTL
described machine, optimize the associated combinational logic, and map
the result into the target technology.
 High level synthesis
•Also called “behavioral synthesis” or “architectural synthesis”
•Goal: To find an architecture whose resources can be
scheduled and allocated to implement an algorithm, such as
for DSP applications etc..
•The starting point of high level synthesis is an input-output
algorithm, with no details about implementation.
•A behavioral synthesis tool executes two main steps in order
to create an architecture of data path elements, control
units, and memory:
- Resource allocation
- Resource scheduling
• Allocation: Data flow graphs display dependencies between data,
and allocation step identifies the operators used in an algorithm and
infers the need for memory resources to hold data implied by the
sequential activity of algorithm.
• Allocation binds these operators and memory resources to datapath
resources. (Eg: multiplication operators can be bound to multiplier
cell)
• Scheduling: The operations in the behavioral description are assigned
to specific clock cycles to implement the ordered sequential flow of
the algorithm.
 High Level Synthesis : example

• Representation of a
behavioral model to
implement 3 procedural
assignments :
A = B+C
D = A *E
M= D - A
a) parse trees, and
b) data flow graph
 Synthesis of Combinational Logic
•Synthesizable combinational logic can be described by
-A net list of structural primitives
-A set of continuous assignment statements
-A level sensitive cyclic behavior

-Some times based on UDPs and assign …… deassign

procedural continuous assignments. But most EDA
vendors have chosen to not to support these options
 Logic synthesis:
A net list of structural primitives

•Verilog code
 Eg: Logic synthesis:
A net list of structural primitives
• Schematic for a netlist of
primitives

y_out1 = ac+ad+ae
y_out2 = bc+bd+be
• The circuit synthesized from the
netlist
(after removing redundant
logic)
 Eg: Logic synthesis:
Continuous assignment statements
• Circuit synthesized from a
continuous assignment
 Eg: Logic synthesis:
Level sensitive cyclic behavior statements
• 2-bit Comparator
• 2-bit Comparator circuit
synthesized from a level
sensitive cyclic behavior
with a for loop
 Eg: Synthesized model for MUX

• 2- bit Mux with

selector logic
 Synthesis of Priority structures
• When branching in the loops such as case or if is not mutually
exclusive, the synthesis tool will create a priority structure.

• Eg: Circuit synthesized from

a mux with priority decode
of input conditions
Verilog Code
 Exploiting logical don’t care conditions
• Some times, simulation results may differ if the default or
branch statements (case or if) makes an explicit assignment
of x or z.
•A synthesis tool will consider casex or casez as case
statements.
•The physical hardware will propagate either 0 or 1, while HDL
model will propagate an x in simulation,
- which may lead to mismatch between results obtained by
simulating seed code and synthesis product
•Tip: An assignment to x in a case or an if statement will be
treated as a don’t care condition in synthesis
 Eg: Latched Seven segment LED display
• Counter and display units
 Verilog code

•A
Simulation results
 Eg: A Level sensitive Cyclic behavior in ALU
• Circuits synthesized from
ALU with z1 &
ALU with z2
Verilog code
 ASIC Cells and resource sharing
•ASIC cell library usually contains cells that are more complex
than combinational primitive gates.
- Eg: most libraries will contain a model for a full-adder cell

•Whether the synthesis tool exploits the available model or

builds another circuit depends on the designer’s Verilog
description.

•The tool must share resources as much as possible to

minimize needless duplication of circuitry.
• Note: use parentheses to control operator grouping and reduce the
size of a circuit
 Result of synthesizing + operator
• Using library full-adder cells
 Result of synthesizing + operator
• Using 5-bit adder blocks with hard-wired inputs to accommodate
4-bit datapaths
•If the data flows within the behavior do not conflict, the
resource can be shared between one or more paths.
• Eg: The addition operators in the continuous assignment are in
mutually exclusive data paths and can be shared in hardware, can
be represented as follows.

assign y_out = sel ? data_a + accum : data_a + data_b;

• The use of parentheses for the implementation of data path with
shared resources forces the synthesis tool to multiplex the data paths
as follows.
Implementation of a data path with shared resources
 Synthesis of Sequential logic with Latches
• Latches are synthesized in two ways
- Intentionally
- Accidentally
• A feedback-free netlist of combinational primitives will synthesize into
latch-free combinational logic
- Synthesis tool may not allow to have feed-back (eg: cross coupled
NAND gate), which leads to an error condition, and code will not
be synthesized.
• A set of continuous assignments of combinational logic must not have
feed back among them, as such models can’t be synthesized.
- Eg: A pair of cross coupled NAND gate with structural feedback
 • Solution: A continuous assignment that uses conditional operator
(? :) with feedback, will synthesize to a latch.
- It is the common and preferred way to intentionally model a
latch.
Eg: A cell of SRAM memory can be modeled as follows

CS – Chip Select, WE – Write Enable are active Low functions

 Accidental Synthesis of Latches
• A four input
OR gate using
cyclic behavior
• Or gate with latch operation
• Circuits without and with latch operation
• Simulation output
• A Verilog description of combinational logic must assign value to the
outputs for all possible values of inputs.
- Otherwise it may lead to synthesis of unwanted latches in the design
• Eg: 2x1 MUX with incomplete decoding of case statement
• Two channel mux with latched
output synthesized from an
incompletely specified case
statement using
a) generic parts
b) parts from a cell library
 Intentional Synthesis of Latches
• A Synthesis tool infers the need for a latch when a register variable in
a level sensitive behavior is assigned value in some threads of activity,
but not in others (eg: an incomplete if statement in a behavior).
• In synthesis, latches implement incompletely specified assignments to
register varibles in case and if statements in a level-sensitive
behavior.
• If case statement has default assignment with feedback or if
statement in a level sensitive behavior assigns variable to itself,
- Synthesis tool will form a mux structure with feedback
• If the behavior is edge sensitive, incomplete case and if statements
synthesize register variables to flip-flops
• Functionality of latch when conditional operator (? :) is used
• In continuous assignment statements – the result will be mux with feedback
• In edge sensitive cyclic behavior – register with gated data path in a feedback
• In level sensitive cyclic behavior - the result will be a hardware latch
• A Latch in a level sensitive
cyclic behavior
• Latched circuit synthesized
• A latch with incomplete
specified description
• Latches synthesized from an
incomplete specified description
• So, the resultant suitable expression, that is completed with feedback
is equivalent to the following conditional assignment statement:

• It is the commonly used to describe a latch.

 Synthesis of Three-State devices
and Bus interfaces
• Allow buses to be shared among multiple devices
• Preferred style: using a continuous assignment statements that has one
branch set to a three state logic value (z)
• Eg: Unidirectional interface to bus & its Verilog code:
• Eg: Bidirectional interface to a bidirectional bus
• Verilog Code:
Synthesis of Sequential logic with Flip-Flops
• A register variable in an edge sensitive behavior will be synthesized as
a flip-flop if
- It is referenced outside the scope of the behavior
- It is referenced within the behavior before it is assigned value or
- It is assigned value in only some of the branches of the activity within the
behavior.

- All of these situations imply the need for memory, which in edge sensitive
behavior dictates as a flip-flop, rather than a latch.
- Incomplete conditional statements will be synthesized using “clock enable”
Synthesis of Sequential logic with Flip-Flops :
Eg: Synchronous data swapping mechanism
• Synthesized circuit for
swap_synch with variables
referenced before being
assigned value
 Eg: 4-bit Parallel load data register
• Verilog code:
• Enables the synthesis
tool to correctly infer
the need for a resettable
flip-flop, active on the
positive edge of the clock, so
that it creates the 4-bit array
of flip-flops
• Synthesis circuit for a 4-bit parallel load data register
Eg: Empty circuit
• assigns value to the register variable D_out, but it is not referenced
outside the scope of the behavior.
• Consequently, synthesis tool will eliminate D_out
• If D_out is declared as output port, then it will be synthesized as
output of flip-flop.
• Verilog code:
 Synthesis of Explicit State Machines

Here, we discuss about the synthesis of following different explicit state

machines:
• a) BCD-to-Excess-3 Code converter
• b) Melay-type NRZ to Manchester line code converter
• c) Moore type NRZ to Manchester line code converter
• d) Sequence generator
a) Synthesis of BCD-to-Excess-3 Code converter
Synthesized circuit of BCD-to- Excess-3 converter
• Simulation results of excess_3b:
• Simulation results of excess_3b & excess_3c:
 Mealy & Moore Machines

• Melay and Moore machines are types of Finite State Machines (FSMs)
used in
- digital logic design,
- control systems, and
- computer science for modeling and designing sequential logic circuits.
Mealy Machines
• Definition:
A Mealy machine is a finite state machine where the output is determined by both the
current state and the current input.
• Characteristics:
• The output can change in the middle of a state transition.
• Typically requires fewer states compared to a Moore machine for the same problem, as outputs
can change with inputs immediately.
• More responsive to input changes because the output can change without waiting for a state
transition.
• Structure:
• Consists of a set of states, a start state, an input alphabet, an output alphabet, a transition
function (that takes a state and an input symbol and returns the next state), and an output
function (that takes a state and an input symbol and returns an output symbol).
• Applications:
• Used where the output needs to react quickly to changes in input.
• Common in scenarios like real-time systems, control systems, and communication protocols.
Moore machines:
• Definition:
A Moore machine is a finite state machine where the output is determined solely by the current
state, not the input.
• Characteristics:
• The output changes only on state transitions.
• Typically requires more states compared to a Mealy machine for the same problem, as outputs
are associated with states.
• More stable outputs as they do not change with input unless a state transition occurs.
• Structure:
• Consists of a set of states, a start state, an input alphabet, an output alphabet, a transition
function (that takes a state and an input symbol and returns the next state), and an output
function (that takes a state and returns an output symbol).
• Applications:
• Used where a more stable and predictable output is required.
• Common in scenarios where outputs need to be steady over periods, such as in digital clocks,
counters, and other timing-based systems.
 b) Synthesis of Melay-type
NRZ to Manchester line code converter
• Verilog code:
• Simulation results:
Net list & Schematic diagram
 NRZ Signals:
•Bipolar non-return-to-zero level:
- In clock language, in bipolar
NRZ-level the voltage "swings" from
positive to negative on the trailing
edge of the previous bit clock cycle.
- An example of this is RS-232, where
"one" is −12 V to −5 V and "zero" is +5
V to +12 V.
 Manchester line code
• Manchester line code, also known as Manchester encoding, is a
method of encoding binary data used in digital communication
systems.
• It combines data and clock signals into a single self-synchronizing data
stream, ensuring that the transmitted signal contains no direct
current (DC) component and has good synchronization properties.
 Example:
To illustrate Manchester encoding of IEEE standard,
consider the binary sequence 10101101:

1.Using the high-to-low transition for '0' and

low-to-high transition for '1':
•1 -> Low-to-high transition
• 0 -> High-to-low transition
2.The resulting Manchester-encoded signal will look
like:
•10101101 -> 01 10 01 10 01 01 10 01
 c) Synthesis of a Moore type
NRZ to Manchester line code converter
• Verilog code:
• Simulation results:
• Synthesized circuit from NRZ-to-Manchester moore converter
 d) Synthesis of Sequence generator
• Eg: Sequence recognizer for detecting three successive 1’s

Fig.a) Input-Output Block diagram and waveforms for a Moore-type input

• ASM chart for Mealy-type FSM
implementation
• ASM chart for Moore-type FSM
realization
Verilog code for Melay
Verilog code for Moore
Test bench code
ASIC Synthesized circuits for Melay & Moore
Shift register based circuits for Melay & Moore Sequence recognizers
• For detecting three successive 1’s in a serial bit stream
 p
• Verilog codes for Melay & Moore:
 Registered Logic
•Variables whose values are assigned synchronously with a
clock signal are said to be registered.
•Registered signals are updated at the active edges of clock
and are stable otherwise.

•The outputs of a Moore type state machines are not

registered, but they can’t glitch with changes at the
machine’s input.
- Their setting time will be longer than if they were registered.
Example
• Multiplexer with registered
output
• Multiplexer with
registered output:
Synthesized diagram