MODELLING OF LATCHES AND FLIP FLOPS

MODELLING OF LATCHES
1. Design d latch

module d_latch(clk,d,q); module tb;

input clk,d; reg clk,d;
output reg q; wire q;

always@(clk,d) d_latch dut(clk,d,q);

begin

if(clk) initial begin

if(d) clk=0;
q<=1;

else $monitor("time=%d , d=%b ,q=%b",$time,d,q);

q<=0; d=0;
else #5 d=1;
q<=q; #4 d=0;
end #6 d=1;
endmodule #3 d=0;

#6 d=1;
time= 0 , d=0 ,q=x
time= 5 , d=1 ,q=1
time= 9 , d=0 ,q=0 #20 $finish;
time= 15 , d=1 ,q=1
time= 18 , d=0 ,q=0
time= 24 , d=1 ,q=0 end
time= 25 , d=1 ,q=1
always #5 clk=~ clk;

initial begin

$dumpfile("dump.vcd");

$dumpvars(0,dut);

end

endmodule
 2. JK latch

module jklatch(clk,j,k,q); module tb;

input clk,j,k; reg clk,j,k;

output reg q; wire q;

always@(clk,j,k) jklatch dut(clk,j,k,q);

begin

if(clk) initial begin

begin clk=0;

if(j==0 && k==0) $monitor("time=%d , j=%b , k =%b , q=%b",$time,j,k,q);

q<=q; j=0 ; k = 0;

#3 k=1 ; #5 j=1;

else if(j==0 && k==1) #4 j = 0 ; #3 k =0;

q<=0;

#20 $finish;

else if(j==1 && k == 0) end

q<=1;

always #4 clk=~clk;

else

q<= ~q; initial begin

end $dumpfile("dump.vcd");

else $dumpvars(0,dut);

q<=q;

end end

endmodule endmodule

time= 0 , j=0 , k =0 , q=x

time= 3 , j=0 , k =1 , q=x
time= 4 , j=0 , k =1 , q=0
time= 8 , j=1 , k =1 , q=0
time= 12 , j=0 , k =1 , q=0
time= 15 , j=0 , k =0 , q=0
 3.SR LATCH

module srlatch(clk,s,r,q); module tb;

input s,r,clk; reg s,r,clk;

output reg q; wire q;

always@(s,r,clk) srlatch dut(clk,s,r,q);

begin initial begin

if(clk) clk=0;

begin

if(s==0 && r==0) $monitor("time=%d , s=%b , r =%b , q=%b" , $time ,

s,r,q);
q<=q;

else if(s==0 && r==1)

s=0 ; r = 0;
q<=0;
#5 s=1 ; #4 r=1;
else if(s==1 && r ==0)
#8 s= 0; #6 r=0;
q<=1;
#20 $finish;
else
end
q<=1'bx;

end
always #5 clk=~clk;

else
initial begin
q<=q;
$dumpfile("dump.vcd");

$dumpvars(0,dut);
end
end
endmodule
endmodule

time= 0 , s=0 , r =0 , q=x

time= 5 , s=1 , r =0 , q=1
time= 9 , s=1 , r =1 , q=x
time= 17 , s=0 , r =1 , q=0
time= 23 , s=0 , r =0 , q=0
4.T LATCH
 LATCH WITH SYNCHRONOUS RESET

1. D latch with synchronous reset

module dlatch(clk,rst,d,q); module tb;

input clk,rst,d; reg clk,rst,d;

output reg q; wire q;

always@(clk,rst,d) dlatch dut(clk,rst,d,q);

begin

if(clk) initial begin

begin clk=0;

if(rst) rst=1;

q<=0; d=0;

else

q<=d; $monitor("d=%b , q=%b",d,q);

end #5 rst =0;

else #4 d=1;

q<=q; #5 d=0;

end #2 d=1;

endmodule #8 d=0;

#2 d=1;

d=0 , q=x
d=0 , q=0 #20 $finish;
d=1 , q=0
d=0 , q=0 end
d=1 , q=0 always #5 clk=~clk;
d=0 , q=0
d=1 , q=0
initial begin

$dumpfile("dump.vcd");

$dumpvars(0,dut);

end

endmodule
 2. JK latch with synchronous reset

module jklatch(j,k,clk,rst,q); module tb;

input j,k,clk,rst; reg j,k,clk,rst;
output reg q; wire q;

always@(j,k,clk,rst) jklatch dut(j,k,clk,rst,q);

begin

if(clk) initial begin

if(rst) clk=0;
q<=0; rst=1;
else j=0;k=0;
begin $monitor("time = %d , j=%b , k=%b , q=%b",$time,j,k,q);
if(j==0 && k ==0)

q<=q; #4 rst=0;
else if(j==0 && k ==1) #4 j=1 ; #5 k=1;
q<=0; #5 j=0 ; #6 k=0;
else if(j==1 && k ==0) #6 j=1 ; #7 k=1;
q<=1; #20 $finish;
else end
q<= ~q; always #5 clk= ~clk;
end

else initial begin

q<=1'bx; $dumpfile("dump.vcd");
end $dumpvars(0,dut);
endmodule end

endmodule
time = 0 , j=0 , k=0 , q=x
time = 8 , j=1 , k=0 , q=1
time = 10 , j=1 , k=0 , q=x
time = 13 , j=1 , k=1 , q=x
time = 18 , j=0 , k=1 , q=0
time = 20 , j=0 , k=1 , q=x
time = 24 , j=0 , k=0 , q=x
time = 30 , j=1 , k=0 , q=x
time = 35 , j=1 , k=0 , q=1
time = 37 , j=1 , k=1 , q=0
time = 40 , j=1 , k=1 , q=x
 3. SR LATCH with synchronous reset

module srlatch(s,r,clk,rst,q); module tb;

input s,r,clk,rst; reg s,r,clk,rst;
output reg q; wire q;
always@(s,r,clk,rst)

begin srlatch dut(s,r,clk,rst,q);

if(clk)

if(rst) initial begin

q<=0; clk=0;
else rst=1;
begin s=0;r=0;
if(s==0 && r ==0) $monitor("time = %d , s=%b , r=%b , q=%b",
$time,s,r,q);
q<=q;

else if(s==0 && r ==1)

#4 rst=0;
q<=0;
#4 s=1 ; #5 r=1;
else if(s==1 && r ==0)
#5 s=1 ; #6 r=0;
q<=1;
#6 s=0 ; #7 r=1;
else if(s==1 && r ==1)
#20 $finish;
q<= 1'bx;
end
else
always #5 clk= ~clk;
q<=q;

end
initial begin
else
$dumpfile("dump.vcd");
q<=1'bx;
$dumpvars(0,dut);
end
end
endmodule
endmodule
time = 0 , s=0 , r=0 , q=x
time = 8 , s=1 , r=0 , q=1
time = 10 , s=1 , r=0 , q=x
time = 13 , s=1 , r=1 , q=x
time = 24 , s=1 , r=0 , q=x
time = 25 , s=1 , r=0 , q=1
time = 30 , s=0 , r=0 , q=x
time = 37 , s=0 , r=1 , q=0
time = 40 , s=0 , r=1 , q=x
time = 45 , s=0 , r=1 , q=0
time = 50 , s=0 , r=1 , q=x
time = 55 , s=0 , r=1 , q=0
4. T LATCH with synchronous reset
 LATCH WITH ASYNCHRONOUS RESET
1. D latch with asynchronous reset

module dlatch(rst,clk,d,q); module tb;

input rst,clk,d; reg rst , clk,d;

output reg q; wire q;

always@(rst,clk,d) dlatch dut(rst,clk,d,q);

begin

if(rst) initial begin

q<=0; clk=0;

else rst=1;

begin d=0;

if(clk) $monitor("time=%d , d=%b , q=%b",

$time,d,q);
q<=d;
#4rst=0;
else
#5 d=1;
q<=q;
#6 d=0;
end
#4 d=1;
end
#8 d=0;
endmodule
#20 $finish;

end

time= 0 , d=0 , q=0

time= 9 , d=1 , q=1 always #5 clk=~clk;
time= 15 , d=0 , q=0
time= 19 , d=1 , q=1
time= 27 , d=0 , q=0 initial begin

$dumpfile("dump.vcd");

$dumpvars(0,dut);

end

endmodule
 2. JK Latch with asynchronous reset

module jklatch(rst,clk,j,k,q); module tb;

input rst,clk,j,k; output reg q; reg rst , clk,j,k;

always@(rst,clk,j,k) wire q;

begin

if(rst) jklatch dut(rst,clk,j,k,q);

q<=0;

else initial begin

begin clk=0;

if(clk) rst=1;

begin j=0;k=0;

if(j==0 && k ==0)

q<=q; $monitor("time=%d , j=%b , k=%b,q=%b",

$time,j,k,q);
else if(j==0 && k ==1)
#7 rst=0;
q<=0;
#5 j=1; #4 k =1;
else if(j==1 && k ==0)
#1 j=0; #6 k= 0;
q<=1;
#9 j=1; #2 k= 1;
else if(j==1 && k ==1)

q<= ~q;
#10 $finish;
else
end
q<=q;
always #4 clk=~clk;
end

else
initial begin
q<=q;
$dumpfile("dump.vcd");
end
$dumpvars(0,dut);
end
end
endmodule
endmodule
time= 0 , j=0 , k=0,q=0
time= 12 , j=1 , k=0,q=1
time= 16 , j=1 , k=1,q=1
time= 17 , j=0 , k=1,q=1
time= 20 , j=0 , k=1,q=0
time= 23 , j=0 , k=0,q=0
time= 32 , j=1 , k=0,q=0
time= 34 , j=1 , k=1,q=0
time= 36 , j=1 , k=1,q=1
 3. SR latch with asynchronous reset
module srlatch(rst,clk,s,r,q); module tb;
input rst,clk,s,r; output reg q; reg rst , clk,s,r;
always@(rst,clk,s,r) wire q;
begin

if(rst) srlatch dut(rst,clk,s,r,q);

q<=0;

else initial begin

begin clk=0;
if(clk) rst=1;
begin s=0;r=0;
if(s==0 && r ==0)

q<=q; $monitor("time=%d , s=%b , r=%b,q=%b",

$time,s,r,q);
else if(s==0 && r ==1)
#7 rst=0;
q<=0;
#5 s=1; #4 r =1;
else if(s==1 && r ==0)
#1 s=0; #6 r= 0;
q<=1;
#9 s=1; #2 r= 1;
else if(s==1 && r ==1)

q<= 1'bx;
#10 $finish;
else
end
q<=q;
always #4 clk=~clk;
end

else
initial begin
q<=q;
$dumpfile("dump.vcd");
end
$dumpvars(0,dut);
end
end
endmodule
endmodule
time= 0 , s=0 , r=0,q=0
time= 12 , s=1 , r=0,q=1
time= 16 , s=1 , r=1,q=1
time= 17 , s=0 , r=1,q=1
time= 20 , s=0 , r=1,q=0
time= 23 , s=0 , r=0,q=0
time= 32 , s=1 , r=0,q=0
time= 34 , s=1 , r=1,q=0
time= 36 , s=1 , r=1,q=x
4. T LATCH with asynchronous reset
 FLIP FLOP MODELLING
FLIP FLOP WITH SYNCHRONOUS RST
1. D flip flop with synchronous reset

module dflipflop(d,clk,rst,q); module tb;

input d,clk,rst; reg d,clk,rst;

output reg q; wire q;

always@(posedge clk) dflipflop dut(d,clk,rst,q);

begin

if(rst) initial begin

q<= 0; clk=0;

else rst=1;

q<=d; d=1;

end $monitor("d=%b , q=%b" , d,q);

endmodule
#5 rst =0;

#4 d=0;
d=1 , q=x
d=1 , q=1 #5 d=1;
d=0 , q=1
#2 d=1;
d=1 , q=1
d=0 , q=1 #7 d=0;
d=0 , q=0
#20 $finish;

end

always #5 clk=~clk;

initial begin

$dumpfile("dump.vcd");

$dumpvars(0,dut);

end

endmodule
 2. J k flip flop with synchronous reset

module jkflipflop(rst,clk,j,k,q); module tb;

input rst , clk, j,k; reg rst , clk,j,k;

output reg q; wire q;

always@(posedge clk) jkflipflop dut(rst , clk, j,k,q);

begin initial begin

if(rst) clk=0;

q<=0; rst=1;

else j=0 ; k =0;

begin

if(j==0 && k==0) $monitor("j=%b , k = %b, q=%b",j,k,q);

q<= q;

else if(j==0 && k==1) #5 rst = 0;

q<= 0; #4 j=1; #1 k=1;

else if(j==1 && k ==0) #6 j=0; #5 k =0;

q<=1; #2 j=1; #6 k=1;

else if(j==1 && k ==1) #10 $finish;

q<= ~q;
end

else

q<=q; always #4 clk=~clk;

end

end initial begin

endmodule $dumpfile("dump.vcd");

$dumpvars(0,dut);
j=0 , k = 0, q=x
j=0 , k = 0, q=0
j=1 , k = 0, q=0 end
j=1 , k = 1, q=0
j=1 , k = 1, q=1 endmodule
j=0 , k = 1, q=1
j=0 , k = 1, q=0
j=0 , k = 0, q=0
j=1 , k = 0, q=0
j=1 , k = 0, q=1
j=1 , k = 1, q=1
j=1 , k = 1, q=0
 3. SR FLIP FLOP with synchronous reset

module srflipflop(rst,clk,s,r,q); module tb;

input rst , clk, s,r; reg rst , clk,s,r;

output reg q; wire q;

srflipflop dut(rst , clk, s,r,q);

always@(posedge clk) initial begin

begin clk=0;

if(rst) rst=1;

q<=0; s=0 ; r =0;

else

begin $monitor("s=%b , r = %b, q=

%b",s,r,q);
if(s==0 && r==0)

q<= q;
#5 rst = 0;
else if(s==0 && r==1)
#4 s=1; #1 r=1;
q<= 0;
#6 s=0; #5 r =0;
else if(s==1 && r ==0)
#2 s=1; #6 r=1;
q<=1;
#10 $finish;
else if(s==1 && r ==1)

q<= 1'bx;
end

else
always #4 clk=~clk;
q<=q;

end
initial begin
end
$dumpfile("dump.vcd");
endmodule
$dumpvars(0,dut);

s=0 , r = 0, q=x
s=0 , r = 0, q=0
end
s=1 , r = 0, q=0
s=1 , r = 1, q=0 endmodule
s=1 , r = 1, q=x
s=0 , r = 1, q=x
s=0 , r = 1, q=0
s=0 , r = 0, q=0
s=1 , r = 0, q=0
s=1 , r = 0, q=1
s=1 , r = 1, q=1
s=1 , r = 1, q=x
4. T flip flop with synchronous reset
 FLIP FLOP WITH ASYNCHRONOUS RESET

1. D flip flop with asynchronous reset

module dff(clk,rst,d,q); module tb;

input clk,rst,d; reg clk,rst,d;

output reg q; wire q;

always@(posedge clk or posedge rst) dff dut(clk,rst,d,q);

begin

if(rst) initial begin

q<=0; clk=0;

else rst=1;

q<=d; d=0;

end

endmodule $monitor("d=%b , q=%b" , d,q);

d=0 , q=0 #5 rst=0;

d=1 , q=0
#3 d=1;
d=1 , q=1
d=0 , q=1 #5 d=0;
d=1 , q=1
#2 d=1;
d=0 , q=1
d=0 , q=0 #7 d=0;

#20 $finish;

end

always #4 clk=~clk;

initial begin

$dumpfile("dump.vcd");

$dumpvars(0,dut);

end

endmodule
 2. JK flip flop with asynchronous reset

module jkff(j,k,clk,rst,q); module tb;

input j,k,clk,rst; reg j,k,clk,rst;
output reg q; wire q;

always@(posedge clk or posedge rst) jkff dut(j,k,clk,rst,q);

begin

if(rst) initial begin

q<=0; clk=0;
else rst=1;
begin j=0;k=0;
if(j==0 && k==0)

q<=q; $monitor("j=%b , k=%b , q=%b", j,k,q);

else if(j== 0 && k==1)

q<=0; #4 rst=0;
else if(j==1 && k==0) #5 j=1; #2 k=1;
q<=1; #2 j=0; #7 k=0;
else if(j==1 && k==1) #4 j=1; #8 k=1;
q<=~q; #8 j=0; #2 k=0;

#20 $finish;
else

q<=q; end
end always #4 clk=~clk;
end

endmodule initial begin

$dumpfile("dump.vcd");
j=0 , k=0 , q=0
j=1 , k=0 , q=0 $dumpvars(0,dut);
j=1 , k=1 , q=0
end
j=1 , k=1 , q=1
j=0 , k=1 , q=1 endmodule
j=0 , k=0 , q=1
j=1 , k=0 , q=1
j=1 , k=1 , q=1
j=1 , k=1 , q=0
j=0 , k=1 , q=0
j=0 , k=0 , q=0
 3. SR flip flop with asynchronous reset

module srff(s,r,clk,rst,q); module tb;

input s,r,clk,rst; reg s,r,clk,rst;

output reg q; wire q;

always@(posedge clk or posedge rst) srff dut(s,r,clk,rst,q);

begin

if(rst) initial begin

q<=0; clk=0;

else rst=1;

begin s=0;r=0;

if(s==0 && r==0)

q<=q; $monitor("s=%b , r=%b , q=%b", s,r,q);

else if(s== 0 && r==1)

q<=0; #4 rst=0;

else if(s==1 && r==0) #5 s=1; #2 r=1;

q<=1; #2 s=0; #7 r=0;

else if(s==1 && r==1) #4 s=1; #8 r=1;

q<=1'bx; #8 s=0; #2 r=0;

#20 $finish;

else

q<=q; end

end always #4 clk=~clk;

end

endmodule initial begin

$dumpfile("dump.vcd");
s=0 , r=0 , q=0
s=1 , r=0 , q=0 $dumpvars(0,dut);
s=1 , r=1 , q=0
end
s=1 , r=1 , q=x
s=0 , r=1 , q=x endmodule
s=0 , r=0 , q=x
s=1 , r=0 , q=x
s=1 , r=0 , q=1
s=1 , r=1 , q=1
s=1 , r=1 , q=x
s=0 , r=1 , q=x
s=0 , r=0 , q=x
4. T flip flop with asynchronous reset