MAR ATHANASIUS COLLEGE OF ENGINEERING,

KOTHAMANGALAM

DEPARTMENT OF ELECTRONICS AND COMMUNICATION

ENGINEERING

ECL 333
DIGITAL SIGNAL PROCESSING LABORATORY
MANUAL

FIFTH SEMESTER,
B. TECH -2019
APJAKTU
 LIST OF EXPERIMENTS

Experiments using Python

Exp. No. Experiment

1. Simulation of Signals

2. Verification of the Properties of DFT

a. Generate and appreciate a DFT matrix

b. Circular Convolution.

c. Parseval’s Theorem

Experiments in DSP Board

Exp. No. Experiment

3. Familiarization of DSP Hardware : LED Blinking and Waveform Generation

4. Familiarisation of DSP Hardware : Sampling and Reproducing an Analog

Waveform
5. Linear convolution

6. FIR Low pass filter

7. IFFT with FFT

8. FFT of signals

9. Overlap Save Block Convolution

10. Overlap Add Block Convolution

 Revision History
Version Date Remarks
1.0 05-11-2021 Baseline Version
Familiarization of LPC Board and updated
1.1 04-11-2021
Lab Manual Part B
1.2 16-12-2021 Added Linear Convolution Experiment
1.3 06-01-2021 Added FIR filter Experiment
1.4 10-02-2022 Added CMSIS DSP library Documention
Table of Contents

Exp 1: Simulation of Signals ................................................................................................................ 5

Exp 2: Verification of the Properties of DFT ..................................................................................... 6
Exp 3: Familiarization of DSP Hardware: LED Blinking and Waveform Generation .................. 7
Exp 4: Familiarization of DSP Hardware: Sampling and Reproducing an Analog Waveform .... 8
Exp 5 : Linear Convolution ................................................................................................................ 10
Exp 6 : FIR Low Pass Filter ............................................................................................................... 11
Exp 7 : IFFT with FFT ....................................................................................................................... 13
APPENDIX A : Python and C codes ................................................................................................. 16
Exp 1: Simulation of Signals: Python Code .................................................................................. 16
Exp 2: Verify of the properties of DFT computationally: Python Code .................................... 18
Exp 3: Familiarization of LPC1769 Board : LED Blinking and Waveform Generation ......... 21
Exp 4: Sampling and Reproducing an Analog Waveform .......................................................... 26
Exp 5: Linear Convolution ............................................................................................................. 28
Exp 6: FIR Low Pass Filter ............................................................................................................ 30
Exp 7: IFFT with FFT .................................................................................................................... 34
APPENDIX B: Introduction to LPC1769 MicrocontrollerTools ................................................... 37
 Exp 1: Simulation of Signals

AIM
To simulate the following signals using Python
1. Unit impulse signal
2. Unit pulse signal
3. Unit ramp signal
4. Bipolar pulse
5. Triangular signal

THEORY
/* Write Notes on Python basics and Numpy */
/*Define the given signals*/
CODE
Refer Appendix A and write the code in lab record
OBSERVATION
/*Paste the obtained plots on the left side of lab record*/
RESULT
 Exp 2: Verification of the Properties of DFT

AIM
a) Generate and appreciate a DFT matrix using python
b) Write a python function that returns the circular convolution of an N1 point sequence
and an N2 point sequence given at the input
c) Prove Parseval’s Theorem using two random complex sequences

METHODOLOGY
1. Generate and appreciate a DFT matrix
a. Write a function that returns the N point DFT matrix for a given N.
b. Plot its real and imaginary parts of VN as images using matshow or imshow
command (in Python) for N = 16, N = 64 and N = 1024
c. Compute the DFTs of 16 point, 64 point and 1024 point random sequences using
the above matrices.
d. Observe the time required for computations for N = 2γ for various values of γ
and plot the time required for computation of DFT via fft function and DFT
matrix and appreciate the computational saving with FFT.
2. Write a python script to perform linear convolution of two sequences and then using
linear convolution, compute circular convolution
3. Verify Parseval’s theorem using two complex sequences each of length 5000.
THEORY
/*Give a brief description on DFT, FFT, Circular convolution and Parseval’s theorem */

CODE
Refer Appendix A and write the code in lab record
OBSERVATION
/* Paste the plots on the left side of Lab Record and write down your observations */

RESULT
 Exp 3: Familiarization of DSP Hardware: LED Blinking and
Waveform Generation

AIM
a) To familiarize with DSP board and to write a C code to Blink a LED in LPC1769 Board.
b) To control turning on of a LED using a switch.
c) To generate a sinusoidal waveform and a square waveform using LPC1769 and observe
the waveform in a DSO
THEORY
/*Give a brief description on LPC 1769 Board */
ALGORITHM
1. Write the Algorithm to Blink a LED.
2. Write the Algorithm to control the turning on of a LED based on the status of a switch.
3. Write the Algorithm to generate a sinusoidal waveform using LPC1769 board.
CODE
Refer Appendix A and write the code in lab record.

OBSERVATION
/*Draw the observed waveforms on graph paper and paste them on the left side of Lab
Record. Also, mention the time period and frequency of the waveform and the delay settings
used to generate the waveform.*/
Sine Wave
Delay Value Frequency Vmax Vmin

Square Wave
Delay Value Frequency Vmax Vmin

RESULT
 Exp 4: Familiarization of DSP Hardware: Sampling and
Reproducing an Analog Waveform

AIM
a) To convert an input analog signal into discreet samples and output the same samples
via DAC using LPC1769 board.
b) To study the effect of sampling rate and aliasing.
THEORY
/*Give a brief description on Nyquist Sampling theorem and aliasing. With the help of
a diagram, explain what happens if a co-sinusoid of frequency 5 kHz is sampled at
a. 14 KHz
b. 8 KHz
*/
PROCEDURE
a) Make a connection between the ground pins of two different LPC1769 boards using a
breadboard.
b) Generate a sinusoid at around 9KHz using the first LPC1769 board and output the
waveform through DAC. This sinusoid will be the input signal for the second
LPC1769 board.
c) Load the second board with the program to sample an input analog signal and
reconstruct it via DAC.
d) Connect the DAC output from board 1 to the ADC of board 2 using a breadboard.
e) Change the delay in the second board to vary the ADC sampling rate and measure the
resulting sampling rate by toggling a GPIO pin.
f) Initially adjust the delay such that the sampling rate satisfies the Nyquist sampling
theorem and measure the frequency of the reconstructed waveform.
g) Now adjust the delay such that the sampling rate doesn’t satisfy the Nyquist sampling
theorem and measure the frequency of the reconstructed waveform.
ALGORITHM
Write the algorithm to sample an input analog signal and reconstruct it via DAC. Also
mention how to determine sampling rate.
CODE
Refer to Appendix A and write the code in lab record.
OBSERVATION
Input Sinusoid Value of ADC ADC Sampling Frequency of
Sl No
Frequency Delay variable Rate Output Sinusoid
1
2
3
4
 Draw the input and output waveforms on graph paper and paste them on the left side
of Lab Record. Also mention the time period and frequency of the waveform and the delay
settings used to generate the waveform.

RESULT
 Exp 5 : Linear Convolution

AIM
To perform linear and circular convolution on given samples of data using LPC
trainer board.

THEORY
/*Write the theory regarding convolution and DAC output voltage*/
ALGORITHM
/*Write the algorithm after reading the code*/
CODE
Refer to Appendix A and write the code in lab record.
OBSERVATION
Signal Sample Values
x(n)
h(n)
y(n) = x(n) ∗ h(n)

Expected DAC output

voltage of signal x(n)
Observed DAC output
voltage for signal x(n)

Expected DAC output

voltage of signal h(n)
Observed DAC output
voltage for signal h(n)

Expected DAC output

voltage of signal y(n)
Observed DAC output
voltage for signal y(n)

RESULT
 Exp 6 : FIR Low Pass Filter

AIM
To design a low pass filter with normalized cut off frequency 𝑣𝑐 = 0.1 and implement
the low pass filter in LPC trainer board. Also plot the frequency response of FIR Filter.

THEORY
/*Write the theory regarding FIR filter and Windowing. */
/*Refer Section 4.4 and 4.5 of the text book: DSP Applications Using C and the TMS320C6x
DSK by Rulph Chassaing */
PROCEDURE
a) Make a connection between the ground pins of two different LPC1769 boards.
b) Generate a sinusoid using the first LPC1769 board and connect it to the ADC of
second LPC1769 board.
c) Design the LPF and generate FIR filter coefficients using python code. Use the
generated filter coefficients for FIR filter implementation in LPC board.
d) Load the second board with FIR filtering program.
e) Input sinusoid after passing to the FIR filter, is observed from the DAC output of
second board.
f) Plot the frequency response of the FIR filter by changing the frequency of input
sinusoid and measuring the amplitude of FIR filter output.
g) Measure the ADC sampling rate by toggling a port pin as in experiment 4.
h) If 𝐹𝑆 is the measured sampling rate, then the frequency corresponding to normalized
frequency 𝑣𝑐 is :
𝐹𝑆
𝑓 = 𝑣𝐶 . Hz
2

Note:
For normalized frequency 𝑣, digital frequency(𝜔) is given by: 𝜔 = 𝑣. 𝜋 rad/sec.
𝐹
𝜔 = 𝜋 𝑟𝑎𝑑/𝑠𝑒𝑐 Corresponds to a frequency 𝑓 = 2𝑆 Hz.
𝐹
∴ 𝜔 = 𝑣. 𝜋 𝑟𝑎𝑑/𝑠𝑒𝑐 Corresponds to a frequency 𝑓 = 𝑣. 2𝑠 Hz.

DESIGN
Let number of FIR filter taps: N = 25 and normalized frequency 𝑣𝑐 = 0.1.
𝑁
Q = ⌊ 2 ⌋ = 12
𝑠𝑖𝑛 (𝑣𝑐 𝑛𝜋)
LPF Impulse response coefficients: ℎ𝑠 = 𝐶𝑛 = , where 𝑛 = 0, ±1, ±2 . . . ±𝑄 and
𝑛𝜋
𝐶0 = 𝑣𝑐 .
Choose window function 𝑤(𝑛) to be a Kaiser window or a Hamming window of length N.
Then FIR filter coefficients h(n) is given by
ℎ(𝑛) = ℎ𝑠 (𝑛). 𝑤(𝑛)
ALGORITHM
/*Write the algorithm after reading the code*/
CODE
Refer to Appendix A and write the code in lab record.
OBSERVATION
ADC Sampling Frequency 𝐹𝑠 :
Normalized cutoff of frequency 𝑣𝑐 :
Designed Cutoff frequency of LPF (in Hz) :

Peak to Amplitude
Input signal
peak voltage of output
Sl No Frequency
of output signal
(Hz)
signal (V) (V)
1
2
3
4

/* Plot the frequency response of the FIR filter in a graph paper and compute the observed cut
off frequency*/

RESULT
 Exp 7 : IFFT with FFT

AIM
To compute IFFT of a signal using FFT routine in LPC trainer board.
THEORY
N point FFT of discreet samples x(n) is given by

𝑁−1
𝑗2𝜋𝑘𝑛
−
𝑋(𝑘) = ∑ 𝑥(𝑛) 𝑒 𝑁 𝑤ℎ𝑒𝑟𝑒 𝑘 = 0 𝑡𝑜 𝑁 − 1 (1)
𝑛=0

N point FFT takes N samples of x(n) (treated as time domain samples) and outputs N samples
in frequency domain.
Corresponding formula for IFFT is :
𝑁−1
1 +
𝑗2𝜋𝑘𝑛
𝑥(𝑛) = ∑ 𝑋(𝑘) 𝑒 𝑁 𝑤ℎ𝑒𝑟𝑒 𝑛 = 0 𝑡𝑜 𝑁 − 1 (2)
𝑁
𝑘=0

Taking conjugate on both sides:

𝑁−1 ∗
∗(
1 +
𝑗2𝜋𝑘𝑛
𝑥 𝑛) = [∑ 𝑋(𝑘) 𝑒 𝑁 ]
𝑁
𝑘=0
As (𝑎𝑏)∗ = 𝑎∗ . 𝑏 ∗
𝑁−1
∗( )
1 𝑗2𝜋𝑘𝑛
∗( ) − 𝑁
𝑥 𝑛 = ∑𝑋 𝑘 𝑒
𝑁
𝑘=0
𝑁−1
1 𝑗2𝜋𝑘𝑛
∗( ) − 𝑁
∴ ∑𝑋 𝑘 𝑒 = 𝑥 ∗ (𝑛)
𝑁
𝑘=0
Taking conjugate on both sides
 𝑁−1 ∗
1 −
𝑗2𝜋𝑘𝑛
[ ∑ 𝑋 ∗ (𝑘) 𝑒 𝑁 ] = 𝑥(𝑛) (3)
𝑁
𝑘=0
But from eqn (2), IFFT of X(k) is x(n).
Below steps details the procedure to obtain IFFT of FFT output X(k) using eqn. (3).
Algorithm to obtain IFFT of X(k) using FFT routine
Step 1: Take conjugate of FFT output samples 𝑋(𝑘) to obtain 𝑋 ∗ (𝑘) and pass it to FFT routine.
Step 2: The output of FFT routine is then divided by a factor N.
Step 3: Take the conjugate of the obtained result to obtain the samples x(n), which is the IFFT
of X(k).
PROCEDURE
Load the program for computing IFFT using FFT into LPC trainer board and observe
the input signal, FFT output and the also the signal obtained after taking IFFT of FFT samples.
CODE
Refer to Appendix A and write the code in lab record.
OBSERVATION
Plot the input signal, FFT output and signal after IFFT in a graph sheet.
RESULT
APPENDIX A
 APPENDIX A : Python and C codes
Exp 1: Simulation of Signals: Python Code
Exp 2: Verify of the properties of DFT computationally: Python Code

2.a. Python code to generate DFT matrix and compare the time elapsed for computing
DFT via FFT function and DFT matrix method
2.b. Circular Convolution and Parseval’s Theorem : Python Code
 Exp 3: Familiarization of LPC1769 Board : LED Blinking and Waveform
Generation
3.a: Code to control a LED using a switch

3.b: Code to control a LED using a switch

3.c: Code to generate a sine wave and a square wave
functions.c file : Code
 Exp 4: Sampling and Reproducing an Analog Waveform
4.a Code to sample input analog signal and regenerate it by passing it to a DAC
 Exp 5: Linear Convolution
5.a Code to perform linear convolution
 Exp 6: FIR Low Pass Filter

6.a Python code to obtain FIR filter coefficients

6.b C code : FIR Filter Implementation

 Exp 7: IFFT with FFT
7.a Code to compute IFFT using FFT routine
 APPENDIX B: Introduction to LPC1769
MicrocontrollerTools
LPC1769 trainer board is used for conductingCycle 1experiments in Digital Signal
Processing Lab. The schematic diagram of LPC1769 trainer board is given in Part-B of the
manual. The board contains many connectors (e.g.: J1, J26, etc.) which enable access to port
pins of LPC1769. It also has test LEDs (e.g.: J3 connector LEDs) which can be used during
experiments.

LPC1769 Microcontroller
LPC1769 is an ARM core based microcontroller from NXP Semiconductors. It is
commonly used for embedded applications requiring low power dissipation.

Some of the main features of LPC1769 microcontroller are:

a. 32-bit ARM processor core
b. 512kB on-chip Flash ROM
c. 64kB RAM
d. 3.3 Volt power supply
e. Maximum operating frequency of 120 MHz
f. Five General Purpose I/O Ports
g. 12-bit ADC with 8 channels
h. 10-bit DAC
i. Four 32-bit Timers

Software Development Tools

LPCXpresso IDE is a software development environment for creating applications for
LPC microcontrollers. It is used to write C programs and then compile them to create binary
file (*.hex) that can be later executed in LPC1769 microcontroller.
FlashMagic is a tool used to write the binary file (created using LPCXpresso) into the
Flash ROM of the microcontroller.

Procedure to execute a program in LPC1769 board

1. Open LPCXpress tool
2. Click on Browse and create a new workspace.
3. Once LPCXpresso is opened, click on ‘Import Project’ and import the project
‘DSP_LAB_ARM’
4. Write the program inside ‘DSP_LAB_ARM\src\test_arm.c’ file
5. If required, right click on test_arm.c file and rename it.
6. After saving the program, click on ‘Build DSP_LAB_ARM’
7. Check for build errors in console window at the bottom
8. If build is successful, binary file DSP_LAB_ARM.hex will be created inside
‘<workspace folder>\DSP_LAB_ARM\Debug’
9. Make necessary wirings on LPC1769 board, connect it to USB port of the PC and
make sure that the board is powered up
10. Note the COM port number that has been assigned to the board from ‘Device
Manager’ in PC
11. Open ‘Flash Magic’ tool
12. In ‘Communications’ section, select the device LPC1769
13. Select the correct COM port
14. Change Oscillator frequency to 12MHz
15. In ‘Erase’ section, select the option ‘Erase all Flash + Code Read Protection’
16. In ‘Hex file’ section, browse and select the correct hex file that has to be written to the
board
17. Click on ‘Start’ to program the device
18. Once programming is over, output can be verified on the board
DIGITAL SIGNAL PROCESSING LAB

MANUAL
PART - B

DEPARTMENT OF ECE
MACE
LPC1769 Board Schematic
 LPC1769 – Register Details
I) Port pin function

1. Pin Function Select Registers (PINSEL0 to PINSEL10)

 PINSEL registers control the functions of device pins
 PINSEL0 is used to control Port 0 bits 15:0
 PINSEL1 is used to control Port 0 bits 31:16
 Similarly other PINSEL registers control other port pins

PINSEL0

Pin Function Function Function Function Reset

Bit
name when 00 when 01 when 10 when 11 value
1:0 P0.0 GPIO Port 0.0 RD1 TXD3 SDA1 00
3:2 P0.1 GPIO Port 0.1 TD1 RXD3 SCL1 00
5:4 P0.2 GPIO Port 0.2 TXD0 AD0.7 Reserved 00
7:6 P0.3 GPIO Port 0.3 RXD0 AD0.6 Reserved 00
9:8 P0.4 GPIO Port 0.4 I2SRX_CLK RD2 CAP2.0 00
11:10 P0.5 GPIO Port 0.5 I2SRX_WS TD2 CAP2.1 00
13:12 P0.6 GPIO Port 0.6 I2SRX_SDA SSEL1 MAT2.0 00
15:14 P0.7 GPIO Port 0.7 I2STX_CLK SCK1 MAT2.1 00
17:16 P0.8 GPIO Port 0.8 I2STX_WS MISO1 MAT2.2 00
19:18 P0.9 GPIO Port 0.9 I2STX_SDA MOSI1 MAT2.3 00
21:20 P0.10 GPIO Port 0.10 TXD2 SDA2 MAT3.0 00
23:22 P0.11 GPIO Port 0.11 RXD2 SCL2 MAT3.1 00
29:24 - Reserved Reserved Reserved Reserved 00
31:30 P0.15 GPIO Port 0.15 TXD1 SCK0 SCK 00

PINSEL1
Pin Function Function Function Function Reset
Bit
name when 00 when 01 when 10 when 11 value
1:0 P0.16 GPIO Port 0.16 RXD1 SSEL0 SSEL 00
3:2 P0.17 GPIO Port 0.17 CTS1 MISO0 MISO 00
5:4 P0.18 GPIO Port 0.18 DCD1 MOSI0 MOSI 00
7:6 P0.19 GPIO Port 0.19 DSR1 Reserved SDA1 00
9:8 P0.20 GPIO Port 0.20 DTR1 Reserved SCL1 00
11:10 P0.21 GPIO Port 0.21 RI1 Reserved RD1 00
13:12 P0.22 GPIO Port 0.22 RTS1 Reserved TD1 00
15:14 P0.23 GPIO Port 0.23 AD0.0 I2SRX_CLK CAP3.0 00
17:16 P0.24 GPIO Port 0.24 AD0.1 I2SRX_WS CAP3.1 00
19:18 P0.25 GPIO Port 0.25 AD0.2 I2SRX_SDA TXD3 00
21:20 P0.26 GPIO Port 0.26 AD0.3 AOUT RXD3 00
23:22 P0.27 GPIO Port 0.27 SDA0 USB_SDA Reserved 00
 25:24 P0.28 GPIO Port 0.28 SCL0 USB_SCL Reserved 00
27:26 P0.29 GPIO Port 0.29 USB_D+ Reserved Reserved 00
29:28 P0.30 GPIO Port 0.30 USB_D- Reserved Reserved 00
31:30 - Reserved Reserved Reserved Reserved 00

2. GPIO Port Direction control registers (FIO0DIR to FIO4DIR)

 This register individually controls the direction of each port pin, i.e. it decides
whether the pin should function as Input or Output
 Bit 0 in FIOxDIR controls pin Px.0, bit 31 in FIOxDIR controls pin Px.31
 Value = 0 => Controlled pin is input
 Value = 1 => Controlled pin is output
 Reset value of FIOxDIR = 0x0

3. Port Output Set register (FIO0SET to FIO4SET)

 This register is used to set a pin as high
 Bit 0 in FIOxSET controls pin Px.0, bit 31 in FIOxSET controls pin Px.31
 Writing 1 produces a HIGH at the corresponding port pin
 Writing 0 has no effect
 Reading this register returns the current contents of the port output register
 Reset value = 0x0

4. Port Output Clear register (FIO0CLRto FIO4CLR)

 This register is used to clear a pin to low
 Bit 0 in FIOxCLR controls pin Px.0, bit 31 in FIOxCLR controls pin Px.31
 Writing 1 produces a LOW at the corresponding port pin
 Writing 0 has no effect
 Reset value = 0x0

5. GPIO port Pin value register FIOxPIN(FIO0PIN to FIO4PIN)

 This register provides the value of port pins.
 Bit 0 corresponds to pin Px.0 and bit 31 corresponds to pin Px.31.

II) DAC Operation

1. PINSEL1 – DAC Output pin configuration

 P0.26 pin has an additional functionality as DAC output pin (AOUT)
 This functionality is enabled by configuring PINSEL1 register
 If bits 21:20 of PINSEL1 register has value ‘10’, DAC output becomes available
at P0.26
 2. DACR – DAC Register
 Input value to the Digital to Analog Converter is written to this register
DACR
Reset
Bit Symbol Value Description
value
5:0 - Reserved, user software should not write ones to reserved bits. NA
After the selected settling time after this field is written with a
new VALUE, the voltage on the AOUT pin (with respect to
15:6 VALUE VSSA) is VALUE x ((VREFP - VREFN)/1024) + VREFN. 0
The settling time of the DAC is 1 us max, and the maximum
current is 700 uA. This allows a maximum update rate of 1
0 MHz.
16 BIAS 0
The settling time of the DAC is 2.5 us and the maximum
current is 350 uA. This allows a maximum update rate of 400
1 kHz.
31:17 - Reserved, user software should not write ones to reserved bits. NA

III) ADC Operation

1. PINSEL1 – ADC Output pin configuration

 P0.23 pin has an additional functionality as ADC channel 0 input pin (AD0.0)
 This functionality is enabled by configuring PINSEL1 register
 If bits 15:14 of PINSEL1 register has value ‘01’, P0.23 acts as AD0.0

2. PCONP – Power Control for Peripherals register

 Bit 12 (PCADC) in PCONP register controls ADC
 If PCADC bit is 1, ADC is enabled. If PCADC bit is 0, ADC’s clock is disabled
(gated off) to conserve power
 Note: Clear the PDN bit in the AD0CR before clearing this bit, and set this bit
before setting PDN
 Reset value of this bit is 0

3. AD0CR – A/D Control Register

 ADCR register must be written to select the operating mode before A/D
conversion can occur
AD0CR
Reset
Bit Symbol Value Description
value
Selects which of the AD0.7:0 pin is to be sampled and
converted. For AD0, bit 0 selects Pin AD0.0, and bit 7 selects
7:0 SEL pin AD0.7. Only one of these bits should be 1 0x1
20:8 Not used in our experiments
1 The A/D converter is operational
21 PDN 0
0 The A/D converter is in power-down mode
23:22 - Reserved, user software should not write ones to reserved bits NA
000 No start (this value should be used when clearing PDN to 0)
001 Start conversion now
010
011
26:24 START 0
100
Not used in our experiments
101
110
111
31:27 Not used in our experiments

4. AD0GDR – A/D Global Data Register

 It holds the result of the most recent A/D conversion that has completed, and also
includes copies of the status flags that go with that conversion
AD0GDR
Reset
Bit Symbol Value Description
value
3:0 - Reserved, user software should not write ones to reserved bits NA
When DONE is 1, this field contains a binary fraction
representing the voltage on the AD0[n] pin selected by the SEL
field, as it falls within the range of VREFP to VREFN. Zero in
15:4 RESULT the field indicates that the voltage on the input pin was less NA
than, equal to, or close to that on VREFN, while 0xFFF
indicates that the voltage on the input was close to, equal to, or
greater than that on VREFP.
30:16 Not used in our experiments
This bit is set to 1 when an A/D conversion completes. It is
cleared when this register is read and when the ADCR is
31 DONE 0
written. If the ADCR is written while a conversion is still in
progress, this bit is set and a new conversion is started.
 CMSIS DSP Library Functions
1. arm_cfft_radix4_instance_f32 :
It is used to create a structure instance for the floating-point complex FFT / IFFT function.
Inbuilt Library function Usage

arm_cfft_radix4_instance_f32 x;

Here x is declared as a structure variable.

arm_cfft_radix4_instance_f32 arm_cfft_radix4_instance_f32 *ptr;

ptr is a pointer to a structure variable of

structure type :
arm_cfft_radix4_instance_f32

2. arm_cfft_radix4_init_f32 :
It is a function to initialise the parameters for computing FFT/IFFT.

Function Prototype:
arm_cfft_radix4_init_f32 (arm_cfft_radix4_instance_f32 * ptr, uint16_t fftLen,
uint8_t ifftFlag, uint8_t bitReverseFlag );

Inbuilt Library function Usage

arm_cfft_radix4_init_f32(ptr, 64, 0, 1);

This initialises the complex FFT (CFFT)

structure to compute 64 point FFT, with
FFT output ordered serially from 0 to
NFFT-1.

ptr is a pointer to the complex FFT structure

variable.
arm_cfft_radix4_init_f32
NFFT = 64.

To compute FFT, ifftFlag = 0. (To compute

IFFT, ifftFlag = 1.

bitReverseFlag = 1 ensures that the FFT

output buffer are filled with FFT values
X(0),X(1) … X(NFFT-1) in proper order.
 3. arm_cfft_radix4_f32 :
C function used to compute floating point FFT or IFFT.
Function Prototype:
arm_cfft_radix4_f32 (arm_cfft_radix4_instance_f32 * ptr, float * DataBuffer);
Inbuilt Library function Usage
arm_cfft_radix4_f32 ( ptr, DataBuffer);

This function computes FFT/IFFT of input

samples present in the array DataBuffer.
After computing FFT/IFFT, DataBuffer
array is over written with the FTT/IFFT
values.
arm_cfft_radix4_f32

ptr is a pointer to the complex FFT structure

variable.

DataBuffer is a floating point array of

length : 2*NFFT

If the input samples x(n) are given by :

𝑥(0) = 𝑎0 + 𝑗 𝑏0
𝑥(1) = 𝑎1 + 𝑗 𝑏1
𝑥(2) = 𝑎2 + 𝑗 𝑏2
…
𝑥(𝑁 − 1) = 𝑎𝑁−1 + 𝑗 𝑏𝑁−1

Then 2N length DataBuffer array must be filled with :

𝑓𝑙𝑜𝑎𝑡 DataBuffer [2 ∗ N] = {𝑎0 , 𝑏0 , 𝑎1 , 𝑏1 , 𝑎2 , 𝑏2 . . . 𝑎𝑁−1 , 𝑏𝑁−1} ;

After FFT, if FFT output X(k) is given by :

𝑋(0) = 𝐴0 + 𝑗 𝐵0
𝑋(1) = 𝐴1 + 𝑗 𝐵1
𝑋(2) = 𝐴2 + 𝑗 𝐵2
…
𝑋(𝑁 − 1) = 𝐴𝑁−1 + 𝑗 𝐵𝑁−1
After FFT, elements of DataBuffer array are : {𝐴0 , 𝐵0 , 𝐴1 , 𝐵1 , 𝐴2 , 𝐵2 . . . 𝐴𝑁−1 , 𝐵𝑁−1}

4. arm_cmplx_mag_f32:
C function used to compute magnitude of FFT/IFFT output.
Function Prototype:
arm_cmplx_mag_f32 (float *FFTBuff, float *MagnitudeBuff, uint32_t NFFT);

Inbuilt Library function Usage

arm_cmplx_mag_f32 (FFTBuffer, MagnitudeBuff, NFFT);

This function computes magnitude of FFT output 𝑋(𝑘)

present in the array FFTBuffer. After computing FFT/IFFT,
MagnitudeBuff array contains the Magnitude of FFT/IFFT
samples |𝑋(𝑘)|
arm_cfft_radix4_f32

FFTBuffer is a floating point array of length : 2*NFFT.

MagnitudeBuff is a floating point array of length : NFFT

 LPC1769 Board – Connector Pins Used

Connector Pin Number Important Function

4 Port 0.1
5 Port 0.0
J1 22 GND
23 GND
24 GND
1 LED Connected
J3
2 LED Connected
1 GND
2 GND
3 P0.26 / AOUT (DAC Out)
J26
6 P0.23 / AD0.0 (ADC Channel 0 Input)
11 GND
12 GND
1 VDD (+3.3 V)
2 VDD (+3.3 V)
J27
3 VDD (+3.3 V)
4 VDD (+3.3 V)