DCF - MODULE III

COMBINATIONAL LOGIC
CIRCUITS
Classification of Digital circuits
Two types of Logic circuits
● Combinational Circuit
In a combinational circuit, the input values
explicitly determine the output
● Sequential Circuit
In a sequential circuit, the output is a function of
the input values as well as the existing state
of the circuit

we can describe the operations of entire circuits using

Boolean expressions Logic diagrams Truth tables
Combinational Logic Circuits
●A combinational circuit consists of input
variables, logic gates, and output variables.
●It is constructed using more than one basic
gates or universal gates
●Eg: adder, subtractor , Multiplexers, demultiplexers,
decoders, encoders, comparators, code conveters etc
 Half Adder
● A combinational circuit that performs the addition
of two bits is called a half adder.
● The truth table for the half adder is listed below:

Carry
it has two inputs X and Y X Y
out
Sum
it has two out puts Sum and Carry out
0 0 0 0
0 1 0 1
● S=X’Y + XY’= X Y
1 0 0 1
● C= XY
1 1 1 0
Implementation of Half-Adder

5
HALF ADDER – using NAND gate
 Full-Adder

√ It performs the addition of three bits at a time

√ The three inputs are A,B and Cin and two outputs
SUM and Cout.
√ We can construct a full adder using two half adders
√ The first half adder will add two inputs A and B. And the
second half adder circuit will add the C-in and the partial
sum output of first half adder.

√ The final C-out will get by OR-ing the C-outs from both
Half adders.

7
 Implementation
■ Full-adder can be implemented with two half adders
and one OR gate (Carry Look-Ahead adder).
■ The C-out and SUM together will give the binary
equivalent of Cin+B+A
S = C (A B)
= A’B’C+ A’BC’ +AB’C’ + ABC
Carry = C(AB’ + A’B) + AB = AB’C + A’BC + AB

8
Simplified Expressions

9
Full adder
 Parallel Binary Adder
●A full adder is capable of adding two 1-bit binary
numbers and a carry-in.
●When two n-bit numbers are to be added, the
number of full adders required will be equal to the
number of bits (n) in each number.
●The addition of LSBs can be done by using either
a half-adder or a full-adder with Cin is grounded.
●The carry out of each full adder is connected to
the carry-in of the next higher order adder.
● A parallel adder is used to add two numbers in parallel form and to
produce the sum bits as parallel outputs.
● Eg: if A3A2A1A0 =1101 and B3B2B1B0 = 0101
4-bit binary Adder-Subtractor
● When the mode input (M) is at a low logic, i.e. '0',
the circuit act as an adder and when the mode
input is at a high logic, i.e. '1', the circuit act as a
subtractor.
● The exclusive-OR gate connected in series
receives input M and one of the inputs B.
● When M is at a low logic, we have B 0 = B.
The full-adders receive the value of B, the input
carry is 0, and the circuit performs A plus B.
● When M is at a high logic, we have B 1 = B' and
C0 = 1.
The B inputs are complemented, and a 1 is added
through the input carry. The circuit performs the
operation A plus the 2's complement of B
 Decimal Adder (BCD Adder)

● A BCD adder adds two 4-bit BCD code groups using

straight binary addition.
● If the sum of this addition is greater than 1001
(decimal 9), add 0110 (decimal 6) to this sum and
generate a carry to the next decimal position.
● A correction is needed when the sum is greater than
01001.
● From the above table, it is clear that if the
produced sum is between 1 to 9, the Binary and
the BCD code is the same.
● But for 10 to 19 decimal numbers, both the codes
are different.
● In the above table, the binary sum combinations
from 10 to 19 give invalid BCD.
● It is obvious from the table that a correction is needed when
the 'Binary Sum' has an output carry K=1.
● The other six combinations from 10 to 15 need correction in
which the bit on the Z8 position is 1.
● In the Binary sum of 8 and 9, the bit on the Z8 position is also 1.
So, the second step fails, and we need to modify it.
● To distinguish these two numbers, we specify that the bit on
the Z4 or Z2 position also needs to be 1 with the bit of Z8
● The condition for a correction and an output carry can be
expressed by the Boolean function:
C=K+Z8.Z4+Z8.Z2

● Once the circuit found the invalid BCD, the circuit adds the
binary number of 6 into the invalid BCD code to make it valid.
√ We take a 4-bit Binary-Adder, which takes addend and augend bits as an
input with an input carry 'Carry in'.
√ The Binary-Adder produces five outputs, i.e., Z8, Z4, Z2, Z1, and an output
carry K.
√ With the help of the output carry K and Z8, Z4, Z2, Z1 outputs, the logical
circuit is designed to identify the Cout
nd
√ The Z8, Z4, Z2, and Z1 outputs of the binary adder are passed into the 2 4-
bit binary adder as an Augend.
nd
√ The addend
st
bit of
th
the 2 4-bit binary adder is designed in such
nd
a way that
rd
the 1 and the 4 bit of the addend number are 0 and the 2 and the 3 bit
are the same as Cout.
√ When the value of Cout isst0, the addend number will be 0000, which produce
the same result as the 1 4-bit binary number.
√ But when the value of the Cout is 1, the addend bit will be 0110, i.e., 6, which
adds with the augent to get the valid BCD number.
 Example: 1001+1000
√ First, add both the numbers using a 4-bit binary adder
and pass the input carry to 0.
√ The binary adder produced the result 0001 and carried
output 'K' 1.
√ Then, find the Cout value to identify that the produced
BCD is invalid or valid using the expression
Cout=K+Z8.Z4+Z8.Z2.
√K=1
Z8 = 0
Z4 = 0
Z2 = 0
Cout = 1+0*0+0*0
Cout = 1+0+0
Cout = 1
√ The value of Cout is 1, which expresses that the
produced BCD stcode is invalid. Then, add the
output of the 1 4-bit binary adder with 0110.
= 0001+0110
= 0111
√ The BCD is represented by the carry output as:
BCD=Cout Z8 Z4 Z2 Z1=1 0 1 1 1
 Binary multiplier
●Multiplication of binary numbers is
performed in the same way as
multiplication of decimal numbers.
●The multiplicand is multiplied by each bit of
the multiplier, starting from the least
significant bit.
●The multiplicand bits are B1 and B0, the
multiplier bits are A1 and A0, and the product is
C3C2C1C0.
●The first partial product is formed by multiplying
B1B0 by A0.
●The multiplication of two bits such as A0 and B0
produces 1 if both bits are 1; otherwise, it
produces 0
●The partial product can be implemented with
AND gates
Binary Multiplier - Diagram
 MAGNITUDE COMPARATOR
●The comparison of two numbers is an
operation that determines whether one
number is greater than, less than, or equal
to the other number.
●A magnitude comparator is a
combinational circuit that compares two
numbers A and B and determines their
relative magnitudes.
●The outcome of the comparison is
specified by three binary variables that
indicate whether A>B, A = B, or A < B.
Comparator
● It is used to compare the magnitudes of two binary
numbers
● Normally it provide an active high when the
numbers are equal
● It also provide outputs that signify which of the
number is greater
● The X-NOR gate is a basic comparator, because its
output is 1 only when two inputs are equal
1 bit magnitude comparator
 2 – bit Comparator
● A 2-bit comparator compares two binary numbers
containing two bits each.
● It produces the relation, one number is equal or greater
than or less than the other.
● A two-bit comparator which has four inputs and three
outputs.
● The first number A is designated as A = A1A0
and the second number is designated as B =
B1B0.
● This comparator produces three outputs as G (G
= 1 if A>B), E (E = 1, if A = B) and L (L = 1 if A<B).
 DECODER
●A decoder is a combinational circuit.
●A decoder accepts a set of inputs that represents a
binary number and activates only that output
corresponding to the input number. All other outputs
remain inactive.
●Fig. 1 shows the block diagram of decoder with ‘N’
inputs and ‘M’ outputs.
N
●There are 2 possible input combinations, for each of
these input combination only one output will be HIGH
(active) all other outputs are LOW
●Some decoder have one or more ENABLE (E) inputs that
are used to control the operation of decoder.

37
BLOCK DIAGRAM OF DECODER

A0 B0
A1
A2 B1
. DECODER . B2
. .
. .
A . .
B
N-1 M-1

N- M- Outputs
Inputs Only one output is High
for each input
38
 2 to 4 Line Decoder:
● Block diagram of 2 to 4 decoder is shown in fig.
● A and B are the inputs. ( No. of inputs =2)
2
● No. of possible input combinations: 2 = 4
2
● No. of Outputs : 2 = 4, they are indicated by D0, D1, D2 and D3
● From the Truth Table it is clear that each output is “1” for only specific
combination of inputs.

TRUTH TABLE
A D
0
INPUTS OUTPUTS
2X4 1
Decode D A B D0 D1 D2 D3
B D2
r 0 0 1 0 0 0
D3
0 1 0 1 0 0
Input Outputs
s 1 0 0 0 1 0
1 1 0 0 0 1

39
BOOLEAN EXPRESSION:
From Truth Table
D0 A B D1 A B
D2 A B D3 AB
LOGIC DIAGRAM:
B
A
A B

D0 A B
D1 A B

D2 A B

D3 A B

40
 3 to 8 Line Decoder:
● Block diagram of 3 to 8 decoder is shown in figure
● A , B and C are the inputs. ( No. of inputs =3)
3
● No. of possible input combinations: 2 = 8
3
● No. of Outputs : 2 = 8, they are indicated by D0 to D7
● From the Truth Table it is clear that each output is “1” for
only specific combination of inputs.

A . D0
B
3X8 .
Decoder .
C .
D7
Input Outputs
s
41
 TRUTH TABLE FOR 3 X 8 DECODER:

INPUTS OUTPUTS

A B C D0 D1 D2 D3 D4 D5 D6 D7

0 0 0 1 0 0 0 0 0 0 0 D0 A B C
0 0 1 0 1 0 0 0 0 0 0 D1 A B C
0 1 0 0 0 1 0 0 0 0 0 D2 A B C
0 1 1 0 0 0 1 0 0 0 0 D3 A B C

1 0 0 0 0 0 0 1 0 0 0 D4 A B C

1 0 1 0 0 0 0 0 1 0 0 D5 A B C

1 1 0 0 0 0 0 0 0 1 0 D6 A B C

1 1 1 0 0 0 0 0 0 0 1 D7 A B C

42
 LOGIC DIAGRAM OF 3 X 8 DECODER:

AB INPUTS
C
AB C

D0 A B C

D1 A B C

D2 A B C
D3 A B C
OUTPUTS
D4 A B C

D5 A B C

D6 A B C

D7 A B C
43
 Gray Code to Binary Conversion
●The MSB of the binary number will be equal to
the MSB of the given gray code.
●Now if the second gray bit is 0, then the second
binary bit will be the same as the previous or the
first bit. If the gray bit is 1 the second binary bit
will alter. If it was 1 it will be 0 and if it was 0 it
will be 1.
●This step is continued for all the bits to do Gray
code to binary conversion.
 Input (gray) Output (Binary)

G4 G3 G2 G1 B4 B3 B2 B1

0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 1
0 1 0 1 0 1 1 0
0 1 1 0 0 1 0 0
0 1 1 1 0 1 0 1
1 0 0 0 1 1 1 1
1 0 0 1 1 1 1 0
1 0 1 0 1 1 0 0
K-map representation of gray codes
Logic diagram
ENCODERS
● An encoder is a combinational logic circuit that converts
n
binary information in the form of ‘2 ’ input lines into ‘n’ output
lines.
● It performs the reverse operation of Decoder.
● Only one input line is active at a time. It produces an N-bit
output code depending on the activated input
n
● The encoder is a 2 : n circuit where n=1,2,3 etc

A0 B0
In A1 B1 ‘N’
pu A2 B2
ts -- Encoder -- O
‘M
’ -- -- ut
A
-- -- B
pu
M-1 - - N-1 ts
4 : 2 Encoder
● The 4 to 2 Encoder consists of four inputs Y3, Y2,
Y1 & Y0 and two outputs A1 & A0.
● At any time, only one of these 4 inputs can be ‘1’ in
order to get the respective binary code at the
output.
 Truth table & Circuit
INPUTS OUTPUTS
Y3 Y2 Y1 Y0 A1 A0
0 0 0 1 0 0
0 0 1 0 0 1
0 1 0 0 1 0
1 0 0 0 1 1

Logical expression for A1 and A0 :

A1 = Y3 + Y2
A0 = Y3 + Y1
Multiplexer & De-multiplexer
 Multiplexer (data Selectors)
● Definition : A multiplexers (MUX) is a device that allows digital information
from several sources to be routed onto a single line for transmission over
that line to a common destination.

● Simply a multiplexer is a many input single output combinational circuit.

● Several data input lines

● Some select line (less than the no. of input lines)

● Single output line

● If there are n data input lines and m select lines,

m
then 2 = n
Multiplexer Block Diagram
Example
 2 to 1 Multiplexers

● A 2 to 1 Mux has two inputs D0 , D1

● One control signal S and one output Z .

● If value of S is zero D0 is selected and if value of S0 is one D1 is

selected.

Truth table
S Z

0 D0
1 D1
2 to 1 MULTIPLEXER
Select
input

Input MUX
Output
● When S= 0, AND gate1 is enabled and AND gate2
is disabled. So Z = D0

● When S = 1, AND gate1 is disabled and AND

gate2 is enabled. So Z = D1
Applications of Multiplexers
● Multiplexers can be used for various applications
● Data selection
● Data routing
● Operation sequencing
● Parallel to serial conversion
● Waveform generation
● Logic function generation
 PRIORITY ENCODERS
√ The encoders will operate correctly, provided that
one and only one decimal input is HIGH at any
given time.
√ In some practical systems, two or more decimal
inputs may inadvertently become HIGH at the
same time.
√ For example, a person operating a keyboard might
press a second key before releasing the first.
√ A priority encoder is a logic circuit that responds to just
one input in accordance with some priority system,
among all those that may be simultaneously HIGH.
√ The most common priority system is based on the
relative magnitudes of the inputs; whichever decimal
input is the largest, is the one that is encoded.
√ Thus, in the above example, a priority encoder would
encode decimal 4 if both 3 and 4 are simultaneously
HIGH.
√ In some practical applications, priority encoders may
have several inputs that are routinely HIGH at the same
time, and the principal function of the encoder in those
cases is to select the input with the highest priority. This
function is called arbitration.
 4:2 Priority Encoder
√ A 4 to 2 priority encoder has 4 inputs : Y3, Y2, Y1 & Y0
and 2 outputs : A1 & A0.
√ Here, the input, Y3 has the highest priority, whereas the
input, Y0 has the lowest priority.
√ In this case, even if more than one input is ‘1’ at the
same time, the output will be the (binary) code
corresponding to the input, which is having higher
priority.
√ It has a third output ‘V’ which is a valid bit indicator and
is set to one when one or more inputs are active or equal
to 1.
√ This valid bit is zero when all the inputs are zero which
indicates that there is no valid input. On this condition,
other outputs are considered as don’t care conditions
and are not inspected when V is zero.
Truth Table of 4:2 Priority
Encoder

V= Y3 + Y2 + Y1 + Y0
V= Y3 + Y2 + Y1 + Y0