Virtual memory: Conceptualization

• The hard drive (secondary memory) is inexpensive and give the illusion of a very
large memory for many programs.
• Ex: many applications (games, video, software program) may require some specific
storage (main memory: 512MB, 2GB, etc) requirements for functioning.
• Yet, they may be huge in size (ex: games may be 20GB, etc).
• Then, how do they survive to run/function with limited main memory?
• It is by virtual memory concept→ larger disk is called (in fact, visualized as) virtual
memory,{conceptually}
• The smaller main memory is→ called physical memory.
Virtual memory: Conceptualization

• It’s a cache again !!??

• Physical memory acts as a cache for slower (virtual) secondary memory.
• Reality:: Programs can access data anywhere in virtual memory →using
virtual addresses.
• The physical memory holds a subset of most recently accessed virtual
memory. → page
• Thus, most accesses hit in physical memory at the speed of DRAM.
• Yet, the program enjoys the capacity of the larger virtual memory. [It is what
the program uses]
 Why virtual memory or why not ?

• Ex: MIPS allows 32-bit address space (i.e. 4GB of addressable locations)
Without Virtual Memory
Program Address = RAM Address

Program Address 1GB Physical

Space (4GB) Memory (RAM)
0
1
2
…

After reaching 1GB of Fact: Each program should get 32b space; But, we could
mem (RAM)., there is allocate space based on the hardware (i.e. RAM→1GB)
no space for remaining used there (30b). Other wise..?
!!

*MIPS: Microprocessor without interlocked pipelined stages (RISC)

 Why virtual memory or why not ?

• Otherwise, there is problem:: go out of memory or crash by referring to wrong

(un-available) RAM address.
• Also, can multiple programs access the same memory address? → what
happens then?
Program1(1GB)
0x00000000 • We don't have any way to
separate what mem loc., they
access…..so they corrupt
values.
VAL#2
VAL#1

Program2(2GB) ❖ Can we provide separate RAM

space to each program
0xFFFF FFFF [instead of all using the same
physical Address 32b space] ??
Space
• Yes, we could give space from disk for the programs → virtual memory
space.
• We need to have a mapping table to say (translate) which mem.address is
mapped to which address in the virtual memory..
• Program address-→mappingRAM address

• All these managed by the OS + assisted by some hardware (TLB: translation

look-aside buffer)
• Summary: Virtual mem., concept allows sharing of mem (RAM) between different
programs (by providing extra-space required from the disk)→bring back when you
need in RAM.→ thus each program feels that there is enough space for it to
run
• Usually, a program may use only a small part of the memory, so rest of it could
reside in the disk

• By this, OS can allocate memory to different OTHER programs (2, 3, …etc) if

there is space.

• Each program will have its own compiled virtual address space→ but, during
run time its virtual address need to be translated to physical address. [ex: say
if vir.addrs is 40→ whats the phy.address in mem?]
 Program 1
virtual address space
Pages are either in main
memory or in secondary
main memory
• Program 1’s total storage (hard disc)
address is divided
into pages.
• Also, all the pages Program 2
of vir.addrs (program disc virtual address space
1) are in disk OR in
phy. mem.
• NOTE: Page 1 of
Program 1 / 2
mapped (translate)
to random mem.
locations
Page Table and Address Mapping

• A 32-bit processor allows 32 bit address for programs

• But, phy.mem may be smaller (1GB) ; so we have 30
bit address.
• So, we translate [i.e. it is called page table] to
accommodate each vir. address to phy. Address [i.e. in
RAM/Disc]
• Only, size (# of bits in VP number and PP number
differ) of vir.page and Phy. page differ
• Now, we keep ‘page offset’ size same [i.e. position of
a data (byte/word) with in a page is same: 12 bits]
With virtual memory…

Program Address Maps to RAM

Address

Program Address 1GB Physical

Space (4GB) Memory
0
1
2 MAP
…

Disk
 • IDEA:: When we have less memory (RAM)→ Map some of the
address space to the disc→ bring them back to RAM when needed.

Program Loads VM map address

Address 0 0 to ram1
Program Address 1GB Physical VM map address
Program Loads Space (4GB) Memory 1 to ram0
Address 1 VM map address
0 1
Program Loads 1 02 3 to ram 2
Address 3 2 MAP 3
Program Loads 3
Address 2 2
➢It’s a miss→ Page Fault
Address 2 (mapped to disk
➢Replace Physical memory
NOTE: the disc gives the earlier)loaded from disc to
content by new program
illusion that physical memory RAM by replacement. addrs content and update the
is so large for all programs to map ( Addrs 0 is in disc now).
use it.→ virtual memory Disk
• Further, these programs can have their own mapping → flexibility.
• That is program 1→map1 memory
• Program 2→map2memory
• Of course, they (map 1/2) goes to different memory locations [do not over
write]
Translation of address

• We have an entry for each VA to map to a PA.

Physical address

translation Later bring from disc→ RAM and update

translation with new PA for 2100 (instead of ‘disc’)

Virtual address

If have 1 entry for each address…then we need

large space to maintain the table itself..!! Not good
Page table
• For better management→ divide memory into chunks [PAGES]
• It is different from considering every address (here it’s a range of address in a
PAGE)

• Ex: a page could cover 2K entries (i.e. address range 0-2000-→ PA: 1000-
3000] ..That means no individual address are considered, instead a range of
address (page) is considered.
• + less page table entries can cover whole address space
• - how to know an intermediate address (possible, but not so flexible like
before, i.e. single entry system)
 Page Table Virtual
VA to PA Mapping
Address Space
VA PA
24575 Physical
1234 2 Address Space
1600 3 20480 16383
2100 disc 20479
12288
16384 12287
16383
0-4095 4096-8191 8192
12288 8191
12287
4096
8192 4095
What is the physical address 8191
for virtual address 300? 0
4096
4095
4096+300 (i.e. base+offset)
0
Page table mapping
• The virtual page number is used to
index the page table.
• If the V bit is on, the page table
supplies the physical page number
(i.e., the starting address of the page
in memory)
• If the valid bit is off, the page resides
only on disk, at specified disk
address.
 Program 1
virtual address space

main memory
• Q: what is phy. Page num for
virtual page 4? (program 1)
• Ans: Phy page =1
Program 2
virtual address space

• Q: what is the phy.page for

vir.page 1 (program 2) ?
• Ans: 7
 Page Table and Address Mapping
Page table register
Page Table maps virtual page Virtual address
numbers to physical frames (each 31 30 29 28 27 15 14 13 12 11 10 9 8 3 2 1 0

program has its page table) Virtual page number Page offset

20 12
Page Table Register (in Valid Physical page number

processor) contains the address

• 32-bit address space.
of the page table. (for any program • Starting address of page
want to execute)
table→ page table Reg.
Page table • Page size=4KB (offset)
Virtual page number is used as • Phy mem = 1GB (2^30)
an index into the page table • Page table entries→2^20
(2^32/2^12)
18

Page Table Entry (PTE): If 0 then page is not

present in memory

describes the page and its 29 28 27 15 14 13 12 11 10 9 8 3 2 1 0

usage Physical page number Page offset

Physical address
• What is Virtual Memory?
• Uses disk as an extension to memory system
• Main memory acts like a cache to hard disk
• Each process has its own virtual address space
• Page: a virtual memory block
• Page fault: a memory miss
• Page is not in main memory  transfer page from disk to memory
• Address translation:
• CPU and OS translate virtual addresses to physical addresses
• Translation can have hierarchy:: because all page table is in main memory ,
every time go for it (its slower, even if we have cache for speedup; because
table is in main. memory)

• Can we put some very urgent (frequently used) data in a high speed memory
?
• → we use TLB ( dedicated hardware/ co-located with chip for performance
[size will be small] )
TLB = Translation Lookaside Buffer
• Address translation is very expensive
• Must translate virtual memory address on every memory access
• Solution: TLB for address translation
• Keep track of most common translations in the TLB
• TLB = Cache for address translation
• A cache for address translations – translation-lookaside buffer (TLB):
TLB
Virtual page Physical page
number Valid Tag address
• TLB holds a subset of translations from the
1
1
From TLB page table.
1
1
Physical memory
• On a page reference, →first look up the
0
1
virtual page number in the TLB; if there is a
Page table
TLB miss→ look up the page table; if miss
Valid
Physical p
age again →then true page fault
or disk address

1
• Tag holds a portion of virtual page number
1
1
in TLB
• Ref :bit is used when a translation is done
Disk storage
1
0
From PT
1
1
(referenced). Useful for replacement (LRU)
0
1
1
0
1
• Given the VA space of 32 bits and VA reference is 0x00003210, assuming that
TLB has no match initially, visualize the process of loading from phy. Mem. [let
page size= 4KB]
Phy. Mem
• Ans: 0x00003210 0x0002
0x0003
Vir (tag) Phy pg # 0x0005
• TLB 0x0004
0x0007

• Phy. Mem (assume size) 27 12 11 0

Page num→says which page; offset-→ where in that page

• Given the VA space of 32 bits and VA reference is 0x00003210, assuming that
TLB has no match initially, visualize the process of loading from phy. Mem. [let
page size= 4KB]
Phy. Mem
• Ans: 0x00003210 0x210 [offset] 0x0002
0x0003
Vir (tag) Phy pg # 0x0005
• TLB 0x00003 0x0005 0x0004
0x0007

27 0x0005 11 0
• Phy. Mem (assume size) 12
0x210 [offset]
 VA 32 bit (MSB 0) i.e. 31bit [2^31]→2GB

• Find the physical address of virtual address 0x247C

using the virtual memory system shown. V. Page 20 bit (MSB 0) i.e. 19bit
• Given: 2 GB of vir. mem and 128 MB of phy. memory divided [2^19]
into 4-KB pages (with 32-bit addressing)

• Ans:
• How many V. Pages→ 2GB/4KB→2^19
• How many P. Pages→128MB/4KB = 2^15
• VA is 32 bit, PA is 28 bit.
• So, in 0x247C, last 12 bits (as page size 4KB) →
offset
Phy. Adrs 28 bit (MSB 0) i.e. 27bit
[2^27] →128MB
Phy. Pages 16 bit (MSB 0) i.e. 15bit
[2^15]
 VA 32 bit (MSB 0) i.e. 31bit [2^31]

• The remaining 19 bits of the VA (i.e. 31-12) give the virtual

page number, so virtual address V. Page 20 bit (MSB 0) i.e. 19bit
0x247C is found in virtual page 0x2. (00002→19 bits) [2^19]

• virtual page 0x2 maps to physical page 0x7FFF.

(top row in PA)

• Thus:
• virtual address 0x247C maps to PA (28bit) 0x7FFF47C.

Phy. Adrs 28 bit (MSB 0) i.e. 27bit

[2^27]
Phy. Pages 16 bit (MSB 0) i.e. 15bit
[2^15]
• Find the physical address of virtual address 0x247C using the page table
shown:

• Ans:
• Assume:: similar page settings as before.
• Now, VA→ V. page | {concatenated} offset

• We know offset is 12 bit [47C]

• From the fig. Virtual page 0x2 to phy. page 0x7FFF.

• So, V.A→ 0x247C maps to P.A→ 0x7FFF47C [28 bit]
• If a computer uses 64-bit virtual addresses, how much virtual memory can it
access?

• Ans: 2^64 bytes

• Consider a virtual memory system that can address a total of 2^32 bytes. You
have unlimited hard drive space, but are limited to only 8 MB of physical
memory. Assume that virtual and physical pages are each 4 KB in size.

• How many bits is the physical address?

• Ans: 2^23 ~ 8MB
• What is the maximum number of virtual pages in the system?
• Ans: 2^32/ 2^12 = 2^20 vir. Pages
• How many physical pages are in the system?
• Ans: 8 MB / 4 KB = 2^11 phy.pages
• How many bits are the virtual and physical page numbers?
• Ans:: virtual page number: 20 bits; physical page number = 11 bits
• Given the VA space of 32 bits and VA reference is 0x00003210, assuming that
TLB has no match initially, visualize the process of loading from phy. Mem. [let
page size= 4KB]
Phy. Mem
• Ans: 0x00003210 0x0002
0x0003
Vir (tag) Phy pg # 0x0005
• TLB 0x0004
0x0007

• Phy. Mem (assume size) 27 12 11 0

• Given the VA space of 32 bits and VA reference is 0x00003210, assuming that
TLB has no match initially, visualize the process of loading from phy. Mem. [let
page size= 4KB]
Phy. Mem
• Ans: 0x00003210 0x210 [offset] 0x0002
0x0003
Vir (tag) Phy pg # 0x0005
• TLB 0x00003 0x0005 0x0004
0x0007

27 0x0005 11 0
• Phy. Mem (assume size) 12
0x210 [offset]
 VA reference is 0x00004210
1. Offset map
2. match Vir (tag) bit of TLB [0x00003] with VA’s page number [0x00004]→miss
3. Load page from PAGE TABLE in main memory [find vir.page 4 (i.e. 4th row)
4. Find the phy.page # 0x0001 (mapping)
5. Update the TLB (2nd entry)
6. Get the translation: 0x0001210 Phy. Mem [Page. Table
0x00004 0x210 [offset] 0x0002
• Ans: 0x00004210 0x0003
Vir (tag) Phy pg # 0x0005
0x00003 0x0005 0x0001
• TLB 0x00004 0x0001 0x0007

0x0001
• Phy. addrs (assume size) 27 12 0x210
 VA reference is 0x00003210
1. Offset map
2. match Vir (tag) bit of TLB [0x00003] with VA’s page number [0x00003]→hit
3. Get the translation: 0x0005210

Phy. Mem [Page. Table

0x00004 0x210 [offset] 0x0002
• Ans: 0x00003210 0x0003
Vir (tag) Phy pg # 0x0005
0x00003 0x0005 0x0001
• TLB 0x00004 0x0001 0x0007

• Phy. addrs (assume size) 27 12 0x210

1. Offset map VA reference is 0x00005210
2. match Vir (tag) bit of TLB [0x00003 or 4] with VA’s page number [0x00005]→miss
3. Replace: TLB entry (any) to load page from PAGE TABLE in main memory [find
vir.page 5 (i.e. 5th row)
4. Find the phy.page # 0x0007 (mapping)
5. Update the TLB (2nd entry)
Phy. Mem [Page. Table
6. Get the translation: 0x0007210
0x00005 0x210 [offset] 0x0002
• Ans: 0x0x00005210 0x0003
Vir (tag) Phy pg # 0x0005
0x0001
• TLB 0x0007

0x0007
• Phy. addrs (assume size) 27 12 0x210
1. Offset map
VA reference is 0x00001210
2. match Vir (tag) bit of TLB [0x00003 or 5] with VA’s page number [0x00001]→miss
3. Replace: TLB entry (any) to load page from PAGE TABLE in main memory [find vir.page 1 (i.e.
1st row: oh its in Disc→ page fault)

Phy. Mem [Page. Table

0x00001 0x210 [offset] 0xF0F0[DISC]
• Ans: 0x0x00001210 0x0003
Vir (tag) Phy pg # 0x0005
0x00003 0x0005 0x0001
• TLB 0x00005 0x0007 0x0007

• Phy. addrs (assume size) 27 12 0x210

1. Offset map
VA reference is 0x00001210
2. match Vir (tag) bit of TLB [0x00003 or 5] with VA’s page number [0x00001]→miss
3. Replace: TLB entry (any) to load page from PAGE TABLE in main memory [find vir.page 1 (i.e.
1st row: oh its in Disc→ page fault)
4. Find the phy.page # disc (go to disc)
5. Update the TLB (1st entry) Phy. Mem [Page. Table
6. Get the translation: long wait 0x00001 0x210 [offset]
• Ans: 0x0x00001210 0xF0F0[DISC]
Vir (tag) Phy pg # 0x0003
0x00001 0xF0F0[DISC] 0x0005
• TLB 0x00005 0x0007 0x0001
0x0007

• Phy. addrs (assume size) 27 12 0x210