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Inventec Power Block Diagram

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Felippe Gomes Nascimento
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38 views57 pages

Inventec Power Block Diagram

Uploaded by

Felippe Gomes Nascimento
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
Available Formats
Download as PDF, TXT or read online on Scribd
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8 7 6 5 4 3 2 1

THIS DRAWING AND SPECIFICATIONS,HEREIN,ARE THE PROPERTY OF INVENTEC


CORPORATION AND SHALL NOT BE REPODUCED,COPIED,OR USED IN WHOLE OR
IN PART AS THE BASIS FOR THE MANUFACTURE OR SALE OF ITEMS WITHOUT
WRITTEN PERMISSION,INVENTEC CORPORATION,2009 ALL RIGHT RESERVED.

F HSF Property:ROHS or Halogen-Free(5L3?) F

E E

D
HARVEY 14 D

CR / HR UMA / DIS
2011.09.02

C C

B B

A A

DRAWER
DESIGN
EE DATE POWER DATE
INVENTEC
CHECK TITLE MODEL,PROJECT,FUNCTION
RESPONSIBLE HARVEY 14
AUGUST 30, 2010
21-OCT-2002 X01 SIZE= VER: SIZE CODE DOC.NUMBER REV
FILE NAME: C CS 1310xxxxx-0-0 X01
DATE CHANGE NO. REV P/N XXX SHEET 1 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Index
D
D

01 Project Name 26 PCH-1 51 SEYMOUR POWER


02 Page Index 27 PCH-2 52 SEYMOUR DP-POWER & LVDS
03 Block Diagram 28 PCH-3 53 SEYMOUR MEMORY INTERFACE
04 Power Procedure 29 PCH-4 54 VRAM DDR3
05 Charger 30 PCH-5 55 DGPU POWER EE
06 Battery Connecter 31 PCH-6 56 DGPU POWER
07 P3V3A, P5V0A 32 PCH-7 57 USB, POWERBUTTON ,TP DB
C 08 P1V5 33 PCH-8 C

09 P1V05S 34 PCH-9
10 P1V8S 35 EC ITE8517E
11 PVSA 36 KB & LED
12 PVCORE-1 37 CRT
13 PVCORE-2 38 LCD & WEBCAN
14 PORT 39 HDMI
15 P3V3S, P5V0S 40 SATA HDD& ODD
16 GREEN CLK 41 LAN
B 17 CPU -1 42 RJ-45 CONN B

18 CPU-2 43 CARD READER


19 CPU-3 44 AUDIO CODEC
20 CPU-4 45 HP & MIC JACK
21 CPU-5 46 WLAN
22 CPU-6 47 USB 3.0 CONN
23 Thermal & Fan 48 SEYMOUR PCI-E INTERFACE
24 DDR3-1 49 SEYMOUR CRT CLK THERMAL
25 DDR3-2 50 SEYMOUR THERMAL SENSOR
A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
INDEX
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS X01
CHANGE by XXX DATE 21-OCT-2002 SHEET 2 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

DDR3 SO-DIMM1
VGA IVY BRIDGE DDR3 1333/1600 MAX 8GB
CRT V-RAM
128M X 16 AMD SEYMOUR 64BIT
PCIE-8X (SOCKET RPGA 989)
37.5MM X 37.5MM
(2GB) S3 PACKAGE
DDR3 DDR3 SO-DIMM2
1333/1600 MAX 8GB
HDMI FDI DMI
D
D

LCM USB USB


PANTHER POINT BLUE TOOTH WEBCAM
CARD READER PCIE USB 2.0
RTL 5239-GR
25MM X 25MM USB USB
RJ-45 RTL 8165EH-CG PCIE USB CONN1 USBCONN2
10/100 LAN
USB 3.0
C WLAN + BT PCIE C
MINI CARD
RTL 8161FH-CG USB CONN3
SATA
GIGA LAN
SATA

HDA LPC SPI ROM


4MB
SATA HDD SATA ODD
HSPI
B B
SPEAKER ALC 3201-GR KBC SPI ROM
AUDIO CODEC ITE IT8517E 1MB

HP JACK
DMIC MAIN BATT
COMBO JACK KEYBOARD TOUCHPAD
THERMAL METER
TI TMP431A SYSTEM CHARGER
A A
DC/DC SYSTEM POWER

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
Block Diagram
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 3 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PVADPTR VADPBL
AC MOS MOS

PVPACK
D DC MOS VRP5V0A
PAD
P5V0A
PAD
VRPVCCSA_IN VCCSA
TPS51461RGER
VRPVSA
PAD
PVSA
D

PVBAT P5V0S
CHARGER MOS 5V / 3.3V MOS
BQ24728 TPS51123RGER VRP3V3A P3V3A 1.8V VRP1V8S P1V8S P1V8S_DGPU
MOS PAD PAD MOS
AT1530F11U

P3V3S P3VSS_DGPU
MOS MOS

1.5V VRP1V5 P1V5 P1V5S P1V5S_DGPU


PAD PAD MOS MOS
C TPS51216RUKR C

1.05V VRP1V05S_VCCP P1V05S_CPU P1V05S_PCH


PAD PAD PAD
TPS51219RTER

P1V0S_DGPU
MOS

B B
VCORE PVCORE
PAD
TPS51650RSLR

AXG PVAXG
PAD
TPS51601DRBR

A A
VCORE_DGPU VRPVCORE_DGPU PVCORE_DGPU
PAD
RT8208BGQW

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER PROCEDURE
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 4 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PVADPTR
OUT VADPBL
L6015
Q6010 NFE31PT222Z1E9L
1 JACK6015 2
1 S D 8 1 2 1 2
3 4

1
2 7

2_5%_6
3 4

1000PF_50V_2

1000PF_50V_2
CSC0402_DY

CSC0402_DY
5 6

R6015
3 6 5 6

1
AC_LED# 7 8 CHG_LED#

1
4 5

2
4

3
5 ACDRV IN G 35 IN 7 8 IN 35

C6018

C6016
C6017

C6015
NMOS_4D3S
ACES_59012_0080N_002_8P
AON7410

2
P3V3AL TMP110825002

1
2

1K_1%_2
1UF_25V_3
1

3
D

R6048
C6033
D6017
SEM_SM24_SOT23_3P_DY
D
D6015

2
C6031

2
1 1 2 2 35
2200PF_50V_2 OUT ADP_ID

0.0015UF_50V_2
Q6012

1
2 1 1SS355VMTE_17
PVPACK AON7410

12K_1%_2
R6047
C6048
1 8
0.1UF_25V_2

S D
1

2 7
1M_5%_2

3 6
R6017
C6019

2
4 5

2
5 BATDRV IN G
NMOS_4D3S

2 1 PVBAT
2

C6032
0.01UF_50V_2
1 S D 8 1 2
2 7 3 4
3 6 R6000
5 4 5 0.01_1%_6
ACDRV OUT G
NMOS_4D3S

POWERPAD_2_0610
Q6011 1 2 PVADPTR PVBAT

1
AON7410
C C6028 C

PAD6015
1
0.1UF_16V_2

4.3K_5%_2
1

1
4.3K_5%_2

2
CSC0402_DY
1UF_25V_3

VRPVADPTR_CSN
VRPVADPTR_CSP
R6018

1
2
R6028

C6029
D6049

C6030

2
BAT54CW
2

2
1 2
A1 A2 IN PVBAT_CHG

2
1

4.7UF_25V_5
CSC0805_DY

10UF_25V_5
5
6
7
8

1
3

Q6000
AON7410

C6000

C6001

C6002
NMOS_4D3S
1

20_5%_5
R6027
P3V3AL

2
1
5
4
3
2
TI_BQ24728_QFN_20P

S
2
C6027

ACPRES
ACDRV
CMSRC
ACP
ACN
0.047UF_25V_3 PVPACK

4
3
2
1
P1V5S PVADPTR
10K_5%_2
1

TML 21 2 1
B VRPVPACK_HG L6000 R6001 B
R6024
300K_1%_2

6 ACDET ETQP3W4R7WFN 0.01_1%_6


1

VCC 20
7 IOUT U6000 19 VRPVPACK_PH 1 2 1 2
R6021

PHASE
8 SDA
2

HIDRV 18 3 4

B0530W_7_DY
9

RSC_0603_DY
PVADPTR SCL

CSC0805_DY

1
10UF_25V_5

10UF_25V_5
BTST 17 1 2 1 2

1
10 ILIM
REGN 16
BATDRV

R7600
35 ADP_PRES OUT R6026 C6026
LODRV

C6010

C6011

C6012
2

D6019
RSC_0402_DY

2.2_5%_2 0.047UF_16V_2
GND
SRN
SRP

D6018

5
6
7
8
1
R6029

1
2 2 1 1

Q6001
AON7410
1UF_10V_2

D
2 1

2
1 2
12
13
14
15

NMOS_4D3S
11

C6025

2
2

1SS355VMTE_17 C6023
D6016
1

0.1UF_16V_2
47K_1%_2

CSC0402_DY
1
BAT54WS

0.1UF_25V_2
CSC0402_DY
R6049

1
2

35 I_ADP OUT

C7600
OUT AC_OK 35

C6021
C6024
4
3
2
1
100PF_50V_2
1
2

VRPVPACK_LG
C6046
RSC_0402_DY

2
CSC0402_DY
1

2
P3V3A
1
R6030

C6022

100K_1%_2
1

R6025
2

A VRPVPACK_CSP A
R6023

10_5%_2
2

1 2

35 6 BATT_DAT BI
ACDET>0.6V = SMBUS OK
2

VRPVPACK_CSN
ACDET>1.8V = ADP_PRES HI 1 2
35 6 BATT_CLK BI
ACDET>2.4V = AC_OK TO CHARGE R6020
36.5_1%_2
CSC0402_DY
1

6.98_1%_2
ACDET>3.15V = AC_OVP
R6046

INVENTEC
C6047

1 2 5
OUT BATDRV
R6043
4.3K_5%_2
2

TITLE
MODEL,PROJECT,FUNCTION
CHARGER
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 5 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3AL
PVPACK
D
D

PHP_PESD5V0S1BB_SOD523_2P

PHP_PESD5V0S1BB_SOD523_2P

PHP_PESD5V0S1BB_SOD523_2P
1

1
2.2K_5%_2

2.2K_5%_2
1

100PF_50V_2

100PF_50V_2

100PF_50V_2
1

1
R6052

R6050

1
D7504

D7505

D7506
C7500

C7501

C7502
2

2
2

2
2

2
CN6050
R6051 1 1
100_5%_2 2 2
35 5 1 2 3
BATT_DAT BI 3
1 2 4
35 5 BI 4
C BATT_CLK 5 5 C
R6053 1 2 6 G1
6 G
100_5%_2 7 7 G G2
R6057 8
P3V3AL 100_5%_2
8

0.1UF_25V_2
2
FOX_BP02083_B84B5_9H_8P

C6050
P3V3AL
2

1
3 3 3

100K_5%_2
1
BAV99W_7_F

BAV99W_7_F

BAV99W_7_F
D7500

D7502
D7501

R6058
1

2
B B
OUT BATT_IN# 35

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SELETOR
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 6 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PVBAT
EN_3V IN IN EN_5V

POWERPAD_2_0610
1

73.2K_1%_2

61.9K_1%_2
1

1
PAD6110

R6110

R6160
1
2

2
D

2
D

VBATP OUT
7 IN 2VREF

TON=3.3V:300KHZ/375KHZ

5V_PG OUT VRP5V0A_PH OUT 7


14

IN VBATP 7

10UF_25V_5
4.7UF_25V_5

4.7UF_25V_5
0.22UF_6.3V_2

1
10UF_25V_5
1

C6123

C6160

C6161
C6110

C6111

8
7
6
5

5
6
7
8
Q6100

Q6150
AON7410

AON7410
D

D
C C

2
25

NMOS_4D3S
NMOS_4D3S

1
6
5
4
3
2

2
2

TML

TRIP2
VFB2
TONSEL
VREF
VFB1
TRIP1

S
G
S

OCP=8AMP C6115 R6114 7 24 R6155 C6155


VO2 VO1
0.1UF_16V_2 2.2_5%_3 8 23 2.2_5%_3 0.1UF_16V_2 OCP=8AMP
2
3
4

4
3
2
1

1
VREG3 PGOOD
1 2 1 2 9 VBST2 VBST1 22 1 2 1 2
VRP3V3A L6100 10 DRVH2 DRVH1 21 L6150 VRP5V0A
14 OUT 1 2 VRP3V3A_HG 11 LL2 LL1 20 VRP5V0A_HG 1 2
OUT 14
ETQP3W3R3WFN
VRP3V3A_PH 12 DRVL2 DRVL1 19 VRP5V0A_PH ETQP3W3R3WFN
VRP3V3A_LG

15.4K_1%_2
SKIPSEL

RSC_0603_DY
5
6
7
8
8
7
6
5

VREG5
RSC_0603_DY
6.8K_1%_2
1

1
GND
1

ENC
EN0

VIN

Q6151
D
AON7702A

AON7702A
R6100

R6150
D

R7615
Q6101

U6100
R7610

TI_TPS51123RGER_QFN_24P
330UF_6.3V

13
14
15
16
17
18
1
2

2
150UF_6.3V
C6100

1
2
+

S
G
S

C6150
+
1

4
3
2
1
10K_1%_2

2
3
4
1
CSC0402_DY

CSC0402_DY
B B
2

1
R6101

10K_1%_2
C7610

2
14 VRP3V3A_LDO OUT OUT VRP5V0A_LDO 14

R6151
C7615
2

330K_5%_2_DY

2
10UF_6.3V_3
1UF_6.3V_2
1

1
VO=((15.4K/10K)+1)*2

1UF_25V_3
C6121

R6113

C6120
C6122
VO=((6.8K/10K)+1)*2
2

2
IN VRP5V0A_LG 14

SKIP:OOA=3.3V; PWM=2VREF; AUTO=GND


14 SKIP_3V_5V IN
A A

14 EN_3V_5V IN

14 VRP5V0A_VIN IN

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P3V3A / P5V0A
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 7 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PVBAT

POWERPAD_2_0610
2

PAD6210
2
P5V0A
D

1
D

1
P0V75S

2.2UF_6.3V_3
1

10UF_25V_5
4.7UF_25V_5
1

1
C6216

5
6
7
8

C6211

C6210
Q6200
FDMC8884

D
NMOS_4D3S
2

2
R6215 C6215
U6200

S
2.2_5%_3 0.1UF_16V_2
12 V5IN VBST 15 1 2 1 2 OCP=16AMP

4
3
2
1
DRVH 14
VRP1V5_HG L6200
15 17 13 1 2 14
EN_P0V75 IN S3 SW OUT VRP1V5
VRP1V5_PH

CSC0402_DY RSC_0603_DY
ETQP3W1R0WFN
C 16 C

2
15 EN_P1V5 IN S5

330UF_2V_9MR_PANA_-35%
POWERPAD1X1M
VRP1V5_LG

2
5
6
7
8

R7620
DRVL 11
R6200

FDMS0310AS

PAD6220
Q6201
D
1 2 6 10

2
DDR3L_SEL IN VREF PGND

1
10K_1%_2

1
20

1
PGOOD

C6200
1

+
VDDQSNS 9

1
G

C7620
8 REFIN VLDOIN 2

4
3
2
1

2
VTT 3

2
VTTSNS 1

7 GND
0.01UF_50V_2

P0V75M_VREF
52.3K_1%_2

0.1UF_16V_2
1

1
2

19 MODE VTTGND 4
R6201

C6217

C6218

18 TRIP VTTREF 5

TML 21
B B
2

2
1

OUT P1V5_PG 15

10UF_6.3V_3

0.22UF_6.3V_2
100K_5%_2
1

2
75K_1%_2

1
TI_TPS51216RUKR_QFN_20P C6220
R6203

R6202

C6221
2

VOUT=REFIN=1.8*(52.3K/(10K+52.3K))
MODE=100KOHM:TRACKING DISCHARGE

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P1V5
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 8 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
D

PVBAT

POWERPAD_2_0610
15 EN_P1V0_VCCP IN

2
100K_5%_2
1

PAD6310
2
R6303

1
2

1
MODE=100KOHM/300KHZ

CSC0805_DY
10UF_25V_5

4.7UF_25V_5
15 VCCIO_PG OUT

1
R6315 C6315

5
6
7
8

C6310

C6311

C6312
2.2_5%_3 0.1UF_16V_2
1 2 1 2
P3V3A

Q6300
FDMC8884

D
17

16

15

14

13
C C

NMOS_4D3S
R6306
10K_5%_2

2
U6300
1 2

PWPD

PGOOD

EN

BST
MODE

S
1 VREF SW 12 VRP1V05S_VCCP_PH
OCP=17AMP

4
3
2
1
1 R6307 2 2 11 VRP1V05S_VCCP_HG
2.2UF_10V_3

21 VCCIO_SEL IN REFIN DH
CHOKE_4PIN_2PIN
1

0_5%_2 3 10 VRP1V05S_VCCP_LG
20 VSS_SENSE_VCCIO IN GSNS DL L6300
C6308

1 2 14 55
1 2 OUT VRP1V05S_VCCP
4 9 3 4

RSC_0603_DY
20 VCC_SENSE_VCCIO IN VSNS V5 3 4

2
COMP

PGND
TRIP

GND

5
6
7
8
2

CYN_PCMB063T_R68MS_4P

R7630
FDMS0310AS
P5V0A

Q6301
D
TI_TPS51219RTER_QFN_16P 5

22UF_6.3V_5

560UF_2.5V
1

1
2 1

2.2UF_6.3V_3

C6300

C6301
G
60.4K_1%_2

CSC0402_DY

+
1
2

1
C6319
R6302

C6316
B 0.01UF_50V_2 B

4
3
2
1

C7630

2
2
1

2
VOUT=1.05V@REFIN=3.3V; VOUT=1.0V@REFIN=GND

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P1V05S_VCCP
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 9 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
D

P3V3A

P3V3A

10UF_6.3V_3
1
U6970

C6971
GMT_AT1530F11U_SOP8_8P
OCP=4.5AMP
C TML 9 C
L6970
1

10_5%_2

8 7 1 2

2
VIN LX OUT VRP1V8S 14
R6970

VRP1V8S_PH
PAN_ELL5PR2R2N

CSC0402_DY
1

13K_1%_2

22UF_6.3V_5
2

R6973

C6974

C6970
1 VCC FB 4 VOUT=((13K+10K)+1)*0.8

2
15 5 2
EN_P1V8 IN EN REF
0.1UF_16V_2
1

1
0.1UF_16V_2
PGND

10K_1%_2
GND
C6972

C6973

R6972
2

2
B B

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P1V8S
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 10 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
D

3300PF_50V_2
1

1
C6522

C6520
0.01UF_50V_2

0.22UF_6.3V_2
1

2
C6521

5.11K_1%_2
1
R6520
2
IN VCCSA_SENSE 21

2
1 2

R6521

1
2
3
4
5
6
RSC_0402_DY OCP=7AMP

COMP

MODE
GND

SLEW
VOUT
VREF
C 25 TML
VRPVSA_PH L6500 C
14 11 24 7 1 2 14
VRPVCCSA_IN IN VIN SW 1 2 OUT VRPVSA
23 VIN SW 8 3 3 4 4
22UF_6.3V_5
1

22 9
0.1UF_16V_2

VIN U6500 SW
1

21 10 CYN_PCMB063T_R33MS_4P
PGND SW
C6511

C6510

20 PGND SW 11

1
19 PGND BST 12 1 2

V5FILT
C6500 C6501 C6502 C6503

PGOOD
V5DRV
C6515

VID0
VID1
2

0.1UF_16V_2 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5 22UF_6.3V_5_DY


2

EN

2
TI_TPS51461RGER_QFN_24P
18
17
16
15
14
13
R6502
1 0_5%_22
14 11 VRPVCCSA_IN IN IN EN_PVCCSA 15

R6524
0_5%_2
B 1 2
IN VCCSA_VID0 21 B
1
10K_5%_2
1UF_6.3V_2

1UF_6.3V_2
1

R6522
C6523

C6524

2
2

R6525
0_5%_2
1 2 21
IN VCCSA_VID1
1
10K_5%_2
R6523

OUT PVCCSA_PG 15

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
VCCSA
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 11 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
R6620 R6622
43K_1%_2 39K_1%_2 PVBAT PAD6610
12 VREF_CPU 1 2 1 2
IN POWERPAD_2_0610
PVBAT_CPU
2+1 2+0 1 1 2
2
OUT 12
R6621 R6623

CSC0805_DY

CSC0805_DY
10UF_25V_5

10UF_25V_5

10UF_25V_5

10UF_25V_5
R6626 3.3K DNP

1
90.9K_1%_2 24K_1%_2

1
1 2 1 2

C6610

C6611

C6612

C6613

C6614

C6615
R6627 56K DNP

+
C6699
68UF_25V
R6711 200K DNP P3V3A

IN
IN

2
2
R6712 30K DNP

0.1UF_16V_2_DY
R6635

100K_1%_NTC
0_5%_2
R6714 DNP 0 VREF_CPU

1
12 1 2 1 2
IN

1
R6716 DNP 0 OUT CPU_CSN1

C6631
C6632 R6636 12

R6618
100PF_50V_2 0_5%_2
D R6719 DNP 0 1 2 1 2
PVBAT_CPU 12 CPU_CSP1 1 2
IN 12 OUT D

2
R6625 R6619

20
20
R6723 DNP 0

12

12

12

2
C6623

12
8.45K_1%_2 15.4K_1%_2 VREF_CPU

5
6
7
8
0.033UF_16V_2

3.3K_1%_2
1
1 2 12
IN
1 2

IN
IN

IN
IN
IN
IN

Q6610
FDMS7692

D
R6626

NMOS_4D3S
CPU_CSN3

CPU_CSP3
P5V0A R6605
V5DRV_CPU 162K_1%_2

12 VSSSENSE

11 VCCSENSE

CPU_CSN2
CPU_CSP2

CPU_CSP1
1 2 12

CPU_CSN1
OUT 1 2 1 2 1 2

1
2.2UF_10V_3
R6617

G
VREF_CPU

S
4.7UF_10V_3
12 OUT R6602 R6603 R6604

C6630
10_5%_3

C6629
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2 PVCORE

10
1

1
2.2UF_6.3V_3

4
3
2
1
56K_1%_2

1
3 4

2
C6634

R6627
1 2

1
L6610

CGFB

CVFB

CCOMP

CCSN3

CCSP3

CCSP2

CCSN2

CCSN1

CCSP1

CF-IMAX

COCP-R

CTHERM

5
6
7
8
PAN_ETQP4LR36ZFC_4P
2

R7661

FDMS0306AS
49 P5V0A

Q6611
GND

D
RSC_0603_DY
P3V3A 13 GOCP-R V5 48

470UF_2V

470UF_2V
1
VREF_CPU

C6600

1
14 47

C6601
IN 12 VREF CDH1

1
R6601 C6622

+
S
C 15 46 1 2 1 2 C

+
V3R3 CBST1
C7661
1

2.2_5%_3 0.1UF_16V_2 CSC0402_DY


2.2UF_6.3V_3

4
3
2
1
12 VR_ON 16 45
IN VR_ON CSW1
C6633

3
PVCORE_PG 17 44

2
28 12 OUT CPGOOD U6600 CDL1
0_5%_2_DY
200K_1%_2
1

VR_SVID_CLK 18 43 V5DRV_CPU
2

20 12 IN VCLK V5DRV IN 12
R6711

R6628

20 VR_SVID_ALERT# 19 42
OUT ALERT# PGND

VR_SVID_DATA
12 OUT CPU_CSN2
20 41
2

20 12 BI VDIO TI_TPS51650RSLR_QFN_48P CDL2

PVBAT_CPU 12 1 2
OUT CPU_PROCHOT# 21 VR_HOT# CSW2 40 IN
R6606 C6624 C6625
22 SLEW CBST2 39 1 2 1 2 0.033UF_16V_2

OUT CPU_CSP2 1 2

5
6
7
8
PVAXG_PG 23 38 2.2_5%_3 0.1UF_16V_2 12
12 OUT GPGOOD CDH2
R6610

Q6620
FDMS7692

D
24 37 1 2 162K_1%_2

NMOS_4D3S
GF_IMAX VBAT

GTHERM

GPWM1
GCOMP

GPWM2

CPWM3
GSKIP#
GCSN1

GCSP1

GCSN2
GCSP2
1

GGFB

GVFB

R6629 R6616 1 2 1 2 1 2
20K_1%_2 10K_5%_3
30K_1%_2
1

R6713 R6607 R6608 R6609


PVCORE

G
B B
R6712

S
0_5%_2 17.8K_1%_2 100K_5%_NTC 28.7K_1%_2
GFX_VCC_SENSE 1 2
IN PVBAT
25

26

27

28

29

30

32

33

34

35

36
21
31

3 4
2

4
3
2
1
2 1
1 2
2

1
GPWM2
R6714
CPWM3
GPWM1

0_5%_2_DY L6620

470UF_2V
1

1
PAN_ETQP4LR36ZFC_4P

470UF_2V
C6602

C6603
R7662

5
6
7
8
R6715 P3V3A RSC_0603_DY

+
R6719

FDMS0306AS
0_5%_2

Q6621
D
GFX_VSS_SENSE 1 2 0_5%_2_DY

2
21 IN 1 2
OUT
OUT
OUT

2 1

3
1
R6721
R6716 0_5%_2
0_5%_2_DY 1 2 C7662

S
CSC0402_DY
13

4
3
2

2
1
1 2 R6731
12 VREF_CPU 1 2 1 2 VREF_CPU 12
IN IN
R6723
C6726 RSC_0402_DY
0_5%_2_DY
100PF_50V_2
1 2
GSKIP# 13
OUT
0_5%_2_DY

0_5%_2_DY

1 2
R6725
15 EN_PVCORE R6718 0_5%_2
IN
1

4.12K_1%_2
0_5%_2

0_5%_2

A A
1

R6730
1

100K_5%_2 P3V3A P1V0S_VCCP


R6630
20K_5%_2
2
R6724

R6720

R6722

R6726
2

0.1UF_16V_2
GPU_CSN1 2

GPU_CSP1 2

GPU_CSP2 2

GPU_CSN2 2

54.9_1%_2
VR_ON

1
130_1%_2
OUT 12

1
2K_5%_2

2K_5%_2
R6728

R6632

R6633

C6635
15.4K_1%_2
1

R6634

R6732
INVENTEC
VREF_CPU 12
IN
1

R6631 2 1

2
8.66K_1%_2
2

2
C6727 R6729
0.1UF_16V_2_DY 100K_1%_NTC 28 12 PVCORE_PG 20 12 VR_SVID_CLK TITLE
OUT IN
2

MODEL,PROJECT,FUNCTION
IN
IN
IN
IN
2

VCORE1
2

12 OUT PVAXG_PG 20 12 BI VR_SVID_DATA


SIZE CODE
DOC.NUMBER REV
1310xxxxx-0-0 X01
A3 CS
R6638
13

13

CHANGE by XXX DATE 21-OCT-2002 SHEET 12 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
D

12 GPU_CSN1
OUT

PVBAT_AXG
13 1 2
IN
C6722
0.033UF_16V_2

5
6
7
8
GPU_CSP1 1 2

Q6710
OUT

FDMS7692

D
12

NMOS_4D3S
R6705
162K_1%_2
R6701 C6720 PVBAT
C 1 2 1 2
1 2 1 2 1 2 PVAXG C

1
S
2.2_5%_3 0.1UF_16V_2
R6702 R6703 R6704
17.8K_1%_2 100K_5%_NTC 28.7K_1%_2

4
3
2
U6710

1
PAD 9 PAD6710
12 GSKIP#
IN POWERPAD_2_0610
1 8

2
BST DRVH 3 3 4 4
2 SKIP# SW 7 1 1 2 2
GPWM1

1
12 3 6
IN PWM VDD
PVBAT_AXG

2
4 5 L6710 OUT 13
5
6
7
8
GND DRVL
PAN_ETQP4LR24AFM_4P

10UF_25V_5

10UF_25V_5
R7671
FDMS0306AS

1
Q6711
P5V0A
D
TI_TPS51601DRBR_SON_8P RSC_0603_DY
C6700

C6710

C6711
+
470UF_2V

1 2
1UF_6.3V_2
1
C6721

2
G

C7671
CSC0402_DY
4
3
2
1
2

B B

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
VCORE2
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 13 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

OCP=7AMP
P3V3AL
P3V3A R6999 VRP5V0A_LG 7
IN
7 IN 5V_PG 1 2
PAD6100 VRP3V3A
2 1 7
2 1 IN 100K_5%_2_DY
POWERPAD_2_0610 PVBAT
PVADPTR 2 1 2 1
OCP=7AMP
D6999 C6998 C6997
D P5V0A 0.1UF_25V_2 0.1UF_25V_2
PVADPTR 1 2 PVBAT
P15V0A D

3
PAD6150
2 1 7 14 BAV70W_7_F
2 1 IN VRP5V0A 2 1 2 1
IN 7 14
VRP5V0A

3
POWERPAD_2_0610 VRP5V0A_VIN OUT 7
D6998 D6997
BAV99W_7_F BAV99W_7_F

1
0.1UF_25V_2

0.1UF_25V_2

0.1UF_25V_2
C6996

C6995

C6994
P3V3AL
35 IN ALWAYS_PW_EN 1 2 EN_3V_5V OUT 7
PAD6103 VRP3V3A_LDO R6997

0.1UF_25V_2

2
200K_5%_2
2 1 7 1K_5%_5
2 1 IN

R6998

C6999
POWERPAD1X1M

2
P5V0AL

VRP5V0A_LDO
PAD6105
C 2 1 7
C
2 1 IN
POWERPAD1X1M
CORE_PWEN R6996 SKIP_3V_5V
35 21 15 1 2 7
IN OUT
SHORT_0402
OCP=12AMP
P1V5

PAD6200 VRP1V5
2 1 8
2 1 IN
POWERPAD_2_0610
P5V0A

OCP=19AMP PAD6510 VRPVCCSA_IN


PVCORE_DGPU 1 2 11
1 2 OUT
POWERPAD1X1M
VRPVCORE_DGPU
PAD6750
B 2 2 1
1
IN 56 B
POWERPAD_2_0610

OCP=12AMP OCP=8AMP
P1V05S_PCH P1V05S_CPU

PAD6301 PAD6300 VRP1V05S_VCCP


2 1 2 1 9 55
2 1 2 1 IN
POWERPAD_2_0610 POWERPAD_2_0610

OCP=4.5AMP
P1V8S

PAD6970
2 1 10
2 1 IN VRP1V8S
A POWERPAD_2_0610 A

OCP=7AMP
PVSA

2
PAD6500
2

POWERPAD_2_0610
1
1
IN VRPVSA 11
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
POWER PORT
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 14 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3S
P3V3A P3V3S
2.665A

10K_5%_2
P15V0A Q567

R1067
1 D S 4
2

10uF_6.3V_3
5

1
1
6 3

2
1M_5%_2
G

C1014
NMOS_4D1S
R1070
P1V5_PG

R1053
FDC655BN 8 1 2
IN
100_5%_2

2
2
R7004
D P15V0A_RC 1 2 R1068
11 IN PVCCSA_PG
1 2 ALL_PWGD_IN OUT 17 35 D

2200pF_50V_2
3
0_5%_2

1000PF_50V_2
Q561 100_5%_2

1
CORE_PWEN# 1

C999
35 17 15 IN G

C1013
R1069
P5V0A P5V0S VCCIO_PG 1
S
15 9 2
IN
SSM3K7002FU

2
3.135A 100_5%_2
2

2
Q558
1 D S 4
2

10uF_6.3V_3
5

1
6 G 3

C1012
NMOS_4D1S
R703
P3V3S FDC655BN RESUME_PWEN
1 2 EN_P1V5
35 IN OUT 8

CSC0402_DY
100K_5%_2

1
RSC_0603_DY

R7005

2
1

1 2

C681
R1071

0_5%_2

2
C C
32

Q559 P1V5S
P1V5
R950
D

1 G 5.647A 35 21 15 14 IN CORE_PWEN 1 2 EN_P1V8


OUT 10

1
S

0.01uF_50V_2
Q560 10K_5%_2
8 1

2
SSM3K7002FU_DY D S

C868
7 2
2

D7000
6 3

NC
5 G 4 3 1

2
10uF_6.3V_3
NMOS_4D3S

1
AON7410

C998
DIODE-BAT54-TAP-PHP
R7006
P5V0S 1 2 R842
35 21 15 14 CORE_PWEN 1 2 EN_P0V75 8
IN OUT P3V3S
RSC_0603_DY

2
0_5%_2
1

100K_5%_2

0.1uF_16V_2
1

10K_5%_2
R1066

C843

R7017
32

B B

2
R7016
Q566 15 9 IN VCCIO_PG 1 2 EN_PVCCSA
OUT 11
D

1 G 0_5%_2
S

SSM3K7002FU_DY
EN_P1V0_VCCP => 1.05V
R657
2

35 21 15 14 CORE_PWEN 1 2 EN_P1V0_VCCP
IN OUT 9
R7021
10K_5%_2 35 CPU_PWEN 1 2 EN_PVCORE 12
IN OUT

0.01uF_50V_2
1
0_5%_2

C662
P1V5S P0V75S

2
220_5%_2
1

22_5%_2
R1073

R841
32

32

Q568 Q545
A A
D

1 G 35 17 15 CORE_PWEN#1 G
IN
S

SSM3K7002FU SSM3K7002FU
2

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
P5V0S & P3V3S
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 15 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3AL RTC_32K_IN OUT 26

P3V3A
L1 GPU_27M_IN OUT 49
D 1 2
BLM15AG121SN1D_500MA C185 0.1UF_16V_2 D
C182 2 1 PCH_25M_IN OUT 27
2 1 GREEN_CLK_25M_OUT
P3V3_RTC LAN_25M_IN OUT 41
0.1UF_16V_2 C186 2.2UF_6.3V_2
16 U9 2 1
P1V05S_PCH

XTAL_OUT
GREEN_CLK_25M_IN 1 XTAL_IN V3.3A 15
P3V3S_DGPU
C183 2 VDD VOUT 14 C188 0.1UF_16V_2
2 1 3 VDDIO_25M_B GND 13 2 1
4 GND NC 12 GPU_27M_IN TYPICAL RTC_32K_IN TRACE <= 6
0.1UF_16V_2 PCH_25M_IN 5 11
25M_B NC
MAX. LENGTH <= 24

VDDIO_25M_A
LAN_25M_IN 6 25M_A VBAT 10 VBAT IN 26
7 GND 32k 9 RTC_32K_IN
P3V3A_LAN 17 TYPICAL GPU_27M_IN TRACE <= 8

22UF_6.3V_5
GND

C184
8 MAX. LENGTH <= 12

2
2 1
TYPICAL LAN_25M_IN TRACE <= 8

C187
0.1UF_16V_2 VS_SLG3NB250V_TQFN_16P
6019B0934701 MAX. LENGTH <= 12

1
C TYPICAL LAN_25M_IN TRACE <= 8 C
(SLG3NB300V SUPPORT 27MHZ) MAX. LENGTH <= 12

R1
1M_5%_2
1 2 IF USE U9 ( SLG3NB250V )

B X2 MOUNT OPEN (PAGE26) OPEN (PAGE41) B


GREEN_CLK_25M_IN 1 3 GREEN_CLK_25M_OUT
X2 D4400 X400
4 2
R1 X501 C402
27pF_50V_2

L1 R958 C403
1

1
27pF_50V_2
C180

C180 C874
C181

25MHz
6018B0044501
C181 C875
C182
2

C183 OPEN (PAGE27) OPEN (PAGE49)


C184 X503 X1
C185 R1041 R29
C186 C962 C35
C187 C965 C36
R906 (PAGE26)
R912 (PAGE27)
R414 (PAGE41)
R120 (PAGE49)
A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
GREEN CLK SLG3NB250
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 16 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P1V8S
6026B0154901_CHIEFRIVER

1
1K_5%_2_DY

2.2K_5%_2
CN510

R4500

R683

CLOCKS
MISC
A28 CLK_DMI_PCH_R_DP 1 2 0_5%_2 CLK_DMI_PCH_DP

2
R684 BCLK R639 IN 27
31 OUT NV_CLE 1 2 H_SNB_IVB# C26 PROC_SELECT# BCLK# A27 CLK_DMI_PCH_R_DN R638 1 2 0_5%_2 CLK_DMI_PCH_DN
IN 27

1K_5%_2TP4500
1 AN34 SKTOCC#
TP30
A16 CLK_DP_PCH_R_DP R689 1 2 0_5%_2 CLK_DP_PCH_DP 27
DPLL_REF_CLK IN
A15 CLK_DP_PCH_R_DN R690 1 2 0_5%_2 CLK_DP_PCH_DN 27
DPLL_REF_CLK# IN
D P1V05S_CPU
TP4501 1 AL33 D

THERMAL
CATERR#
TP30

62_5%_2

DDR3
H_PECI CPU_DRAMRST#

R748
35 31 AN33 R8 17
OUT PECI SM_DRAMRST# OUT

MISC
2
R750
35 IN CPU_PROCHOT# 1 2 CPU_PROCHOT#_R AL32 PROCHOT# SM_RCOMP[0] AK1 SM_RCOMP0 R737 1 2 140_1%_2
SM_RCOMP[1] A5 SM_RCOMP1 R693 1 2 25.5_1%_2
56_5%_2

47pF_50V_2
SM_RCOMP2

1
SM_RCOMP[2] A4 R694 1 2 200_1%_2

C805
31 OUT PM_THRMTRIP# AN32 THERMTRIP#

R749

2
1 2

PWR MANAGEMENT
PRDY# AP29 TP4502 1
10K_5%_2 TP30
PREQ# AP27 XDP_PREQ# TP4503 1 TP30

JTAG & BPM


TCK AR26 XDP_TCLK TP4504 1 TP30
TMS AR27 XDP_TMS TP4505 1 TP30
28 BI H_PM_SYNC AM34 PM_SYNC TRST# AP30 XDP_TRST# TP4506 1 TP30
C C
TDI AR28 XDP_TDI_R TP4507 1 TP30
TDO AP26 XDP_TDO TP4508 1 TP30
31 IN H_CPUPWRGD AP33 UNCOREPWRGOOD

R799 DBR# AL35 XDP_DBRESET#


TP4509 1 TP30
17 PM_DRAM_PWRGD_CPU
1 V8
2 PM_DRAM_PWRGD_CPU_R
IN SM_DRAMPWROK

130_1%_2 BPM#[0] AT28 TP4510 1


TP30
BPM#[1] AR29 TP4511 1
TP30
R790 BPM#[2] AR30 TP4512 1
TP30
P3V3A P1V5S 46 35 30 IN BUF_PLT_RST#1 AR33
2 BUF_PLT_RST#_CPU RESET# BPM#[3] AT30 TP4513 1
TP30
BPM#[4] AP32 TP4514 1
TP30
1.5K_1%_1/16W AR31 TP4515 1

750_1%_2
BPM#[5] TP30

1
BPM#[6] AT31 TP4516 1
TP30
BPM#[7] AR32 TP4517 1
TP30

R789
0.1uF_16V_2
200_5%_2
1

200_5%_2
1
C4502
R14115

R800

2
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
B B
2

U500
P1V5
28 PM_DRAM_PWRGD 1 5
IN ALL_PWGD_IN
B VCC
PM_DRAM_PWRGD_CPU
35 15 2 4 17
IN A Y OUT P3V3S

1K_1%_2
3
RSC_0402_DY

GND

R807
1

NXP_74AHC1G09GV_SOT753_5P XDP_DBRESET# R788 1 2 1K_5%_2


6019B0773901
R14117

R801
(OD AND GATE)

2
1 2 DIMM_DRAMRST# OUT 24 25 P1V05S_CPU

3
2

1K_5%_2
Q539
R4531 XDP_TDO R792 1 2 51_5%_2
1 2
PCH_DDR_RST 1 D
3

27 21 2 51_5%_2
G
IN XDP_TMS R1076 1
RSC_0402_DY Q575
2 51_5%_2
S

XDP_TDI_R R1074 1
D

35 15 CORE_PWEN# 1 G BSS138
IN R804 XDP_PREQ# R1075 1 2 51_5%_2_DY
CPU_DRAMRST#
2

17 1 2
IN
S

SSM3K7002FU_DY XDP_TRST# R791 1 2 51_5%_2


A 0_5%_2_DY A
0.047uF_16V_2

2 51_5%_2
2

XDP_TCLK
4.99K_1%_2

R1077 1
1

1
C809

R805
2

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU - 1
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 17 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P1V05S_CPU
CN510 6026B0154901_CHIEFRIVER
R736
PEG_ICOMPI J22 CPU_PEG_ICOMPI 1 2
PEG_ICOMPO J21
28 DMI_TX0_DN B27 H22 24.9_1%_2
IN DMI_TX1_DN
DMI_RX#[0] PEG_RCOMPO
28 B25
IN DMI_RX#[1]
28
28
IN
IN
DMI_TX2_DN
DMI_TX3_DN
A25
B24
DMI_RX#[2]
DMI_RX#[3] PEG_RX#[0] K33 PEG_RX0_C_DN
IN 48
CLOSE TO CPU

DMI
M35 PEG_RX1_C_DN 48
DMI_TX0_DP
PEG_RX#[1]
PEG_RX2_C_DN
IN
28 B28 L34 48
IN DMI_TX1_DP
DMI_RX[0] PEG_RX#[2]
PEG_RX3_C_DN
IN
28 B26 J35 48
IN DMI_TX2_DP
DMI_RX[1] PEG_RX#[3]
PEG_RX4_C_DN
IN
28 A24 J32 48
IN DMI_TX3_DP
DMI_RX[2] PEG_RX#[4]
PEG_RX5_C_DN
IN 18 IN PEG_TX0_DN C628 1 2 0.1UF_16V_2 PEG_TX0_C_DN OUT 48
28 B23 H34 48
IN DMI_RX[3] PEG_RX#[5]
PEG_RX6_C_DN
IN
D PEG_RX#[6] H31
IN 48
DMI_RX0_DN PEG_RX7_C_DN PEG_TX1_DN 1 2 PEG_TX1_C_DN

PCI EXPRESS* - GRAPHICS


28 OUT G21 DMI_TX#[0] PEG_RX#[7] G33
IN 48 18 IN C622 0.1UF_16V_2 OUT 48 D
28 DMI_RX1_DN E22 G30
OUT DMI_RX2_DN
DMI_TX#[1] PEG_RX#[8]
28 F21 F35
OUT DMI_RX3_DN
DMI_TX#[2] PEG_RX#[9]
18 IN PEG_TX2_DN C629 1 2 0.1UF_16V_2 PEG_TX2_C_DN OUT 48
28 D21 E34
OUT DMI_TX#[3] PEG_RX#[10]
PEG_RX#[11] E32
28 OUT DMI_RX0_DP G22 DMI_TX[0] PEG_RX#[12] D33 18 IN PEG_TX3_DN C623 1 2 0.1UF_16V_2 PEG_TX3_C_DN OUT 48
28 DMI_RX1_DP D22 D31
OUT DMI_RX2_DP
DMI_TX[1] PEG_RX#[13]
28 F20 B33
OUT DMI_RX3_DP
DMI_TX[2] PEG_RX#[14]
18 IN PEG_TX4_DN C626 1 2 0.1UF_16V_2 PEG_TX4_C_DN OUT 48
28 C21 C32
OUT DMI_TX[3] PEG_RX#[15]

PEG_RX[0] J33 PEG_RX0_C_DP


IN 48 18 IN PEG_TX5_DN C624 1 2 0.1UF_16V_2 PEG_TX5_C_DN OUT 48
L35 PEG_RX1_C_DP 48
PEG_RX[1] IN

Intel(R) FDI
K34 PEG_RX2_C_DP 48
PEG_RX[2] IN
28 OUT FDI_TX0_DN A21 FDI0_TX#[0] PEG_RX[3] H35 PEG_RX3_C_DP
IN 48 18 IN PEG_TX6_DN C601 1 2 0.1UF_16V_2 PEG_TX6_C_DN OUT 48
28 FDI_TX1_DN H19 H32 PEG_RX4_C_DP 48
OUT FDI_TX2_DN
FDI0_TX#[1] PEG_RX[4]
PEG_RX5_C_DP
IN
28 E19 G34 48
OUT FDI_TX3_DN
FDI0_TX#[2] PEG_RX[5]
PEG_RX6_C_DP
IN 18 IN PEG_TX7_DN C620 1 2 0.1UF_16V_2 PEG_TX7_C_DN OUT 48
28 F18 G31 48
OUT FDI_TX4_DN
FDI0_TX#[3] PEG_RX[6]
PEG_RX7_C_DP
IN
28 B21 F33 48
OUT FDI_TX5_DN
FDI1_TX#[0] PEG_RX[7] IN
28 C20 F30
OUT FDI_TX6_DN
FDI1_TX#[1] PEG_RX[8]
28 D18 E35
OUT FDI_TX7_DN
FDI1_TX#[2] PEG_RX[9]
28 E17 E33
OUT FDI1_TX#[3] PEG_RX[10]
18 IN PEG_TX0_DP C631 1 2 0.1UF_16V_2 PEG_TX0_C_DP OUT 48
PEG_RX[11] F32
PEG_RX[12] D34
C 28 FDI_TX0_DP A22 E31 18 PEG_TX1_DP C619 1 2 0.1UF_16V_2 PEG_TX1_C_DP 48
C
OUT FDI_TX1_DP
FDI0_TX[0] PEG_RX[13] IN OUT
28 G19 C33
OUT FDI_TX2_DP
FDI0_TX[1] PEG_RX[14]
28 E20 B32
OUT FDI_TX3_DP
FDI0_TX[2] PEG_RX[15]
18 IN PEG_TX2_DP C630 1 2 0.1UF_16V_2 PEG_TX2_C_DP OUT 48
28 G18
OUT FDI_TX4_DP
FDI0_TX[3]
PEG_TX0_DN
28 B20 M29 18
OUT FDI1_TX[0] PEG_TX#[0] OUT
28 OUT FDI_TX5_DP C19 FDI1_TX[1] PEG_TX#[1] M32 PEG_TX1_DN
OUT 18 18 IN PEG_TX3_DP C618 1 2 0.1UF_16V_2 PEG_TX3_C_DP OUT 48
28 FDI_TX6_DP D19 M31 PEG_TX2_DN 18
OUT FDI_TX7_DP
FDI1_TX[2] PEG_TX#[2]
PEG_TX3_DN
OUT
28 F17 L32 18
OUT FDI1_TX[3] PEG_TX#[3]
PEG_TX4_DN
OUT 18 IN PEG_TX4_DP C627 1 2 0.1UF_16V_2 PEG_TX4_C_DP OUT 48
L29 18
FDI_FSYNC0
PEG_TX#[4]
PEG_TX5_DN
OUT
28 J18 K31 18
IN FDI0_FSYNC PEG_TX#[5] OUT
28 IN FDI_FSYNC1 J17 FDI1_FSYNC PEG_TX#[6] K28 PEG_TX6_DN
OUT 18 18 IN PEG_TX5_DP C621 1 2 0.1UF_16V_2 PEG_TX5_C_DP OUT 48
J30 PEG_TX7_DN 18
FDI_INT
PEG_TX#[7] OUT
28 H20 J28
IN FDI_INT PEG_TX#[8]
PEG_TX#[9] H29 18 IN PEG_TX6_DP C625 1 2 0.1UF_16V_2 PEG_TX6_C_DP OUT 48
28 FDI_LSYNC0 J19 G27
P1V05S_CPU IN FDI_LSYNC1
FDI0_LSYNC PEG_TX#[10]
28 H17 E29
IN FDI1_LSYNC PEG_TX#[11]
18 IN PEG_TX7_DP C600 1 2 0.1UF_16V_2 PEG_TX7_C_DP OUT 48
PEG_TX#[12] F27
PEG_TX#[13] D28
R686 PEG_TX#[14] F26
1 2 CPU_EDP_COMPIO A18 eDP_COMPIO PEG_TX#[15] E25
A17 eDP_ICOMPO
24.9_1%_2 18 CPU_EDP_HPD# B16 M28 PEG_TX0_DP 18
IN eDP_HDP# PEG_TX[0]
PEG_TX1_DP
OUT
B PEG_TX[1] M33
OUT 18 B
M30 PEG_TX2_DP 18
PEG_TX[2] OUT
eDP

C15 L31 PEG_TX3_DP 18


eDP_AUX PEG_TX[3]
PEG_TX4_DP
OUT
D15 L28 18
eDP_AUX# PEG_TX[4]
PEG_TX5_DP
OUT
K30 18
PEG_TX[5]
PEG_TX6_DP
OUT
K27 18
PEG_TX[6]
PEG_TX7_DP
OUT
C17 J29 18
eDP_TX[0] PEG_TX[7] OUT
F16 eDP_TX[1] PEG_TX[8] J27
C16 eDP_TX[2] PEG_TX[9] H28
G15 eDP_TX[3] PEG_TX[10] G28
PEG_TX[11] E28
C18 eDP_TX#[0] PEG_TX[12] F28
E16 eDP_TX#[1] PEG_TX[13] D27
D16 E26
eDP_TX#[2] PEG_TX[14] P1V05S_CPU
F15 eDP_TX#[3] PEG_TX[15] D25

*BOM

1K_5%_2
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
for LVDS panel

R4533
2
A CPU_EDP_HPD# 18
A
IN

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU - 2
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 18 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CN510
CN510 AE2 M_CLK_DDR2_DP 25
6026B0154901_CHIEFRIVER
SB_CLK[0]
M_CLK_DDR2_DN
OUT
AD2 25
M_B_DQ<0>
SB_CLK#[0]
M_CKE2
OUT
6026B0154901_CHIEFRIVER 25 C9 R9 25
BI M_B_DQ<1>
SB_DQ[0] SB_CKE[0] OUT
25 A7
BI M_B_DQ<2>
SB_DQ[1]
25 D10
BI M_B_DQ<3>
SB_DQ[2]
25 C8
SA_CLK[0] AB6 M_CLK_DDR0_DP
OUT 24 BI M_B_DQ<4>
SB_DQ[3]
M_CLK_DDR3_DP
25 A9 AE1 25

DDR SYSTEM MEMORY B


SA_CLK#[0] AA6 M_CLK_DDR0_DN
OUT 24 BI SB_DQ[4] SB_CLK[1] OUT
25 M_B_DQ<5> A8 AD1 M_CLK_DDR3_DN 25
D 24 BI M_A_DQ<0> C5 SA_DQ[0] SA_CKE[0] V9 M_CKE0
OUT 24 BI M_B_DQ<6>
SB_DQ[5] SB_CLK#[1]
M_CKE3
OUT
25 D9 R10 25
24 BI M_A_DQ<1> D5 SA_DQ[1] BI M_B_DQ<7>
SB_DQ[6] SB_CKE[1] OUT D
25 D8
24 BI M_A_DQ<2> D3 SA_DQ[2] BI M_B_DQ<8>
SB_DQ[7]
25 G4
24 BI M_A_DQ<3> D2 SA_DQ[3] BI M_B_DQ<9>
SB_DQ[8]
25 F4
24 BI M_A_DQ<4> D6 SA_DQ[4] SA_CLK[1] AA5 M_CLK_DDR1_DP
OUT 24 BI M_B_DQ<10>
SB_DQ[9]
25 F1 AB2

DDR SYSTEM MEMORY A


24 BI M_A_DQ<5> C6 SA_DQ[5] SA_CLK#[1] AB5 M_CLK_DDR1_DN
OUT 24 BI M_B_DQ<11>
SB_DQ[10] RSVD_TP[11]
25 G1 AA2
24 BI M_A_DQ<6> C2 SA_DQ[6] SA_CKE[1] V10 M_CKE1
OUT 24 BI M_B_DQ<12>
SB_DQ[11] RSVD_TP[12]
25 G5 T9
24 BI M_A_DQ<7> C3 SA_DQ[7] BI M_B_DQ<13>
SB_DQ[12] RSVD_TP[13]
25 F5
24 BI M_A_DQ<8> F10 SA_DQ[8] BI M_B_DQ<14>
SB_DQ[13]
25 F2
24 BI M_A_DQ<9> F8 SA_DQ[9] BI M_B_DQ<15>
SB_DQ[14]
25 G2
24 BI M_A_DQ<10> G10 SA_DQ[10] RSVD_TP[1] AB4 BI M_B_DQ<16>
SB_DQ[15]
25 J7 AA1
24 BI M_A_DQ<11> G9 SA_DQ[11] RSVD_TP[2] AA4 BI M_B_DQ<17>
SB_DQ[16] RSVD_TP[14]
25 J8 AB1
24 BI M_A_DQ<12> F9 SA_DQ[12] RSVD_TP[3] W9 BI M_B_DQ<18>
SB_DQ[17] RSVD_TP[15]
25 K10 T10
24 BI M_A_DQ<13> F7 SA_DQ[13] BI SB_DQ[18] RSVD_TP[16]
25 M_B_DQ<19> K9
24 BI M_A_DQ<14> G8 SA_DQ[14] BI M_B_DQ<20>
SB_DQ[19]
25 J9
24 BI M_A_DQ<15> G7 SA_DQ[15] BI M_B_DQ<21>
SB_DQ[20]
25 J10
24 BI M_A_DQ<16> K4 SA_DQ[16] RSVD_TP[4] AB3 BI M_B_DQ<22>
SB_DQ[21]
M_CS#2
25 K8 AD3 25
24 BI M_A_DQ<17> K5 SA_DQ[17] RSVD_TP[5] AA3 BI M_B_DQ<23>
SB_DQ[22] SB_CS#[0]
M_CS#3
OUT
25 K7 AE3 25
24 BI M_A_DQ<18> K1 SA_DQ[18] RSVD_TP[6] W10 BI M_B_DQ<24>
SB_DQ[23] SB_CS#[1] OUT
25 M5 AD6
24 BI M_A_DQ<19> J1 SA_DQ[19] BI M_B_DQ<25>
SB_DQ[24] RSVD_TP[17]
25 N4 AE6
24 BI M_A_DQ<20> J5 SA_DQ[20] BI M_B_DQ<26>
SB_DQ[25] RSVD_TP[18]
25 N2
24 BI M_A_DQ<21> J4 SA_DQ[21] BI M_B_DQ<27>
SB_DQ[26]
25 N1
24 BI M_A_DQ<22> J2 SA_DQ[22] SA_CS#[0] AK3 M_CS#0
OUT 24 BI M_B_DQ<28>
SB_DQ[27]
25 M4
24 BI M_A_DQ<23> K2 SA_DQ[23] SA_CS#[1] AL3 M_CS#1
OUT 24 BI M_B_DQ<29>
SB_DQ[28]
M_ODT2
C 24 M_A_DQ<24> M8 AG1 25 BI N5 SB_DQ[29] SB_ODT[0] AE4
OUT 25 C
BI M_A_DQ<25>
SA_DQ[24] RSVD_TP[7]
25 BI M_B_DQ<30> M2 SB_DQ[30] SB_ODT[1] AD4 M_ODT3
OUT 25
24 N10 AH1
BI M_A_DQ<26>
SA_DQ[25] RSVD_TP[8]
25 BI M_B_DQ<31> M1 SB_DQ[31] RSVD_TP[19] AD5
24 N8
BI M_A_DQ<27>
SA_DQ[26]
25 BI M_B_DQ<32> AM5 SB_DQ[32] RSVD_TP[20] AE5
24 N7
BI M_A_DQ<28>
SA_DQ[27]
25 BI M_B_DQ<33> AM6 SB_DQ[33]
24 M10
BI M_A_DQ<29>
SA_DQ[28]
M_ODT0 25 BI M_B_DQ<34> AR3 SB_DQ[34]
24 M9 AH3 24
BI M_A_DQ<30>
SA_DQ[29] SA_ODT[0]
M_ODT1
OUT 25 BI M_B_DQ<35> AP3 SB_DQ[35]
24 N9 AG3 24
BI M_A_DQ<31>
SA_DQ[30] SA_ODT[1] OUT 25 BI M_B_DQ<36> AN3 SB_DQ[36]
24 M7 AG2
BI M_A_DQ<32>
SA_DQ[31] RSVD_TP[9]
25 BI M_B_DQ<37> AN2 SB_DQ[37] SB_DQS#[0] D7 M_B_DQS0_DN
OUT 25
24 AG6 AH2
BI M_A_DQ<33>
SA_DQ[32] RSVD_TP[10]
25 BI M_B_DQ<38> AN1 SB_DQ[38] SB_DQS#[1] F3 M_B_DQS1_DN
OUT 25
24 AG5
BI M_A_DQ<34>
SA_DQ[33]
25 BI M_B_DQ<39> AP2 SB_DQ[39] SB_DQS#[2] K6 M_B_DQS2_DN
OUT 25
24 AK6
BI M_A_DQ<35>
SA_DQ[34]
25 BI M_B_DQ<40> AP5 SB_DQ[40] SB_DQS#[3] N3 M_B_DQS3_DN
OUT 25
24 AK5
BI M_A_DQ<36>
SA_DQ[35]
25 BI M_B_DQ<41> AN9 SB_DQ[41] SB_DQS#[4] AN5 M_B_DQS4_DN
OUT 25
24 AH5
BI M_A_DQ<37>
SA_DQ[36]
M_A_DQS0_DN 25 BI M_B_DQ<42> AT5 SB_DQ[42] SB_DQS#[5] AP9 M_B_DQS5_DN
OUT 25
24 AH6 C4 24
BI M_A_DQ<38>
SA_DQ[37] SA_DQS#[0]
M_A_DQS1_DN
OUT 25 BI M_B_DQ<43> AT6 SB_DQ[43] SB_DQS#[6] AK12 M_B_DQS6_DN
OUT 25
24 AJ5 G6 24
BI M_A_DQ<39>
SA_DQ[38] SA_DQS#[1]
M_A_DQS2_DN
OUT 25 BI M_B_DQ<44> AP6 SB_DQ[44] SB_DQS#[7] AP15 M_B_DQS7_DN
OUT 25
24 AJ6 J3 24
BI M_A_DQ<40>
SA_DQ[39] SA_DQS#[2]
M_A_DQS3_DN
OUT 25 BI M_B_DQ<45> AN8 SB_DQ[45]
24 AJ8 M6 24
BI M_A_DQ<41>
SA_DQ[40] SA_DQS#[3]
M_A_DQS4_DN
OUT 25 BI M_B_DQ<46> AR6 SB_DQ[46]
24 AK8 AL6 24
BI M_A_DQ<42>
SA_DQ[41] SA_DQS#[4]
M_A_DQS5_DN
OUT 25 BI M_B_DQ<47> AR5 SB_DQ[47]
24 AJ9 AM8 24
BI M_A_DQ<43>
SA_DQ[42] SA_DQS#[5]
M_A_DQS6_DN
OUT 25 BI M_B_DQ<48> AR9 SB_DQ[48]
24 AK9 AR12 24
BI M_A_DQ<44>
SA_DQ[43] SA_DQS#[6]
M_A_DQS7_DN
OUT 25 BI M_B_DQ<49> AJ11 SB_DQ[49] SB_DQS[0] C7 M_B_DQS0_DP
OUT 25
24 AH8 AM15 24
BI M_A_DQ<45>
SA_DQ[44] SA_DQS#[7] OUT 25 BI M_B_DQ<50> AT8 SB_DQ[50] SB_DQS[1] G3 M_B_DQS1_DP
OUT 25
24 AH9
BI M_A_DQ<46>
SA_DQ[45]
25 BI M_B_DQ<51> AT9 SB_DQ[51] SB_DQS[2] J6 M_B_DQS2_DP
OUT 25
B 24 BI AL9 SA_DQ[46]
25 M_B_DQ<52> AH11 M3 M_B_DQS3_DP 25
B
24 BI M_A_DQ<47> AL8 SA_DQ[47] BI M_B_DQ<53>
SB_DQ[52] SB_DQS[3]
M_B_DQS4_DP
OUT
25 AR8 AN6 25
24 BI M_A_DQ<48> AP11 SA_DQ[48] BI M_B_DQ<54>
SB_DQ[53] SB_DQS[4]
M_B_DQS5_DP
OUT
25 AJ12 AP8 25
24 BI M_A_DQ<49> AN11 SA_DQ[49] SA_DQS[0] D4 M_A_DQS0_DP
OUT 24 BI M_B_DQ<55>
SB_DQ[54] SB_DQS[5]
M_B_DQS6_DP
OUT
25 AH12 AK11 25
24 BI M_A_DQ<50> AL12 SA_DQ[50] SA_DQS[1] F6 M_A_DQS1_DP
OUT 24 BI M_B_DQ<56>
SB_DQ[55] SB_DQS[6]
M_B_DQS7_DP
OUT
25 AT11 AP14 25
24 BI M_A_DQ<51> AM12 SA_DQ[51] SA_DQS[2] K3 M_A_DQS2_DP
OUT 24 BI M_B_DQ<57>
SB_DQ[56] SB_DQS[7] OUT
25 AN14
24 BI M_A_DQ<52> AM11 SA_DQ[52] SA_DQS[3] N6 M_A_DQS3_DP
OUT 24 BI M_B_DQ<58>
SB_DQ[57]
25 AR14
24 BI M_A_DQ<53> AL11 SA_DQ[53] SA_DQS[4] AL5 M_A_DQS4_DP
OUT 24 BI M_B_DQ<59>
SB_DQ[58]
25 AT14
24 BI M_A_DQ<54> AP12 SA_DQ[54] SA_DQS[5] AM9 M_A_DQS5_DP
OUT 24 BI M_B_DQ<60>
SB_DQ[59]
25 AT12
24 BI M_A_DQ<55> AN12 SA_DQ[55] SA_DQS[6] AR11 M_A_DQS6_DP
OUT 24 BI SB_DQ[60]
25 M_B_DQ<61> AN15 AA8 M_B_A<0> 25
24 BI M_A_DQ<56> AJ14 SA_DQ[56] SA_DQS[7] AM14 M_A_DQS7_DP
OUT 24 BI M_B_DQ<62>
SB_DQ[61] SB_MA[0]
M_B_A<1>
BI
25 AR15 T7 25
24 BI M_A_DQ<57> AH14 SA_DQ[57] BI M_B_DQ<63>
SB_DQ[62] SB_MA[1]
M_B_A<2>
BI
25 AT15 R7 25
24 BI M_A_DQ<58> AL15 SA_DQ[58] BI SB_DQ[63] SB_MA[2]
M_B_A<3>
BI
T6 25
24 BI M_A_DQ<59> AK15 SA_DQ[59]
SB_MA[3]
M_B_A<4>
BI
T2 25
24 BI M_A_DQ<60> AL14 SA_DQ[60]
SB_MA[4]
M_B_A<5>
BI
T4 25
24 BI M_A_DQ<61> AK14 SA_DQ[61] SA_MA[0] AD10 M_A_A<0>
BI 24
SB_MA[5]
M_B_A<6>
BI
T3 25
24 BI M_A_DQ<62> AJ15 SA_DQ[62] SA_MA[1] W1 M_A_A<1>
BI 24 M_B_BS0
SB_MA[6]
M_B_A<7>
BI
25 AA9 R2 25
24 BI M_A_DQ<63> AH15 SA_DQ[63] SA_MA[2] W2 M_A_A<2>
BI 24 OUT M_B_BS1
SB_BS[0] SB_MA[7]
M_B_A<8>
BI
25 AA7 T5 25
SA_MA[3] W7 M_A_A<3>
BI 24 OUT M_B_BS2
SB_BS[1] SB_MA[8]
M_B_A<9>
BI
25 R6 R3 25
SA_MA[4] V3 M_A_A<4>
BI 24 OUT SB_BS[2] SB_MA[9]
M_B_A<10>
BI
AB7 25
SA_MA[5] V2 M_A_A<5>
BI 24
SB_MA[10]
M_B_A<11>
BI
R1 25
SA_MA[6] W3 M_A_A<6>
BI 24
SB_MA[11]
M_B_A<12>
BI
T1 25
24 OUT M_A_BS0 AE10 SA_BS[0] SA_MA[7] W6 M_A_A<7>
BI 24 M_B_CAS#
SB_MA[12]
M_B_A<13>
BI
25 AA10 AB10 25
24 OUT M_A_BS1 AF10 SA_BS[1] SA_MA[8] V1 M_A_A<8>
BI 24 OUT SB_CAS# SB_MA[13] BI
25 M_B_RAS# AB8 R5 M_B_A<14> 25
A 24 OUT M_A_BS2 V6 SA_BS[2] SA_MA[9] W5 M_A_A<9>
BI 24 OUT M_B_WE#
SB_RAS# SB_MA[14]
M_B_A<15>
BI A
25 AB9 R4 25
SA_MA[10] AD8 M_A_A<10>
BI 24 OUT SB_WE# SB_MA[15] BI
V4 M_A_A<11> 24
SA_MA[11]
M_A_A<12>
BI FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
W4 24
M_A_CAS#
SA_MA[12]
M_A_A<13>
BI
24 AE8 AF8 24
OUT M_A_RAS#
SA_CAS# SA_MA[13]
M_A_A<14>
BI
24 AD9 V5 24
OUT M_A_WE#
SA_RAS# SA_MA[14]
M_A_A<15>
BI
24 AF9 V7 24
OUT SA_WE# SA_MA[15] BI

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU - 3
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 19 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P1V05S_CPU
PVCORE CN510 6026B0154901_CHIEFRIVER
IMAX = 53A VTT
AG35 VCC1
AG34
AG33
VCC2
VCC3
POWER VCCIO1
VCCIO2
AH13
AH10
22uF_6.3V_5 AG32 AG10

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5
VCC4 VCCIO3
1

1
AG31 VCC5 VCCIO4 AC10
C745

C737

C743

C744

C739

C731

C749

C728

C755

C761

C760

C758

C706

C752

C756

C754
AG30 VCC6 VCCIO5 Y10
AG29 VCC7 VCCIO6 U10
AG28 VCC8 VCCIO7 P10
AG27 VCC9 VCCIO8 L10
2

2
AG26 VCC10 VCCIO9 J14
AF35 VCC11 VCCIO10 J13
AF34 VCC12 VCCIO11 J12
AF33 VCC13 VCCIO12 J11
AF32 VCC14 VCCIO13 H14
D AF31 VCC15 VCCIO14 H12
D

PEG AND DDR

22uF_6.3V_5
1
AF30 H11

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5
VCC16 VCCIO15

1
AF29 VCC17 VCCIO16 G14

C753

C707

C759

C757
AF28 VCC18 VCCIO17 G13
AF27 VCC19 VCCIO18 G12
AF26 F14

22uF_6.3V_5

22uF_6.3V_5
VCC20 VCCIO19

1
AD35 F13

2
VCC21 VCCIO20

2
AD34 F12

C730

C736
VCC22 VCCIO21
AD33 VCC23 VCCIO22 F11
AD32 VCC24 VCCIO23 E14
AD31 VCC25 VCCIO24 E12

2
AD30 VCC26
AD29 VCC27 VCCIO25 E11
AD28 VCC28 VCCIO26 D14
AD27 VCC29 VCCIO27 D13
AD26 VCC30 VCCIO28 D12
AC35 VCC31 VCCIO29 D11
AC34 VCC32 VCCIO30 C14
AC33 C13
AC32
VCC33
VCC34
VCCIO31
VCCIO32 C12 VCCIO IMAX = 8.5A
AC31 VCC35 VCCIO33 C11
AC30 VCC36 VCCIO34 B14
AC29 VCC37 VCCIO35 B12
C AC28 VCC38 VCCIO36 A14 C
10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5
1

1
AC27 VCC39 VCCIO37 A13
AC26 VCC40 VCCIO38 A12
C725

C738

C723

C742

C727

AA35 VCC41 VCCIO39 A11


AA34 VCC42
AA33 VCC43 VCCIO40 J23
AA32
2

VCC44
AA31 VCC45
AA30 VCC46
AA29 VCC47

CORE SUPPLY
AA28 VCC48
AA27 VCC49 P1V05S_CPU
AA26 VCC50
Y35 VCC51
Y34 VCC52
Y33 VCC53
10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5
1

1
Y32

75_1%_2
130_1%_2
VCC54
Y31 VCC55
C722

C748

C729

C724

C726

R755

R753
Y30 VCC56
Y29 VCC57
Y28 VCC58
Y27
2

2
VCC59

SVID
Y26 VCC60
B V35 AJ29 H_CPU_SVIDALRT# 1 2 43_5%_2 VR_SVID_ALERT# B
VCC61 VIDALERT# R751 OUT 12
V34 AJ30 H_CPU_SVIDCLK R4538 1 2 0_5%_2 VR_SVID_CLK 12
VCC62 VIDSCLK
VR_SVID_DATA
OUT
V33 AJ28 H_CPU_SVIDDAT R4539 1 2 0_5%_2 12
VCC63 VIDSOUT OUT
V32 VCC64
V31 VCC65
V30 VCC66 PVCORE
V29 VCC67
V28 VCC68

1
V27

100_1%_2
VCC69
V26 VCC70

R734
U35 VCC71
U34 VCC72
U33 VCC73
U32

2
VCC74
VCCSENSE 12
U31 VCC75
VSSSENSE
OUT
U30 OUT 12
VCC76

100_1%_2
1
U29 VCC77
U28 VCC78

R735
U27 VCC79
U26 VCC80
R35 VCC81
R34

2
VCC82
R33 VCC83
R32 VCC84
A R31 P1V05S_CPU A
SENSE LINES

VCC85
R30 VCC86
R29 VCC87

10_1%_2
R28 VCC88 VCC_SENSE AJ35
R27 VCC89 VSS_SENSE AJ34

R691
R26 VCC90
P35 VCC91
P34 VCC92

2
P33 B10 VCC_SENSE_VCCIO 9
VCC93 VCCIO_SENSE OUT

INVENTEC
P32 A10 VSS_SENSE_VCCIO 9
VCC94 VSS_SENSE_VCCIO OUT

10_1%_2
P31 VCC95
P30 VCC96

R692
P29 VCC97
P28 VCC98 TITLE
P27 VCC99 MODEL,PROJECT,FUNCTION

2
P26 VCC100
CPU - 4
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 20 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P0V75M_VREF P0V75M_VREF_H P1V5S

CPUDDR_WR_VREF1_M CPUDDR_WR_VREF2_M PAD4500

1K_1%_2_DY
1 2

1
1 2
R4562 R4564
1 2 1 2 Q4503 R4561
POWERPAD1X1M_DY
Q4504 R4563

R4565
0_5%_2_DY 0_5%_2_DY
21 DDR_WR_VREF01 2 3 21 DDR_WR_VREF02 2 3
IN IN FOR C/R STUFF NA

1K_5%_2_DY

1K_5%_2_DY
S D S D 3 2

AM2302N
D S

2
Q4504

Q4503

AM2302N
FOR H/R NA STUFF

Q538
AM2302N

G
R4563
R4561

1K_1%_2_DY
1
1

1
PCH_DDR_RST 17 21 27 PCH_DDR_RST 17 21 27
IN IN
2

2
CORE_PWEN

R4566
35 15 14 IN

470pF_50V_2_DY
D

2
PVAXG D

C808
100_1%_2
2
PVAXG
CN510 6026B0154901_CHIEFRIVER

R756

2
IMAX = 33A
AT24 POWER AK35 GFX_VCC_SENSE

1
VAXG1 VAXG_SENSE OUT 12
AT23 AK34 GFX_VSS_SENSE 12
VAXG2 VSSAXG_SENSE OUT

SENSE

2
AT21

100_1%_2
22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5
VAXG3

LINES
1

1
AT20 VAXG4

R757
AT18
C735

C732

C746

C750

C740

C733

C741
VAXG5
C747

AT17 VAXG6
AR24 VAXG7 P0V75M_VREF_H
AR23

1
VAXG8
2

VREF
AR21 VAXG9
AR20 VAXG10
AR18 VAXG11
AR17 VAXG12
AP24 VAXG13 SM_VREF AL1
AP23 VAXG14
AP21 VAXG15
AP20 B4 DDR_WR_VREF01 21
C VAXG16 SA_DIMM_VREFDQ
DDR_WR_VREF02
OUT C
AP18 D1 21
VAXG17 SB_DIMM_VREFDQ OUT
AP17 VAXG18

0.1uF_16V_2
1
AN24 VAXG19
AN23 VAXG20

C787
AN21 VAXG21
AN20

GRAPHICS
VAXG22
AN18 VAXG23
AN17

2
VAXG24
AM24 VAXG25 VDDQ1 AF7
AM23 AF4 P1V5S

DDR3 -1.5V RAILS


VAXG26 VDDQ2
AM21 VAXG27 VDDQ3 AF1
AM20 VAXG28 VDDQ4 AC7 5A
AM18 VAXG29 VDDQ5 AC4
AM17 VAXG30 VDDQ6 AC1
AL24 VAXG31 VDDQ7 Y7
AL23 Y4
330UF_2V_9MR_PANA_-35%

VAXG32 VDDQ8
AL21 Y1

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5
VAXG33 VDDQ9

1
AL20 VAXG34 VDDQ10 U7

C765

C763

C762

C767

C766

C768
AL18 VAXG35 VDDQ11 U4
AL17 VAXG36 VDDQ12 U1
AK24 VAXG37 VDDQ13 P7
1
C807

AK23 VAXG38 VDDQ14 P4


+

2
B AK21 VAXG39 VDDQ15 P1 B
AK20 VAXG40
2

AK18 VAXG41
AK17 VAXG42
AJ24 VAXG43
AJ23 VAXG44
AJ21 VAXG45
AJ20 VAXG46
AJ18 VAXG47 PVSA
AJ17 VAXG48
SA RAIL

AH24 VAXG49
AH23 VAXG50 SYSTEM AGENT IMAX = 6A
AH21 VAXG51 VCCSA1 M27
AH20 VAXG52 VCCSA2 M26
AH18 L26

10uF_6.3V_5

10uF_6.3V_5

10uF_6.3V_5
VAXG53 VCCSA3

1
AH17 VAXG54 VCCSA4 J26

C7051

C7041
J25

C721
VCCSA5
VCCSA6 J24
VCCSA7 H26
VCCSA8 H25

2
P1V8S IMAX = 1.2A
1.8V RAIL

A A
MISC

B6 H23 VCCSA_SENSE 11
VCCPLL1 VCCSA_SENSE OUT
A6 VCCPLL2
A2
10uF_6.3V_5

22uF_6.3V_5

VCCPLL3
1uF_6.3V_2

1uF_6.3V_2
1

VCCSA_VID0
C711

C710

C709

C708

C22 11
VCCSA_VID[0]
VCCSA_VID1
OUT
C24 11
VCCSA_VID[1]
VCCIO_SEL
OUT
A19 9
VCCIO_SEL OUT
2

FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CPU - 5
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 21 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CN510 6026B0154901_CHIEFRIVER
CN510 6026B0154901_CHIEFRIVER
CN510 6026B0154901_CHIEFRIVER
RSVD28 L7
T35 VSS161 VSS234 F22 AT35 VSS1 VSS81 AJ22
RSVD29 AG7
T34 VSS162 VSS235 F19 AT32 VSS2 VSS82 AJ19
1 CFG0 AK28 CFG[0] RSVD30 AE7
TP4520 T33 VSS163 VSS236 E30 AT29 VSS3 VSS83 AJ16
CFG1 AK29 CFG[1] RSVD31 AK2
T32 VSS164 VSS237 E27 AT27 VSS4 VSS84 AJ13
1 CFG2 AL26 CFG[2] RSVD32 W8
TP4521 T31 VSS165 VSS238 E24 AT25 VSS5 VSS85 AJ10
CFG3 AL27 CFG[3]
T30 VSS166 VSS239 E21 AT22 VSS6 VSS86 AJ7
1 CFG4 AK26 CFG[4]
TP4522 T29 VSS167 VSS240 E18 AT19 VSS7 VSS87 AJ4
1 CFG5 AL29 CFG[5] RSVD33 AT26
TP4523 T28 VSS168 VSS241 E15 AT16 VSS8 VSS88 AJ3
1 CFG6 AL30 CFG[6] RSVD34 AM33
TP4524 T27 VSS169 VSS242 E13 AT13 VSS9 VSS89 AJ2
1 CFG7 AM31 CFG[7] RSVD35 AJ27
TP4525 T26 VSS170 VSS243 E10 AT10 VSS10 VSS90 AJ1
CFG8 AM32 CFG[8]
P9 VSS171 VSS244 E9 AT7 VSS11 VSS91 AH35
CFG9 AM30 CFG[9] VCC_DIE_SENSE AH27
P8 VSS172 VSS245 E8 AT4 VSS12 VSS92 AH34
CFG10 AM28 CFG[10] VSS_DIE_SENSE AH26
P6 VSS173 VSS246 E7 AT3 VSS13 VSS93 AH32
CFG11 AM26 CFG[11]
P5 VSS174 VSS247 E6 AR25 VSS14 VSS94 AH30
CFG12 AN28 CFG[12]
P3 VSS175 VSS248 E5 AR22 VSS15 VSS95 AH29
D CFG13 AN31 CFG[13] RSVD37 T8
P2 VSS176 VSS249 E4 AR19 VSS16 VSS96 AH28
CFG14 AN26 CFG[14] RSVD38 J16 D
N35 VSS177 VSS250 E3 AR16 VSS17
CFG15 AM27 CFG[15] RSVD39 H16
N34 VSS178 VSS251 E2 AR13 VSS18 VSS98 AH25
CFG16 AK31 CFG[16] RSVD40 G16
N33 E1 AR10 AH22

RESERVED
VSS179 VSS252 VSS19 VSS99
CFG17 AN29 CFG[17]
N32 VSS180 VSS253 D35 AR7 VSS20 VSS100 AH19
N31 VSS181 VSS254 D32 AR4 VSS21 VSS101 AH16
N30 VSS182 VSS255 D29 AR2 VSS22 VSS102 AH7
N29 VSS183 VSS256 D26 AP34 VSS23 VSS103 AH4
RSVD_NCTF1 AR35
N28 VSS184 VSS257 D20 AP31 VSS24 VSS104 AG9
AJ31 VAXG_VAL_SENSE RSVD_NCTF2 AT34
N27 VSS185 VSS258 D17 AP28 VSS25 VSS105 AG8
AH31 VSSAXG_VAL_SENSE RSVD_NCTF3 AT33
N26 VSS186 VSS259 C34 AP25 VSS26 VSS106 AG4
AJ33 VCC_VAL_SENSE RSVD_NCTF4 AP35
M34 VSS187 VSS260 C31 AP22 VSS27 VSS107 AF6
AH33 VSS_VAL_SENSE RSVD_NCTF5 AR34
L33 VSS188 VSS261 C28 AP19 VSS28 VSS108 AF5
L30 VSS189 VSS262 C27 AP16 VSS29 VSS109 AF3
L27 VSS190 VSS263 C25 AP13 VSS30 VSS110 AF2
AJ26 RSVD5
L9 VSS191 VSS264 C23 AP10 VSS31 VSS111 AE35
L8 VSS192 VSS265 C10 AP7 VSS32 VSS112 AE34

RSVD_NCTF6 B34
A33
L6
L5
VSS193
VSS194
VSS VSS266
VSS267
C1
B22
AP4
AP1
VSS33
VSS34
VSS113
VSS114
AE33
AE32

VSS
RSVD_NCTF7
L4 VSS195 VSS268 B19 AN30 VSS35 VSS115 AE31
RSVD_NCTF8 A34
L3 VSS196 VSS269 B17 AN27 VSS36 VSS116 AE30
RSVD_NCTF9 B35
L2 VSS197 VSS270 B15 AN25 VSS37 VSS117 AE29
RSVD_NCTF10 C35
L1 VSS198 VSS271 B13 AN22 VSS38 VSS118 AE28
C F25 RSVD8
K35 VSS199 VSS272 B11 AN19 VSS39 VSS119 AE27 C
K32 VSS200 VSS273 B9 AN16 VSS40 VSS120 AE26
F24 RSVD9
K29 VSS201 VSS274 B8 AN13 VSS41 VSS121 AE9
F23 RSVD10
K26 VSS202 VSS275 B7 AN10 VSS42 VSS122 AD7
D24 RSVD11 RSVD51 AJ32
J34 VSS203 VSS276 B5 AN7 VSS43 VSS123 AC9
G25 RSVD12 RSVD52 AK32
J31 VSS204 VSS277 B3 AN4 VSS44 VSS124 AC8
G24 RSVD13
H33 VSS205 VSS278 B2 AM29 VSS45 VSS125 AC6
E23 RSVD14
H30 VSS206 VSS279 A35 AM25 VSS46 VSS126 AC5
D23 RSVD15
H27 VSS207 VSS280 A32 AM22 VSS47 VSS127 AC3
C30 RSVD16
H24 VSS208 VSS281 A29 AM19 VSS48 VSS128 AC2
A31 RSVD17
H21 VSS209 VSS282 A26 AM16 VSS49 VSS129 AB35
B30 RSVD18
H18 VSS210 VSS283 A23 AM13 VSS50 VSS130 AB34
B29 RSVD19
H15 VSS211 VSS284 A20 AM10 VSS51 VSS131 AB33
D30 RSVD20 BCLK_ITP AN35 XDP_BCLK_ITP_DP TP4518 1
TP30 H13 VSS212 VSS285 A3 AM7 VSS52 VSS132 AB32
B31 RSVD21 BCLK_ITP# AM35XDP_BCLK_ITP_DNTP4519 1
TP30 H10 VSS213 AM4 VSS53 VSS133 AB31
A30 RSVD22
H9 VSS214 AM3 VSS54 VSS134 AB30
C29 RSVD23
H8 VSS215 AM2 VSS55 VSS135 AB29
H7 VSS216 AM1 VSS56 VSS136 AB28
H6 VSS217 AL34 VSS57 VSS137 AB27
J20 RSVD24
H5 VSS218 AL31 VSS58 VSS138 AB26
B18 RSVD25 RSVD_NCTF11 AT2
H4 VSS219 AL28 VSS59 VSS139 Y9
RSVD_NCTF12 AT1
H3 VSS220 AL25 VSS60 VSS140 Y8
RSVD_NCTF13 AR1
H2 VSS221 AL22 VSS61 VSS141 Y6
B H1 VSS222 AL19 VSS62 VSS142 Y5 B
J15 RSVD27
G35 VSS223 AL16 VSS63 VSS143 Y3
G32 VSS224 AL13 VSS64 VSS144 Y2
G29 VSS225 AL10 VSS65 VSS145 W35
KEY B1
G26 VSS226 AL7 VSS66 VSS146 W34
G23 VSS227 AL4 VSS67 VSS147 W33
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER G20 AL2 W32
VSS228 VSS68 VSS148
G17 VSS229 AK33 VSS69 VSS149 W31
G11 VSS230 AK30 VSS70 VSS150 W30
F34 VSS231 AK27 VSS71 VSS151 W29
F31 VSS232 AK25 VSS72 VSS152 W28
R796 F29 AK22 W27
CFG0 1 2 VSS233
AK19
VSS73 VSS153
W26
VSS74 VSS154
1K_1%_2 FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER AK16 VSS75 VSS155 U9
AK13 VSS76 VSS156 U8
R797 AK10 U6
CFG2 1 2
AK7
VSS77 VSS157
U5
VSS78 VSS158
1K_1%_2_DY AK4 VSS79 VSS159 U3

R798
CFG[2] : PCI Express* Static x16 Lane Numbering Reversal. AJ25 VSS80 VSS160 U2
CFG4 1 2 1 = Normal operation
0 = Lane numbers reversed
1K_1%_2_DY
FOX_PZ98927_3641_41F_Huronriver_989P_CHIEFRIVER
R794
A CFG5 1 2 A
1K_1%_2 CFG[4] : eDP enable
R795
1 = Disabled
CFG6 1 2 0 = Enabled
1K_1%_2
CFG[6:5] : PCI Express Bifurcation:
00 = 1 x8, 2 x4 PCI Expres
R793 01 = reserved
CFG7 1 2 10 = 2 x8 PCI Express
11 = 1 x16 PCI Express
1K_1%_2_DY
CFG[7] :PEG DEFER TRAINING
1: (Default) PEG Train immediately following RESETB deassertion
INVENTEC
0: PEG Wait for BIOS for training TITLE
MODEL,PROJECT,FUNCTION
CPU - 6
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 22 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

FAN CONN
P3V3S P5V0S

C602
2 1

4.7K_5%_2

4.7K_5%_2
D 4.7uF_6.3V_3

1
C574 D

R598
2 1

R631
0.1uF_16V_2
CN500

2
1 1
2 2 THERMAL SENSOR(LOCAL)
35 FAN_TACH1 3 G1
OUT 3 G
35 IN CPUFAN1_ON# CSC0402_DY 4 4 G G2 NCT7717U I2C / SMBus address is 1001000xb (x is R/W bit).
1

ACES_50273_0047N_001_4P U510
50 35 THM_CLK 1 5 THM_DAT 35 50
6012A0081607 BI SCL SDA BI
C530

2 GND P3V3S
R116
THERMTRIP# 3 4 1 2
2

49 35 OUT ALERT# VDD

P3V3S NUVO_NCT7717U_SOT23_5P
22_5%_2
6019B0914301
R1018

4.7uF_6.3V_3
1 2

1
0.1uF_16V_2
2
7.5K_1%_2

C4412
C679
C C
P3V3S

2
R115

1
10K_5%_2_DY CO- LAY U2 (OPEN)
2 1
U2
1 2 1 TRIPSET0 TRIPSET1 6
2 GND VS 5
R114 3 4
OUT# HYSTSET
10K_5%_2_DY

TI_TMP302BDRLR_SOT_6P_DY
6019B0843501_DY

B B

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
THERMAL & FAN
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 23 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P1V5
P1V5
4.32A
CN511
19 M_A_A<0> 98 5 M_A_DQ<0> 19
BI M_A_A<1> 97
A0 DQ0
M_A_DQ<1>
BI CN511
19 7 19 75 44
BI M_A_A<2> 96
A1 DQ1
M_A_DQ<2>
BI VDD1 VSS16
19 15 19 76 48
BI A2 DQ2 BI VDD2 VSS17

100uF_6.3V_DY
M_A_A<3> 95 17 M_A_DQ<3> 81 49

0.1uF_16V_2

0.1uF_16V_2

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5
19 BI A3 DQ3 BI 19 VDD3 VSS18

1uF_6.3V_2

1uF_6.3V_2
1

1
19 M_A_A<4> 92 4 M_A_DQ<4> 19 82 54
BI M_A_A<5> 91
A4 DQ4
M_A_DQ<5>
BI VDD4 VSS19
6 87 55

C712

C772

C769

C770

C771

C776

C774

C775
19 BI A5 DQ5 BI 19 VDD5 VSS20

+
19 M_A_A<6> 90 16 M_A_DQ<6> 19 88 60
D BI M_A_A<7> 86
A6 DQ6
M_A_DQ<7>
BI VDD6 VSS21
19 18 19 93 61
BI M_A_A<8> 89
A7 DQ7
M_A_DQ<8>
BI VDD7 VSS22
D
19 21 19 94 65
BI A8 DQ8 BI VDD8 VSS23

2
19 M_A_A<9> 85 23 M_A_DQ<9> 19 99 66
BI M_A_A<10>
A9 DQ9
M_A_DQ<10>
BI VDD9 VSS24
19 107 33 19 100 71
BI M_A_A<11>84
A10_AP DQ10
M_A_DQ<11>
BI VDD10 VSS25
19 35 19 105 72
BI M_A_A<12>83
A11 DQ11
M_A_DQ<12>
BI VDD11 VSS26
19 22 19 106 127
BI M_A_A<13>
A12 DQ12
M_A_DQ<13>
BI VDD12 VSS27
19 119 24 19 111 128
BI M_A_A<14>80
A13 DQ13
M_A_DQ<14>
BI VDD13 VSS28
19 34 19 112 133
BI M_A_A<15>78
A14 DQ14
M_A_DQ<15>
BI VDD14 VSS29
19 36 19 117 134
BI A15 DQ15
M_A_DQ<16>
BI VDD15 VSS30
39 19 118 138
M_A_BS0
DQ16
M_A_DQ<17>
BI VDD16 VSS31
19 109 41 19 123 139
IN M_A_BS1
BA0 DQ17
M_A_DQ<18>
BI P3V3S VDD17 VSS32
19 108 51 19 124 144
IN M_A_BS2
BA1 DQ18
M_A_DQ<19>
BI VDD18 VSS33
19 79 53 19 145
IN BA2 DQ19 BI VSS34
19 M_CS#0 114 40 M_A_DQ<20> 19 199 150
IN M_CS#1
S0# DQ20
M_A_DQ<21>
BI VDDSPD VSS35
19 121 42 19 151
IN S1# DQ21 BI VSS36

2.2uF_16V_3

0.1uF_16V_2
M_CLK_DDR0_DP M_A_DQ<22>

1
19 101 50 19 77 155
IN M_CLK_DDR0_DN
CK0 DQ22
M_A_DQ<23>
BI NC1 VSS37

C4109
19 103 52 19 122 156
IN CK0# DQ23 BI NC2 VSS38

C810
19 M_CLK_DDR1_DP
102 57 M_A_DQ<24> 19 125 161
IN M_CLK_DDR1_DN
CK1 DQ24
M_A_DQ<25>
BI NCTEST VSS39
19 104 59 19 162
IN M_CKE0
CK1# DQ25
M_A_DQ<26>
BI VSS40
19 73 67 19 198 167
IN M_CKE1
CKE0 DQ26
M_A_DQ<27>
BI DIMM_DRAMRST#
EVENT# VSS41
74 69 30 168

2
19 IN CKE1 DQ27 BI 19 25 17 IN RESET# VSS42
19 M_A_CAS# 115 56 M_A_DQ<28> 19 172
IN M_A_RAS#
CAS# DQ28
M_A_DQ<29>
BI VSS43
19 110 58 19 173
IN M_A_WE#
RAS# DQ29
M_A_DQ<30>
BI VSS44
C 19 IN 113 WE# DQ30 68
BI 19 1 VREF_DQ VSS45 178 C
24 SA0_DIM0 197 70 M_A_DQ<31> 19 126 179
IN SA1_DIM0
SA0 DQ31
M_A_DQ<32>
BI VREF_CA VSS46
24 201 129 19 184
IN PCH_3S_SMCLK
SA1 DQ32
M_A_DQ<33>
BI VSS47
27 25 202 131 19 185
IN SCL DQ33 BI VSS48
27 25 PCH_3S_SMDAT
200 141 M_A_DQ<34> 19 2 189
IN SDA DQ34
M_A_DQ<35>
BI VSS1 VSS49
143 19 3 190
M_ODT0
DQ35
M_A_DQ<36>
BI P0V75S_DIMM0_VREF_DQ
VSS2 VSS50
19 116 130 19 P0V75S_DIMM0_VREF_CA 8 195
IN M_ODT1
ODT0 DQ36
M_A_DQ<37>
BI VSS3 VSS51
19 120 132 19 9 196
IN ODT1 DQ37
M_A_DQ<38>
BI VSS4 VSS52
140 19 13
DQ38
M_A_DQ<39>
BI 0.5A 0.5A VSS5
11 142 19 14
DM0 DQ39
M_A_DQ<40>
BI VSS6
P0V75S
28 147 19 19
DM1 DQ40
M_A_DQ<41>
BI VSS7
46 149 19 20
DM2 DQ41
M_A_DQ<42>
BI VSS8
63 157 19 25
DM3 DQ42 BI VSS9
1A

2.2uF_16V_3

2.2uF_16V_3
136 159 M_A_DQ<43> 26 203

0.1uF_16V_2

0.1uF_16V_2
DM4 DQ43 BI 19 VSS10 VTT1

1
153 146 M_A_DQ<44> 19 31 204
DM5 DQ44
M_A_DQ<45>
BI VSS11 VTT2
170 148 32

C664

C665

C788

C773
DM6 DQ45 BI 19 VSS12
187 158 M_A_DQ<46> 19 37 G1
DM7 DQ46
M_A_DQ<47>
BI VSS13 G1
160 19 38 G2
DQ47 BI VSS14 G2
19 M_A_DQS0_DP 12 163 M_A_DQ<48> 19 43
IN DQS0 DQ48 BI VSS15

2
19 M_A_DQS1_DP 29 165 M_A_DQ<49> 19
IN M_A_DQS2_DP 47
DQS1 DQ49
M_A_DQ<50>
BI FOX_AS0A626_J8R6_7H_204P
19 175 19
IN M_A_DQS3_DP 64
DQS2 DQ50
M_A_DQ<51>
BI
19 177 19
IN M_A_DQS4_DP137
DQS3 DQ51
M_A_DQ<52>
BI
19 164 19
B IN M_A_DQS5_DP154
DQS4 DQ52
M_A_DQ<53>
BI B
19 166 19
IN M_A_DQS6_DP171
DQS5 DQ53
M_A_DQ<54>
BI
19 174 19
IN M_A_DQS7_DP188
DQS6 DQ54
M_A_DQ<55>
BI

1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2
1

1
19 176 19
IN M_A_DQS0_DN 10
DQS7 DQ55
M_A_DQ<56>
BI
19 181 19
IN DQS#0 DQ56 BI

C833

C830

C831

C832
19 M_A_DQS1_DN 27 183 M_A_DQ<57> 19
IN M_A_DQS2_DN 45
DQS#1 DQ57
M_A_DQ<58>
BI
19 191 19
IN M_A_DQS3_DN 62
DQS#2 DQ58
M_A_DQ<59>
BI
19 193 19
IN M_A_DQS4_DN135
DQS#3 DQ59
M_A_DQ<60>
BI
180

2
19 IN DQS#4 DQ60 BI 19
19 M_A_DQS5_DN152 182 M_A_DQ<61> 19
IN DQS#5 DQ61 BI
19 M_A_DQS6_DN169 192 M_A_DQ<62> 19
IN M_A_DQS7_DN186
DQS#6 DQ62
M_A_DQ<63>
BI
19 194 19 P1V5 P1V5
IN DQS#7 DQ63 BI
FOX_AS0A626_J8R6_7H_204P
P0V75S_DIMM0_VREF_DQ
1

1
P3V3S
1K_1%_2

1K_1%_2
P0V75S_DIMM0_VREF_CA
R4104

R759
10K_5%_2_DY

10K_5%_2_DY

P0V75M_VREF
1

P0V75M_VREF
2

2
R662 R761
R840

R4102

1 2 1 2

Note : 0_5%_2_DY
0_5%_2
2

A A
1

1
1K_1%_2

1K_1%_2
SA0_DIM0
SO-DIMMA SPD Address is 0xA0 IN 24 CPUDDR_WR_VREF1_M
R660

R760
SA1_DIM0
SO-DIMMA TS Address is 0x30 IN 24
R663
1

1
10K_5%_2

10K_5%_2

1 2
2

2
R839

R838

0_5%_2
2

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
DDR3 - 1
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 24 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P1V5
CN512
19 BI M_B_A<0> 98 A0 DQ0 5 M_B_DQ<0>
BI 19 4.32A CN512
19 M_B_A<1> 97 7 M_B_DQ<1> 19
BI M_B_A<2>
A1 DQ1
M_B_DQ<7>
BI 75 VDD1 VSS16 44
19 96 15 19
BI M_B_A<3>
A2 DQ2
M_B_DQ<3>
BI 76 VDD2 VSS17 48
19 95 17 19
BI A3 DQ3 BI 81 49

0.1uF_16V_2

0.1uF_16V_2

22uF_6.3V_5

22uF_6.3V_5

22uF_6.3V_5
M_B_A<4> M_B_DQ<4> VDD3 VSS18

1uF_6.3V_2

1uF_6.3V_2
1

1
19 92 4 19
BI M_B_A<5>
A4 DQ4
M_B_DQ<5>
BI 82 VDD4 VSS19 54
19 91 6 19
BI A5 DQ5 BI 87 55

C784

C783

C778

C779

C781

C780

C782
M_B_A<6> M_B_DQ<6> VDD5 VSS20
19 90 16 19
BI M_B_A<7>
A6 DQ6
M_B_DQ<2>
BI 88 VDD6 VSS21 60
19 86 18 19
BI M_B_A<8>
A7 DQ7
M_B_DQ<8>
BI 93 VDD7 VSS22 61
19 89 21 19
BI M_B_A<9>
A8 DQ8
M_B_DQ<9>
BI 94 VDD8 VSS23 65
85 23

2
19 BI A9 DQ9 BI 19 99 66
VDD9 VSS24
D 19 M_B_A<10> 107 33 M_B_DQ<10> 19
BI M_B_A<11>
A10_AP DQ10
M_B_DQ<11>
BI 100 VDD10 VSS25 71
19 BI 84 A11 DQ11 35
BI 19 105 VDD11 VSS26 72 D
19 M_B_A<12> 83 22 M_B_DQ<12> 19
BI M_B_A<13>
A12 DQ12
M_B_DQ<13>
BI 106 VDD12 VSS27 127
19 119 24 19
BI M_B_A<14>
A13 DQ13
M_B_DQ<14>
BI 111 VDD13 VSS28 128
19 80 34 19
BI M_B_A<15>
A14 DQ14
M_B_DQ<15>
BI 112 VDD14 VSS29 133
19 78 36 19
BI A15 DQ15
M_B_DQ<16>
BI 117 VDD15 VSS30 134
39 19
M_B_BS0
DQ16
M_B_DQ<17>
BI 118 VDD16 VSS31 138
19 109 41 19
IN M_B_BS1
BA0 DQ17
M_B_DQ<18>
BI P3V3S 123 VDD17 VSS32 139
19 108 51 19
IN M_B_BS2
BA1 DQ18
M_B_DQ<19>
BI 124 VDD18 VSS33 144
19 79 53 19
IN M_CS#2
BA2 DQ19
M_B_DQ<20>
BI VSS34 145
19 114 40 19
IN M_CS#3
S0# DQ20
M_B_DQ<21>
BI 199 VDDSPD VSS35 150
19 121 42 19
IN M_CLK_DDR2_DP
S1# DQ21
M_B_DQ<22>
BI VSS36 151
101 50

0.1uF_16V_2
19 IN CK0 DQ22 BI 19

1
77 NC1 VSS37 155
19 M_CLK_DDR2_DN 103 52 M_B_DQ<23> 19
IN M_CLK_DDR3_DP
CK0# DQ23
M_B_DQ<24>
BI 122 NC2 VSS38 156

C811
19 102 57 19
IN M_CLK_DDR3_DN
CK1 DQ24
M_B_DQ<25>
BI 125 NCTEST VSS39 161
19 104 59 19
IN M_CKE2
CK1# DQ25
M_B_DQ<26>
BI VSS40 162
19 73 67 19
IN M_CKE3
CKE0 DQ26
M_B_DQ<27>
BI 198 EVENT# VSS41 167
19 74 69 19
IN CKE1 DQ27 BI DIMM_DRAMRST# 30 168

2
M_B_CAS# 115 56 M_B_DQ<28> 24 17 IN RESET# VSS42
19 IN CAS# DQ28 BI 19 172
VSS43
19 M_B_RAS# 110 58 M_B_DQ<29> 19
IN M_B_WE#
RAS# DQ29
M_B_DQ<31>
BI VSS44 173
19 113 68 19
IN SA0_DIM1
WE# DQ30
M_B_DQ<30>
BI 1 VREF_DQ VSS45 178
25 197 70 19
IN SA1_DIM1
SA0 DQ31
M_B_DQ<36>
BI 126 VREF_CA VSS46 179
25 201 129 19
IN PCH_3S_SMCLK
SA1 DQ32
M_B_DQ<37>
BI VSS47 184
27 24 202 131 19
C IN PCH_3S_SMDAT
SCL DQ33
M_B_DQ<34>
BI VSS48 185 C
27 24 200 141 19
IN SDA DQ34
M_B_DQ<35>
BI 2 VSS1 VSS49 189
143 19
M_ODT2
DQ35
M_B_DQ<32>
BI 3 VSS2 VSS50 190
19 116 130 19
IN M_ODT3
ODT0 DQ36
M_B_DQ<33>
BI 8 VSS3 VSS51 195
19 120 132 19
IN ODT1 DQ37 BI P0V75S_DIMM1_VREF_DQ P0V75S_DIMM1_VREF_CA 9 VSS4 VSS52 196
140 M_B_DQ<39> 19
DQ38 BI 13 VSS5
11 DM0 DQ39 142 M_B_DQ<38>
BI 19
0.5A 0.5A 14 VSS6
28 147 M_B_DQ<41> 19
DM1 DQ40
M_B_DQ<45>
BI 19 VSS7 P0V75S
46 149 19
DM2 DQ41 BI

2.2uF_16V_3

2.2uF_16V_3
20

0.1uF_16V_2

0.1uF_16V_2
VSS8
M_B_DQ<46>

1
63 157 19
DM3 DQ42 BI 25 VSS9
136 DM4 DQ43 159 M_B_DQ<42>
BI 19 1A

C667

C668

C777

C789
26 VSS10 VTT1 203
153 146 M_B_DQ<44> 19
DM5 DQ44
M_B_DQ<40>
BI 31 VSS11 VTT2 204
170 148 19
DM6 DQ45
M_B_DQ<43>
BI 32 VSS12
187 158 19
DM7 DQ46
M_B_DQ<47>
BI 37 VSS13 G1 G1
160

2
DQ47 BI 19 38 G2
M_B_DQS0_DP M_B_DQ<48> VSS14 G2
19 12 163 19
IN M_B_DQS1_DP
DQS0 DQ48
M_B_DQ<53>
BI 43 VSS15
19 29 165 19
IN M_B_DQS2_DP
DQS1 DQ49
M_B_DQ<54>
BI
19 47 175 19 FOX_AS0A626_U4RG_7H_204P
IN M_B_DQS3_DP
DQS2 DQ50
M_B_DQ<55>
BI
19 64 177 19
IN M_B_DQS4_DP
DQS3 DQ51
M_B_DQ<49>
BI
19 137 164 19
IN M_B_DQS5_DP
DQS4 DQ52
M_B_DQ<52>
BI
19 154 166 19
IN M_B_DQS6_DP
DQS5 DQ53
M_B_DQ<51>
BI
19 171 174 19
IN M_B_DQS7_DP
DQS6 DQ54
M_B_DQ<50>
BI
19 188 176 19
IN DQS7 DQ55 BI

1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2
1

1
B 19 M_B_DQS0_DN 10 181 M_B_DQ<58> 19 B
IN M_B_DQS1_DN
DQS#0 DQ56
M_B_DQ<61>
BI

C836

C835

C834

C837
19 27 183 19
IN M_B_DQS2_DN
DQS#1 DQ57
M_B_DQ<62>
BI
19 45 191 19
IN M_B_DQS3_DN
DQS#2 DQ58
M_B_DQ<63>
BI
19 62 193 19
IN M_B_DQS4_DN
DQS#3 DQ59
M_B_DQ<57>
BI
19 135 180 19
IN DQS#4 DQ60 BI

2
19 M_B_DQS5_DN 152 182 M_B_DQ<56> 19
IN M_B_DQS6_DN
DQS#5 DQ61
M_B_DQ<59>
BI
19 169 192 19
IN M_B_DQS7_DN
DQS#6 DQ62
M_B_DQ<60>
BI P1V5 P1V5
19 186 194 19
IN DQS#7 DQ63 BI
FOX_AS0A626_U4RG_7H_204P
P0V75S_DIMM1_VREF_DQ
1

1
P0V75S_DIMM1_VREF_CA
1K_1%_2

1K_1%_2
R642

R740
P3V3S
P0V75M_VREF P0V75M_VREF
2

2
10K_5%_2_DY

R665 R739
1

1 2 1 2
10K_5%_2
1

0_5%_2_DY
R4114

0_5%_2
R809

1
1K_1%_2

1K_1%_2
CPUDDR_WR_VREF2_M
R643

R738
Note :
2
2

SA1_DIM1 R666
IN 25
A SO-DIMMA SPD Address is 0xA4 1 2 A
2

2
SO-DIMMA TS Address is 0x34 SA0_DIM1 0_5%_2
10K_5%_2_DY

IN 25
1

10K_5%_2
R4113

R808
2

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
DDR3 - 2
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 25 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

C874
1 R910 2 2 1
P3V3AL
P3V3AL_RTC_BAT

1
1

2
20K_5%_2 18PF_50V_2_DY

1uF_6.3V_2
2
P3V3_RTC R958
1 2 X501

BAT54C_30V_0.2A

C860
32.768KHZ_DY

A2
10M_5%_2_DY 6018A0001401_DY
P3V3_RTC C875

4
3
2 1
C 3
18PF_50V_2_DY

D4400
R906
IF USE U9 R964 1 2 RTC_32K_IN IN 16
1 2
D4400 OPEN

POWERPAD2X2M
2
0_5%_2

A1
CN4400

1uF_6.3V_2
1

1
20K_5%_2

1uF_6.3V_2

PAD402
U519
D

1
1M_5%_2
XTAL32RTC_IN LPC_AD<0>

C859
A20 C38

2
R4400
1
VBAT RTCX1 FWH0/LAD0 BI 35 46

R969
D

C878
2 1 1 2 16
- + OUT FWH1/LAD1 A38 LPC_AD<1>
BI 35 46
1K_5%_2 XTAL32RTC_OUT C20 B37 LPC_AD<2>

1
RTCX2 FWH2/LAD2 BI 35 46
C37 LPC_AD<3>

2
FWH3/LAD3 BI 35 46

RTC
P3V3_RTC_RTCRST# D20

LPC
LOTES_AAA_BAT_032_K01_A_2P RTCRST#

1
D36 LPC_FRAME# 35 46 P3V3S
6026B0116301 P3V3_RTC_SRTCRST# G22
FWH4/LFRAME# OUT
SRTCRST#
LDRQ0# E36 R876
2 1
K22 INTRUDER# LDRQ1#/GPIO23 K36 1
TP30
P3V3A R898
TP4700 10K_5%_2
P5V0S 1 2 PCH_INTVRMEN C17 V5 SERIRQ 35
INTVRMEN SERIRQ BI

1K_5%_2
1
330K_5%_2

R4706
1
Q565 AM3 SATA_HDD_RX_DN 40
HDA_BITCLK R1086
SATA0RXN IN
G 44 1 2 HDA_BITCLK_PCH N34 AM1 SATA_HDD_RX_DP 40
OUT HDA_BCLK SATA0RXP IN

SATA 6G
AP7 SATA_HDD_TX_DN

2
SATA0TXN OUT 40
HDA_SYNC 1 R4704 2 HDA_SYNC_Q 2 3 33_5%_2 HDA_SYNC_PCH L34 AP5 SATA_HDD_TX_DP
44 BI S D HDA_SYNC SATA0TXP OUT 40

33_5%_2 SSM3K7002FU PCSPKR T10


1

AM10
1M_5%_2

44 OUT SPKR SATA1RXN


R4705

SATA1RXP AM8
HDA_RST# 1 R975 2 HDA_RST#_PCH K34 AP11
44 OUT HDA_RST# SATA1TXN
P3V3S SATA1TXP AP10
33_5%_2
R873
C 1 2 HDA_SDIN0 E34 AD7 SATA_ODD_RX_DN C
2

44 IN IN 40

IHDA
HDA_SDIN0 SATA2RXN
AD5 SATA_ODD_RX_DP 40
SATA2RXP
SATA_ODD_TX_DN
IN
1K_5%_2_DY G34 AH5 40
P5V0S HDA_SDIN1 SATA2TXN OUT
AH4 SATA_ODD_TX_DP 40
SATA2TXP OUT
C34 HDA_SDIN2

1
SATA3RXN AB8
Q553 A34 HDA_SDIN3 SATA3RXP AB10
AF3

G
SSM3K7002FU SATA3TXN
SATA3TXP AF1
HDA_SDO 2 3HDA_SDO_R 1 R952 2 HDA_SDO_PCH A36

SATA
44 OUT S D HDA_SDO
1

33_5%_2 SATA4RXN Y7
22pF_50V_2

P3V3A SATA4RXP Y5
R953 1 2 GPIO33 C36 HDA_DOCK_EN#/GPIO33 SATA4TXN AD3
C928

1K_5%_2_DY SATA4TXP AD1


N32 HDA_DOCK_RST#/GPIO13
1 2 GPIO13 Y3
2

R976 SATA5RXN
10K_5%_2 SATA5RXP Y1 P1V05S_PCH
SATA5TXN AB3
1 2 PCH_TCK J3 AB1

JTAG
R857 JTAG_TCK SATA5TXP
51_5%_2
PCH_TMS H7 Y11 SATAICOMPO 1 R934 2
26 OUT JTAG_TMS SATAICOMPO

ME_FLASH_EN 35 37.4_1%_2
IN 26 OUT PCH_TDI K5 JTAG_TDI SATAICOMPI Y10
B B
1K_5%_2
1 R14086 2

26 PCH_TDO H1
OUT JTAG_TDO
R935
SATA3RCOMPO AB12 SATA3RCOMPO 1 2

SATA3COMPI AB13 49.9_1%_2


HDA_SDO_PCH

PCH_SPI_CLK T3 AH1 SATA3RBIAS 1 R890 2 P3V3S


26 OUT SPI_CLK SATA3RBIAS

Flash Descriptor Security Overide 750_1%_2

SPI
26 PCH_SPI_CS0# Y14
OUT SPI_CS0#
R881 1
2
HDA_SDO_PCH : High : Enable 26 PCH_SPI_CS1# T1 10K_5%_2
OUT SPI_CS1#
Low : Disable SATALED# P3 LED_SATA#
OUT 36

26 PCH_SPI_SI V4 V14 2nd_WLAN_RF_OFF# 46


OUT SPI_MOSI SATA0GP/GPIO21 OUT
26 PCH_SPI_SO U3 P1 1 R933 2
IN SPI_MISO SATA1GP/GPIO19

P3V3A 10K_5%_2
ITL_PANTHERPOINT_FCBGA_989P BBSTRAP0
IN 30
P3V3A
0.1UF_16V_2

P3V3A
1

R851
3.3K_5%_2
2

1 2
C923

R991
A 1 2 210_1%_2 A
R945

1 R927 2
3.3K_5%_2
210_1%_2
2

PCH_SPI_CLK 1 R947 2 HSPI_CLK


26 BI BI 35 1 R863 2
1

U520 0_5%_2
210_1%_2
PCH_SPI_CS0# 1 8 PCH_SPI_CS1# 1 R946 2 HSPI_CS0# PCH_TMS
26 IN CE# VDD R879 26 BI BI 35 26 IN
26 PCH_SPI_SO 2 7 0_5%_2 0_5%_2 26 PCH_TDI
OUT 3
SO HOLD#
6 PCH_SPI_CLK_ROM 1 2 PCH_SPI_CLK
IN PCH_TDO
WP# SCK IN 26 PCH_SPI_SI 1 R948 2 HSPI_SI 26 IN
4 5 PCH_SPI_SI 26 BI BI 35
VSS SI IN 26

ACES_91960_0084L_8P
6026B0150101
26 BI PCH_SPI_SO 1
0_5%_2
R989
0_5%_2
2 HSPI_SO
BI 35
2 R864 1
100_1%_2
2 R928 1
INVENTEC
100_1%_2 TITLE
BIOS ROM 4MB 2 R853 1 MODEL,PROJECT,FUNCTION
PCH - 1
MXIC_MX25L3206EM2I_12G_SOP_8P 100_1%_2
DOC.NUMBER REV
P/N : 6019B0794701 SIZE
A3
CODE
CS
1310xxxxx-0-0 X01

CHANGE by XXX DATE 21-OCT-2002 SHEET 26 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3A

C915 0.1uF_16V_2
U519 R918 10K_5%_2
P3V3S 46 PCIE_WLAN_RX_C_DN BG34
IN PERN1
46 PCIE_WLAN_RX_C_DP BJ34 E12 GPIO11 2 1
IN PERP1 SMBALERT#/GPIO11
46 PCIE_WLAN_TX_C_DN AV32
PCIE_WLAN_TX_DN
OUT 1 2 PETN1

SMBUS
R878 46 PCIE_WLAN_TX_C_DP AU32
PCIE_WLAN_TX_DP H14 PCH_3A_SMCLK 27
1 2 10K_5%_2 CLKREQ_WLAN#
IN 27 46 OUT 1 2 PETP1 SMBCLK BI
C914 0.1uF_16V_2
PCH_3A_SMDAT
BE34 C9 27
R887 CLKREQ_CR#
PERN2 SMBDATA BI
1 2 10K_5%_2 27 43 BF34
IN PERP2
BB32 PETN2
AY32 PETP2
1 R4739 2 10K_5%_2 EDID_SELECT# A12 PCH_DDR_RST
IN 27 SML0ALERT#/GPIO60 OUT 17 21 27
PCIE_CR_RX_C_DN
C939 0.1uF_16V_2
BG36
43 IN PERN3
PCIE_CR_RX_C_DP BJ36 C8 PCH_3M_SMCLK 2 R854 1 2.2K_5%_2
1 R1030 2 10K_5%_2 DGPU_PRSNT# 43 IN PERP3 SML0CLK
IN 27 PCIE_CR_TX_C_DN PCIE_CR_TX_DNAV34
43 OUT 1 2 PETN3
D 43 PCIE_CR_TX_C_DP PCIE_CR_TX_DPAU34 G12 PCH_3M_SMDAT 2 1
OUT 1 2 PETP3 SML0DATA
D
2.2K_5%_2
R14067 DGPU_PRSNT# R922

PCI-E*
1 2 10K_5%_2_DY 27 C940 0.1uF_16V_2 BF36
IN PERN4
BE36 PERP4 10K_5%_2
AY34 C13 GPIO74 1 R917 2
PETN4 SML1ALERT#/PCHHOT#/GPIO74
BB34 PETP4
E14 PCH_THM_SMCLK 35
C917 0.1uF_16V_2
SML1CLK/GPIO58 BI
41 PCIE_LAN_RX_C_DN BG37
IN PERN5
41 PCIE_LAN_RX_C_DP BH37 M16 PCH_THM_SMDAT 35
P3V3A IN PERP5 SML1DATA/GPIO75 BI
41 PCIE_LAN_TX_C_DN AY36
PCIE_LAN_TX_DN
OUT 1 2 PETN5
PCIE_LAN_TX_C_DP BB36
PCIE_LAN_TX_DP
41 OUT 1 2 PETP5
1 R965 2 2.2K_5%_2
1 R4742 2 10K_5%_2 CLKREQ_LAN# C916 0.1uF_16V_2 BJ38
IN 27 41 PERN6
1 2
BG38 PERP6
R4880 AU36 PETN6 CL_CLK1 M7 R977
1 2 1K_5%_2 PCH_DDR_RST 17 21 27 2.2K_5%_2
IN AV36 PETP6

Controller
BG40 PERN7 CL_DATA1 T11 P3V3A

Link
BJ40 PERP7
AY40 PETN7

2
BB40 PETP7 CL_RST1# P10
R996 DGPU_PWR_EN IN 30 52 55 56
BE38 PERN8
C BC38 PERP8 10K_5%_2 1 C
AW38 PETN8
Q554

1
AY38

G
PETP8
SSM3K7002FU
P3V3A PEG_A_CLKRQ#/GPIO47 M10 CLKREQ_GPU# 3 D S 2
Y40 CLKOUT_PCIE0N
Y39 CLKOUT_PCIE0P
AB37 CLK_PEG_DN 48
GPIO73
CLKOUT_PEG_A_N
CLK_PEG_DP
OUT
R856 1 2 10K_5%_2 J2 AB38 48
PCIECLKRQ0#/GPIO73 CLKOUT_PEG_A_P OUT

46 CLK_PCIE_WLAN_DN R1048 1 2 0_5%_2 AB49


CLK_PCIE_WLAN_R_DN AV22 CLK_DMI_PCH_DN 17
OUT CLK_PCIE_WLAN_DP R1050
CLKOUT_PCIE1N CLKOUT_DMI_N OUT
46 1 2 0_5%_2 AB47
CLK_PCIE_WLAN_R_DP AU22 CLK_DMI_PCH_DP 17
OUT CLKOUT_PCIE1P CLKOUT_DMI_P OUT
46 27 CLKREQ_WLAN# M1
IN PCIECLKRQ1#/GPIO18
CLK_DP_PCH_DN
AM12 17
CLKOUT_DP_N
CLK_DP_PCH_DP
OUT
AM13 17
CLK_PCIE_CR_DN
CLKOUT_DP_P OUT
43 R1044 1 2 0_5%_2 CLK_PCIE_CR_R_DN AA48
OUT CLKOUT_PCIE2N

CLOCKS
43 CLK_PCIE_CR_DP R1046 1 2 0_5%_2 CLK_PCIE_CR_R_DP AA47
OUT CLKOUT_PCIE2P
CLKIN_DMI_N BF18 CLKIN_DMI_PCH_DN
R980 1 2 10K_5%_2
43 27 CLKREQ_CR# V10 BE18 CLKIN_DMI_PCH_DP
R981 1 2 10K_5%_2
IN PCIECLKRQ2#/GPIO20 CLKIN_DMI_P

B CLK_PCIE_LAN_DN 1 2 0_5%_2 Y37 BJ30 B


41 OUT R1049 CLK_PCIE_LAN_R_DN CLKOUT_PCIE3N CLKIN_GND1_N CLKIN_BUF_CPYCLK_DN
R984 1 2 10K_5%_2
41 CLK_PCIE_LAN_DP R1047 1 2 0_5%_2 CLK_PCIE_LAN_R_DP Y36 BG30 CLKIN_BUF_CPYCLK_DP
R1004 1 2 10K_5%_2
OUT CLKOUT_PCIE3P CLKIN_GND1_P

41 27 CLKREQ_LAN# A8
IN PCIECLKRQ3#/GPIO25
CLKIN_DOT_96N G24 CLKIN_BUF_DOT96_DN
R973 1 2 10K_5%_2
P3V3A P3V3S P3V3S P3V3A CLKIN_DOT_96P E24 CLKIN_BUF_DOT96_DP
R972 1 2 10K_5%_2
Y43 CLKOUT_PCIE4N
Y45 CLKOUT_PCIE4P
R911 AK7 CLKIN_SATA_DN
R937 1 2 10K_5%_2
2.2K_5%_2

2.2K_5%_2

2.2K_5%_2

2.2K_5%_2

CLKIN_SATA_N
1 210K_5%_2 GPIO26 L12 AK5 CLKIN_SATA_DP
R936 1 2 10K_5%_2
1 R916

1 R915

1 R909

1 R908

PCIECLKRQ4#/GPIO26 CLKIN_SATA_P

V45 CLKOUT_PCIE5N REFCLK14IN K45 CLKIN_BUF_REF14


R1036 1 2 10K_5%_2
V46 CLKOUT_PCIE5P
XTAL25PCH_OUT
R4755
210K_5%_2
2

1 GPIO44 L14 H45 CLKIN_PCI_FB 30 R1041


PCH_3S_SMCLK PCIECLKRQ5#/GPIO44 CLKIN_PCILOOPBACK IN XTAL25PCH_IN 1 2
2

25 24 BI 1 R912 2 PCH_25M_IN
SSM3K7002FU IN 16
1M_5%_2_DY
0_5%_2
S

AB42 CLKOUT_PEG_B_N XTAL25_IN V47 XTAL25PCH_IN


1
G AB40 CLKOUT_PEG_B_P XTAL25_OUT V49 XTAL25PCH_OUT P1V05S_PCH 1 3
R858
D

4 2
210K_5%_2

27PF_50V_2_DY
1 GPIO56 E6

27PF_50V_2_DY
PCH_3A_SMCLK PEG_B_CLKRQ#/GPIO56
27 BI Q547

C965
1

1
X503
23

Y47 PCH_XCLK_RCOMP 1 R1043 2


XCLK_RCOMP
A 25 24 PCH_3S_SMDAT A
BI

C962
V40 CLKOUT_PCIE6N
SSM3K7002FU V42 CLKOUT_PCIE6P
90.9_1%_2 25MHZ_DY
S

R932
210K_5%_2
1 6018B0044501_DY
G 1 GPIO45 T13 PCIECLKRQ6#/GPIO45

2
D

FLEX CLOCKS

V38 K43 EDID_SELECT# 27


27 BI PCH_3A_SMDAT Q548
CLKOUT_PCIE7N CLKOUTFLEX0/GPIO64 IN
V37 CLKOUT_PCIE7P
3

R921 CLKOUTFLEX1/GPIO65 F47


1 210K_5%_2 GPIO46 K12 PCIECLKRQ7#/GPIO46

INVENTEC
CLKOUTFLEX2/GPIO66 H47
AK14 CLKOUT_ITPXDP_N
AK13 K49 DGPU_PRSNT# 27
CLKOUT_ITPXDP_P CLKOUTFLEX3/GPIO67 OUT
TITLE
ITL_PANTHERPOINT_FCBGA_989P MODEL,PROJECT,FUNCTION
PCH - 2
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 27 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U519

18 DMI_RX0_DN BC24 BJ14 FDI_TX0_DN 18


IN DMI_RX1_DN
DMI0RXN FDI_RXN0
FDI_TX1_DN
IN
18 BE20 AY14 18
IN DMI_RX2_DN
DMI1RXN FDI_RXN1
FDI_TX2_DN
IN
18 BG18 BE14 18
IN DMI_RX3_DN
DMI2RXN FDI_RXN2
FDI_TX3_DN
IN
18 BG20 BH13 18
IN DMI3RXN FDI_RXN3
FDI_TX4_DN
IN
BC12 18
DMI_RX0_DP
FDI_RXN4
FDI_TX5_DN
IN
18 BE24 BJ12 18
IN DMI_RX1_DP
DMI0RXP FDI_RXN5
FDI_TX6_DN
IN
18 BC20 BG10 18
IN DMI1RXP FDI_RXN6 IN
18 DMI_RX2_DP BJ18 BG9 FDI_TX7_DN 18
D IN DMI_RX3_DP
DMI2RXP FDI_RXN7 IN
18 BJ20
IN DMI3RXP
FDI_TX0_DP D
BG14 18
DMI_TX0_DN
FDI_RXP0
FDI_TX1_DP
IN
AW24 BB14

DMI
18 OUT DMI0TXN FDI_RXP1 IN 18

FDI
18 DMI_TX1_DN AW20 BF14 FDI_TX2_DP 18
OUT DMI_TX2_DN
DMI1TXN FDI_RXP2
FDI_TX3_DP
IN
18 BB18 BG13 18
OUT DMI_TX3_DN
DMI2TXN FDI_RXP3
FDI_TX4_DP
IN
18 AV18 BE12 18
OUT DMI3TXN FDI_RXP4
FDI_TX5_DP
IN
BG12 18
DMI_TX0_DP
FDI_RXP5
FDI_TX6_DP
IN
18 AY24 BJ10 18
OUT DMI_TX1_DP
DMI0TXP FDI_RXP6
FDI_TX7_DP
IN
18 AY20 BH9 18
OUT DMI_TX2_DP
DMI1TXP FDI_RXP7 IN
18 AY18
OUT DMI_TX3_DP
DMI2TXP
18 AU18
P1V05S_PCH OUT DMI3TXP
FDI_INT
AW16 18
FDI_INT OUT
R983
1 2 PCH_DMI_ZCOMP BJ24 AV12 FDI_FSYNC0 18
DMI_ZCOMP FDI_FSYNC0 OUT P3V3_RTC
49.9_1%_2 BG25 BC10 FDI_FSYNC1 18
DMI_IRCOMP FDI_FSYNC1 OUT

330K_5%_2_DY 330K_5%_2
R982

1
1 2 PCH_DMI2RBIAS BH21 AV14 FDI_LSYNC0 18
DMI2RBIAS FDI_LSYNC0 OUT

R956
750_1%_2 BB10 FDI_LSYNC1 18
FDI_LSYNC1 OUT

2
C P3V3S DSWVRMEN A18 PCH_DSWVRMEN C

1
SUS_PWR_DN_ACK 1 R907 R971 RSMRST#

R957
35 28 2 PCH_SUSACK# C12 E22 1 2 28 35
IN SUSACK# DPWROK IN
0_5%_2_DY 0_5%_2

1 R868
2 PCH_SYSRESET#K3 B9 PCIE_WAKE#
SYS_RESET# WAKE# IN 28 41 46

System Power Management


10K_5%_2

2
P3V3S
PVCORE_PG 1 R930 2 P12 N3 PCI_CLKRUN# 1 R8672
12 IN SYS_PWROK CLKRUN#/GPIO32
0_5%_2 8.2K_5%_2

SB_PWRGD 1 R4782 2 L22 G8 1 TP4701


35 IN PWROK SUS_STAT#/GPIO61 TP30
0_5%_2

1 R926 2 L10 N14 1 TP4702


APWROK SUSCLK/GPIO62 TP30
0_5%_2

17 PM_DRAM_PWRGD B13 D10 R861 1 2 0_5%_2_DY


OUT DRAMPWROK SLP_S5#/GPIO63

35 28 RSMRST# C21 H4 R862 1 2 0_5%_2 SLP_S4# 35


IN RSMRST# SLP_S4# OUT
B B
35 28 SUS_PWR_DN_ACK K16 F4 R860 1 2 0_5%_2 SLP_S3# 35
OUT SUSWARN#/SUSPWRDNACK/GPIO30 SLP_S3# OUT
P3V3A
35 SB_PWRBTN# E20 G10 R859 1 2 0_5%_2_DY
IN PWRBTN# SLP_A#

2 1 0.1uF_16V_2_DY
C877 2 R9661 GPIO31 H20 G16 1 TP4703
ACPRESENT/GPIO31 SLP_SUS# TP30
10K_5%_2

2 R913 1 GPIO72 E10 AP14 H_PM_SYNC P3V3A


BATLOW#/GPIO72 PMSYNCH OUT 17
10K_5%_2

2 R849 1 PM_RI# A10 K14 GPIO29 1 R4795 2


RI# SLP_LAN#/GPIO29
10K_5%_2
10K_5%_2
ITL_PANTHERPOINT_FCBGA_989P

P3V3A
R959
35 28 SUS_PWR_DN_ACK 1 2
IN
10K_5%_2

A 46 41 28 PCIE_WAKE# 1 2 A
IN
R850
1K_5%_2

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PCH - 3
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 28 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3S

U519
PCH_LCD_BKEN J47 AP43

2.2K_5%_2

2.2K_5%_2
38 OUT L_BKLTEN SDVO_TVCLKINN

R1001 1

R1045 1
38 PCH_LCDVDD_EN M45 AP45
D OUT L_VDD_EN SDVO_TVCLKINP

38 PCH_LCD_PWM P45 AM42 D


OUT L_BKLTCTL SDVO_STALLN
SDVO_STALLP AM40
38 PCH_LCD_CLK T40
BI L_DDC_CLK

2
38 PCH_LCD_DAT K47 AP39
BI L_DDC_DATA SDVO_INTN
SDVO_INTP AP40
T45 L_CTRL_CLK
P39 L_CTRL_DATA

2 R979 1 PCH_LVD_IBG AF37 P38


LVD_IBG SDVO_CTRLCLK
AF36 LVD_VBG SDVO_CTRLDATA M39 P3V3S
2.37K_1%_2
AE48

LVDS
LVD_VREFH
AE47 LVD_VREFL DDPB_AUXN AT49

SSM3K7002FU
DDPB_AUXP AT47

1
1M_5%_2
DDPB_HPD AT40
PCH_LCD_TXACL_DN

R834
38 AK39
OUT LVDSA_CLK#

1
38 PCH_LCD_TXACL_DP AK40 AV42
OUT LVDSA_CLK DDPB_0N

Q543
DDPB_0P AV40

G
38 PCH_LCD_TXA0_DN AN48 AV45
OUT LVDSA_DATA#0 DDPB_1N

2
38 PCH_LCD_TXA1_DN AM47 AV46
OUT PCH_LCD_TXA2_DN
LVDSA_DATA#1 DDPB_1P
29 OUT PCH_HDMI_HPD 2 S D 3 HDMI_HPD
IN 39
38 AK47 AU48
OUT LVDSA_DATA#2 DDPB_2N

Digital Display Interface


AJ48 AU47

20K_5%_2
LVDSA_DATA#3 DDPB_2P

2
C DDPB_3N AV47 C
PCH_LCD_TXA0_DP AN47 AV49

R831
38 OUT LVDSA_DATA0 DDPB_3P
38 PCH_LCD_TXA1_DP AM49
OUT PCH_LCD_TXA2_DP
LVDSA_DATA1
38 AK49
OUT LVDSA_DATA2
AJ47 LVDSA_DATA3 DDPC_CTRLCLK P46

1
DDPC_CTRLDATA P42

AF40 LVDSB_CLK#
AF39 LVDSB_CLK DDPC_AUXN AP47
DDPC_AUXP AP49
AH45 LVDSB_DATA#0 DDPC_HPD AT38
AH47 LVDSB_DATA#1
AF49 LVDSB_DATA#2 DDPC_0N AY47
AF45 LVDSB_DATA#3 DDPC_0P AY49
DDPC_1N AY43
AH43 LVDSB_DATA0 DDPC_1P AY45
AH49 LVDSB_DATA1 DDPC_2N BA47
AF47 LVDSB_DATA2 DDPC_2P BA48
AF43 LVDSB_DATA3 DDPC_3N BB47
DDPC_3P BB49

37 PCH_CRT_B N48 M43 PCH_HDMI_CLK 39


B OUT CRT_BLUE DDPD_CTRLCLK BI B

CRT
37 PCH_CRT_G P49 M36 PCH_HDMI_DAT 39
OUT PCH_CRT_R
CRT_GREEN DDPD_CTRLDATA BI
37 T49
OUT CRT_RED

R1035 1 2 150_1%_2 DDPD_AUXN AT45


37 PCH_CRT_CLK T39 AT43
R1037 1 2 150_1%_2 OUT PCH_CRT_DAT
CRT_DDC_CLK DDPD_AUXP
PCH_HDMI_HPD
37 M40 BH41 29
OUT CRT_DDC_DATA DDPD_HPD IN
R1039 1 2 150_1%_2
0_5%_2 BB43 PCH_HDMI_TX2_DN
DDPD_0N OUT 39
PCH_CRT_HSYNC 1 R4804 2 PCH_CRT_HSYNC_PCH M47 BB45 PCH_HDMI_TX2_DP
37 OUT CRT_HSYNC DDPD_0P OUT 39
37 PCH_CRT_VSYNC 1 2 PCH_CRT_VSYNC_PCH M49 BF44 PCH_HDMI_TX1_DN 39
OUT CRT_VSYNC DDPD_1N OUT
PCH_HDMI_TX1_DP
BE44 39
R4805
DDPD_1P OUT
PCH_HDMI_TX0_DN
BF42 39
0_5%_2
DDPD_2N OUT
PCH_HDMI_TX0_DP
PCH_DAC_IREF T43 BE42 39
DAC_IREF DDPD_2P OUT
PCH_HDMI_TXCL_DN
T42 BJ42 39
CRT_IRTN DDPD_3N OUT
PCH_HDMI_TXCL_DP
BG42 39
DDPD_3P OUT
R1002 1
1K_1%_2

ITL_PANTHERPOINT_FCBGA_989P

CLOSE TO PCH
2

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PCH - 4
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 29 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3A

U519
10K_5%_2
RSVD1 AY7
30 GPIO55 1 R1031 2 AV7 30 GPIO59 1 R848 2
IN RSVD2 OUT
1K_5%_2_DY BG26 TP1 RSVD3 AU3
30 2ND_WWAN_GPS_OFF# 1 2
BJ26 TP2 RSVD4 BG4 OUT
BH25 TP3 R901 10K_5%_2
GPIO55 : TOP-BLOCK SWAP OVERRIDE BJ16 TP4 RSVD5 AT10
BG16 BC8
LOW=A16 SWAP OVERRIDE AH38
TP5 RSVD6
30 OUT BOARD_ID0 R960 1 210K_5%_2_DY
HIGH=DEFAULT AH37
TP6
AU2 30 BOARD_ID1 R905 1 210K_5%_2_DY
TP7 RSVD7 OUT
D AK43 TP8 RSVD8 AT4
BOARD_ID2 1 210K_5%_2_DY
30 OUT R902
AK45 TP9 RSVD9 AT3 D
C18 AT1 BOARD_ID3 1 210K_5%_2_DY
26 BBSTRAP0 1 R875 2 TP10 RSVD10 30 OUT R967
IN N30 TP11 RSVD11 AY3
BOARD_ID4
1K_5%_2_DY 30 R899 1 210K_5%_2_DY
H3 TP12 RSVD12 AT5 OUT
AH12 AV3 BOARD_ID5 1 210K_5%_2_DY
BBSTRAP1 1 R1029 TP13 RSVD13 30 OUT R914

NVRAM
30 2
IN AM4 TP14 RSVD14 AV1
1K_5%_2_DY AM5 BB1
TP15 RSVD15

RSVD
Y13 BA3 30 BOARD_ID0 R961 1 2 10K_5%_2
DGPU_PWM_SELECT# 1 R999
TP16 RSVD16 OUT
30 2 K24 BB5
IN TP17 RSVD17
30 OUT BOARD_ID1 R903 1 2 10K_5%_2
1K_5%_2_DY L24 TP18 RSVD18 BB3
AB46 BB7 30 BOARD_ID2 R904 1 2 10K_5%_2
TP19 RSVD19 OUT
AB45 TP20 RSVD20 BE8
30 BOARD_ID3 R968 1 2 10K_5%_2
BBSTRAP1 BBSTRAP0 BOOT BIOS RSVD21 BD4 OUT
BF6 30 BOARD_ID4 R900 1 2 10K_5%_2
0 0 LPC RSVD22 OUT
30 BOARD_ID5 R920 1 2 10K_5%_2
0 1 Reserved (NAND) B21 TP21 RSVD23 AV5 OUT
M20
1 0 -- AY16
TP22
TP23
1 1 SPI BG46 TP24 RSVD24 AV10
ID5 ID4 ID3 ID2 ID1 ID0
RSVD25 AT8
UMA 0 0 0 0 0 0
P3V3S 47 USB3_P1_RX_DN BE28 AY5
C IN USB3RN1 RSVD26
SG 0 0 0 0 0 1 C
BC30 USB3RN2 RSVD27 BA2
BE32 USB3RN3
BJ32 USB3RN4 RSVD28 AT12
47 IN USB3_P1_RX_DP BC28 USB3RP1 RSVD29 BF3
R1027 1 2 DGPU_HOLD_RST# 30 48 BE30
IN USB3RP2
10K_5%_2 BF32 USB3RP3
BG32 C24 USB_P0_DN 47
R1025 1 2 DGPU_SELECT#
IN 30
USB3RP4 USBP0N BI
8.2K_5%_2
47 OUT USB3_P1_TX_DN AV26 USB3TN1 USBP0P A24 USB_P0_DP
BI 47 USB3.0
BB26 C25 USB_P1_DN 47
USB3TN2 USBP1N BI
R1020 1 2 DGPU_PWR_EN#
IN 30 55 AU28 USB3TN3 USBP1P B25 USB_P1_DP
BI 47 USB2.0 DB (DeBug Port)
1K_5%_2 AY30 USB3TN4 USBP2N C26
USB30_SMI# 47 OUT USB3_P1_TX_DP AU26 USB3TP1 USBP2P A26
R14066 1 2
IN 30 AY26 K28
USB3TP2 USBP3N
8.2K_5%_2 AV28 H28
USB3TP3 USBP3P
R14063 1 2 ACCEL_INT# 30 AW30 E28
IN USB3TP4 USBP4N
8.2K_5%_2 USBP4P D28
C28 USB_P5_DN 38
P3V3S USBP5N BI
P3V3S USBP5P A28 USB_P5_DP
BI 38 WEBCAM
USBP6N C29
USBP6P B29
1 2 PCI_INTA# K40 N28
10K_5%_2

8.2K_5%_2
1

R403 PIRQA# USBP7N


R1022

R401 1 2 8.2K_5%_2 PCI_INTB# K38 PIRQB# USBP7P M28


B R402 1 2 8.2K_5%_2 PCI_INTC# H38 L30 USB_P8_DN 46 B
PIRQC# USBP8N BI

PCI
R400 1 2 8.2K_5%_2 PCI_INTD# G38 PIRQD# USBP8P K30 USB_P8_DP
BI 46 WLAN COMBO

USB
G30 USB_P9_DN 47
USBP9N BI
48 30 OUT DGPU_HOLD_RST# C46 REQ1#/GPIO50 USBP9P E30 USB_P9_DP
BI 47 USB2.0 DB (DeBug Port)
2

30 DGPU_SELECT# C44 C30


OUT DGPU_PWR_EN#
REQ2#/GPIO52 USBP10N
55 30 E40 A30
DGPU_PWR_EN OUT 27 52 55 56 OUT REQ3#/GPIO54 USBP10P
USBP11N L32
2

30 BBSTRAP1 D47 K32


IN DGPU_PWM_SELECT#
GNT1#/GPIO51 USBP11P
30 E42 G32
Q555 P3V3S OUT GNT2#/GPIO53 USBP12N
S

30 GPIO55 F46 E32


55 30 IN DGPU_PWR_EN#
1 G
IN GNT3#/GPIO55 USBP12P
SSM3K7002FU USBP13N C32
USBP13P A32
D

30 USB30_SMI# G42
IN GPIO3
PIRQE#/GPIO2
R14065 1 28.2K_5%_2 G40 PIRQF#/GPIO3
3

R14064 1 28.2K_5%_2 GPIO4 C42 PIRQG#/GPIO4 USBRBIAS# C33


30 IN ACCEL_INT# D44 PIRQH#/GPIO5 CLOSE TO PCH
P3V3A
USBRBIAS B33 PCH_USBBIAS 1 R951 2
R923 1 2 PCH_PME# K10 PME# 22.6_1%_2
P3V3A 10K_5%_2_DY
48 43 41 30 PLT_RST# C6 A14 GPIO59 30
OUT PLTRST# OC0#/GPIO59
BOARD_ID0
IN
C1005 K20 30
OC1#/GPIO40 IN
0.1uF_16V_2 R1026 22_5%_2 OC2#/GPIO41 B17 BOARD_ID1
IN 30
35 CLK_LPC_EC 1 2 CLK_LPC_EC_R H49 C16 BOARD_ID2 30
1 2 OUT CLKIN_PCI_FB
CLKOUT_PCI0 OC3#/GPIO42
BOARD_ID3
IN
A 27 OUT 1 2 CLKIN_PCI_FB_R H43 CLKOUT_PCI1 OC4#/GPIO43 L16
IN 30 A
R1033 22_5%_2 J48 A16 BOARD_ID4 30
CLKOUT_PCI2 OC5#/GPIO9
BOARD_ID5
IN
K42 D14
5

CLKOUT_PCI3 OC6#/GPIO10 IN 30
U527 CLK_LPC_DEBUG 1 R997 2 CLK_LPC_DEBUG_R H40 C14 2ND_WWAN_GPS_OFF#
46 OUT CLKOUT_PCI4 OC7#/GPIO14 IN 30
1
+

46 35 17 OUT BUF_PLT_RST# 4
PLT_RST#
22_5%_2 ITL_PANTHERPOINT_FCBGA_989P
2 30 41 43 48
100K_5%_2

IN
1

-
R1064

TC7SZ08FU
3

INVENTEC
2

TITLE
MODEL,PROJECT,FUNCTION
PCH - 5
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 30 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3S
P3V3A

WLAN_RF_OFF# 1 R924 2 10K_5%_2 U519


R994
10K_5%_2
46 31 OUT 35 31 IN PCI_SERR# T7 BMBUSY#/GPIO0 TACH4/GPIO68 C40 GPIO68 1 2

35 IN EC_SMI# A42 TACH1/GPIO1 TACH5/GPIO69 B41 GPIO69 1 R992 2

BTOFF 1 R1088 2 10K_5%_2 DGPU_HPD_INTR# H36 C41 10K_5%_2


31 OUT 31 IN TACH2/GPIO6 TACH6/GPIO70

EC_SCI# E38 A40 GPIO71 1 R993 2


35 IN TACH3/GPIO7 TACH7/GPIO71
D GPIO24 1 R1081 2 10K_5%_2 10K_5%_2
2 R847 1 GPIO8 C10 GPIO8
D
GPIO15 1 R1082 2 10K_5%_2 1K_5%_2_DY
P3V3S 31 OUT BTOFF C4 LAN_PHY_PWR_CTRL/GPIO12 P1V05S_CPU
GPIO15 G2 P4 A20GATE

56_5%_2_DY
GPIO15 A20GATE IN 35

1
P3V3S
AU16 PCH_PECI 1 R940 2 H_PECI

R14081
PECI IN 17 35
2 R883 1 GPIO16 U2 SATA4GP/GPIO16 0_5%_2_DY

CPU/MISC
R880 10K_5%_2 P5 KB_RST#

GPIO
PCI_SERR# 1 2 RCIN# IN 31 35
35 31 OUT 10K_5%_2
10K_5%_2 DGPU_PWROK
D40 AY11 H_CPUPWRGD

2
DGPU_HPD_INTR# 1 R974 2 56
52 35 31 IN TACH0/GPIO17 PROCPWRGD OUT 17
31 OUT
2 R872 1 GPIO22 T5 AY10 PM_THRMTRIP#_PCH 1 R14080 2 PM_THRMTRIP#
SCLOCK/GPIO22 THRMTRIP# IN 17
10K_5%_2
P3V3A GPIO24 E8 T14 390_5%_2
40 31 ODD_PRSNT# 1 R886 2 200K_5%_2 GPIO24 INIT3_3V#
OUT
2 R963 1 GPIO27 E16
GPIO37 1 R866 2 1K_5%_2_DY GPIO27
31 OUT AY1 NV_CLE
10K_5%_2_DY DF_TVS OUT 17
HDD_LOCK_LED 1 R1080 2 10K_5%_2_DY P3V3S 2 1 GPIO28 P8 GPIO28
31 OUT AH8
R877 1K_5%_2_DY TS_VSS1

TEMP_ALERT# 1 R882 2 10K_5%_2 2 1 GPIO34 K1 STP_PCI#/GPIO34


31 OUT AK11
R869 10K_5%_2 TS_VSS2
C KB_RST# 1 R870 2 10K_5%_2 2 1 GPIO35 K4 GPIO35 C
35 31 OUT AH10
R925 10K_5%_2_DY TS_VSS3
40 31 IN ODD_PRSNT#V8 SATA2GP/GPIO36
TS_VSS4 AK10
P3V3S 31 IN GPIO37 M5 SATA3GP/GPIO37
NC_1 P37
R995 2 1 GPIO38 N2 SLOAD/GPIO38
56
52 35 31 DGPU_PWROK 1 2
OUT R874 10K_5%_2
100K_5%_2_DY 2 1 GPIO39 M3 SDATAOUT0/GPIO39

GPIO37 1 R865 2 R871 10K_5%_2


31 OUT 31 OUT HDD_LOCK_LED
V13 SDATAOUT1/GPIO48 VSS_NCTF_15 BG2
100K_5%_2
31 OUT TEMP_ALERT#V3 SATA5GP/GPIO49/TEMP_ALERT# VSS_NCTF_16 BG48

46 31 OUT WLAN_RF_OFF#
D6 GPIO57 VSS_NCTF_17 BH3

VSS_NCTF_18 BH47

A4 VSS_NCTF_1 VSS_NCTF_19 BJ4

A44 VSS_NCTF_2 VSS_NCTF_20 BJ44

A45 VSS_NCTF_3 VSS_NCTF_21 BJ45


B B

NCTF
A46 VSS_NCTF_4 VSS_NCTF_22 BJ46

A5 VSS_NCTF_5 VSS_NCTF_23 BJ5

A6 VSS_NCTF_6 VSS_NCTF_24 BJ6

B3 VSS_NCTF_7 VSS_NCTF_25 C2

B47 VSS_NCTF_8 VSS_NCTF_26 C48

BD1 VSS_NCTF_9 VSS_NCTF_27 D1

BD49 VSS_NCTF_10 VSS_NCTF_28 D49

BE1 VSS_NCTF_11 VSS_NCTF_29 E1

BE49 VSS_NCTF_12 VSS_NCTF_30 E49

BF1 VSS_NCTF_13 VSS_NCTF_31 F1

BF49 VSS_NCTF_14 VSS_NCTF_32 F49

ITL_PANTHERPOINT_FCBGA_989P
A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PCH - 6
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 31 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P1V05S_PCH P3V3S

1.61A 63MA
U519
D AA23 U48 P3V3S_PCH_VCCADAC 1 L528 2
AC23
VCCCORE[1]
POWER VCCADAC
MLZ1608M100WT
D

220uF_2V_DY
VCCCORE[2]

0.01uF_50V_2

0.1uF_16V_2

22uF_6.3V_5
1uF_6.3V_2

1uF_6.3V_2
1

CRT
AD21

10uF_6.3V_5
VCCCORE[3]

1uF_6.3V_2
1

1
250MA_0603

C4783

1
AD23 U47

VCC CORE
VCCCORE[4] VSSADAC P3V3S

+
AF21 VCCCORE[5]
1MA

C904

C892

C889

C959

C961

C960
AF23 VCCCORE[6]

C897
AG21 VCCCORE[7]
AG23

2
VCCCORE[8]

2
AG24 AK36

2
VCCCORE[9] VCCALVDS
AG26 VCCCORE[10]
AG27 VCCCORE[11] VSSALVDS AK37
AG29 VCCCORE[12] P1V8S
AJ23

LVDS
AJ26
VCCCORE[13]
VCCCORE[14] VCCTX_LVDS[1] AM37 40MA
AJ27 VCCCORE[15]
AJ29 AM38 P1V8S_PCH_VCCTX_LVDS 1 L526 2
P1V05S_PCH VCCCORE[16] VCCTX_LVDS[2]
AJ31 VCCCORE[17]
FBM_11_160808_121T

0.01uF_50V_2

0.01uF_50V_2
AP36

22uF_6.3V_5
3.8A VCCTX_LVDS[3]

P1V05S_PCH 200MA_0603

1
VCCTX_LVDS[4] AP37

C1000
AN19 VCCIO[28]

C945

C949
L520 P3V3S
C 1 2 BJ22 C

HVCMOS
VCCAPLLEXP

2
0603_DY
178MA

0.1uF_16V_2
V33
10uF_6.3V_5_DY

VCC3_3[6]
1

1
AN16 VCCIO[15]

P1V05S_PCH
C851

C888
AN17 VCCIO[16]
VCC3_3[7] V34
3.8A P1V05S_PCH
2

P1V5S_VCCAFDI_VRM

2
AN21 VCCIO[17]
147MA 47MA
AN26 AT20 SOURCE IS
10uF_6.3V_5

VCCIO[18]
1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2
P1V05S_CPU
1

1
VCCVRM[3] AT16
AN27

VCCIO
VCCIO[19]
P1V05S_PCH
C4722

C935
C937

C907

C905

C887

C866

AP21

DMI
VCCIO[20]
VCCDMI[1] AT20
AP23
2

2
VCCIO[21]

AP24 VCCIO[22] 75MA


P3V3S VCCCLKDMI AB36

1uF_6.3V_2_DY
AP26 VCCIO[23]

1
B 178MA B
AT24 VCCIO[24]

C933
P1V8S
1

0.1uF_16V_2

AN33
C911

VCCIO[25]
2MA

2
VCCDFTERM[1] AG16

0.1uF_16V_2
AN34 VCCIO[26]
P1V5S_VCCAFDI_VRM

1
2

BH29 VCC3_3[3] VCCDFTERM[2] AG17


P1V05S_PCH

C903
147MA

NAND / SPI
VCCDFTERM[3] AJ16
P1V05S_PCH

2
AP16 VCCVRM[2]
VCCDFTERM[4] AJ17

R941 P3V3A
1 2 BG6 VccAFDIPLL
FDI

0_5%_2_DY
AP17 VCCIO[27] 10MA
VCCSPI V1

1uF_6.3V_2
AU20 VCCDMI[2]

1
P1V05S_PCH ITL_PANTHERPOINT_FCBGA_989P
A A

C849
47MA

2
AU20 SOURCE IS P1V5S_VCCAFDI_VRM P1V5S
P1V05S_CPU
PAD4700
1 1 2
2

POWERPAD1X1M
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
PCH - 7
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 32 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3S P3V3A
1MA P1V05S_PCH
P1V05S_PCH
178MA 3.8A

1
U519 P3V3A
R1051

0.1uF_16V_2
1 2 AD49 N26
VCCACLK
POWER VCCIO[29]

2
1uF_6.3V_2
1
C882
0_5%_2_DY D530
0.1uF_16V_2

P26
10uF_6.3V_5
VCCIO[30]

NC
1

T16 VCCDSW3_3

C885
3 1
P28

2
VCCIO[31]
C862
C963

C931

2 1 V12 DCPSUSBYP VCCIO[32] T27 P5V0A


BAT54_30V_0.2A

2
P1V05S_PCH 0.1uF_16V_2_DY T29 P3V3A 1MA
2

VCCIO[33] R970
T38 VCC3_3[5] 1 2

0.1uF_16V_2
VCCSUS3_3[7] T23 65MA 10_5%_2

1
R4874
D 1 2 BH23 VCCAPLLDMI2
1 2

USB
0_5%_2_DY
VCCSUS3_3[8] T24 D
C884

C879
AL29 VCCIO[14]
V23 0.1uF_16V_2
VCCSUS3_3[9] P3V3A
C906 1 2

2
2 1 AL24 DCPSUS[3] VCCSUS3_3[10] V24
C881 65MA
1uF_6.3V_2_DY VCCSUS3_3[6] P24 0.1uF_16V_2

Clock and Miscellaneous


P1V05S_PCH
AA19 VCCASW[1] P1V05S_PCH
803MA
AA21 VCCASW[2] VCCIO[34] T26

P5V0A_PCH_V5REF_SUSU
22uF_6.3V_5

22uF_6.3V_5

AA24 M26
VCCASW[3] V5REF_SUS P3V3S
1uF_6.3V_2

1uF_6.3V_2

1uF_6.3V_2
1

2
AA26 VCCASW[4] C908 P3V3A
D532
C910

C909

C895

C899

C898
DCPSUS[4] AN23 1 2

NC
AA27 VCCASW[5]
VCCSUS3_3[1] AN24 1uF_6.3V_2_DY 65MA 3 1
AA29
2

2 VCCASW[6]
P5V0S
AA31 BAT54_30V_0.2A
VCCASW[7]

P1V05S_PCH R1042
AC26 VCCASW[8] V5REF P34 P5V0S_PCH_V5REF 1 2 1MA
C 75MA C
P3V3A
AC27 VCCASW[9] 10_5%_2

1
PCI/GPIO/LPC

1uF_6.3V_2
N20
1 L530 2 P1V05S_PCH_VCCADPLLA VCCSUS3_3[2]
AC29 VCCASW[10] 65MA

C964
MLZ1608M100WT N22
2.2uF_6.3V_3

VCCSUS3_3[3]
22uF_6.3V_5

0.1uF_16V_2

250MA_0603
1

AC31 VCCASW[11] C880


VCCSUS3_3[4] P20 1 2

2
C966

C967

C968

AD29 VCCASW[12] P3V3S


VCCSUS3_3[5] P22 1uF_6.3V_2
AD31 VCCASW[13]
2

W21 VCCASW[14] VCC3_3[1] AA16 178MA


C894
W23 VCCASW[15] VCC3_3[8] W16 2 1

75MA 0.1uF_16V_2
W24 VCCASW[16] VCC3_3[4] T34
L531 P1V05S_PCH_VCCADPLLB C865 0.1uF_16V_2
1 2
P1V5S_VCCAFDI_VRM W26 VCCASW[17] 1 2
MLZ1608M100WT
0.1uF_16V_2

P3V3S
2.2uF_6.3V_3

250MA_0603 147MA
1

W29 C863 0.1uF_16V_2


22uF_6.3V_5

0.1uF_16V_2

VCCASW[18]
1

1 2
178MA
C861

W31 VCCASW[19]
C938

C973

C974

B VCC3_3[2] AJ2 B
W33 VCCASW[20]
AF13
2

VCCIO[5] P1V05S_PCH
2

N16 DCPRTC
VCCIO[12] AH13 3.8A
C864
Y49 AH14

SATA
VCCVRM[4] VCCIO[13] 1 2

1uF_6.3V_2 P1V05S_PCH
VCCIO[6] AF14
BD47 VCCADPLLA
P1V05S_PCH AK1 1 L519 2 P1V5S_VCCAFDI_VRM
VCCAPLLSATA
BF47 VCCADPLLB
0603_DY
50MA C900 2 1 1uF_6.3V_2 147MA
VCCVRM[1] AF11
AF17 VCCIO[7]
AF33 VCCDIFFCLKN[1]
P1V05S_PCH C891 1uF_6.3V_2 AF34 VCCDIFFCLKN[2] VCCIO[2] AC16 P1V05S_PCH
2 1
AG34 VCCDIFFCLKN[3]
C896 2 1 1uF_6.3V_2 VCCIO[3] AC17
C890
95MA 3.8A
AG33 VCCSSC VCCIO[4] AD17 1 2

A C893 0.1uF_16V_2 1uF_6.3V_2 A


P1V05S_PCH 2 1 V16 DCPSST

R978 0_5%_2_DY
MISC

1 2 T17 DCPSUS[1] VCCASW[22] T21 P1V05S_PCH


V19
P1V05S_PCH DCPSUS[2]

1 2 803MA
VCCASW[23] V21
C883 1uF_6.3V_2_DY
RTC CPU

2MA
BJ8 V_PROC_IO
VCCASW[21] T19
P3V3A
INVENTEC
1

1
0.1uF_16V_2

0.1uF_16V_2
4.7uF_6.3V_3

BJ8 SOURCE IS
1

1
0.1uF_16V_2

0.1uF_16V_2
1uF_6.3V_2

P3V3_RTC
P1V05S_CPU 10MA
HDA
C912

C919

C918

TITLE
C857

C870

C858

A22 VCCRTC VCCSUSHDA P32


MODEL,PROJECT,FUNCTION
1MA C886 PCH - 8
2

ITL_PANTHERPOINT_FCBGA_989P 1 2
2

DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
0.1uF_16V_2
CHANGE by XXX DATE 21-OCT-2002 SHEET 33 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U519
AY4 VSS[159] VSS[259] H46
AY42 VSS[160] VSS[260] K18
AY46 VSS[161] VSS[261] K26
AY8 VSS[162] VSS[262] K39
B11 VSS[163] VSS[263] K46
B15 K7 U519
VSS[164] VSS[264]
H5 VSS[0]
B19 VSS[165] VSS[265] L18
B23 VSS[166] VSS[266] L2
AA17 VSS[1] VSS[80] AK38
B27 VSS[167] VSS[267] L20
AA2 VSS[2] VSS[81] AK4
B31 VSS[168] VSS[268] L26
AA3 VSS[3] VSS[82] AK42
B35 VSS[169] VSS[269] L28
AA33 VSS[4] VSS[83] AK46
B39 VSS[170] VSS[270] L36
AA34 VSS[5] VSS[84] AK8
B7 VSS[171] VSS[271] L48
AB11 VSS[6] VSS[85] AL16
F45 VSS[172] VSS[272] M12
AB14 VSS[7] VSS[86] AL17
BB12 VSS[173] VSS[273] P16
AB39 VSS[8] VSS[87] AL19
BB16 VSS[174] VSS[274] M18
AB4 VSS[9] VSS[88] AL2
D BB20 VSS[175] VSS[275] M22
AB43 VSS[10] VSS[89] AL21
BB22 VSS[176] VSS[276] M24
AB5 VSS[11] VSS[90] AL23 D
BB24 VSS[177] VSS[277] M30
AB7 VSS[12] VSS[91] AL26
BB28 VSS[178] VSS[278] M32
AC19 VSS[13] VSS[92] AL27
BB30 VSS[179] VSS[279] M34
AC2 VSS[14] VSS[93] AL31
BB38 VSS[180] VSS[280] M38
AC21 VSS[15] VSS[94] AL33
BB4 VSS[181] VSS[281] M4
AC24 VSS[16] VSS[95] AL34
BB46 VSS[182] VSS[282] M42
AC33 VSS[17] VSS[96] AL48
BC14 VSS[183] VSS[283] M46
AC34 VSS[18] VSS[97] AM11
BC18 VSS[184] VSS[284] M8
AC48 VSS[19] VSS[98] AM14
BC2 VSS[185] VSS[285] N18
AD10 VSS[20] VSS[99] AM36
BC22 VSS[186] VSS[286] P30
AD11 VSS[21] VSS[100] AM39
BC26 VSS[187] VSS[287] N47
AD12 VSS[22] VSS[101] AM43
BC32 VSS[188] VSS[288] P11
AD13 VSS[23] VSS[102] AM45
BC34 VSS[189] VSS[289] P18
AD19 VSS[24] VSS[103] AM46
BC36 VSS[190] VSS[290] T33
AD24 VSS[25] VSS[104] AM7
BC40 VSS[191] VSS[291] P40
AD26 VSS[26] VSS[105] AN2
BC42 VSS[192] VSS[292] P43
AD27 VSS[27] VSS[106] AN29
BC48 VSS[193] VSS[293] P47
AD33 VSS[28] VSS[107] AN3
BD46 VSS[194] VSS[294] P7
AD34 VSS[29] VSS[108] AN31
BD5 VSS[195] VSS[295] R2
AD36 VSS[30] VSS[109] AP12
BE22 VSS[196] VSS[296] R48
AD37 VSS[31] VSS[110] AP19
BE26 VSS[197] VSS[297] T12
AD38 VSS[32] VSS[111] AP28
BE40 VSS[198] VSS[298] T31
C BF10 VSS[199] VSS[299] T37
AD39 VSS[33] VSS[112] AP30 C
AD4 VSS[34] VSS[113] AP32
BF12 VSS[200] VSS[300] T4
AD40 VSS[35] VSS[114] AP38
BF16 VSS[201] VSS[301] W34
AD42 VSS[36] VSS[115] AP4
BF20 VSS[202] VSS[302] T46
AD43 VSS[37] VSS[116] AP42
BF22 VSS[203] VSS[303] T47
AD45 VSS[38] VSS[117] AP46
BF24 VSS[204] VSS[304] T8
AD46 VSS[39] VSS[118] AP8
BF26 VSS[205] VSS[305] V11
AD8 VSS[40] VSS[119] AR2
BF28 VSS[206] VSS[306] V17
AE2 VSS[41] VSS[120] AR48
BD3 VSS[207] VSS[307] V26
AE3 VSS[42] VSS[121] AT11
BF30 VSS[208] VSS[308] V27
AF10 VSS[43] VSS[122] AT13
BF38 VSS[209] VSS[309] V29
AF12 VSS[44] VSS[123] AT18
BF40 VSS[210] VSS[310] V31
AD14 VSS[45] VSS[124] AT22
BF8 VSS[211] VSS[311] V36
AD16 VSS[46] VSS[125] AT26
BG17 VSS[212] VSS[312] V39
AF16 VSS[47] VSS[126] AT28
BG21 VSS[213] VSS[313] V43
AF19 VSS[48] VSS[127] AT30
BG33 VSS[214] VSS[314] V7
AF24 VSS[49] VSS[128] AT32
BG44 VSS[215] VSS[315] W17
AF26 VSS[50] VSS[129] AT34
BG8 VSS[216] VSS[316] W19
AF27 VSS[51] VSS[130] AT39
BH11 VSS[217] VSS[317] W2
AF29 VSS[52] VSS[131] AT42
BH15 VSS[218] VSS[318] W27
AF31 VSS[53] VSS[132] AT46
BH17 VSS[219] VSS[319] W48
AF38 VSS[54] VSS[133] AT7
BH19 VSS[220] VSS[320] Y12
AF4 VSS[55] VSS[134] AU24
B H10 VSS[221] VSS[321] Y38
AF42 VSS[56] VSS[135] AU30 B
BH27 VSS[222] VSS[322] Y4
AF46 VSS[57] VSS[136] AV16
BH31 VSS[223] VSS[323] Y42
AF5 VSS[58] VSS[137] AV20
BH33 VSS[224] VSS[324] Y46
AF7 VSS[59] VSS[138] AV24
BH35 VSS[225] VSS[325] Y8
AF8 VSS[60] VSS[139] AV30
BH39 VSS[226] VSS[328] BG29
AG19 VSS[61] VSS[140] AV38
BH43 VSS[227] VSS[329] N24
AG2 VSS[62] VSS[141] AV4
BH7 VSS[228] VSS[330] AJ3
AG31 VSS[63] VSS[142] AV43
D3 VSS[229] VSS[331] AD47
AG48 VSS[64] VSS[143] AV8
D12 VSS[230] VSS[333] B43
AH11 VSS[65] VSS[144] AW14
D16 VSS[231] VSS[334] BE10
AH3 VSS[66] VSS[145] AW18
D18 VSS[232] VSS[335] BG41
AH36 VSS[67] VSS[146] AW2
D22 VSS[233] VSS[337] G14
AH39 VSS[68] VSS[147] AW22
D24 VSS[234] VSS[338] H16
AH40 VSS[69] VSS[148] AW26
D26 VSS[235] VSS[340] T36
AH42 VSS[70] VSS[149] AW28
D30 VSS[236] VSS[342] BG22
AH46 VSS[71] VSS[150] AW32
D32 VSS[237] VSS[343] BG24
AH7 VSS[72] VSS[151] AW34
D34 VSS[238] VSS[344] C22
AJ19 VSS[73] VSS[152] AW36
D38 VSS[239] VSS[345] AP13
AJ21 VSS[74] VSS[153] AW40
D42 VSS[240] VSS[346] M14
AJ24 VSS[75] VSS[154] AW48
D8 VSS[241] VSS[347] AP3
AJ33 VSS[76] VSS[155] AV11
E18 VSS[242] VSS[348] AP1
AJ34 VSS[77] VSS[156] AY12
E26 VSS[243] VSS[349] BE16
AK12 VSS[78] VSS[157] AY22
G18 VSS[244] VSS[350] BC16
AK3 VSS[79] VSS[158] AY28
A G20 VSS[245] VSS[351] BG28 A
G26 VSS[246] VSS[352] BJ28
G28 ITL_PANTHERPOINT_FCBGA_989P
VSS[247]
G36 VSS[248]
G48 VSS[249]
H12 VSS[250]
H18 VSS[251]
H22 VSS[252]
H24 VSS[253]
H26 VSS[254]
H30
H32
H34
VSS[255]
VSS[256]
VSS[257]
INVENTEC
F3 VSS[258] TITLE
MODEL,PROJECT,FUNCTION
ITL_PANTHERPOINT_FCBGA_989P PCH - 9
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 34 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3AL
L516
20MA 1 2 P3V3AL_EC_VSTBY LID_SW# 38 47
SB_PWRBTN#
IN
OUT 28

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2

0.1uF_16V_2
P3V3S USBPWR_EN

1
OUT 47
BLM15AG121SN1D_500mA
1

C848

C796

C797

C817
2MA L515
TP24 TP306 CAPS_LED# 36
1 2 P3V3S_EC_VCC OUT

1
BLM15AG121SN1D_500mA

0.1uF_16V_2
2

2
HSPI_SI 26
HSPI_SO
OUT

C794
OUT 26
HSPI_CLK 26
HSPI_CS0#
OUT
OUT 26 P3V3S
P3V3S SB_PWRGD

2
OUT 28
1 R303 2
2 R822 1 1 R772 2 2.2K_5%_2
R821
D 1 2 100K_5%_2
10K_5%_2 R771

114
121

127
1 2 2.2K_5%_2 D

11

19
10K_5%_2

26
50
92

74

84
83
82

20

99
98
97
96
93
D528

3
U514
31 EC_SMI# 2 2 1 1 EC_SMI#_D 46 26 LPC_AD<0> 10 110 THM_CLK 23 50
OUT BI LAD0_GPM0_3_X SMCLK0_GPB3_X BI

VBAT
VSTBY
VSTBY
VSTBY
VSTBY
VSTBY

VSTBY

L80LLAT_WUI7_GPE7_UP
VCC

AVCC

EGCLK_WUI27_GPE3_DN
EGCS#_WUI26_GPE2_DN
EGAD_WUI25_GPE1_DN

L80HLAT_BAO_WUI24_GPE0_DN

HMOSI_GPH6_ID6_DN
HMISO_GPH5_ID5_DN
HSCK_GPH4_ID4_DN
HSCE#_WUI19_GPH3_ID3_DN
CLKRUN#_WUI16_GPH0_ID0_DN
46 26 LPC_AD<1> 9 111 THM_DAT 23 50
BI LPC_AD<2>
LAD1_GPM1_3_X SMDAT0_GPB4_X
BATT_CLK
BI
46 26 8 SM BUS 115 5 6
P3V3S 1SS355VMTE_17 BI LPC_AD<3>
LAD2_GPM2_3_X SMCLK1_GPC1_X
BATT_DAT
BI P5V0A
46 26 7 116 5 6
BI BUF_PLT_RST#
LAD3_GPM3_3_X SMDAT1_GPC2_X
R770 BI
46 30 17 22 117 EC_PECI 1 243_5%_2 H_PECI 17 31
P3V3S IN CLK_LPC_EC
LPCRST#_WUI4_GPD2_UP PECI_SMCLK2_WUI22_GPF6_3_UP IN
R998 30 13 118 SUS_PWR_DN_ACK 28
1 2 IN LPC_FRAME#
LPCCLK_GPM4_3_X SMDAT2_WUI23_GPF7_3_UP IN R318
46 26 6 1 2 10K_5%_2
D529 IN LFRAME#_GPM5_3_X
CORE_PWEN#
17
10K_5%_2 PS2CLK0_TMB0_GPF0_UP 85
OUT 15 1 R319 2 10K_5%_2
1 R767 2 RSMRST# 17 86 ODD_MD#

PS/2
EC_SCI# 2 1 EC_SCI#_D 28 OUT LPCPD#_WUI6_GPE6_DN PS2DAT0_TMB1_GPF1_UP IN 40
31 OUT 2 1
89 TP_CLK
10K_5%_2 PS2CLK2_WUI20_GPF4_UP BI 47 P3V3A
31 A20GATE 126 90 TP_DAT 47
OUT SERIRQ
GA20_GPB5_3_X PS2DAT2_WUI21_GPF5_UP BI
1SS355VMTE_17 26 5
P3V3AL BI SERIRQ_GPM6_3_X
D527 15 ECSMI#_GPD4_3_UP
23 LPC 1 R823 2
ECSCI#_GPD3_UP 10K_5%_2_DY
1 1 2 2 EC_RST# 14 WRST# GPIO R775
1 2 10K_5%_2_DY
31 KB_RST# 4
P3V3AL OUT CHG_LED
KBRST#_GPB6_3_X
35 16
1SS355VMTE_17 OUT PWUREQ#_BBO_SMCLK2ALT_GPC7_3_UP
R802
R766 1 2 24 PWR_LED# 36 47
1 2 PWM0_GPA0_UP
KB_BLON 1
OUT
PWM1_GPA1_UP 25
CPU_PROCHOT# TP305
C 100K_5%_2 100K_5%_2_DY PWM2_GPA2_UP 28
OUT 17 C
0.1uF_16V_2

ADP_SEL AC_LED
1

119 29 35
RESUME_PWEN
CRX0_GPC0_DN
CIR
PWM3_GPA3_UP
CPUFAN1_ON#
OUT
1

15 123 30 23
OUT CTX0_TMA0_GPB2_3_DN PWM4_GPA4_UP OUT
100K_5%_2

ADP_SEL : 31 EC_LCD_PWM 1
C792

PWM5_GPA5_UP
PU : 90W (SG) TP310
R769

PD : 65W (UMA)
DGPU_PWROK 80 PWM
2

56
52 31 IN DAC4_DCD0#_GPJ4_3_X
GPU_THROT# 104 47 FAN_TACH1
2

49 OUT DSR0#_GPG6_X TACH0A_GPD6_3_DN IN 23


28 SLP_S3# 33 48 ALL_PWGD_IN 15 17
IN RF_AMBER_LED#
GINT_CTS0#_GPD5_UP TACH1A_TMA1_GPD7_3_DN IN
36 88
OUT ME_FLASH_EN
PS2DAT1_RTS0#_GPF3_UP
26 81 120 ALWAYS_PW_EN 14
OUT ODD_PWEN#
DAC5_RIG0#_GPJ5_3_X
UART port
TMRI0_WUI2_GPC4_3_DN OUT
40 87 124 CPU_PWEN 15
OUT WOL_PWEN#
PS2CLK1_DTR0#_GPF2_UP TMRI1_WUI3_GPC6_3_DN OUT
41 109
P5V0A OUT TXD_SOUT0_GPB1_UP
47 TP_OFF_LED# 108
TO TP-LED BD ← OUT RXD_SIN0_GPB0_UP
470_5%_2

BATT_IN# 125 EC_PWRBTN#


1

6 71 47
IN I_ADP
ADC5_DCD1#_WUI29_GPI5_3_X PWRSW_GPE4_3_UP
1
IN
5 72 18 QWEB#
IN ADC6_DSR1#_WUI30_GPI6_3_X RI1#_WUI0_GPD0_3_UP
R10

AC_OK 73 21 SLP_S4#
TP309 P3V3AL
5 IN ADC7_CTS1#_WUI31_GPI7_3_X RI2#_WUI1_GPD1_UP IN 28
5 ADP_PRES 35 WAKE UP
IN RF_WHITE_LED#
RTS1#_WUI5_GPE5_DN
36 34
OUT1 ADP_EN
PWM7_RIG1#_GPA7_UP
107 112 CORE_PWEN
3 2

OUT 14 15 21

10K_5%_2_DY

10K_5%_2_DY
DTR1#_SBUSY_GPG1_ID7_DN RING#_PWRFAIL#_CK32KOUT_LPCRST#_GPB7_DN
CHG_LED#

1
OUT 5 TP308 PCH_THM_SMDAT 95
27 BI CTX1_WUI18_SOUT1_GPH2_SMDAT3_ID2_DN
27 PCH_THM_SMCLK 94
BI CRX1_WUI17_SIN1_SMCLK3_GPH1_ID1_DN

R845

R828
B Q102 B
ITE_ITE8517E_G_LQFP_128P
D

35 EC_SPI_CLK 105
35 IN CHG_LED 1 G OUT EC_SPI_CS0#
FSCK
35 101
OUT FSCE#

2
EC_SPI_SI 102 EXTERNAL SERIAL FLASH
35 OUT FMOSI
S

35 EC_SPI_SO 103 66 MB_ID0 35 35 MB_ID0


SSM3K7002FU IN FMISO ADC0_GPI0_3_X
MB_ID1
IN OUT
67 35
P5V0A ADC1_GPI1_3_X IN MB_ID1
2

1 KSO16 56 68 1 35 OUT
KSO16_SMOSI_GPC3_3_DN ADC2_GPI2_3_X

1
TP300 1 KSO17 57 69 THERMTRIP# TP307

10K_5%_2

10K_5%_2
KSO17_SMISO_GPC5_3_DN ADC3_GPI3_3_X IN 49
23
TP301
560_5%_2

1 CORE_PWEN_D# ADP_ID
1

32 70 5
PWM6_SSCK_GPA6_UP ADC4_WUI28_GPI4_3_X IN

R844

R824
TP311
R14

31 PCI_SERR# 100 A/D D/A


OUT1 SSCE0#_GPG2_X
SPI ENABLE
106 SSCE1#_GPG0_X
TP303

2
76 AMP_EN 44
SCAN_OUT<0>
TACH2_GPJ0_3_X
WWAN_IND# 1
OUT
36 77
3 2

AC_LED# OUT 5
36 OUT SCAN_OUT<1> 37
KSO0_PD0 GPJ1_3_X
78 BT_IND 1 TP302 P3V3S
36 OUT KSO1_PD1 DAC2_TACH0B_GPJ2_3_X
SCAN_OUT<2> 38 79 WLAN_IND# TP304
36 OUT KSO2_PD2 DAC3_TACH1B_GPJ3_3_X IN 46
Q103 SCAN_OUT<3> 39
36 OUT KSO3_PD3
D

SCAN_OUT<4> 40 1 2 10K_5%_2
35 IN AC_LED 1 G
36 OUT SCAN_OUT<5> 41
KSO4_PD4 R708
1 2 10K_5%_2
36 OUT KSO5_PD5 R324
SCAN_OUT<6> 42 KBMX
36 OUT KSO6_PD6
S

36 SCAN_OUT<7> 43
SSM3K7002FU OUT SCAN_OUT<8>
KSO7_PD7
36 44
OUT KSO8_ACK#
2

36 SCAN_OUT<9> 45
OUT KSO9_BUSY
DB SI PV MV
36 SCAN_OUT<10> 46
A OUT SCAN_OUT<11>
KSO10_PE
A
36 51 2
OUT SCAN_OUT<12>
KSO11_ERR#
CLOCK
CK32KE_GPJ7_3_X
MB_ID0 0 1 0 1
KSI3_SLIN#

52 128
KSI1_AFD#
KSI0_STB#

KSI2_INIT#

36 OUT KSO12_SLCT CK32K_GPJ6_3_X


36 SCAN_OUT<13> 53
OUT KSO13
MB_ID1 0 1

VCORE
36 SCAN_OUT<14> 54 AVSS
0 1
P3V3AL OUT KSO14
KSI4
KSI5
KSI6
KSI7

1
VSS

VSS
VSS
VSS
113
122

36 SCAN_OUT<15> 55
C798 OUT KSO15

0_5%_2

0_5%_2
P3V3AL EC ROM 1MB

R14102

R14103
2 1
P/N :????????????
58
59
60

62
63
64
65

27
49

113
122

75

1 12
61

91

0.1uF_16V_2
0.1uF_16V_2

2
INVENTEC
R777 36 SCAN_IN<0>
1 2 IN
C816

U511 36 SCAN_IN<1>
EC_SPI_CS0# 1 8
IN SCAN_IN<2>
35 IN CE# VDD 3.3K_5%_2 36 IN
2 7
35 OUT EC_SPI_SO SO HOLD# 36 IN SCAN_IN<3>
1 2 3 6 EC_SPI_CLK SCAN_IN<4> TITLE
2

WP# SCK IN 35 36 IN
4 5 EC_SPI_SI 35 36 SCAN_IN<5> MODEL,PROJECT,FUNCTION
VSS SI IN IN SCAN_IN<6> ITE8517
R773 36 IN
3.3K_5%_2 ACES_91960_0084L_8P 36 SCAN_IN<7> DOC.NUMBER REV
IN SIZE CODE
6026B0150101 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 35 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3A
POWER LED
KeyBoard CONN(30 pin) LED_SINGLE_3PIN_B

1
100_5%_2
NC

R117
CN508
35 SCAN_IN(1) 1 D534
OUT 1
SCAN_IN(7) 2

NC
35 OUT 2
D SCAN_IN(6) 3 R1078

2
35 OUT SCAN_OUT(9) 4
3
47 35 IN PWR_LED#1 1 2 2 1 2 D
35 IN 4
SCAN_IN(4) 5 360_5%_2
35 OUT 5
35 SCAN_IN(5) 6
OUT SCAN_OUT(0) 7
6
EVL_12_21_T3D_CP1Q2B12Y_2C_2P
35 IN 7
35 SCAN_IN(2) 8 6011B0115101
OUT SCAN_IN(3) 9
8
35 OUT 9
35 SCAN_OUT(5) 10
IN SCAN_OUT(1) 11
10
35 IN 11
35 SCAN_IN(0) 12
OUT SCAN_OUT<2> 13
12
35 IN 13
35 SCAN_OUT<4> 14
IN SCAN_OUT<7> 15
14
35 IN 15
35 SCAN_OUT<8> 16
IN 16
35
35
IN
IN
SCAN_OUT<6>
SCAN_OUT<3>
17
18
17
18
SATA LED & HDD HALTED LED
35 SCAN_OUT<12> 19
IN SCAN_OUT<13> 20
19
35 IN 20
35 SCAN_OUT<14> 21
IN SCAN_OUT<11> 22
21
P5V0S
35 IN 22
P3V3S 35 SCAN_OUT<10> 23
IN SCAN_OUT<15> 24
23
WHITE

NC
35 IN 25
24
ESD U547
25 P3V3S

5
C 26 26 TC7SET08FU D533 C
27

NC
27 LED_SATA# 1

+
CAPS_LED# 1 R810 2 100_5%_2 28 26 IN
35 IN 28 4 1 2 1 R1059 2
29 G2 1 2
29 G 2
RF_W_LED#_AND R815 2 150_5%_2 30 G1
36 IN 1 30 G 330_5%_2

-
36 RF_LED#_AND 1 2 31
IN 32
31
150_5%_2 32 EVL_12_21_T3D_CP1Q2B12Y_2C_2P

3
R814
ACES_50690_0324N_001_32P 6011B0115101
6012B0372601
P5V0S
R118
C790
1 2
2 1
0_5%_2_DY
5

0.1uF_16V_2
U512
1
+

4 RF_LED#_AND 36
RF_AMBER_LED# 2
OUT
35 IN
-

TC7SET08FU
B B
3

P5V0S
C791
2 1
5

0.1uF_16V_2
U513
1
+

4 RF_W_LED#_AND 36
RF_WHITE_LED# 2
OUT
35 IN
-

TC7SET08FU
3

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
KB CONN & LED
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 36 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

0_5%_2_DY
1 R717 2 CRT_R CRT_R 2 R1107 1 GPU_CRT_R
37 OUT IN 49
75_1%_2_DY
0_5%_2_DY
P5V0S_CRTVDD CRT_G 2 R1109 1 GPU_CRT_G
P5V0S 37 OUT IN 49
1 R718 2 CRT_G 0_5%_2_DY
U3050 CRT_B 2 R1108 1 GPU_CRT_B
75_1%_2_DY 37 OUT IN 49
5 1

10uF_6.3V_5
IN OUT 33_5%_2_DY

1
2 CRT_HSYNC 2 R1106 1 GPU_CRT_HSYNC
GND P3V3S 1 R715 2 CRT_B 37 OUT IN 49
1

C3051
4 3
1uF_6.3V_2

DIS EN
75_1%_2_DY 33_5%_2_DY
C3050

CRT_VSYNC 2 R1100 1 GPU_CRT_VSYNC


37 OUT IN 49
NUVO_NCT3521U_SOT23_5P R3050
1 2 0_5%_2_DY

2
PCH_CRT_R_CLK 2 R1105 1 GPU_CRT_CLK
D 1K_5%_2 BI 49
2

0_5%_2_DY
D
PCH_CRT_R_DAT 2 R1101 1 GPU_CRT_DAT BI 49

PCH_CRT_R 1 L512 2 CRT_R


29 IN OUT 37
FBM_10_160808_300T
PCH_CRT_G 1 L511 2 CRT_G
29 IN OUT 37
FBM_10_160808_300T P5V0S_CRTVDD
PCH_CRT_B 1 L513 2 CRT_B
29 IN OUT 37
FBM_10_160808_300T P5V0S P5V0S P5V0S
R719 1

R714 1

R716 1

1
12pF_50V_2

12pF_50V_2

12pF_50V_2

12pF_50V_2

12pF_50V_2

12pF_50V_2
150_1%_2

150_1%_2

150_1%_2

C692

C694

C693

2
C691

C690

C689
CN502
37 CRT_R 1
IN 1

D521

D519

D520
37 CRT_G 2
IN 2
2

2
3 3 3 37 CRT_B 3
IN 4
3
4

BAV99_DY

BAV99_DY

BAV99_DY
5 5
C 6 6
C
7 7

1
8 8
9 9
10 10
11 11
37 CRT_DAT 12 G1
P3V3S BI CRT_HSYNC_CN 13
12 G
G2
37 IN 13 G
37 CRT_VSYNC_CN 14
IN CRT_CLK 15
14
37 BI 15
C674
1
100K_5%_2

2 1 SUYIN_070546HR015M251ZR_15P
R671

1uF_6.3V_2 6012B0318901
2
1
5

+
5

29 PCH_CRT_VSYNC
2 4 CRT_VSYNC 37
IN 2 4 OUT
3

U506
-
TC7SZ126FU
B P3V3S P5V0S_CRTVDD B
3

1 R722 2
1 R720 2
2.2K_5%_2
P3V3S R672
2.2K_5%_2
1 2
C695 2.2K_5%_2 1 R721 2
2 1
2.2K_5%_2
1
5

1uF_6.3V_2 + R1112
29 BI PCH_CRT_CLK 1 2 PCH_CRT_R_CLK 2 3 CRT_CLK
BI 37
5

S D

SSM3K7002FU
29 PCH_CRT_HSYNC
2 4 CRT_HSYNC 37
IN 2 4 OUT 0_5%_2

G
U507

Q527
3

- TC7SZ126FU

1
3

R1111
29 BI PCH_CRT_DAT 1 2 PCH_CRT_R_DAT 2 S D 3 CRT_DAT
BI 37

C1

C2
SSM3K7002FU
0_5%_2
D518

Q528
33_5%_2

1
CRT_HSYNC R713 CRT_HSYNC_CN
A 37 IN 1 2
OUT 37
CHENMKO_CHPZ6V2_3P_DY
A

A
37 CRT_VSYNC 1 2 CRT_VSYNC_CN 37
IN OUT
C1

C2

R670 33_5%_2
D517

CHENMKO_CHPZ6V2_3P_DY

INVENTEC
A

TITLE
MODEL,PROJECT,FUNCTION
CRT CONN
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 37 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P3V3S_LCDVDD
P3V3S P3V3S_LCDVDD
C557
2 1

1
4.7uF_6.3V_3
0.1uF_16V_2

C572

2.2K_5%_2

2.2K_5%_2
R572 1

1
D
P3V3A D

R571
2
U501
CN503
1 1
5 1

2
IN OUT
2 2
GND 2
3
PCH_LCDVDD_EN 3
1

4 3 29
DIS EN IN 29 PCH_LCD_CLK 4
1uF_6.3V_2

BI PCH_LCD_DAT
4
5
C599

29 BI 5
NUVO_NCT3521U_SOT23_5P 6 6

R597 1
100K_5%_2
29 PCH_LCD_TXA0_DN 7
IN PCH_LCD_TXA0_DP
7
29 8
IN 8
2

9 9
29 PCH_LCD_TXA1_DN 10
P3V3S_LCDVDD IN 10
29 PCH_LCD_TXA1_DP 11
IN 11

2
12 12
29 PCH_LCD_TXA2_DN 13
IN PCH_LCD_TXA2_DP
13
R595 29 14
1 2 IN 14
15 15
100_5%_3 PCH_LCD_TXACL_DN
29 16
IN PCH_LCD_TXACL_DP
16
29 17
IN 17
1000PF_50V_2_DY 18 18
19 19
2 1
PVBAT_LCD 20 20
C 29 PCH_LCD_PWM C596 21 C
IN LCD_BKEN
21
38 22
IN 22
23 23
24
P3V3S 24
25 25
38 USB_P5_R_DN 26
USB_P5_DN
IN USB_P5_R_DP
26

1
30 IN R2250 1 2 0_5%_2USB_P5_R_DN
OUT 38 38 IN 27 27 G G1

4.7uF_25V_5
WEBCAM 30 IN USB_P5_DP R2251 1 2 0_5%_2USB_P5_R_DP
OUT 38 28 28 G G2
DMIC_CLK 29

10uF_6.3V_5
44 38 IN 29

1
C597
44 38 DMIC_CLK 38 DMIC_DAT_CN 30
IN DMIC_DAT
OUT OUT 30
R626 1 2 33_5%_2

C592
44 DMIC_DAT_CN 38
OUT OUT ACES_50203_03001_001_30P

2
6012B0431201
1 CSC0402_DY

1 CSC0402_DY

1 CSC0402_DY

2
2 2 3
3
IO IO

P5V0S
C1026

C2252

2 C2253

1 1 4 4
GND Vcc
PHP_PRTR5V0U2X_SOT143_4P_DY
B B
2

D511

PVBAT PVBAT_LCD

PAD508
1 1 2
2

POWERPAD1x1m
2 S D 3

AO3409_DY
0.22UF_16V_DY
R623 1
20K_5%_2_DY

Q511
2

C591
D503

1
NC

47 35 IN LID_SW# 3 1 LCD_BKEN OUT 38


2

2
DIODE-BAT54-TAP-PHP
PCH_LCD_BKEN 1 R628 2
29 IN
A A
R622 1

3K_5%_2
10K_5%_2_DY
R627 1
100K_5%_2

2
2

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
LCD CONN
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 38 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
D

P0V0S_HDMI
P5V0S_CRTVDD
3

Q542
D

1 G R780 1 2 680_5%_2
R784 1 2 680_5%_2
S

R785 1 2 680_5%_2
SSM3K7002FU 1 2 CN509
R781 680_5%_2 HDMI_TX2_C_DP 1
1 R833 2 1 2 680_5%_2
39 IN 1
2

R782 2 G1
2 GND
100K_5%_2 R783 1 2 680_5%_2
39 HDMI_TX2_C_DN 3 G2
R829 1 2 680_5%_2 IN HDMI_TX1_C_DP 4
3 GND
G3
C 1 2 680_5%_2
39 IN 4 GND C
R830 5 G4
5 GND
39 HDMI_TX1_C_DN 6
IN HDMI_TX0_C_DP 7
6

PCH_HDMI_TX2_DP HDMI_TX2_C_DP 39 IN 7
29 IN C824 1 20.1uF_16V_2
OUT 39 8 8
29 PCH_HDMI_TX2_DN C823 1 20.1uF_16V_2 HDMI_TX2_C_DN 39 39 HDMI_TX0_C_DN 9
IN OUT IN HDMI_TXCL_C_DP 10
9

PCH_HDMI_TX1_DP HDMI_TX1_C_DP 39 IN 10
29 IN C803 1 20.1uF_16V_2
OUT 39 11 11
29 PCH_HDMI_TX1_DN C804 1 20.1uF_16V_2 HDMI_TX1_C_DN 39 39 HDMI_TXCL_C_DN 12
IN OUT IN 13
12
13
29 PCH_HDMI_TX0_DP C799 1 20.1uF_16V_2 HDMI_TX0_C_DP 39
IN OUT P5V0S_CRTVDD 14 14
29 PCH_HDMI_TX0_DN C801 1 20.1uF_16V_2 HDMI_TX0_C_DN 39 39 HDMI_CLK 15
IN OUT BI HDMI_DAT 16
15

PCH_HDMI_TXCL_DP HDMI_TXCL_C_DP 39 BI 16
29 IN C800 1 20.1uF_16V_2
OUT 39 17 17
29 PCH_HDMI_TXCL_DN C802 1 20.1uF_16V_2 HDMI_TXCL_C_DN 39 18
IN OUT HDMI_HPD 19
18
29 OUT 19

1
4.7uF_6.3V_3
FOX_QJ1119L_NV32_7H_19P

C12718
6012B0335901
P5V0S_CRTVDD

3
D526 BAV99_DY

2
2 1
B B

P3V3S P5V0S_CRTVDD

D525 3 BAT54A

1 R746 2 1 R778 2 1 2
2.2K_5%_2 2.2K_5%_2

1 R787 2 1 R779 2
2.2K_5%_2 2.2K_5%_2

29 PCH_HDMI_CLK 2 3 HDMI_CLK 39
BI S D BI
SSM3K7002FU

Q536
G

A A
1

29 PCH_HDMI_DAT 2 3 HDMI_DAT 39
BI S D BI
SSM3K7002FU

Q533
G
1

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
HDMI CONN
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 39 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P5V0S
SATA HDD CABLE CONN on MB
CN525
1 1
2 2

1
3

22uF_6.3V_5

0.1uF_16V_2
3
D

C1008

C1007
4 4
5 5
D
6 6
7 7

2
8 8
9 9
10 10
11 11
12 12
13 13
14 14
26 SATA_HDD_RX_DP C971 1 2 0.01uF_50V_2 SATA_HDD_RX_C_DP 15
OUT SATA_HDD_RX_DN C972 1 2
15
26 0.01uF_50V_2 SATA_HDD_RX_C_DN 16
OUT 16
17 17 G G1
26 SATA_HDD_TX_DN C970 1 2 0.01uF_50V_2 SATA_HDD_TX_C_DN 18 G2
IN SATA_HDD_TX_DP C969 1 2
18 G
26 0.01uF_50V_2 SATA_HDD_TX_C_DP 19 G3
IN 19 G
20 20 G G4
FOX_GS12201_1011_9H_20P

6012B0238201

C C

SATA ODD CABLE CONN on MB


P5V0S_ODD P3V3S
P15V0A P5V0A P5V0S_ODD
1 R819 2
10K_5%_2
CN514

22uF_6.3V_5

0.1uF_16V_2
ODD_MD#
1

1
35 IN 1
2 2

C814

C815
3
560K_1%_2
B Q540 3 B
1

1 D S 4 4 4
2 5
1 R818 5
R820

2
5 6

2
6
6 3 1K_5%_2 7
G 7
NMOS_4D1S
31 ODD_PRSNT# 1 R843 2 8
OUT 8
2

FDC655BN 0_5%_2_DY 9 9
10 10
11 11
1
3

12
0.1uF_25V_2

12
Q541 13 13
C813
D

14 14
35 ODD_PWEN#
1 G
IN 26 OUT SATA_ODD_RX_DP C847 1 2 0.01uF_50V_2SATA_ODD_RX_C_DP 15 15
26 SATA_ODD_RX_DN C846 1 2 0.01uF_50V_2 SATA_ODD_RX_C_DN16
OUT 16
S

SSM3K7002FU 17 17 G G1
26 SATA_ODD_TX_DN C854 1 2 0.01uF_50V_2SATA_ODD_TX_C_DN 18 G2
IN 18 G
2

26 SATA_ODD_TX_DP C844 1 2 0.01uF_50V_2 SATA_ODD_TX_C_DP 19 G3


IN 20
19 G
G4
20 G

FOX_GS12201_1011_9H_20P

6012B0238201

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SATA HDD & SATA ODD
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 40 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P1V0_LAN
R412 200_5%_2
P3V3A_LAN
CLOSE TO LAN CHIP
1 2 P1V0_LAN_REG PIN3 PIN9 PIN13 PIN29 PIN41 PIN45
Q400 P3V3A RISING TIME (10%~90%) MUST >1MS AND <100MS
PIN6

3
SSM3K7002FU P3V3A
Q401
0.5A CLOSE TO LAN CHIP

1
D
AM2321P
PIN12 PIN27 PIN39 PIN42 PIN47 PIN48

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2
1 G L400

C406

C409

C411

C412

C413

C415

C418
S D 1 2
2

S
3
SWF2520CF_2R2M_R15_DY

4.7UF_6.3V_3_DY
2

0.1UF_16V_2_DY
G

2
0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2
1

1
PAD401 P3V3_LAN_REG LDO MODE(RTL8165EH)

1
35 WOL_PWEN# 1 2

C414

C416

C419

C421

C422

C423
IN

C404

C405
1 2 L400,C404,C405 OPEN
D

1
1 2
R411

0.1UF_16V_2
D

0.1UF_16V_2_DY
750K_1%_2

C408

4.7UF_6.3V_3_DY
POWERPAD1X1M X5R
P1V0_LAN_EVDD

2
C417

C420
PAD400

1
LDO MODE(RTL8165EH)
PAD401,C417,C420 OPEN 1 2
1 2

2
C407 , C410
POWERPAD1X1M CLOSE TO

0.1UF_16V_2
2X5R

1UF_16V_3
RTL8165EH

1
PIN21

C407

C410
2

2
R414
16 IN LAN_25M_IN 1 2 XTAL2 XTAL1
0_5%_2 P1V0_LAN

P3V3A_LAN
C402 27PF_50V_2_DY P3V3A_LAN
C C
2 1 XTAL2 P1V0_LAN RTL8161FH(10/100/1000) / RTL8165EH(10/100)
LED_LANRXACT# OUT 42
P3V3A_LAN MOUNT OPEN PART
2
3

X400 GPO_SMBALERT OUT 41


R406
25MHZ_DY
2.49K_1%_2 LED_LANLINK# OUT 42
LDO MODE R408 (0V) L400,PAD401,R407
MOUNT R407, OPEN R4078
6018B0044501_DY
1 2
ENABEL SWITCHING REGULATOR
(ONLY 10/100) C404,C405,C417,C420
SWITCHING
4
1

P3V3_LAN_REG
MOUNT R408, OPEN R407 L400,PAD401,R407
2 1 XTAL1
DISABEL SWITCHING REGULATOR MODE C404,C405,C417,C420 R408
41
49
48
47
46
45
44
43
42
40
39
38
37

P1V0_LAN_REG

0_5%_2_DY
C403 27PF_50V_2_DY MOUNT R408, OPEN R407

2
ENABLE LDO REGULATOR
P1V0_LAN
TML
AVDD33
AVDD33
RSET
AVDD10
CKXTAL2
CKXTAL1
NC
NC
LED0
DVDD33
GPO
EESK_LED1

(ONLY 10/100)

R407
RTL8165EH 3.3V:ENABLE SWITCHING REGULATOR
OR EXTERNAL 1.05V INPUT MODE.
P3V3A_LAN (10/100)

1
42 IN LAN_TRD0_DP 1 MDIP0 REGOUT 36
2 R408 1 0V:ENABLE LDO REGULATOR
42 IN LAN_TRD0_DN 2 MDIN0 VDDREG 35
3 34
42 OUT LAN_TRD1_DP 4
NC
MDIP1
U400 VDDREG
ENSWREG 33
0_5%_2 P3V3S
RTL8161FH 3.3V:ENABLE SWITCHING REGULATOR
42 OUT LAN_TRD1_DN 5 32 EEDI_SDA 1 2
B 6
MDIN1
NC
EEDI
EEDO_LED3 31 R4031 10K_5%_2
(10/100/1000) 0V:DISABLE SWITCHING REGULATOR B
LAN_TRD2_DP 7 30 EECS_SCL 1 2
42
42
IN
IN LAN_TRD2_DN 8
NC
NC
RTL8165EH EECS
DVDD10 29 R404 10K_5%_2
9 NC LANWAKEB 28 PCIE_WAKE# OUT 28 41 46
42 OUT LAN_TRD3_DP 10 NC DVDD33 27
42 LAN_TRD3_DN 11 26 R4091 2 1K_1%_2
OUT NC ISOLATEB
12 NC PERSTB 25 PLT_RST# IN 30 43 48
2 15K_1%_2
REFCLK_N
REFCLK_P

R4101
CLKREQB
DVDD10

EVDD10

P3V3A_LAN
HSON
HSOP

REA_RTL8165EH_VB_CGT_QFN_48P
HSIN
HSIP

GND
NC
NC

20
21
22
23
24
13
14
15
16
17
18
19

P1V0_LAN
RTL8161FH = 6019B0928101(10/100/1000)
RTL8165EH = 6019B0928301(10/100)
1
TP400 TP30

P1V0_LAN_EVDD

1 2
R405 10K_5%_2 P3V3A_LAN
A 41 27 OUT CLKREQ_LAN# A
41 27 OUT CLKREQ_LAN# 1 2
27 IN PCIE_LAN_TX_C_DP R4001 10K_5%_2
27 IN PCIE_LAN_TX_C_DN
46 41 28 OUT PCIE_WAKE# 1 2
CLK_PCIE_LAN_DP R4011 10K_5%_2
27 IN
27 IN CLK_PCIE_LAN_DN
C400 0.1UF_16V_2 41 GPO_SMBALERT 1 2
OUT
PCIE_LAN_RX_C_DP
INVENTEC
27 2 1 PCIE_LAN_RX_DP R4021 1K_1%_2_DY
OUT
27 OUT PCIE_LAN_RX_C_DN 2 1 PCIE_LAN_RX_DN IF THERE ARE NO OTHER APPLICATION, REMOVE R402

C401 0.1UF_16V_2
TITLE
C401, C400 CLOSE TO LAN CHIP PIN 22, 23 MODEL,PROJECT,FUNCTION
LAN

DOC.NUMBER REV
SIZE CODE
1310xxxxx-0-0 X01
A3 CS
CHANGE by DATE SHEET 41 of 57
XXX 21-OCT-2002
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U470 FOR GIGALAN


D
U502 FOR 10/100 LAN D

1 U470 24
TCT1 MCT1
41 OUT LAN_TRD0_DN 3 TD1- MX1- 22 LAN_TRD0_CN_DN IN 42
41 OUT LAN_TRD0_DP 2 TD1+ MX1+ 23 LAN_TRD0_CN_DP IN 42
4 TCT2 MCT2 21
41 IN LAN_TRD1_DN 6 TD2- MX2- 19 LAN_TRD1_CN_DN OUT 42
41 IN LAN_TRD1_DP 5 TD2+ MX2+ 20 LAN_TRD1_CN_DP OUT 42
7 TCT3 MCT3 18
41 OUT LAN_TRD2_DN 9 TD3- MX3- 16 LAN_TRD2_CN_DN IN 42
41 OUT LAN_TRD2_DP 8 TD3+ MX3+ 17 LAN_TRD2_CN_DP IN 42
10 TCT4 MCT4 15
41 IN LAN_TRD3_DN 12 TD4- MX4- 13 LAN_TRD3_CN_DN OUT 42
41 IN LAN_TRD3_DP 11 TD4+ MX4+ 14 LAN_TRD3_CN_DP OUT 42

2
75_5%_2

75_5%_2

75_5%_2

75_5%_2
BOTH_GSL5009_1_LF_24P_DY

R470

R471

R472

R473
6016B0010401_DY

C C

1
1 U502 16
RD+ RX+
C470

1 1

1
2 RD- RX- 15
0.01UF_50V_2 3 CT1 CT4 14
4 NC1 NC4 13
2 5 NC2 NC3 12 C471
CAP VALUE SHOULD BE 6 CT2 CT3 11
1000PF_2000V_6
7 TD+ TX+ 10
0.01UF ~ 0.4UF 8 9

2
TD- TX-

BOTH_NS0014_LF_16P
6016B0008101

B B

JACK500 P3V3A_LAN
42 OUT LAN_TRD0_CN_DP 1 1
42 OUT LAN_TRD0_CN_DN 2 2
LAN_TRD1_CN_DP 3 G1 R731
42 IN 3 G1
LAN_TRD2_CN_DP 4 G2 510_5%_2
42 OUT 4 G2
42 OUT LAN_TRD2_CN_DN 5 5 A1 A1 LED_R_LANLINK# 1 2 LED_LANLINK# IN 41
42 IN LAN_TRD1_CN_DN 6 6 A2 A2
42 IN LAN_TRD3_CN_DP 7 7 B1 B1 LED_R_LANRXACT# 1 2 LED_LANRXACT# IN 41
42 IN LAN_TRD3_CN_DN 8 8 B2 B2
R745
SANTA_130452_06_8P 510_5%_2

6026B0200401

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
RJ45 & TRANSFORMER
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 42 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

★RTS5239GR = 6019B0928001

1000PF_50V_2
1
RTS5229GR = 6019B0900701
P1V8S_CARD

C701

1
0.1uF_16V_2
2

C716
PLT_RST# SD_CD#

2
48 41 30 IN IN 43

27 CLKREQ_CR# SD_WP 43 P3V3S


OUT IN
D
R119 D
1 2
10K_5%_2

19
25
24
23
22
21
20
ZDIFF : 100 OHM U532

TML
CLKREQ#
PERST#
MS_INS#
SD_CD#
SP7
GPIO
27 PCIE_CR_TX_C_DP 1 18 SD_DATA2_R R701 1 2 0_5%_2 SD_DATA2 43
IN 2
HSIP SP6
17 SD_DATA3_R
BI
27 IN PCIE_CR_TX_C_DN HSIN SP5 R702 1 2 0_5%_2 SD_DATA3
BI 43
27 CLK_PCIE_CR_DP 3 16 SD_CMD_R R706 1 2 0_5%_2 SD_CMD 43
IN 4
REFCLKP SP4
15 P1V8S_CARD
BI
27 CLK_PCIE_CR_DN
IN 0.1uF_16V_2 5
REFCLKN DV33_18
14 SD_CLK_R R7031 1 2 0_5%_2 SD_CLK

CARD_3V3
C702 HSOP SP3 OUT 43
2 1 PCIE_CR_RX_DP 6 13 SD_DATA0_R R704 1 2 0_5%_2 SD_DATA0

DV12_S
HSON SP2 BI 43

3V3_IN
RREF
PCIE_CR_RX_C_DP

AV12
27 OUT

SP1

1
CSC0402_DY
27 PCIE_CR_RX_C_DN 2 1 PCIE_CR_RX_DN
OUT

C7091
C703 0.1uF_16V_2
REALTEK_RTS5239_GR_QFN_24P

7
8
9
10
12
11
P1V2_CR

2
4.7uF_6.3V_3
1

1
0.1uF_16V_2
1 R700 2

C704
C C

C713
6.2K_1%_2 SD_DATA1_R 1 2 SD_DATA1
BI 43
R705 0_5%_2
P3V3S

2
2
100MA
C7111
P1V2_S_CR

1
2 1

10uF_6.3V_5
0.1uF_16V_2

C7061
4.7uF_6.3V_3

C705
C7101
2 1

2
0.1uF_16V_2

P3V3S_CR

800MA

B B

CN523
43 SD_DATA3 1 G1
BI DAT3 GND

P3V3S_CR 43 SD_CMD 2 G2
BI CMD GND

3 VSS CD_WP_COM 12
800MA
4 11 SD_CD# 43
VDD CD OUT
43 SD_CLK 5 10 SD_WP 43
IN CLK WP OUT
1
10uF_6.3V_5

6 9
C1050

SD_DATA2 43
VSS DAT2 BI
43 SD_DATA0 7 8 SD_DATA1 43
BI DAT0 DAT1 BI
PLAS_CS1S_125_14P
2

6026B0103603

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
CARD READER
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 43 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

44 SPKR_L_DP
OUT
44 SPKR_L_DN
OUT
44 SPKR_R_DN
OUT P5V0S_PVDD_AUDIO C500,C503
44 SPKR_R_DP
OUT PLACE NEST TO PIN 38
P5V0S
1A P5V0S_PVDD_AUDIO
35 AMP_EN
OUT P5V0S_AUDIO_AVDD
L3
1 2
P3V3S
MPZ1608S221AT

X5R

1
1
R503

10uF_10V_5

0.1uF_16V_2
4.7UF_10V_3
1 2
P5V0S_AUDIO_AVDD

0.1uF_16V_2
D

C521

C522

C523
0.1uF_16V_2
44 38 DMIC_DAT P3V3S 10K_5%_2_DY
IN D

C500
33.5 MA

C503
DMIC_CLK C501,C502
44 38 OUT PLACE NEXT TO PIN 1 5 MA

2
10pF_50V_2_DY

10pF_50V_2_DY
1

2
1UF_6.3V_2
1
1

49
48
47
46
45
44
43
42
41
40
39
38
37
C507

C508

0.1uF_16V_2
PIN39 PIN39 PIN46

C502

C501
2

TML

SPDIFO

EAPD/COMBO_JACK

PVDD2

SPK-R+

SPK-R-

PVSS2

PVSS1

SPK-L-

SPK-L+

PVDD1

AVDD2

AVSS2
2

2
C506 2.2uF_6.3V_3
1 DVDD1 CBP 36 2 1
R513
1 2 44 38 DMIC_DAT 2 35 X5R
IN GPIO0/DMIC-DATA CBN

4.7K_5%_2_DY R502 2 C512 2.2uF_6.3V_3


44 38 DMIC_CLK 1 3 34 2 1
OUT GPIO1/DMIC-CLK CPVEE
33_5%_2
X5R INT-SPKR CONN CN526
44 26 IN HDA_RST# 4 33 HP_R OUT 45
PD#
U528 HP-OUT-R
44 SPKR_L_DP 1
IN 1
26 IN HDA_SDO 5 SDATA-OUT HP-OUT-L 32 HP_L OUT 45 44 IN SPKR_L_DN 2 2
C 44 SPKR_R_DN 3 G1 C
R500 2 C505 HDA_BITCLK_CODEC
REALTEK_ALC3201_GRT_MQFN_48P IN 3 G1
26 IN HDA_BITCLK 1 6 BIT-CLK MIC1-VREFO-L 31 MIC_REF-L OUT 45 44 IN SPKR_R_DP 4 4 G2 G2

22_5%_2 2 1
7 DVSS2 MIC1-VREFO-R 30 MIC_REF-R OUT 45
ACES_50224_0040N_001_4P
R501 2 CSC0402_DY 6012B0069911
26 HDA_SDIN0 1 HDA_SDIN0_CODEC 8 29
OUT SDATA-IN MIC2-VREFO
C514 10uF_6.3V_5
22_5%_2 9 28 2 1
DVDD-IO LDO-CAP
C524
26 HDA_SYNC 10 27 X5R 1000PF_50V_2
IN SYNC VREF
2 1
SPKR_L_DP

1UF_6.3V_2
1

1
HDA_RST# 11 26 C513,C515

0.1uF_16V_2
44 26 IN RESET# AVSS1
R506

C513
C516 PLACE NEXT TO PIN 27

C515
C504 1 2 2 1 12 PCBEEP AVDD1 25
2 1 SPKR_L_DN 2 1
4.7K_5%_2_DY

MONO-OUT
1K_5%_2 0.1uF_16V_2
2

2
2
LINE2-R

LINE1-R
Sense A

Sense-B
CSC0402_DY C525

LINE2-L

LINE1-L
MIC2-R

MIC1-R
MIC2-L

MIC1-L
JDREF
1000PF_50V_2
R505

C526
26 PCSPKR DIGITAL P5V0S_AUDIO_AVDD 1000PF_50V_2
IN 2 1
(INCLUDE THERMAL PAD) SPKR_R_DN
1

B 33.5 MA B
13
14
15
16
17
18
19
20

22
23
24
21
ANALOG
SPKR_R_DP 2 1

4.7UF_10V_3
MOAT 40MIL

1
1

0.1uF_16V_2
C519,C520 C527

C520
PLACE NEXT TO PIN 25 1000PF_50V_2

C519
2
20K_1%_2
R512

2
2
R512
1

SENSE_A PLACEMENT
NEAR
CODEC
MIC_R 45
IN
MIC_L 45
IN

P5V0S_AUDIO_AVDD PAD500
P5V0S 1 2
A 33.5 MA 1 2 A
R509 L500 POWERPAD_2_0610
45 IN HPS 1 2 1 2
BLM18PG600SN1D
39.2K_1%_2 SENSE_A

10UF_10V_5
500MA_0603

1uF_6.3V_2

1
1
MICS 1 R510 2
45 IN
C509

C511
20K_1%_2

R509,R510
INVENTEC
2

2
PLACEMENT NEAR
CODEC TITLE
MODEL,PROJECT,FUNCTION
AUDIO CODEC
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 44 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
D

44 IN MIC_REF-R

44 IN MIC_REF-L

2.2K_5%_2

2.2K_5%_2
2

2
R600

R601
1

1
JACK501
5 5 X5R
6 MICS 1K_5%_2 C876 2.2UF_16V_3
6 OUT 44 R604
2 MIC_R_JACK 1 L522 2 1 2 MIC_R_C 2 1 MIC_R
2 OUT 44

MIC JACK
Normal OPEN
4
1
3
4
1
3
MIC_L_JACK
BLM18PG600SN1D
1
BLM18PG600SN1D
2 1 2 MIC_L_C 2 1 MIC_L
OUT 44

1
2.2UF_16V_3

100PF_50V_2

100PF_50V_2
L524 R605 C930
SINGA_2SJ2284_002143_6P
C 1K_5%_2
X5R C
6026B0176001

C929

C872
2

2
D531
2
3
1

PHP_PESD5V2S2UT_SOT23_3P

JACK502
3
B HP JACK
Normal OPEN
3
1
4
1
4
2
HP_L_JACK

HP_R_JACK
L535 1
BLM18PG600SN1D
L527 1
2

2
HP_L_R

HP_R_R
1R1060 75_5%_2
2

1R1019 75_5%_2
2
HP_L

HP_R
IN 44

44
B
2
6
IN
6 BLM18PG600SN1D
5 5

1000PF_50V_2_DY

1000PF_50V_2_DY
1

1
SINGA_2SJ2284_002143_6P
100PF_50V_2

100PF_50V_2

1
6026B0176001
C1003
C956

C957
C609

C1004
2 1
44 HPS
OUT
0.1UF_16V_2_DY
2

2
X7R

C610
2 1

0.1UF_16V_2_DY
X7R

C611
2 1
A A
0.1UF_16V_2_DY

X7R
C612
2 1

0.1UF_16V_2_DY
X7R
INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
HP JACK & MIC JACK
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 45 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

WLAN CONN (MINICARD)


D P3V3S P1V5S
D

2.2uF_6.3V_3_DY
0.1uF_16V_2
4.7uF_6.3V_3

1uF_6.3V_2
1

1
C785

C683

C684

C685
2

2
1 CN507 2
41 28 PCIE_WAKE#
OUT TP30 3
WAKE# 3.3V
4
TP1300 1 CH_DATA GND
TP30 1 5 6

2
TP1301 CH_CLK 1.5V
27 CLKREQ_WLAN# 7 8 LPC_FRAME# 26 35 D524
OUT 9
CLKREQ# LPC_FRAME#
10
IN
LPC_AD<3>

NC
GND LPC_AD3 BI 26 35
27 CLK_PCIE_WLAN_DN 11 12 LPC_AD<2> 26 35 1 3 WLAN_RF_OFF# 31
IN 13
REFCLK- LPC_AD2
14
BI IN
27 CLK_PCIE_WLAN_DP LPC_AD<1> 26 35
IN 15
REFCLK+ LPC_AD1
16
BI
LPC_AD<0> 26 35
17
GND LPC_AD0
18
BI DIODE-BAT54-TAP-PHP
46 35 30 17 BUF_PLT_RST#
C IN 19
LPC_DEBUG_RST# GND
20 C
30 CLK_LPC_DEBUG
IN 21
LPC_PCI_CLK W_DISABLE#
22 BUF_PLT_RST# 17 30 35 46
23
GND PERST#
24
IN
27 PCIE_WLAN_RX_C_DN
OUT 25
PERn0 +3.3Vaux
26
27 PCIE_WLAN_RX_C_DP
OUT PERp0 GND

1000PF_50V_2
27 GND 1.5V 28

1
29 GND SMB_CLK 30
31 32

C686
27 PCIE_WLAN_TX_C_DN
P3V3S IN PETn0 SMB_DATA
27 PCIE_WLAN_TX_C_DP 33 34
IN 35
PETp0 GND
36 USB_P8_DN 30
37
GND USB_D-
38
BI
USB_P8_DP 30
Reserved USB_D+ BI

2
39 40
Reserved GND P1V5S
41 42 WLAN_IND# 35
43
Reserved LED_WWAN#
44
OUT
Reserved LED_WLAN#
45 +V3AL LED_WPAN# 46
47 PWR_LED# 1.5V 48
49 NUM_LED# GND 50
26 2nd_WLAN_RF_OFF# 51 52
IN CAPS_LED# 3.3V

G1 G G G2
BELLW_80003_4023_52P
6026B0140707
B B

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
WLAN & BT
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 46 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

P5V0A P5V0A_USB3
USB 2.0 BOARD Cable CONN on MB TouchPad Module CONN C12712
U525
2 1
1 8
P5V0A GND OUT1

330uF_6.3V
P3V3A 22uF_6.3V_5 2 IN1 OUT2 7

1
3 IN2 OUT3 6
CN1 47 35 USBPWR_EN 4 5
C825 IN EN# OC#

+
C996
1 1 2 1
2 UPI_UP7534ARA8_15_MSOP_8P
2
3 3 10uF_6.3V_5

2
4 4
5 5 CN516
6 USBPWR_EN 35 47 1
D 6 IN 1
7 7 35 BI TP_DAT 2 2
8 USB_P1_DP 30 35 TP_CLK 3 G1 D
8
9 USB_P1_DN
BI BI 4
3 G
G2 P5V0A_USB3
9 BI 30 4 G
10 10 TP_SMBUS_DAT 5 5
11
12
11
12
13
USB_P9_DP
USB_P9_DN
BI
BI
30
30
TP_SMBUS_CLK 6 6
USB 3.0 CONN P5V0A_USB3

22uF_6.3V_5_DY
13 ACES_50503_00601_001_6P
14 14 U529

1
6012B0112702

0.1uF_16V_2
G1 G 15 15 PHP_PRTR5V0U2X_SOT143_4P_DY
G2 16

C12694
G 16 GND Vcc

C2404
1 1 4 4

ACES_50501_01641_001_16P

2
IO IO
6012B0104503 2 2 3 3

CN518
1 VBUS
USB_P0_DN 1 L537 2 USB_P2_L_DN 2
30
TOUCHPAD LED ON MB 30
BI
BI USB_P0_DP 4 3 USB_P2_L_DP 3
4
D-
D+
GND
WCM_2012_900T
30 USB3_P1_RX_DN 5 G1
OUT USB3_P1_RX_DP 6
SSRX- G1
G2
30 OUT
C POWER BUTTON CONN ON MB P3V3A
USB3_P1_TX_DN 2
C2405 0.1uF_16V_2
1 USB3_P3_TX_C_DN
7
8
SSRX+
GND
G2
G3 G3
G4
C
30 IN SSTX- G4
510_5%_2 30 USB3_P1_TX_DP 2 1 USB3_P3_TX_C_DP 9
P3V3A R23 IN SSTX+

1 2 CN517 C2406 FOX_UEA111GC_R14EC_7H_9P


P5V0A D2400 0.1uF_16V_2
D2400
6012B0370301
CN504 1 G1
1 1 3
1 1 2 4 5
2 35 IN TP_OFF_LED# 2 2 4 G2
2 10 9 7 6
36 35 PWR_LED# 3 G1
IN EC_PWRBTN# 4
3 G
G2
35 OUT 4 G SEMTECH_RCLAMP0524P.TCT_SLP2510P8_10P_DY

LID_SW# 5 ACES_50224_00201_001_2P SEMTECH_RCLAMP0524P.TCT_SLP2510P8_10P_DY


35 OUT 5
38 6 6012A0117201

8
6

ACES_50503_00601_001_6P
P3V3A
R50
6012B0112702
1 2
100K_5%_2
P3V3AL
R51 C50
1 2 2 1
100K_5%_2
B 0.1uF_16V_2 B

for PCH for CPU

SCREW220_0_396_1P

SCREW220_0_396_1P

SCREW330_600_0_1P

SCREW330_600_0_1P

SCREW330_600_0_1P

SCREW330_600_0_1P
S4700

S4701
FOR FAN

S4500

S4501

S4502

S4503
FOR M/B 1 S1 1 STD500
SCREW280_800_1P CHANGE TO 600_900_900_1P STDPAD_1.15_6.0_TOP
3.4MM

1
S2 S11

1
1 1
6052B0035901
SCREW280_800_1P SCREW600_900_800_1P
1 S3
1 S12
NUT PN :
SCREW280_800_1P
SCREW600_900_800_1P 6052B0160501
1 S4

SCREW280_800_1P FOR EMI


1 S5 1 STD507
A 1 S13 A
SCREW280_800_1P STDPAD_1.15_6-TOP
SCREW115_0_500_1P 4.2MM
1 S6
6052B0129701
CHANGE TO 115_0_800_1P
SCREW280_800_1P FIX1 FIX2 FIX3 FIX4
1 1 1 1
1 S7
FIX_MASK FIX_MASK FIX_MASK FIX_MASK
SCREW280_800_1P FIX5 FIX6 FIX7 FIX8
1 1 1 1
1 S8

INVENTEC
FIX_MASK FIX_MASK FIX_MASK FIX_MASK
SCREW280_800_1P
1 S9

SCREW280_800_1P TITLE

1 S10 MODEL,PROJECT,FUNCTION
USB 3.0 CONN & M/B TO D/B CONN
SCREW280_800_1P DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 47 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

F F

U4

CLOSE TO GPU
AF30 PCIE_RX0P PCIE_TX0P AH30
AE31 PCIE_RX0N PCIE_TX0N AG31
PEG_RX0_DN C42 1 2 0.1UF_16V_2 PEG_RX0_C_DN
48 IN OUT 18
AE29 PCIE_RX1P PCIE_TX1P AG29
AD28 AF28 PEG_RX1_DN C41 1 2 0.1UF_16V_2 PEG_RX1_C_DN
PCIE_RX1N PCIE_TX1N 48 IN OUT 18

PEG_RX2_DN C46 1 2 0.1UF_16V_2 PEG_RX2_C_DN


AD30 PCIE_RX2P PCIE_TX2P AF27 48 IN OUT 18
AC31 PCIE_RX2N PCIE_TX2N AF26
PEG_RX3_DN C19 1 2 0.1UF_16V_2 PEG_RX3_C_DN
48 IN OUT 18

AC29 PCIE_RX3P PCIE_TX3P AD27


PEG_RX4_DN C47 1 2 0.1UF_16V_2 PEG_RX4_C_DN
AB28 PCIE_RX3N PCIE_TX3N AD26 48 IN OUT 18
E E
PEG_RX5_DN C16 1 2 0.1UF_16V_2 PEG_RX5_C_DN
AB30 AC25
48 IN OUT 18
PCIE_RX4P PCIE_TX4P
AA31 PCIE_RX4N PCIE_TX4N AB25
PEG_RX6_DN C24 1 2 0.1UF_16V_2 PEG_RX6_C_DN
48 IN OUT 18

AA29 PCIE_RX5P PCIE_TX5P Y23


PEG_RX7_DN C22 1 2 0.1UF_16V_2 PEG_RX7_C_DN
Y28 PCIE_RX5N PCIE_TX5N Y24 48 IN OUT 18

Y30 PCIE_RX6P PCIE_TX6P AB27


W31 PCIE_RX6N PCIE_TX6N AB26
PEG_RX0_DP C43 1 2 0.1UF_16V_2 PEG_RX0_C_DP
48 IN OUT 18

W29 Y27 PEG_RX1_DP C40 1 2 0.1UF_16V_2 PEG_RX1_C_DP


V28
PCIE_RX7P PCIE_TX7P
Y26
48 IN OUT 18
PCIE_RX7N PCIE_TX7N

PEG_RX2_DP C45 1 2 0.1UF_16V_2 PEG_RX2_C_DP


48 IN OUT 18
PEG_TX7_C_DP V30 W24 PEG_RX7_DP
18 BI PEG_TX7_C_DN U31
PCIE_RX8P PCIE_TX8P
W23 PEG_RX7_DN
BI 48
PEG_RX3_DP PEG_RX3_C_DP
18 BI PCIE_RX8N PCIE_TX8N
BI 48 48 IN C18 1 2 0.1UF_16V_2 OUT 18

PCI EXPRESS INTERFACE


PEG_RX4_DP C25 1 2 0.1UF_16V_2 PEG_RX4_C_DP
18 BI PEG_TX6_C_DP U29 PCIE_RX9P PCIE_TX9P V27 PEG_RX6_DP
BI 48
48 IN OUT 18
PEG_TX6_C_DN T28 U26 PEG_RX6_DN
18 BI PCIE_RX9N PCIE_TX9N
BI 48
PEG_RX5_DP PEG_RX5_C_DP
48 IN C17 1 2 0.1UF_16V_2 OUT 18

PEG_TX5_C_DP T30 U24 PEG_RX5_DP


D 18 BI PEG_TX5_C_DN R31
PCIE_RX10P PCIE_TX10P
U23 PEG_RX5_DN
BI 48
PEG_RX6_DP PEG_RX6_C_DP D
18 BI PCIE_RX10N PCIE_TX10N
BI 48 48 IN C23 1 2 0.1UF_16V_2 OUT 18

PEG_RX7_DP C21 1 2 0.1UF_16V_2 PEG_RX7_C_DP


18 BI PEG_TX4_C_DP R29 PCIE_RX11P PCIE_TX11P T26 PEG_RX4_DP
BI 48
48 IN OUT 18
PEG_TX4_C_DN P28 T27 PEG_RX4_DN
18 BI PCIE_RX11N PCIE_TX11N
BI 48

PEG_TX3_C_DP P30 T24 PEG_RX3_DP


18 BI PEG_TX3_C_DN N31
PCIE_RX12P PCIE_TX12P
T23 PEG_RX3_DN
BI 48
18 BI PCIE_RX12N PCIE_TX12N BI 48

PEG_TX2_C_DP N29 P27 PEG_RX2_DP


18 BI PEG_TX2_C_DN M28
PCIE_RX13P PCIE_TX13P
P26 PEG_RX2_DN
BI 48
18 BI PCIE_RX13N PCIE_TX13N
BI 48
P3V3S_DGPU
PEG_TX1_C_DP M30 P24 PEG_RX1_DP
18 BI PEG_TX1_C_DN L31
PCIE_RX14P PCIE_TX14P
P23 PEG_RX1_DN
BI 48
C37
18 BI PCIE_RX14N PCIE_TX14N
BI 48 1 2

0.1UF_16V_2
PEG_TX0_C_DP L29 M27 PEG_RX0_DP
18 BI PEG_TX0_C_DN K30
PCIE_RX15P PCIE_TX15P
N26 PEG_RX0_DN
BI 48
18 BI PCIE_RX15N PCIE_TX15N
BI 48

5
U1
DGPU_HOLD_RST# 1

+
CLOCK 30 IN 4 PEG_SLT_RST#
27 BI CLK_PEG_DP AK30 PCIE_REFCLKP
2
OUT 48
CLK_PEG_DN AK32 P1V0S_DGPU
C 27 BI PCIE_REFCLKN
R30 C

-
1 2 TC7SZ08FU

3
CALIBRATION
100K_5%_2
FOR PARK-S3 PIN_N10 MUST NEED TO PULL DOWN TO GND PCIE_CALRP Y22 1 R64 21.27K_1%_2
GPU_PWRGD
N10 PWRGOOD PCIE_CALRN AA221 R66 22K_5%_2

R13
PLT_RST# 1 2
10K_5%_2
2

48 IN PEG_SLT_RST# AL27 PERSTB


43 41 30 IN
R62

0_5%_2_DY

AMD_SEYMOUR_XT_S3_FCBGA_631P THIS PART IS ONLY FOR INTEL PLATFORM


1

B B

A A

INVENTEC
TITLE

MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3

SIZE CODE DOC.NUMBER REV


C CS 1310xxxxx-0-0 X01
CHANGE by XXX DATE 21-OCT-2002 SHEET 48 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

MEM_ID3 MEM_ID2 MEM_ID1 MEM_ID0 U4

0 0 0 0 TBD
0 0 0 1 TBD TXCAP_DPA3P AF2
TXCAM_DPA3N AF4
0 0 1 0 TBD TP5 1 Y11 DVCLK
P1V8S_DGPU AE9 DVCNTL_0 TX0P_DPA2P AG3
F 0 0 1 1 TBD L9 DVCNTL_1 TX0M_DPA2N AG5 F
N9 DVO DPA
DVCNTL_2
TX1P_DPA1P AH3
AE8 DVDATA_12 TX1M_DPA1N AH1

10K_5%_2_DY

10K_5%_2_DY

10K_5%_2_DY
STRAPS PIN DESCRIPTION OF DEFAULT SETTING AD9 DVDATA_11

10K_5%_2
1

1
AC10 DVDATA_10 TX2P_DPA0P AK3
AD7 DVDATA_9 TX2M_DPA0N AK1
TX_PWRS_ENB GPIO0 PCIE FULL TX OUTPUT SWING

R2

R3

R33

R61
AC8 DVDATA_8
AC7 DVDATA_7 TXCBP_DPB3P AK5
TX_DEEMPH_EN GPIO1 PCIE TRANSMITTER DE-EMPHASIS ENABLED AB9 DVDATA_6 TXCBM_DPB3N AM3

2
AB8 DVDATA_5
BIF_GEN2_EN_A GPIO2 PCIE GEN2 ENABLED AB7 DVDATA_4 TX3P_DPB2P AK6
MEM_ID3 AB4 DVDATA_3 TX3M_DPB2N AM5
BIF_DEBUG_ACCESS GPIO4 DEBUG SIGNALS MUXED OUT MEM_ID2 AB2 DVDATA_2
DPB
MEM_ID1 Y8 DVDATA_1 TX4P_DPB1P AJ7
GPIO7_BLON CONTROL BACKLIGHT ON/OFF MEM_ID0 Y7 DVDATA_0 TX4M_DPB1N AH6

BIF_VGA_DIS GPIO9 VGA ENABLED TX5P_DPB0P AK8


TX5M_DPB0N AL7
ROMIDCFG(2:0) GPIO[11:13] MEMORY APERTURE SIZE SELECT P1V8S_DGPU
150MA W6 DPC_VDD18#3
DPC
V6 DP_VSSR#13
TXCCP_DPC3P V4
AC6 DPC_VDD18#1 TXCCM_DPC3N U5
P1V0S_DGPU AC5 DPC_VDD18#2
TX0P_DPC2P W3
110MA AA5 DPC_VDD10#1 TX0M_DPC2N V2
E IF GPIO_22_EN=0 , THEN GPIO[11:13] DEFINES THE PRIMARY MEMORYAPERTURE SIZE AA6 DPC_VDD10#2
E
TX1P_DPC1P Y4
TX1M_DPC1N W5
GPIO_13 GPIO_12 GPIO_11 MEMORY APERTURE SIZE
U1 DP_VSSR#14 TX2P_DPC0P AA3
W1 DP_VSSR#15 TX2M_DPC0N Y2
0 0 1 512/256 MB (DEFAULT) U3 DP_VSSR#16 R77
Y6 DP_VSSR#17 DPC_CALR J8 1 2
1 1 0 RESERVED AA1 DP_VSSR#18
150_5%_2

I2C
P3V3S_DGPU
R1 SCL
R3 SDA

1 R57 2 AM26 GPU_CRT_R


P3V3S_DGPU GENERAL PURPOSE I/O
R
AK26
OUT 37
RB
4.7K_5%_2 GPU_GPIO0 U6
GPIO25_TDI 1 2
49 OUT GPU_GPIO1 U10
GPIO_0
AL25 GPU_CRT_G
49 IN R40 10K_5%_2 49 OUT GPIO_1 G
OUT 37
GPIO24_TRSTB 1 2 GPU_GPIO2 T10 AJ25

2
49 IN R58 10K_5%_2 49 OUT GPIO_2 GB
GPUTHERM_INT# R46 1 2 10K_5%_2 D1 GPU_THM_DAT U8
49 IN GPU_GPIO2 1 2
50 OUT GPU_THM_CLK U7
GPIO_3_SMBDATA
AH24 GPU_CRT_B

NC
49 IN R54 10K_5%_2_DY 50 OUT GPIO_4_SMBCLK B
OUT 37
GPU_GPIO0 R49 1 2 10K_5%_2 GPU_THROT# 3 1 T9 AG25
49 IN GPU_GPIO1 1 2
35 OUT 1 T8
GPIO_5_AC_BATT
DAC1
BB
49 IN R52 10K_5%_2 TP3
GPIO_6
GPIO27_TMS R73 1 2 10K_5%_2 GPU_LCM_BLEN T7 AH26 GPU_CRT_HSYNC
D 49 OUT 49 OUT GPU_GPIO8 P10
GPIO_7_BLON HSYNC
AJ27 GPU_CRT_VSYNC
OUT 37 49
D
DIODE-BAT54-TAP-PHP 49 OUT GPIO_8_ROMSO VSYNC
OUT 37 49
GPU_GPIO9 P4
49 IN GPU_GPIO9 R45 1 2 10K_5%_2_DY
49 OUT P2
GPIO_9_ROMSI

GPU_GPIO11 1 2 GPIO_10_ROMSCK R37


49 IN R48 10K_5%_2 GPU_GPIO11 N6 AD22
1 2 P1V8S_DGPU
49 IN GPU_GPIO12 R44 1 2 10K_5%_2_DY
49 OUT GPU_GPIO12 N5
GPIO_11 RSET

GPU_GPIO13 49 OUT GPIO_12 499_1%_2


49 IN R43 1 2 10K_5%_2_DY GPU_GPIO13 N3 AG24 70MA
49 IN GPU_GPIO23 R41 1 2 10K_5%_2_DY
49 OUT Y9
GPIO_13 AVDD
AE22
GPIO_14_HPD2 AVSSQ
GPU_CRT_VSYNC R39 1 2 10K_5%_2_DY
49 37 IN GPU_CRT_HSYNC 56 OUT POW_SW0 N1 GPIO_15_PWRCNTL_0 L9
49 37 IN R38 1 2 10K_5%_2_DY R15 M4 AE23 45MA 1 2
49 IN GPU_GPIO22 R42 1 2 10K_5%_2_DY 1 2 THERMTRIP# OUT 23
35 GPUTHERM_INT# R6
GPIO_16 VDD1DI
AD23
49 IN BBEN R55 1 2 10K_5%_2_DY
49 OUT W10
GPIO_17_THERMAL_INT VSS1DI
FBM_11_160808_121T
GPIO_18_HPD3
GPU_GPIO8 R53 1 2 10K_5%_2_DY 0_5%_2
49 IN 49 OUT CTF M2 GPIO_19_CTF
CTF: POW_SW1 P8 AM12
Q3 56 OUT BBEN P7
GPIO_20_PWRCNTL_1
SEYMOUR/PARK
NC/R2
AK12
GPU CRITICAL TEMPER ATURE SHANG DOWN 110°C 49 OUT GPIO_21_BB_EN NC/R2B

3
SSM3K7002FU GPU_GPIO22 N8
49 OUT GPU_GPIO23 N7
GPIO_22_ROMCSB
AL11
49 OUT GPIO26_TCK R74 1 2 10K_5%_2 D R16 R17
49 OUT GPIO_23_CLKREQB NC/G2
AJ11
49 IN CTF R47 1 2 10K_5%_2 G 1 1 2 1 2 CTF IN 49 GPIO24_TRSTB L6
NC/G2B

49 IN TESTEN R60 1 2 5.11K_1%_2


49 OUT GPIO25_TDI L5
JTAG_TRSTB
AK10
49 OUT
S

JTAG_TDI NC/B2
GPU_LCM_BLEN R59 1 2 10K_5%_2 10K_5%_2 10K_5%_2
49 IN 49 OUT GPIO26_TCK L3 JTAG_TCK NC/B2B AL9

0.1UF_16V_2
GPIO27_TMS

1
L1
49 OUT JTAG_TMS
2

1 K4 JTAG_TDO
R21 TESTEN TP6 K7 AH12
C14 OUT
1 2 49 TESTEN SWAPLOCKB/C
1 AF24 TESTEN_LEGACY NC/Y AM10
TP1 AJ9
NC/COMP
20K_5%_2
2
AB13 GENERICA
C W8 GENERICB GENLK_CLK AL13 C
W9 GENERICC GENLK_V2SYNC AJ13
P1V8S_DGPU W7 GENERICD
PX_EN
AD10
52 OUT GENERICE_HPD4
AD19
NC/VDD2IDI
AC14 HPD1 NC/VSS2IDI AC19

1
2 R63 1 AB16 PX_EN
499_1%_2
5.11K_1%_2
R24 AE20
NC/A2VDD

NC/A2VDDQ AE17

2 2

1
TSVSSQ/A2VSSQ AE19

R26 AC16
C54 VREFG
249_1%_2 AG13
0.1UF_16V_2 SWAPLOCKA/R2SET

2
P1V8S_DGPU

1
DDC/AUX AE6
DDC1CLK
PLL/CLOCK
75MA L5 DDC1DATA AE5
1 2 AF14 DPLL_PVDD
AE14 DPLL_PVSS AUX1P AD2
10UF_6.3V_3

FBM_11_160808_121T AUX1N AD4


0.1UF_16V_2
1

AD14 DPLL_VDDC DDC2CLK AC11


C53

C52

DDC2DATA AC13
B B
C35 P3V3S_DGPU
1 2 AM28 XTALIN AUX2P AD13
2

AK28 XTALOUT AUX2N AD11

1
3
2

1M_5%_2
P1V0S_DGPU 22PF_50V_2
R65 0_5%_2_DY
27MHZ

1
1 2 AC22 XO_IN DDCCLK_AUX3P AD20

R29
1 2 AB22 AC20
X1

XO_IN2 DDCDATA_AUX3N
125MA R67 0_5%_2_DY
R103 R106
C36 AE16 2.2K_5%_2 2.2K_5%_2
L6 2 R120 DDCCLK_AUX5P
4
1

1 2 1 2 GPU_27M_IN 1 2 AD16
16 IN DDCDATA_AUX5N

2
0_5%_2
22PF_50V_2 6018B0054301 AC1 GPU_CRT_CLK
FBM_11_160808_121T DDC6CLK
OUT 37
0.1UF_16V_2
10UF_6.3V_3

GPU_THERMDA THERMAL GPU_CRT_DAT


1

T4 AC3
50 OUT GPU_THERMDC T2
DPLUS DDC6DATA
OUT 37
50 OUT DMINUS
C55
C57

P1V8S_DGPU R5 TS_FDO
2

AD17
2

TSVDD
AC17 TSVSS

5MA L7
1 2

POW_SW1 POW_SW0 +VDDC_GPU FBM_11_160808_121T


AMD_SEYMOUR_XT_S3_FCBGA_631P

0.1UF_16V_2
10UF_6.3V_3

1
0 0 1.1V
0 1 1V 1

C59
C29

A 1 0 0.95V A

2
INVENTEC
2

1 1 0.9V

TITLE

MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3

SIZE CODE DOC.NUMBER REV


C CS 1310xxxxx-0-0 X01
CHANGE by XXX DATE 21-OCT-2002 SHEET 49 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U4

D
AA27 PCIE_VSS#1 GND#1 A3 D
AB24 PCIE_VSS#2 GND#2 A30
AB32 PCIE_VSS#3 GND#3 AA13
AC24 PCIE_VSS#4 GND#4 AA16
AC26 PCIE_VSS#5 GND#5 AB10
AC27 PCIE_VSS#6 GND#6 AB15
P3V3S_DGPU AD25 PCIE_VSS#7 GND#7 AB6
AD32 PCIE_VSS#8 GND#8 AC9
AE27 PCIE_VSS#9 GND#9 AD6
R32 AF32 PCIE_VSS#10 GND#10 AD8
2 1 AG27 PCIE_VSS#11 GND#11 AE7
AH32 PCIE_VSS#12 GND#12 AG12
10K_5%_2 K28 AH10
PCIE_VSS#13 GND#13

1
K32 PCIE_VSS#14 GND#14 AH28
R108 Q11 L27 PCIE_VSS#15 GND#15 B10
0_5%_2 M32 B12

G
SSM3K7002FU PCIE_VSS#16 GND#16
N25 PCIE_VSS#17 GND#17 B14
49 BI GPU_THM_CLK 1 2 GPU_THM_R_CLK 2 S D 3 THM_CLK BI 23 35 N27 PCIE_VSS#18 GND#18 B16
P25 PCIE_VSS#19 GND#19 B18
P32 PCIE_VSS#20 GND#20 B20
49 BI GPU_THM_DAT 1 2 GPU_THM_R_DAT 2 S D 3 THM_DAT BI 23 35 R27 PCIE_VSS#21 GND#21 B22
T25 PCIE_VSS#22 GND#22 B24
R1017 Q12 T32 PCIE_VSS#23 GND#23 B26
C C

G
0_5%_2 SSM3K7002FU U25 PCIE_VSS#24 GND#24 B6
U27 PCIE_VSS#25 GND#25 B8
V32 C1

1
PCIE_VSS#26 GND#26
R31 W25 PCIE_VSS#27 GND#27 C32
2 1 W26 PCIE_VSS#28 GND#28 E28
10K_5%_2 W27 PCIE_VSS#29 GND#29 F10
Y25 PCIE_VSS#30 GND#30 F12
Y32 PCIE_VSS#31 GND#31 F14
GND#32 F16
P3V3S_DGPU GND#33 F18
GND#34 F2
GND#35 F20
M6 GND#56 GND#36 F22
N11 NC#5 GND#37 F24
P3V3S_DGPU N12 NC#6 GND#38 F26
N13 GND#59 GND#39 F6
N16
N18
GND#60
GND#61
GND GND#40
GND#41
F8
G10
N21 GND#62 GND#42 G27

NA
0.1UF_16V_2_DY

P6 G31
10K_5%_2_DY

GND#63 GND#43
P9 GND#64 GND#44 G8
1
1

R12 GND#65 GND#45 H14


B R15 H17 B
R56

GND#66 GND#46
C77

R17 GND#67 GND#47 H2


R20 GND#68 GND#48 H20
2

T13 GND#69 GND#49 H6


2

T16 GND#70 GND#50 J27


T18 GND#71 GND#51 J31
U3 T21 GND#72 GND#52 K11
T6 GND#73 GND#53 K2
1 VDD SMCLK 8 GPU_THM_R_CLK
U15 GND#74 GND#54 K22
49 IN GPU_THERMDA 2 DXP SMDATA 7 GPU_THM_R_DAT
U17 GND#75 GND#55 K6
49 IN GPU_THERMDC 3 DXN ALERT 6
U20 GND#76
4 THERM GND 5
1000PF_50V_2_DY

U9 GND#77
V13 GND#78
TI_TMP431B_MSOP_8P_DY
1

V16 GND#79
V18 GND#80
C5103

Y10 GND#81
Y15 GND#82
Y17 GND#83 VSS_MECH#1 A32
Y20 AM1
2

GND#84 VSS_MECH#2
R11 GND#85 VSS_MECH#3 AM32
T11 GND#86

A A
AMD_SEYMOUR_XT_S3_FCBGA_631P

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 50 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U4

C67 0.1UF_16V_2
P1V5S_DGPU P1V8S_DGPU_VDDR
MEM I/O P1V8S_DGPU
1.2A PCIE
L2
H13 AB23 1 2 440MA

0.1UF_16V_2

10UF_6.3V_3
VDDR1#1 PCIE_VDDR#1

1UF_6.3V_2

1UF_6.3V_2
H16 VDDR1#2 PCIE_VDDR#2 AC23

1
H19 AD24 MPZ1608S221AT
VDDR1#3 PCIE_VDDR#3

4.7UF_6.3V_3

4.7UF_6.3V_3
J10 AE24 2A_0603

2.2UF_6.3V_2

C105
1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2
VDDR1#4 PCIE_VDDR#4

C68

C65

C66
J23 VDDR1#5 PCIE_VDDR#5 AE25
D

C5185

C116

C157

C158

C138

C161
J24 VDDR1#6 PCIE_VDDR#6 AE26
D

C76
J9 VDDR1#7 PCIE_VDDR#7 AF25

2
K10 VDDR1#8 PCIE_VDDR#8 AG26
K23 VDDR1#9 P1V0S_DGPU

2
K24 VDDR1#10
K9 L23
L11
VDDR1#11 PCIE_VDDC#1
L24 2A

10UF_6.3V_3
VDDR1#12 PCIE_VDDC#2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2
L12 VDDR1#13 PCIE_VDDC#3 L25

1
L13 VDDR1#14 PCIE_VDDC#4 L26
L20 M22

C103

C102

C104
VDDR1#15 PCIE_VDDC#5

C64

C62
L21 N22

C4
P1V8S_DGPU VDDR1#16 PCIE_VDDC#6
L22 VDDR1#17 PCIE_VDDC#7 N23
219MA PCIE_VDDC#8 N24

2
L8 PCIE_VDDC#9 R22
1 2
PCIE_VDDC#10 T22
MLZ1608M100WT U22

0.1UF_16V_2
10UF_6.3V_3
LEVEL PCIE_VDDC#11
PVCORE_DGPU

1UF_6.3V_2
250MA_0603
TRANSLATION

PCIE_VDDC#12 V22

1
AA20 VDD_CT#1

C63 AA21 VDD_CT#2 14A

C60

C61
AB20 VDD_CT#3 VDDC#1 AA15
CORE
AB21 VDD_CT#4 VDDC#2 N15
N17
P3V3S_DGPU

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2

1UF_6.3V_2
VDDC#3
2

1
VDDC#4 R13
I/O
C 60MA VDDC#5 R16 C

C100
AA17 R18

C98

C85

C89

C92

C86

C96

C90

C94

C84

C87

C69
VDDR3#1 VDDC#6
AA18 VDDR3#2 VDDC#7 Y21
0.1UF_16V_2
10UF_6.3V_3

AB17 VDDR3#3 VDDC#8 T12


1

AB18 T15

2
VDDR3#4 VDDC#9
T17
C95

VDDC#10
C30

V12 VDDR4#1 VDDC#11 T20


Y12 VDDR4#2 VDDC#12 U13
U12 U16
2

VDDR4#3 VDDC#13
2

U18

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3

10UF_6.3V_3
VDDC#14

2.2UF_6.3V_2

2.2UF_6.3V_2
AA11 NC#1 VDDC#15 V21

1
AA12 V15
P1V8S_DGPU NC#2 VDDC#16
VDDC#17 V17

C88

C91

C33

C31

C27

C32
V11 NC#3 VDDC#18 V20
L10
170MA 1 2
U11 NC#4 VDDC#19 Y13

POWER
VDDC#20 Y16

2
FBM_11_160808_121T VDDC#21 Y18
0.1UF_16V_2
1UF_6.3V_2
1

M11
200MA_0603 VDDC#22
VDDC#23 M12
MEM CLK

1UF_6.3V_2

1UF_6.3V_2
BIF_VDDC
C81

C80

IN 52

1
L17 NC_VDDRHA

C101
C49
L16
2

NC_VSSRHA
B P1V8S_DGPU_VDDR B
PVCORE_DGPU

2
40MA PLL

P1V8S_DGPU AM30 PCIE_VDDR


BIF_VDDC#1 R21 14A

0.1UF_16V_2

0.1UF_16V_2
U21

4.7UF_6.3V_3
L13

1UF_6.3V_2

1UF_6.3V_2
75MA BIF_VDDC#2

1
1 2 L8 NC_MPV18
10UF_6.3V_3

FBM_11_160808_121T
0.1UF_16V_2

C93

C82

C83

C97

C99
1

200MA_0603 H7 SPV18
C115

ISOLATED
C79

H8 CORE I/O M13

2
SPV10 VDDCI#1
VDDCI#2 M15
P1V8S_DGPU J7 SPVSS VDDCI#3 M16
2

VDDCI#4 M17
L11 M18
50MA 1 2
VDDCI#5
VDDCI#6 M20
VDDCI#7 M21
10UF_6.3V_3

FBM_11_160808_121T N20
0.1UF_16V_2

VDDCI#8
1

200MA_0603
C106

C107

P1V0S_DGPU
A A
2

AMD_SEYMOUR_XT_S3_FCBGA_631P
L12
100MA 1 2
1

0.1UF_16V_2
10UF_6.3V_3

FBM_11_160808_121T
200MA_0603
C110

C112
2

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 51 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U4

DP E/F POWER DP A/B POWER P1V8S_DGPU


P1V8S_DGPU
440MA AG15 DPEF_VDD18#1 DPAB_VDD18#1 AE11 300MA
AG16 DPEF_VDD18#2 DPAB_VDD18#2 AF11

P3V3S P1V0S_DGPU
P1V0S_DGPU
P3V3S

10K_5%_2_DY
C56 240MA
AG20 DPEF_VDD10#1 DPAB_VDD10#1 AF6 220MA
BACO MODE

1
AG21 DPEF_VDD10#2 DPAB_VDD10#2 AF7
1 2

R109
0.1UF_16V_2_DY AG14 DP_VSSR#19 DP_VSSR#1 AE1
U10 AH14 DP_VSSR#20 DP_VSSR#2 AE3

5
AM14 AG1

2
DP_VSSR#21 DP_VSSR#3
DGPU_PWR_EN TC7SET08FU_DY AM16 AG6
1 DP_VSSR#22 DP_VSSR#4

+
56 55 30 27 IN
D 4 PX_MODE 52 55 56
AM18 DP_VSSR#23 DP_VSSR#5 AH5
OUT D
PX_EN# 2 P1V8S_DGPU
Q16 P1V8S_DGPU

-
3
440MA AF16 AE13 300MA

D
DPEF_VDD18#3 DPAB_VDD18#3
PX_EN

3
49 1 G AG17 AF13
IN DPEF_VDD18#4 DPAB_VDD18#4

P1V0S_DGPU

S
P1V0S_DGPU
SSM3K7002FU_DY R110
1 2 AF22 AF8 220MA

2
240MA AG22
DPEF_VDD10#3
DPEF_VDD10#4
DPAB_VDD10#3
DPAB_VDD10#4 AF9
0_5%_2_DY

P5V0S AF23 DP_VSSR#24 DP_VSSR#6 AF10

1K_5%_2_DY
AG23 DP_VSSR#25 DP_VSSR#7 AG9
P5V0S

1
AM20 DP_VSSR#26 DP_VSSR#8 AH8

1K_5%_2_DY
AM22 DP_VSSR#27 DP_VSSR#9 AM6

R112
AM24 DP_VSSR#28 DP_VSSR#10 AM8

R111
P3V3S

2
VDDC_ON R36 R35

2
OUT 52 1 AF17
2 AE10
1 2
DPEF_CALR DPAB_CALR
U12
5

C TC7SET08FU_DY 150_1%_2 150_1%_2


C
DGPU_PWROK 1 1.0V_ON OUT 52 P1V8S_DGPU P1V8S_DGPU
+

56 35 31 OUT 4 AG18 DPEF_VDD18#5


DP PLL POWER
DPAB_VDD18#5 AG8 300MA

3
PX_MODE 2

3
56 55 52 Q17 AF19 AG7
IN DP_VSSR#29 DP_VSSR#11
440MA
-

D
1 G Q18
1
3

G
AG19 AG10
S

DPEF_VDD18#6 DPAB_VDD18#6
SSM3K7002FU_DY

S
AF20 DP_VSSR#30 DP_VSSR#12 AG11
SSM3K7002FU_DY
2

2
AMD_SEYMOUR_XT_S3_FCBGA_631P

U4

LVDS CONTROL
VARY_BL AB11
DIGON AB12
B

P1V0S_DGPU
DEFULT IS PX5.0 B

BACO MODE BIF_VDDC IN 51


TXCLK_UP_DPF3P AH20
TXCLK_UN_DPF3N AJ19
2 S D 3
TXOUT_U0P_DPF2P AL21
Q19 AK20
PVCORE_DGPU TXOUT_U0N_DPF2N
G

AM2302N_DY
TXOUT_U1P_DPF1P AH22
52 1.0V_ON
1

IN TXOUT_U1N_DPF1N AJ21
R113
1 2 TXOUT_U2P_DPF0P AL23
TXOUT_U2N_DPF0N AK22
0_5%_2
AK24
4.7UF_6.3V_3

4.7UF_6.3V_3

TXOUT_U3P
1

TXOUT_U3N AJ23
C109
C58

PVCORE_DGPU LVTMDP

ALPHA_AO3416_SOT23_3P_DY AL15
2

TXCLK_LP_DPE3P
TXCLK_LN_DPE3N AK14
S D
A S D
A
D
S

TXOUT_L0P_DPE2P AH16
TXOUT_L0N_DPE2N AJ15

Q20 TXOUT_L1P_DPE1P AL17


G
G

TXOUT_L1N_DPE1N AK16
G

52 IN VDDC_ON TXOUT_L2P_DPE0P AH18


TXOUT_L2N_DPE0N AJ17

TXOUT_L3P
TXOUT_L3N
AL19
AK18 INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
DOC.NUMBER REV
AMD_SEYMOUR_XT_S3_FCBGA_631P SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 52 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U4

GDDR5/DDR3 GDDR5/DDR3

54 BI DQA0(0) K27 DQA0_0 MAA0_0/MAA_0 K17 MAA0(0) BI 54


54 BI DQA0(1) J29 DQA0_1 MAA0_1/MAA_1 J20 MAA0(1) BI 54
54 BI DQA0(2) H30 DQA0_2 MAA0_2/MAA_2 H23 MAA0(2) BI 54
54 BI DQA0(3) H32 DQA0_3 MAA0_3/MAA_3 G23 MAA0(3) BI 54
54 BI DQA0(4) G29 DQA0_4 MAA0_4/MAA_4 G24 MAA0(4) BI 54
54 BI DQA0(5) F28 DQA0_5 MAA0_5/MAA_5 H24 MAA0(5) BI 54
DQA0(6) MAA0(6)

MEMORY INTERFACE
54 F32 J19 54
BI DQA0_6 MAA0_6/MAA0_6 BI
54 BI DQA0(7) F30 DQA0_7 MAA0_7/MAA0_7 K19 MAA0(7) BI 54
54 BI DQA0(8) C30 DQA0_8 MAA1_0/MAA_8 J14 MAA0(8) BI 54
54 BI DQA0(9) F27 DQA0_9 MAA1_1/MAA_9 K14 MAA0(9) BI 54
54 BI DQA0(10) A28 DQA0_10 MAA1_2/MAA_10 J11 MAA0(10) BI 54
54 BI DQA0(11) C28 DQA0_11 MAA1_3/MAA_11 J13 MAA0(11) BI 54
54 BI DQA0(12) E27 DQA0_12 MAA1_4/MAA_12 H11 MAA0(12) BI 54
D 54 DQA0(13) G26 G11 VM_A_BA2 54
BI DQA0_13 MAA1_5/MAA_BA2 BI D
54 BI DQA0(14) D26 DQA0_14 MAA1_6/MAA_BA0 J16 VM_A_BA0 BI 54
54 BI DQA0(15) F25 DQA0_15 MAA1_7/MAA_BA1 L15 VM_A_BA1 BI 54
54 BI DQA0(16) A25 DQA0_16
54 BI DQA0(17) C25 DQA0_17 WCKA0_0/DQMA0_0 E32 VM_R_ADQM#(0) BI 54
54 BI DQA0(18) E25 DQA0_18 WCKA0B_0/DQMA0_1 E30 VM_R_ADQM#(1) BI 54
54 BI DQA0(19) D24 DQA0_19 WCKA0_1/DQMA0_2 A21 VM_R_ADQM#(2) BI 54
54 BI DQA0(20) E23 DQA0_20 WCKA0B_1/DQMA0_3 C21 VM_R_ADQM#(3) BI 54
54 BI DQA0(21) F23 DQA0_21 WCKA1_0/DQMA1_0 E13 VM_R_ADQM#(4) BI 54
54 BI DQA0(22) D22 DQA0_22 WCKA1B_0/DQMA1_1 D12 VM_R_ADQM#(5) BI 54
54 BI DQA0(23) F21 DQA0_23 WCKA1_1/DQMA1_2 E3 VM_R_ADQM#(6) BI 54
54 BI DQA0(24) E21 DQA0_24 WCKA1B_1/DQMA1_3 F4 VM_R_ADQM#(7) BI 54
54 BI DQA0(25) D20 DQA0_25
54 BI DQA0(26) F19 DQA0_26 EDCA0_0/QSA0_0 H28 VM_R_ADQSA(0) BI 54
54 BI DQA0(27) A19 DQA0_27 EDCA0_1/QSA0_1 C27 VM_R_ADQSA(1) BI 54
54 BI DQA0(28) D18 DQA0_28 EDCA0_2/QSA0_2 A23 VM_R_ADQSA(2) BI 54
54 BI DQA0(29) F17 DQA0_29 EDCA0_3/QSA0_3 E19 VM_R_ADQSA(3) BI 54
54 BI DQA0(30) A17 DQA0_30 EDCA1_0/QSA1_0 E15 VM_R_ADQSA(4) BI 54
54 BI DQA0(31) C17 DQA0_31 EDCA1_1/QSA1_1 D10 VM_R_ADQSA(5) BI 54
54 BI DQA0(32) E17 DQA1_0 EDCA1_2/QSA1_2 D6 VM_R_ADQSA(6) BI 54
54 BI DQA0(33) D16 DQA1_1 EDCA1_3/QSA2_3 G5 VM_R_ADQSA(7) BI 54
54 BI DQA0(34) F15 DQA1_2
54 BI DQA0(35) A15 DQA1_3 DDBIA0_0/QSA0_0B H27 VM_R_ADQSA#(0) BI 54
C 54 BI DQA0(36) D14 DQA1_4 DDBIA0_1/QSA0_1B A27 VM_R_ADQSA#(1) BI 54 C
54 BI DQA0(37) F13 DQA1_5 DDBIA0_2/QSA0_2B C23 VM_R_ADQSA#(2) BI 54
54 BI DQA0(38) A13 DQA1_6 DDBIA0_3/QSA0_3B C19 VM_R_ADQSA#(3) BI 54
54 BI DQA0(39) C13 DQA1_7 DDBIA1_0/QSA1_0B C15 VM_R_ADQSA#(4) BI 54
54 BI DQA0(40) E11 DQA1_8 DDBIA1_1/QSA1_1B E9 VM_R_ADQSA#(5) BI 54
54 BI DQA0(41) A11 DQA1_9 DDBIA1_2/QSA1_2B C5 VM_R_ADQSA#(6) BI 54
P1V5S_DGPU 54 DQA0(42) C11 H4 VM_R_ADQSA#(7) 54
BI DQA1_10 DDBIA1_3/QSA1_3B BI
54 BI DQA0(43) F11 DQA1_11
54 BI DQA0(44) A9 DQA1_12 ADBIA0/ODTA0 L18 VM_R_ODTA0 BI 54
1

54 BI DQA0(45) C9 DQA1_13 ADBIA1/ODTA1 K16 VM_R_ODTA1 BI 54


R79 DQA0(46) F9
54 BI DQA1_14
40.2_1%_2 DQA0(47) D8 H26 DDR_CLKA0
54 BI DQA1_15 CLKA0 OUT 53 54
54 BI DQA0(48) E7 DQA1_16 CLKA0B H25 DDR_CLKA0# OUT 53 54
54 BI DQA0(49) A7 DQA1_17
0.1UF_16V_2
12

DQA0(50) DDR_CLKA1
1

C7 G9
100_5%_2

54 BI DQA1_18 CLKA1 OUT 53 54


54 BI DQA0(51) F7 DQA1_19 CLKA1B H9 DDR_CLKA1# OUT 53 54
C119

DQA0(52)
R69

54 A5
BI DQA1_20
54 BI DQA0(53) E5 DQA1_21 RASA0B G22 DDR_RASA0# OUT 54
P1V5S_DGPU 54 BI DQA0(54) C3 DQA1_22 RASA1B G17 DDR_RASA1# OUT 54
DQA0(55) E1
2

54 BI DQA1_23
54 BI DQA0(56) G7 DQA1_24 CASA0B G19 DDR_CASA0# OUT 54
DQA0(57) DDR_CASA1#
1

54 G6 G16 54
BI DQA1_25 CASA1B OUT
54 BI DQA0(58) G1 DQA1_26
B DQA0(59) DDR_CSA0#_0 OUT B
R80

40.2_1%_2 54 G3 H22 54
BI DQA1_27 CSA0B_0
54 BI DQA0(60) J6 DQA1_28 CSA0B_1 J22
54 BI DQA0(61) J1 DQA1_29
DQA0(62) J3 G13 DDR_CSA1#_0 OUT
0.1UF_16V_2
12

100_5%_2

54 BI DQA1_30 CSA1B_0 54
1

54 BI DQA0(63) J5 DQA1_31 CSA1B_1 K13


C120
R81

P1V5S_DGPU K26 K20 DDR_CKEA0 54


MVREFDA CKEA0 OUT
J26 MVREFSA CKEA1 J17 DDR_CKEA1 OUT 54
R78 240_1%_2
2

1 2 J25 MEM_CALRN0 WEA0B G25 DDR_WEA0# OUT 54


1 2 K25 MEM_CALRP0 WEA1B H10 DDR_WEA1# OUT 54
R68 240_1%_2

R72 R70
GDDR5 / DDR3
54 BI VM_RESET 1 2 2 1 L10 DRAM_RST
MAA0_8/MAA_13 G20 MAA13 BI 54
51_5%_2 10_5%_2 K8 G14
120PF_50V_2

CLKTESTA MAA1_8/RSVD
4.99K_1%_2
1

L7 CLKTESTB
C108

R71

AMD_SEYMOUR_XT_S3_FCBGA_631P
2

A A

R84 R86 R95 R94

INVENTEC
54 53 IN DDR_CLKA1
1 2 1 DDR_CLKA1#
2
OUT 5353
54 54 IN DDR_CLKA01 2 1 2 DDR_CLKA0#
OUT 53 54
1

56_5%_2
1

56_5%_2
56_5%_2 56_5%_2
C130 C144 TITLE
0.01UF_50V_2 0.01UF_50V_2
MODEL,PROJECT,FUNCTION
SEYMOUR XT-S3
2
2

DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 53 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

U5
U7 VREFC_U10 M8 E3 DQA0(41)
VREFC_U7 M8 E3 DQA0(16) U8 U6 54 BI VREFCA DQL0
BI 53
54 BI VREFD_U7 H1
VREFCA DQL0
F7 DQA0(17)
BI 53
54 BI VREFC_U8 M8 VREFCA DQL0 E3 DQA0(30)
BI 53 54 BI VREFC_U9 M8 VREFCA DQL0 E3 DQA0(38)
BI 53 54 BI VREFD_U10 H1 VREFDQ DQL1 F7 DQA0(47)
BI 53
54 BI VREFDQ DQL1
F2 DQA0(22)
BI 53
54 BI VREFD_U8 H1 VREFDQ DQL1 F7 DQA0(24)
BI 53 54 BI VREFD_U9 H1 VREFDQ DQL1 F7 DQA0(33)
BI 53 DQL2 F2 DQA0(45)
BI 53
MAA0(0) N3
DQL2
F8 DQA0(19)
BI 53
DQL2 F2 DQA0(27)
BI 53 DQL2 F2 DQA0(39)
BI 53 54 53 BI MAA0(0) N3 A0 DQL3 F8 DQA0(46)
BI 53
54 53 BI MAA0(1) P7
A0 DQL3
H3 DQA0(20)
BI 53
54 53 BI MAA0(0) N3 A0 DQL3 F8 DQA0(26)
BI 53 54 53 BI MAA0(0) N3 A0 DQL3 F8 DQA0(35)
BI 53 54 53 BI MAA0(1) P7 A1 DQL4 H3 DQA0(44)
BI 53
54 53 BI MAA0(2) P3
A1 DQL4
H8 DQA0(21)
BI 53
54 53 BI MAA0(1) P7 A1 DQL4 H3 DQA0(28)
BI 53 54 53 BI MAA0(1) P7 A1 DQL4 H3 DQA0(37)
BI 53 54 53 BI MAA0(2) P3 A2 DQL5 H8 DQA0(43)
BI 53
54 53 BI MAA0(3) N2
A2 DQL5
G2DQA0(18)
BI 53
54 53 BI MAA0(2) P3 A2 DQL5 H8 DQA0(25)
BI 53 54 53 BI MAA0(2) P3 A2 DQL5 H8 DQA0(32)
BI 53 54 53 BI MAA0(3) N2 A3 DQL6 G2DQA0(40)
BI 53
54 53 BI MAA0(4)
A3 DQL6
H7 DQA0(23)
BI 53
54 53 BI MAA0(3) N2 A3 DQL6 G2DQA0(31)
BI 53 54 53 BI MAA0(3) N2 A3 DQL6 G2DQA0(34)
BI 53 54 53 BI MAA0(4) P8 A4 DQL7 H7 DQA0(42)
BI 53
F 54 53 BI P8 A4 DQL7
BI 53 MAA0(4) P8 H7 DQA0(29) MAA0(4) P8 H7 DQA0(36) MAA0(5) P2 F
54 53 BI MAA0(5) P2 A5
54 53 BI MAA0(5) P2
A4 DQL7
BI 53 54 53 BI MAA0(5) P2
A4 DQL7
BI 53 54 53 BI MAA0(6) R8
A5

54 53 BI MAA0(6) R8 A6
54 53 BI MAA0(6) R8
A5 54 53 BI MAA0(6) R8
A5 54 53 BI MAA0(7) R2
A6
D7 DQA0(55)
54 53 BI MAA0(7) R2 A7 DQU0 D7 DQA0(15)
BI 53
54 53 BI MAA0(7) R2
A6
D7 DQA0(3)
54 53 BI MAA0(7) R2
A6
D7 DQA0(62)
54 53 BI MAA0(8) T8
A7 DQU0
C3 DQA0(48)
BI 53

54 53 BI MAA0(8) T8 A8 DQU1 C3 DQA0(9)


BI 53
54 53 BI MAA0(8) T8
A7 DQU0
C3 DQA0(5)
BI 53 54 53 BI MAA0(8) T8
A7 DQU0
C3 DQA0(57)
BI 53 54 53 BI MAA0(9) R3
A8 DQU1
C8 DQA0(54)
BI 53

54 53 BI MAA0(9) R3 A9 DQU2 C8 DQA0(13)


BI 53
54 53 BI MAA0(9) R3
A8 DQU1
C8 DQA0(2)
BI 53 54 53 BI MAA0(9) R3
A8 DQU1
C8 DQA0(63)
BI 53 54 53 BI MAA0(10) L7
A9 DQU2
C2 DQA0(51)
BI 53

54 53 BI MAA0(10) L7 A10_AP DQU3 C2 DQA0(11)


BI 53
54 53 BI MAA0(10) L7
A9 DQU2
C2 DQA0(0)
BI 53 54 53 BI MAA0(10) L7
A9 DQU2
C2 DQA0(59)
BI 53 54 53 BI MAA0(11) R7
A10_AP DQU3
A7 DQA0(52)
BI 53

54 53 BI MAA0(11) R7 A11 DQU4 A7 DQA0(12)


BI 53
54 53 BI MAA0(11) R7
A10_AP DQU3
A7 DQA0(4)
BI 53 54 53 BI MAA0(11) R7
A10_AP DQU3
A7 DQA0(60)
BI 53 54 53 BI MAA0(12) N7
A11 DQU4
A2 DQA0(49)
BI 53

54 53 BI MAA0(12) N7 A12 DQU5 A2 DQA0(8)


BI 53
54 53 BI MAA0(12) N7
A11 DQU4
A2 DQA0(1)
BI 53 54 53 BI MAA0(12) N7
A11 DQU4
A2 DQA0(61)
BI 53 54 53 BI MAA13 T3
A12 DQU5
B8 DQA0(53)
BI 53

54 53 BI MAA13 T3 A13 DQU6 B8 DQA0(14)


BI 53
54 53 BI MAA13 T3
A12 DQU5
B8 DQA0(6)
BI 53 54 53 BI MAA13 T3
A12 DQU5
B8 DQA0(56)
BI 53 54 53 BI T7
A13 DQU6
A3 DQA0(50)
BI 53
T7 A14 DQU7 A3 DQA0(10)
BI 53
54 53 BI T7
A13 DQU6
A3 DQA0(7)
BI 53 54 53 BI T7
A13 DQU6
A3 DQA0(58)
BI 53
M7
A14 DQU7
BI 53
M7 A14 DQU7
BI 53 A14 DQU7
BI 53 A15_BA3 P1V5S_DGPU
A15_BA3 P1V5S_DGPU M7 M7
A15_BA3 P1V5S_DGPU A15_BA3 P1V5S_DGPU
VM_A_BA0 M2 B2 2.64A
54 53 IN VM_A_BA0 M2 BA0 VDD#B2 B2 2.64A VM_A_BA0 VM_A_BA0 2.64A 54 53 IN VM_A_BA1
BA0 VDD#B2

VM_A_BA1 N8 D9 54 53 IN M2 BA0 VDD#B2 B2 2.64A 54 53 IN M2 BA0 VDD#B2 B2 54 53 IN N8 BA1 VDD#D9 D9


54 53 IN VM_A_BA2 M3
BA1 VDD#D9
G7 54 53 IN VM_A_BA1 N8 BA1 VDD#D9 D9 54 53 IN VM_A_BA1 N8 BA1 VDD#D9 D9 54 53 IN VM_A_BA2 M3 BA2 VDD#G7 G7
54 53 IN BA2 VDD#G7
K2 54 53 IN VM_A_BA2 M3 BA2 VDD#G7 G7 54 53 IN VM_A_BA2 M3 BA2 VDD#G7 G7 VDD#K2 K2
VDD#K2
VDD#K2 K2 VDD#K2 K2 VDD#K8 K8
VDD#K8 K8
VDD#K8 K8 VDD#K8 K8 VDD#N1 N1
VDD#N1 N1
N1 N1 DDR_CLKA1 J7 N9
54 53 IN DDR_CLKA0 J7 CK VDD#N9 N9
DDR_CLKA0 J7
VDD#N1
N9 DDR_CLKA1 J7
VDD#N1
N9
54 53 IN DDR_CLKA1# K7
CK VDD#N9
R1
54 53 IN DDR_CLKA0# K7 C_K_ VDD#R1 R1 54 53 IN DDR_CLKA0# K7
CK VDD#N9
R1
54 53 IN DDR_CLKA1# K7
CK VDD#N9
R1
54 53 IN DDR_CKEA1 K9
C_K_ VDD#R1
R9
54 53 IN DDR_CKEA0 K9 CKE_CKE0 VDD#R9 R9 54 53 IN DDR_CKEA0 K9
C_K_ VDD#R1
R9
54 53 IN DDR_CKEA1 K9
C_K_ VDD#R1
R9
54 53 IN CKE_CKE0 VDD#R9
54 53 IN CKE_CKE0 VDD#R9 54 53 IN CKE_CKE0 VDD#R9

VM_R_ODTA1 K1 A1
54 53 IN VM_R_ODTA0 K1 ODT_ODT0 VDDQ#A1 A1
VM_R_ODTA0 K1 A1 VM_R_ODTA1 K1 A1
54 53 IN DDR_CSA1#_0 L2
ODT_ODT0 VDDQ#A1
A8
54 53 IN DDR_CSA0#_0 L2 C_S__C_S_0_ VDDQ#A8 A8 54 53 IN DDR_CSA0#_0 L2
ODT_ODT0 VDDQ#A1
A8
54 53 IN DDR_CSA1#_0 L2
ODT_ODT0 VDDQ#A1
A8
54 53 IN DDR_RASA1# J3
C_S__C_S_0_ VDDQ#A8
C1
54 53 IN DDR_RASA0# J3 R_A_S_ VDDQ#C1 C1 54 53 IN DDR_RASA0# J3
C_S__C_S_0_ VDDQ#A8
C1
54 53 IN DDR_RASA1# J3
C_S__C_S_0_ VDDQ#A8
C1
54 53 IN DDR_CASA1# K3
R_A_S_ VDDQ#C1
C9
54 53 IN DDR_CASA0# K3 C_A_S_ VDDQ#C9 C9 54 53 IN DDR_CASA0# K3
R_A_S_ VDDQ#C1
C9
54 53 IN DDR_CASA1# K3
R_A_S_ VDDQ#C1
C9
54 53 IN DDR_WEA1# L3
C_A_S_ VDDQ#C9
D2
E 54 53 IN DDR_WEA0# L3 W_E_ VDDQ#D2 D2 54 53 IN DDR_WEA0# L3
C_A_S_ VDDQ#C9
D2
54 53 IN DDR_WEA1# L3
C_A_S_ VDDQ#C9
D2
54 53 IN W_E_ VDDQ#D2
E9 E
VDDQ#E9 E9 54 53 IN W_E_ VDDQ#D2
E9
54 53 IN W_E_ VDDQ#D2
E9
VDDQ#E9
F1
VDDQ#E9 VDDQ#E9 VDDQ#F1
VDDQ#F1 F1
F1 F1 VM_R_ADQSA(5) F3 H2
53 BI VM_R_ADQSA(2) F3 DQSL VDDQ#H2 H2
VM_R_ADQSA(3) F3
VDDQ#F1
H2 VM_R_ADQSA(4) F3
VDDQ#F1
H2
53 BI VM_R_ADQSA(6) C7
DQSL VDDQ#H2
H9
53 BI VM_R_ADQSA(1) C7 DQSU VDDQ#H9 H9 53 BI VM_R_ADQSA(0) C7
DQSL VDDQ#H2
H9
53 BI VM_R_ADQSA(7) C7
DQSL VDDQ#H2
H9
53 BI DQSU VDDQ#H9
53 BI DQSU VDDQ#H9 53 BI DQSU VDDQ#H9

VM_R_ADQM#(5) E7 A9
53 BI VM_R_ADQM#(2) E7 DML VSS#A9 A9
VM_R_ADQM#(3) E7 A9 VM_R_ADQM#(4) E7 A9
53 BI VM_R_ADQM#(6) D3
DML VSS#A9
B3
53 BI VM_R_ADQM#(1) D3 DMU VSS#B3 B3 53 BI VM_R_ADQM#(0) D3
DML VSS#A9
B3
53 BI VM_R_ADQM#(7) D3
DML VSS#A9
B3
53 BI DMU VSS#B3
E1
VSS#E1 E1 53 BI DMU VSS#B3
E1
53 BI DMU VSS#B3
E1
VSS#E1
G8
VSS#E1 VSS#E1 VSS#G8
VSS#G8 G8
G8 G8 VM_R_ADQSA#(5) G3 J2
53 BI VM_R_ADQSA#(2) G3 D_Q_S_L_ VSS#J2 J2
VM_R_ADQSA#(3) G3
VSS#G8
J2 VM_R_ADQSA#(4) G3
VSS#G8
J2
53 BI VM_R_ADQSA#(6) B7
D_Q_S_L_ VSS#J2
J8
53 BI VM_R_ADQSA#(1) B7 D_Q_S_U_ VSS#J8 J8 53 BI VM_R_ADQSA#(0) B7
D_Q_S_L_ VSS#J2
J8
53 BI VM_R_ADQSA#(7) B7
D_Q_S_L_ VSS#J2
J8
53 BI D_Q_S_U_ VSS#J8
M1
VSS#M1 M1 53 BI D_Q_S_U_ VSS#J8
M1
53 BI D_Q_S_U_ VSS#J8
M1
VSS#M1
M9
VSS#M1 VSS#M1 VSS#M9
VSS#M9 M9
VSS#M9 M9 VSS#M9 M9 VSS#P1 P1
VSS#P1 P1
P1 P1 VM_RESET T2 P9
54 53 BI VM_RESET T2 R_E_S_E_T_ VSS#P9 P9
VM_RESET T2
VSS#P1
P9 VM_RESET T2
VSS#P1
P9
54 53 BI R_E_S_E_T_ VSS#P9
T1
VSS#T1 T1 54 53 BI R_E_S_E_T_ VSS#P9
T1
54 53 BI R_E_S_E_T_ VSS#P9
T1 L8
VSS#T1
T9
VSS#T1 VSS#T1 ZQ_ZQ0 VSS#T9
L8 ZQ_ZQ0 VSS#T9 T9
L8 ZQ_ZQ0 VSS#T9 T9 L8 ZQ_ZQ0 VSS#T9 T9

1
1

1
R83 B1
R99 B1 VSSQ#B1
VSSQ#B1 R96 B1 R87 B1 243_1%_2 B9
243_1%_2 B9 VSSQ#B1 VSSQ#B1 VSSQ#B9
VSSQ#B9 243_1%_2 B9 243_1%_2 B9 D1
VSSQ#B9 VSSQ#B9 VSSQ#D1
VSSQ#D1 D1
VSSQ#D1 D1 VSSQ#D1 D1 VSSQ#D8 D8
D8

2
VSSQ#D8
D8 D8 E2
2

VSSQ#D8 VSSQ#D8 VSSQ#E2


E2

2
VSSQ#E2
VSSQ#E2 E2 VSSQ#E2 E2 J1 NC_ODT1 VSSQ#E8 E8
J1 NC_ODT1 VSSQ#E8 E8
J1 NC_ODT1 VSSQ#E8 E8 J1 NC_ODT1 VSSQ#E8 E8 L1 NC_C_S_1_ VSSQ#F9 F9
D L1 NC_C_S_1_ VSSQ#F9 F9
L1 NC_C_S_1_ VSSQ#F9 F9 L1 NC_C_S_1_ VSSQ#F9 F9 J9 NC_CE1 VSSQ#G1 G1 D
J9 NC_CE1 VSSQ#G1 G1
J9 NC_CE1 VSSQ#G1 G1 J9 NC_CE1 VSSQ#G1 G1 L9 NC_ZQ1 VSSQ#G9 G9
L9 NC_ZQ1 VSSQ#G9 G9
L9 NC_ZQ1 VSSQ#G9 G9 L9 NC_ZQ1 VSSQ#G9 G9
96-BALL
96-BALL
96-BALL 96-BALL SDRAM DDR3
SDRAM DDR3
SDRAM DDR3 SDRAM DDR3
SAM_K4W2G1646B_HC12_FBGA_96P
SAM_K4W2G1646B_HC12_FBGA_96P
SAM_K4W2G1646B_HC12_FBGA_96P SAM_K4W2G1646B_HC12_FBGA_96P

P1V5S_DGPU
P1V5S_DGPU P1V5S_DGPU
P1V5S_DGPU P1V5S_DGPU P1V5S_DGPU
P1V5S_DGPU P1V5S_DGPU

4.99K_1%_2 4.99K_1%_2
1
4.99K_1%_2 4.99K_1%_2

4.99K_1%_2 4.99K_1%_2
1

1
4.99K_1%_2 4.99K_1%_2

4.99K_1%_2 4.99K_1%_2

4.99K_1%_2 4.99K_1%_2
1

2
4.99K_1%_2 4.99K_1%_2

4.99K_1%_2 4.99K_1%_2
1

R85

R88
R101

R92

R105

R97

R76
R91

2
VREFC_U10
2

2
VREFC_U7 54 BI VREFD_U10
2

1
54 BI VREFD_U7 VREFC_U8 VREFC_U9 54 BI

1
54 BI 54 BI 54 BI

0.1UF_16V_2
VREFD_U8 VREFD_U9

1
54 BI 54 BI
0.1UF_16V_2

0.1UF_16V_2
1

1
0.1UF_16V_2

0.1UF_16V_2

0.1UF_16V_2
1

2
0.1UF_16V_2

0.1UF_16V_2
1

C123
2

R82
C155

C117
R100

R89
C143

C159

C149
R93

R104

C133

C113
R98
R90

R75

2
2

2
2

1
2

1
C C

P1V5S_DGPU
P1V5S_DGPU
P1V5S_DGPU P1V5S_DGPU

10UF_6.3V_3

2.2UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2
10UF_6.3V_3

1
2.2UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

10UF_6.3V_3

10UF_6.3V_3
1

2.2UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

2.2UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2

0.1UF_6.3V_2
1

C131

C124

C125

C127

C146

C147
C141

C142

C153

C152

C154

C134

C160

C128

C38

C44
C118

C135

C145

C139

C137

C151

C132

C129

C121

C148

C136
C73

C75

C140

C150
C70

C71

C48

C39
C122

2
2

2
B B

A A

INVENTEC
TITLE

MODEL,PROJECT,FUNCTION
VRAM DDR3

SIZE CODE DOC.NUMBER REV


C CS 1310xxxxx-0-0 X01
CHANGE by XXX DATE 21-OCT-2002 SHEET 54 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

VPCIE 14 9 IN VRP1V05S_VCCP
P1V0S_DGPU

3.4A
P15V0A
Q301 P3V3S_DGPU
1 D S 4 P3V3S
D 2 Q10

10uF_6.3V_3
AM2321P
60MA D

1
5

1M_5%_2
6 G 3 2 S D 3

C302

200_5%_2
0.1UF_16V_2
NMOS_4D1S

R300

10K_5%_2

1
FDC655BN
6.3A/30V

R28
R27
C28
1

2
R301

2
P15V0A_RC 1 2

2
3

2200pF_50V_2
R22 3
0_5%_2 DGPU_PWR_EN#

1
55 30 IN
Q300

D
1 2

D
1
DGPU_PWR_EN# 1 G

C301
55 30 IN G 1K_5%_2
Q9

S
S
CSC0402_DY

SSM3K7002FU 2
1

SSM3K7002FU

2
C300

2
2

C C

DEFULT IS PX5.0
P15V0A

560K_1%_2_DY
BACO MODE

1
P1V5S_DGPU
P1V5

R19
B P15V0A 1.2A B
P1V8S
P1V8S_DGPU
1

P3V3A

3 2
Q15
Q14 1 8
P3V3A R11
3.1A SSM3K7002FU_DY 2
S D
7
560K_1%_2 3 6
R18 R20

D
1 2 1 1 2 4 5
2

G G
Q4 NMOS_4D3S
4 1

2.2UF_6.3V_2
100K_5%_2_DY

S
S D

1
0_5%_2_DY AON7410

0.01UF_50V_2_DY
2

3
3

Q5
SSM3K7002FU 5

C74
2
R12 3 6 8A/30V
D

D
G
PX_MODE 1
2.2UF_6.3V_2
1 2 1 G NMOS_4D1S
52 56 G
IN
1

C51
FDC655BN
0.01UF_50V_2

2
S

S
1

100K_5%_2
C72
3

Q13
6.3A/30V

2
C13

SSM3K7002FU_DY
2

2
D

DGPU_PWR_EN 1
2

56 52 30 27 IN G
2
S

Q6
SSM3K7002FU R102
1 2
2

A 0_5%_2 A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
DGPU POWER EE
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 55 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PVBAT

D
D
P5V0A

CSC0805_DY
4.7UF_25V_5_DY

10UF_25V_5
R6755

1
5
6
7
8
240K_5%_2

C6760

C6761

C6762
Q6750
1 2

FDMC7696

D
NMOS_4D3S
R6752 C6753

2
1 2 U6750 2.2_5%_3 0.1UF_16V_2
1 16 TON BOOT 13 1 2 1 2

1
R6756

1UF_6.3V_2

1UF_6.3V_2

S
10_5%_2 9 VDDP OCP=19A
C6754

C6757

4
3
2
1
UGATE 12 VRPVCORE_DGPU_HG
L6750 CHOKE_4PIN_2PIN
VRPVCORE_DGPU
2

2 2 11 VRPVCORE_DGPU_PH 1 2
VDD PHASE 1 2 OUT 14
3 4

5
6
7
8
3 4
VRPVCORE_DGPU_LG

RSC_0603_DY
LGATE 8

330UF_2V_9MR_PANA_-35%
CYN_PCMB063T_R68MS_4P

FDMS0308AS

1
Q6751

1
D

2K_1%_2
52 35 31 OUT DGPU_PWROK 4 PGOOD

R7675

R6750
10 CS G0 7 POW_SW0 IN 49
1

1
C 3 C

2
FB

C6750
S

2
R6758

+
9.53K_1%_2 14 POW_SW1
G1 IN 49

4
3
2
1
R6780
R6753 2

16.2K_1%_2
CSC0402_DY
DGPU_PWR_EN 1 2

1
15 5 1
2

55 52 30 27 IN EN_DEM D1

2
8.66K_1%_2

C7675

R6751
0_5%_2 17 6
GND D0
1 2
1 R6754
PX_MODE 1 R6781 2 VOUT
52
55 IN 21K_1%_2

2
0_5%_2_DY REA_RT8208BGQW_WQFN_16P

P.S. R6750(R1)R6751(R2)R6753(R3)R6754(R4)
B B

A A

INVENTEC
TITLE
MODEL,PROJECT,FUNCTION
DGPU POWER
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 56 of 57

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

POWER BUTTON BOARD P3V3A_PBN


USB BOARD P5V0A_PBN

1
PAD9200
1

2 2
P5V0A_DB
57 PWR_LED#_PBN 3
OUT 3
DGND_USB

CN9100 57 EC_PWRBTN#_PBN 4
C9100 OUT 4
2 1
1 1
LID SW LID_SW#_PBN 5

PHP_PESD5V0S1BB_SOD523_2P_DY

PHP_PESD5V0S1BB_SOD523_2P_DY

PHP_PESD5V0S1BB_SOD523_2P_DY
+ 2 P3V3A_PBN 57 IN 5
4
4
2
330uF_6.3V 3 6
3 P5V0A_DB P5V0A_USB2 C9200
6
4

DGND_PBN
DGND_USB
4
D

DGND_PBN

2
5 C9101 0.1uF_16V_2 U9200
5 1
57 USBPWR_EN_UB 6
2 1 U9100 2 1 VDD SMDPAD6_100_28X118 D
IN 6
1 8 3

2
7 GND OUT GND

330uF_6.3V
7 1uF_6.3V_2 2

1
2 IN OUT 7 OUT
57 USB_P1_UB_DP 8
BI 8

D9201

D9202

D9203
3 IN OUT 6
USB_P1_UB_DN 9

C9102
57 BI 9
USBPWR_EN_UB
OUT LID_SW#_PBN

+
57 4 EN 5 57
10 10 IN OC# MAG_MH248BESO_SOT23_3P

1
57 USB_P9_UB_DP 11 GMT_G547E1P81U_MSOP_8P 6019B0602501 DGND_PBN
BI USB_P9_UB_DN 12
11
57 BI 12

1
13 13

DGND_USB
14 14
15 15 G G1
16 16 G G2 DGND_USB DGND_USB

DGND_PBN
DGND_PBN
DGND_USB

DGND_USB DGND_PBN DGND_PBN DGND_PBN


1 S9201 1 S9200
1 S9100 ACES_50501_01641_001_16P P3V3A_PBN
SCREW230_500_1P SCREW230_500_1P
SCREW280_800_1P
DGND_USB

S9101

1
1

100_5%_2
SCREW280_650_NP_1P POWER LED

2 R9201
P5V0A_USB2 POWER BUTTON
DGND_USB

2
C9103
1 USB 2.0 CONN 1 57 OUT EC_PWRBTN#_PBN2
SW9200
2 4 4
D9100

CN9101 PWR_LED#_PBN 1 2 1 R9200 2

DGND_USB
1 3 57 IN
C 22uF_6.3V_5 1 3 C
1 VCC G1 G1 100_5%_2
USB_P1_UB_DN 1 L9100 2 USB_P1_UB_L_DN 2 G2
57 BI D- G2 TEMIC_NTC033_XJ1J_X160T_4P 19_217_W1D_AP1Q2QY_3T
57 USB_P1_UB_DP 4 3 USB_P1_UB_L_DP 3 G3
BI D+ G3
6026B0052301 6011B0028601
4 4 G4 G4
DGND_PBN
WCM_2012_900TU9101 SYN_020133GR004M53BZL_4P
2 2 3 3
IO IO
P5V0A_USB2
DGND_USB

DGND_USB

1 4
1
Vcc 4

PHP_PRTR5V0U2X_SOT143_4P_DY
GND P3V3A_TP
PAD9000 TOUCHPAD R / L BOARD
TO MB 1 1

57 TP_DAT_TPB 2
BI 2

P5V0A_USB2 57 TP_CLK_TPB 3
BI 3

4 SW9000
DGND_USB

2
C9104
1 USB 2.0 CONN 2 57 BI TP_SMBUS_DAT_TPB 5
4

45
4 57 OUT L_KEY_TPB 1 1 4 4 L KEY
CN9102 DGND_USB
2 2 5 5

DGND_TP
22uF_6.3V_5 57 TP_SMBUS_CLK_TPB 6
BI 6 5
4 3 3 6 6
B L9101
1 VCC G1 G1 B
57 USB_P9_UB_DN 1 2 USB_P9_UB_L_DN 2 G2
BI USB_P9_UB_DP 4
D- G2
SMDPAD6_100_28X118
57 3 USB_P9_UB_L_DP 3 G3
BI D+ G3

DGND_TP
DGND_TP
1 S9000 DIP_TMG_533_Q_T_R_6P
4 4 G4 G4
WCM_2012_900TU9102 SYN_020133GR004M53BZL_4P
SCREW210_300_1P DGND_TP DGND_TP 6026B0001201
2 2 3
3
1 S9001
IO IO
SW9000,SW9001
P5V0A_USB2 SCREW210_300_1P
★PIN2,5 IS GND
DGND_USB

1
DGND_USB

4 TO T/P MODULE SW9001


1
GND Vcc
4

57 IN L_KEY_TPB 1 PAD9001
1 57 OUT R_KEY_TPB 1 1 4 4 R KEY
PHP_PRTR5V0U2X_SOT143_4P_DY 2 5
2 5

DGND_TP
57 R_KEY_TPB 2 3 6
IN 2 3 6

DGND_TP 3 3
DIP_TMG_533_Q_T_R_6P
57 TP_CLK_TPB 4 6026B0001201
BI 4
DGND_TP
57 TP_DAT_TPB 5
BI 5

6 6

TP_SMBUS_DAT_TPB 7
A 57 BI 7
1 FIX9001 1 FIX9002 1 FIX9004 A
57 TP_SMBUS_CLK_TPB 8 FIX_MASKFIX_MASKFIX_MASK
BI 8

SMDPAD8_100_28X118 1 FIX9003 1 FIX9005


P3V3A_TP
FIX_MASKFIX_MASK

1 FIX9100 1 FIX9101 1 FIX9102 1 FIX9103


for Dauther Board
INVENTEC
FIX_MASK FIX_MASK FIX_MASK FIX_MASK
1 FIX9200 1 FIX9201 1 FIX9202 1 FIX9203
FIX_MASK FIX_MASK FIX_MASK FIX_MASK
TITLE
MODEL,PROJECT,FUNCTION
USB, POWER BUTTON DB
DOC.NUMBER REV
SIZE CODE 1310xxxxx-0-0 X01
A3 CS
CHANGE by XXX DATE 21-OCT-2002 SHEET 57 of 57

8 7 6 5 4 3 2 1

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