IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO.

2, MARCH 2008 841

Analysis and Optimization of Switched-Capacitor

DC–DC Converters
Michael D. Seeman, Student Member, IEEE, and Seth R. Sanders, Member, IEEE

Abstract—Analysis methods are developed that fully determine

a switched-capacitor (SC) dc–dc converter’s steady-state perfor-
mance through evaluation of its output impedance. This analysis
method has been verified through simulation and experimentation.
The simple formulation developed permits optimization of the ca-
pacitor sizes to meet a constraint such as a total capacitance or
total energy storage limit, and also permits optimization of the
switch sizes subject to constraints on total switch conductances
or total switch volt-ampere (V-A) products. These optimizations
then permit comparison among several switched-capacitor topolo-
Fig. 1. Model of an idealized switched-capacitor converter.
gies, and comparisons of SC converters with conventional mag-
netic-based dc–dc converter circuits, in the context of various ap-
plication settings. Significantly, the performance (based on conduc-
tion loss) of a ladder-type converter is found to be superior to that of the switch sizes subject to constraints on total switch conduc-
of a conventional magnetic-based converter for medium to high tances or total switch volt-ampere (V-A) products. These opti-
conversion ratios.
mizations are carried out for a set of representative switched-ca-
Index Terms—Analysis, dc–dc converter, output impedance, pacitor topologies. These optimizations then permit comparison
switched-capacitor.
among several switched-capacitor topologies, and comparisons
of SC converters with conventional magnetic-based dc–dc con-
I. INTRODUCTION verter circuits. The performance (based on conduction loss) of
a ladder-type converter is found to be superior to that of a con-
ventional boost converter for medium to high conversion ratios.
T HIS paper develops analysis methods that fully determine
a switched-capacitor (SC) dc–dc converter’s steady-state
performance through evaluation of its output impedance. This II. SWITCHED-CAPACITOR CONVERTER IMPEDANCE ANALYSIS
resistive impedance is a function of frequency and has two
asymptotic limits: one where resistive paths dominate the With the model in Fig. 1, the converter provides an ideal dc
impedance, and another where charge transfers among ideal- voltage conversion ratio under no load conditions, and all con-
ized capacitors dominate the impedance. This work develops version losses are manifested by voltage drop associated with
a network theoretic analysis of these two asymptotic limits, non-zero load current through the output impedance [1], [5].
which can be used to evaluate both the converter efficiency and The resistive output impedance accounts for capacitor charging
output regulation as a function of load for a broad class of SC and discharging losses and resistive conduction losses. Addi-
converters. Simulations and experiments have been performed tional losses due to short-circuit current and parasitic capaci-
to verify the analysis methods. tances, in addition to gate-drive losses, can be incorporated into
The comprehensive analysis and design calculations given the model. However, they will not be considered here since these
here are new, but connect with the analysis framework devel- effects are generally application and implementation dependent.
oped in the pioneering work of [1]. The work in [1], [2] offered Insight gained can be used to model effects of parasitic capaci-
a network theoretic formulation for computation of open-circuit tances [8]. For the present, our aim is to provide a general anal-
dc–dc conversion ratios, and a rather involved method for com- ysis and design framework.
putation of output impedance. Reference [1] and other previous The low-frequency output impedance in Fig. 1 sets
analysis work [3]–[7] mainly focused on the performance anal- the maximum converter power, constrained by a minimal
ysis (i.e., output impedance computation) for a single converter efficiency objective, and also determines the open-loop load
topology. regulation properties. There are two asymptotic limits to
The simple formulation developed permits optimization of output impedance, the slow and fast switching limits, as re-
the capacitor sizes to meet a constraint such as a total capaci- lated to switching frequency. The slow switching limit (SSL)
tance or total energy storage limit, and also permits optimization impedance is calculated assuming that the switches and all other
conductive interconnects are ideal, and that the currents flowing
Manuscript received October 5, 2006; revised August 8, 2007. Recommended between input and output sources and capacitors are impulsive,
for publication by Associate Editor P. Jain. modeled as charge transfers. The SSL impedance is inversely
The authors are with the Department of Electrical Engineering and Com- proportional to switching frequency. The fast switching limit
puter Science, University of California, Berkeley, CA 94720 USA (e-mail:
[email protected]). (FSL) occurs when the resistances associated with switches,
Digital Object Identifier 10.1109/TPEL.2007.915182 capacitors and interconnect dominate, and the capacitors act
0885-8993/$25.00 © 2008 IEEE
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842 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

effectively as fixed voltage sources. In the FSL, current flow

occurs in a frequency-independent piecewise constant pattern.
The set of converters considered in this paper is limited to
two-phase converters made solely of ideal capacitors, resistive
switches, and input and output voltage sources. Two-phase con-
verters switch alternately between two configurations. Multi-
phase converters [4] are outside the scope of this paper, but can
be considered using similar methods. This paper does not ad-
dress the more fundamental topological conditions needed to
determine whether or not a specific circuit constitutes a well-for-
mulated two-phase converter. Rather, the paper assumes that
the circuits under consideration all have well-defined two-phase
operation. References [1], [2] begin to address the topological
question of what constitutes a well-formulated two-phase SC
dc–dc circuit, though the characterization given is not complete.

Fig. 2. 3 V to 1 V ladder circuit.

A. Slow-Switching Limit Impedance

For the slow-switching limit (SSL) impedance analysis, the

finite resistances of the switches, capacitors, and interconnect
are neglected. A pair of charge multiplier vectors and can
be derived for any standard non-degenerate two-phase SC con-
verter. The charge multiplier vectors correspond to charge flows
that occur immediately after the switches are closed to initiate
each respective phase of the SC circuit. Each element of a charge
multiplier vector corresponds to a specific capacitor or inde-
pendent voltage source, and represents the charge flow into that
component, normalized with respect to the output charge flow.
As outlined in [1], the charge multiplier vectors can be uniquely
computed using the KCL constraints in each topological phase
and the constraint that the two charge multiplier quantities on
each capacitor are equal and opposite.
The charge multiplier vector is defined as

(1) Fig. 3. Charge flow in ladder converter. (a) phase 1 (b) phase 2.

where each component is the ratio of charge transfer in each

element during phase 1 of the switching period to the charge In each of these charge multiplier vectors, the first compo-
delivered to the output during a full period. If charge flows into nent corresponds to the output charge flow, thus these two com-
the element during phase 1, the corresponding entry in the ponents must sum to one. The last component of each charge
vector is positive. Vector is defined analogously, for phase multiplier vector corresponds to the charge flow into the input
2. The charge multiplier vector can be partitioned into output, source, and is non-zero during only phase 2 in this example.
capacitor and input components, respectively The charge multiplier vectors, the capacitor characteristics,
and the switching frequency are the only data needed to de-
(2) termine the output impedance under the asymptotic SSL con-
dition. The calculation, developed here, is based on Tellegen’s
For the ladder network example of Fig. 2, the charge multiplier Theorem [9] which states that for any network, any vector of
vectors can be obtained through network analysis using Kir- branch voltages that satisfies KVL is orthogonal to any vector
choff’s Current Law (KCL) [1]. In this example, and in all other of branch currents (or equivalently charge flows) that satisfies
examples encountered by the authors, the charge multiplier vec- KCL. This theorem is applied in each of the two configurations
tors can be obtained by inspection (in Fig. 3). The charge from for a two-phase switched capacitor converter operating in pe-
the input source flows into C4 during phase 2. In phase 1, that riodic steady state, where the input is short-circuited and the
charge is transferred into C3. By considering alternating phases, output is connected to an independent dc voltage source. The
the charge flow in each component can be found charge flow per period (or average current flow) into the single
independent source then defines the output impedance.
Application of Tellegen’s theorem to the switched capacitor
(3) converter, in each of its two configurations, yields
(4) and , where and are the respective steady
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SEEMAN AND SANDERS: ANALYSIS AND OPTIMIZATION OF SWITCHED-CAPACITOR DC–DC CONVERTERS 843

state network voltage vectors in phases 1 and 2. Additively com-

bining these two applications of Tellegen’s theorem, and noting
that the input voltage source has value zero, yields

(5)

where the first term corresponds to the constant output voltage

source and the terms under the summation correspond to the
capacitor branches. Recall that and that
for each capacitor branch (due to charge conservation in
periodic steady-state). By defining and
and multiplying (5) by , the net charge delivered to
the output in a period, we obtain

Fig. 4. Switch charge flow in ladder converter. (a) Phase 1, (b) Phase 2.
(6)

impedance can be determined by simply examining the charge

where . In (6), the first term corresponds to
flow in the converter without simulation or complicated network
the product of the constant output voltage and the total charge
analysis.
flow into this independent voltage source, and each term in the
summation corresponds to energy loss associated with a specific
capacitor. It is of direct interest here that none of the capacitor B. Fast Switching Limit Impedance
voltages need to be explicitly calculated for this analysis. Rather,
can be computed from The other asymptotic limit, the fast switching limit (FSL),
is characterized by constant current flows between capacitors.
(7) The switch on-state impedances and other resistances are suf-
ficiently large such that during each phase, the capacitors do
where is the capacitance value of the th capacitor, assuming not approach equilibrium. In the asymptotic limit, the capacitor
linear capacitors. Introducing (7) into (6), and then dividing the voltages are modeled as constant. The circuit loss is related only
result by yields to conduction loss in resistive elements. The concept of the FSL
impedance is introduced informally in [5].
The duty cycle of the converter is important when considering
(8) the FSL impedance since currents flow during the entirety of
each phase. For this analysis, a duty cycle of 50% is assumed
for simplicity. Duty cycle differing from 50% can be included
We note that corresponds to the th entry of the charge in the following analysis without much difficulty if another duty
multiplier vector , since these entries are for the capacitors. cycle is used. Additionally, only the on-state switch resistance is
Dividing (8) by the switching frequency then directly yields the considered; other parasitic resistance [e.g., capacitor equivalent
average output impedance for the slow-switching asymptotic series resistance (ESR)] can be similarly incorporated into the
limit model if desired.
The values are defined as the charge flow through each
(9) switch during the phase in which the switch is on. Even in
the FSL, the charge flows must follow the same pattern as in
the SSL, constrained by and . For the switches that are
The converter’s loss in terms of the series output impedance
on during phase 1, the corresponding values can be de-
can be expressed in terms of capacitor loss. The product
termined from the components. Analogously, corresponding
in (6) represents the energy loss by charging and dis-
values for switches that conduct during phase 2 can be de-
charging capacitor in each cycle, and could be used to cal-
termined from the components. The values of are inde-
culate the converter’s loss even with a nonlinear capacitor. In
pendent of duty cycle as they simply represent the charge flow
the following discussion, attention is restricted to the case of
through the switches that ensure charge conservation on the cir-
linear capacitors. The sum of the energy lost through the capac-
cuit’s capacitors. The values for the switches in the ladder
itors is equal to the calculated loss associated with the output
converter in Fig. 2 can be determined directly. The charge flows
impedance for a given load.
in the switches during both phases are shown in Fig. 4, resulting
This powerful result yields a simple calculation of this asymp-
in an vector of
totic output impedance and some intuition into the operation of
SC converters. The output impedance directly models the losses
in the circuit due to capacitor charging and discharging. This (10)
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844 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

For positive power flow (i.e., from the input to output source), single real output resistance, it is now possible to optimize the
the sign of each component of the vector indicates the direc- components in order to minimize that output impedance. Min-
tion of current flow with respect to the blocking voltage of a imal output impedance corresponds to maximum efficiency for
switch. A positive quantity indicates the switch conducts posi- a given power delivered, and dually, corresponds to maximum
tive current while on and blocks positive voltage while off. This power delivery for a given loss. This section develops optimality
switch must be implemented using an active transistor. A nega- computations for the slow switching limit (SSL) and the fast
tive quantity indicates the switch conducts negative current and switching limit (FSL) impedance. When optimizing over capac-
blocks positive voltage and is suitable for diode implementation itances, one should minimize the output impedance that is asso-
(if the forward voltage drop is tolerable). For power flow in the ciated only with the capacitances, namely the SSL impedance.
opposite direction, the switch types reverse. Analogously, when optimizing over switch sizes, one should
In the FSL, the current through the on-state switches is as- minimize the FSL output impedance. The final design step is to
sumed to be constant. Given the charge flow vector, the current choose a maximum operating frequency for which the parasitic
in each switch is easily determined losses are acceptable. The total capacitance and switch conduc-
tance should be adjusted such that the total impedance meets
(11) the design goal and the SSL and FSL impedances are balanced.
The last step ensures that the total switch and capacitor sizes
where is the charge flow through switch during a single pe-
(and costs) are minimized for the intended power level.
riod. The factor of two appears because of the 50% duty cycle.
The optimization procedure requires knowledge of the com-
Substituting and into (11)
ponent working voltages, unlike the output impedance analysis.
yields
The working voltage for a capacitor is the maximum voltage
(12) on the capacitor during steady-state converter operation. For a
transistor (switch), the working voltage is the voltage it blocks
The current through the switches is only dependent on the vector during steady-state converter operation. For open-circuit opera-
, which is obtainable by inspection. The network voltages tion, these working voltages can be found by inspection in most
never need to be found in this analysis, simplifying computa- examples, or by the process outlined in [1]. This analysis is
tion significantly. based on combining KVL constraints for the two phase topolo-
The average power loss due to each individual switch is equal gies, in combination with a known source voltage. The result is
to the instantaneous on-state power loss multiplied by its duty the computation of vectors denoted and for the working
cycle. Since the total loss of the SC converter in the FSL is just voltages of the capacitors and switches, respectively, ratioed to
the sum of the switch losses, the total circuit loss is given by the converter output voltage.
The optimization is based on a physical size (or cost) con-
(13) straint for the devices. When capacitors are optimized, their total
energy storage capability is held constant. Or, in the case when
where is the on-state resistance of switch . all capacitors must be rated for the same voltage, the total capac-
Since the input and output charge flow in the SC converter is itance is held constant. Likewise, when the switch sizes are opti-
constrained by the conversion ratio , all the power loss in an mized, the total V-A capacity product is held constant. This V-A
ideal SC converter (as analyzed here) is modeled by the output metric translates to a constraint on the G- products summed
voltage drop. Thus the output impedance can be determined by over the switches (G refers to switch conductance). If all the
equating the actual power loss of the circuit with the apparent switches are rated for the same voltage, the constraint reduces
power loss due to the output impedance. Since this power loss is to holding the sum of the switch conductances constant.
proportional to the square of the output current, the FSL output
impedance can be obtained by inspection A. SSL Capacitor Optimization
The capacitor optimization uses a constraint that holds the
(14) total energy storage capability, summed over all capacitors,
fixed to a constant . This constraint can be mathematically
expressed as
Similar to the SSL output impedance in (9), the FSL output
impedance is given simply in terms of component parameters
(15)
and the switch charge multiplier coefficients of each switch. The
power loss due to these conduction losses is equal to the equiva-
lent power loss through the output impedance. These two simple where represents the value of capacitor and rep-
forms of the output impedance (given in (9) for the SSL and (14) resents the rated voltage of capacitor . The energy storage capa-
for the FSL) can be used to provide strong guidance for the de- bility of a capacitor is related to its rated voltage, as that dictates
sign of switched-capacitor power converters. its size and cost, not the maximum voltage it sees during opera-
tion. However, the capacitor’s working voltage must be less than
III. COMPONENT OPTIMIZATION the rated voltage to avoid damaging the component, and should
Given that all converter losses attributed to the capacitors be close to the rated voltage to achieve good utilization of the
and resistive switches can be reflected in the computation of a device.
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SEEMAN AND SANDERS: ANALYSIS AND OPTIMIZATION OF SWITCHED-CAPACITOR DC–DC CONVERTERS 845

A function is defined to perform the constrained optimiza- The optimized SSL output impedance (from (21)) thus sim-
tion plifies to

(16) (23)

where the first term represents the SSL output impedance These optimization results for the single-voltage technology are
(scaled by switching frequency as it does not effect the min- very simple to utilize in switched-capacitor converter design.
imization) and the second term incorporates the constraint
in (15). The impedance is minimized by equating the partial B. FSL Switch Optimization and Sizing
derivatives of with respect to and with zero Like capacitors, the switches in a SC converter can be opti-
mized, yielding dramatic performance increases. This optimiza-
(17) tion is carried out in the asymptotic fast switching limit where
output impedance is directly related to switch conductance. This
(18) optimization assumes a duty cycle of 50%.
The switch VA product, summed over all switches, is used
as the cost-based metric in this optimization. This V-A metric
Equation (18) simply repeats the constraint in (15). corresponds to a constraint on the G- product summed over
The relationship in (17) sets up a proportionality between the switches, for both discrete and integrated switches. Paral-
, and . The energy constraint can be used to find an leling discrete switches increases total conductance, whereas
expression for the value of each capacitor placing switches in series increases voltage blocking while de-
creasing conductance. To increase voltage blocking without re-
(19) ducing conductance, the number of devices used scales quadrat-
ically, motivating the G- metric.
The optimal energy storage of each capacitor is proportional to In an integrated application, the same total G- constraint
the – product of each capacitor applies. The transistor length and nominal voltage scale lin-
early with process feature size. In addition, switch conductance
scales proportionally with transistor width and inversely with
(20)
transistor length. A cost metric , related to the area (or width
multiplied by length) of a specific transistor, can be written as
When the total energy is constrained, the optimal capacitor (in units of , i.e., S- ).
energies are proportional to the product of their rated voltage This constraint, applicable to both discrete and integrated
and their charge multiplier coefficients. In addition, the ripple transistors, can be expressed as
voltage on each capacitor is directly proportional to that capac-
itor’s rated voltage. (24)
The optimized output impedance can be calculated by com-
bining (9) and (19) where is the conductance of switch and is the
rated voltage of switch . As in the capacitor optimization,
(21) is the voltage the device can support, not necessarily
the voltage it blocks in normal operation. Naturally, the rated
voltage must be larger than the nominal blocking voltage.
By optimizing the capacitors, the output impedance becomes A Lagrange optimization function is formed to minimize
proportional to the square of the sum of the products of voltages the FSL output impedance while satisfying the constraint in (24)
and charge flows (V-A product) of each capacitor. The optimiza-
tion can improve the performance of an SC converter designed
in an ad-hoc manner significantly, especially one with a large
conversion ratio.
(25)
If all capacitors in a SC converter are rated for the same
voltage, as in the ladder topology or in applications with inte- The first term corresponds to the FSL output impedance (the
grated capacitors, the optimization results can be simplified. In factor of two in (14) does not affect the optimization) and the
this case, we constrain total capacitance to a value of , and second term corresponds to the constraint in (24). The mini-
the value of each individual capacitor is given by mization is performed by taking the partial derivative of (25)
with respect to and setting it to zero
(22)
(26)
Each capacitor is sized proportionally to its charge multiplier
coefficient. With optimized capacitors, the voltage ripple on Again, differentiating with respect to yields the constraint in
each capacitor is set equal in magnitude. (24).
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846 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

Equation (26) yields a proportionality between and the

ratio between the switch’s charge multiplier coefficient and its
voltage rating. This proportionality, when combined with the
G- constraint in (24), yields an expression for the optimal
conductance of each switch

(27)

Comparing the optimal conductance to the optimal capac-

itance in (19) makes it evident that the two optimizations are
analogous.
The optimal FSL output impedance is obtained by substi-
tuting (27) into (14)

(28)

Similar to the optimal SSL impedance, the optimal FSL output

impedance is related to the square of the sum of the V-A prod-
ucts. This simple form of the optimal output impedance allows
the comparison of various SC converter topologies. Several SC
converter topologies are compared in Section IV.
Many SC converters use switches with a single voltage
rating. For instance, many IC-based converters only use the
native NMOS transistors of the process since these transistors
perform the best. In addition, topologies such as the ladder
converter utilize switches that must all block the same voltage.
The switch-cost constraint discussed in the previous section
simplifies into a constraint on total switch conductance .
The optimal conductance of each switch simplifies to

(29)

likewise, when all switches are rated for an identical voltage, the
optimal FSL output impedance simplifies to

(30)

The performance of a converter is related to the square of the

sum of the charge multiplier coefficients. Topologies with a
small sum of these coefficients perform better for a given switch Fig. 5. Five step-up SC converter topologies. (a) Ladder. (b) Cockcroft–Walton
conductance than a topology with a large sum of coefficients. Multiplier. (c) Fibonacci. (d) Series-Parallel. (e) Doubler.
In integrated applications or other applications where single-
voltage switches must be used, this optimization can be used.
A comparison of SC converters based on single-voltage devices Step-up versions of the topologies are considered, as shown
is performed in Section IV. in Fig. 5, although step-down versions would yield identical
results. The commonly-used Dickson Charge Pump is a simple
IV. COMPARISON OF SC CONVERTER TOPOLOGIES transformation of the Cockcroft–Walton multiplier, constructed
A number of SC converter topologies exist in the literature by connecting the negative plate of each capacitor to either
[1], [3]–[5], [10], [11]but the merits of each have never been node A or B. The capacitors in the Dickson charge pump
compared in a methodical way. The optimizations in Sec- form two star networks while the capacitors in the Cock-
tions III-A and III-B can be used to provide a performance croft–Walton multiplier form two linear strings. The optimal
comparison among different common SC converter topologies. output impedance for all topologies in both asymptotic limits is
Fig. 5 shows five converter topologies discussed in the litera- evaluated for a range of conversion ratios (represented by ).
ture. When evaluating the FSL output impedance, the converters
The first comparison uses the cost metrics in Section III are evaluated on the ratio (the ratio between
and assumes that devices of every voltage rating are available. the G- product of the converter and the switch G- product
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SEEMAN AND SANDERS: ANALYSIS AND OPTIMIZATION OF SWITCHED-CAPACITOR DC–DC CONVERTERS 847

Fig. 7. (a) SSL and (b) FSL performance metrics with single-voltage devices.
Fig. 6. (a) SSL and (b) FSL performance metrics with optimal-voltage devices.

the Fibonacci and Doubler topologies, exhibit mediocre per-

summed over all switches). For a given cost constraint and con- formance in both the SSL and FSL comparisons. However,
version ratio, the converter with the highest metric is the one since the switches and capacitors used in their implementations
with the lowest FSL output impedance. Likewise, when the SSL support a range of different voltages and most of the switches
output impedance is considered, the converters are evaluated on are not ground-referenced, practical implementation would be
the ratio , where a larger metric corre- difficult if not impossible.
sponds to a smaller SSL impedance. The second comparison performed assumes that all devices
After performing the optimization and comparison, the five must be of the same voltage rating. In integrated applications
topologies are compared in Fig. 6. At a conversion ratio of two, using standard CMOS processes, the switches and capacitors are
all topologies perform identically. Upon further inspection, for usually all rated for the same voltage. The process is chosen such
2 only, these five topologies are actually identical. Con- that this voltage rating corresponds to the maximum voltage
verters that do well in the SSL comparison, such as the se- seen on any device. However, the switches and capacitors can
ries-parallel topology, do poorly in the FSL comparison. Con- be rated differently from each other, ie. if the highest-voltage
versely, topologies such as the Cockcroft–Walton multiplier and switch is rated for 1 V, a 1 V process would be used, even if
the Ladder topology that perform well in the FSL comparison some capacitors support a higher voltage.
typically perform poorly in the SSL comparison. Some con- The comparative results using identically-rated switches and
verters use capacitors efficiently and others use switches effi- transistors are shown in Fig. 7. The series-parallel topology is
ciently, but none of these converters are superior in both asymp- still optimal in the SSL comparison, as all capacitors in that
totes. For converters designed using a capacitor-limited process, topology also support the same voltage. Likewise, the ladder
a series-parallel topology would work best, while switch-limited topology is optimal in the FSL comparison, as all switches in
designs should use a topology such as the Cockcroft–Walton that topology support the same voltage. However, the exponen-
multiplier or ladder topology. tial converters are now relatively poor in both comparisons be-
The exponential converters (where the conversion ratio is cause they involve a wide range of device stresses, which is im-
exponentially related to the number of capacitors), such as practical in implementation. These comparisons can be used to
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848 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

Fig. 8. (a) Standard boost converter. (b) Transformer-bridge converter.

Fig. 9. Performance metric comparison.

select the best topology for any given application. Reference [8]
includes more computational details for these converters. The step-up ladder-type SC converter is considered first. All
switches in the ladder topology must be rated for 1 V. The lowest
V. COMPARISON WITH CONVENTIONAL DESIGNS two switches in the ladder structure have an component of
while the other switches simply have an
Switched-capacitor converters have several advantages component of 1. Thus, the sum of the components is
over conventional inductor-based dc–dc converters. With a
switched-capacitor converter, conduction and switching losses
are not additional losses, but are already incorporated in the (31)
output impedance based losses calculated in Sections II–A
and Sections II-B. The only losses that are not included in the
The optimal FSL output impedance of this converter (con-
output impedance are the gate drive losses, losses associated
strained such that ) is thus
with parasitic capacitances and control power. Short-circuit
(shoot-through) power can be eliminated by the use of suf-
ficiently non-overlapping clocks. Stray capacitances from (32)
dynamic nodes must be minimized and their losses incorpo-
rated into the efficiency of the converter if the strays are not Computing the ratio of this output resistance to the square of
eliminated. These losses are further considered in [8]. the output voltage yields the performance metric of the ladder
A SC converter and a conventional dc–dc converter can be circuit, . This metric is also plotted in Fig. 9.
compared directly when conduction loss is considered. The sil-
icon area (for the switches and control functions) is the domi- The boost converter in Fig. 8(a) is operated at duty cycle
nant cost in many dc–dc converters. A converter with a signifi- to achieve a step-up ratio of n. The duty cycle of switch S1
cantly-lower switch conductance loss may have a cost advantage is and the duty cycle of switch S2 is
over a converter with a higher switch loss. For the SC converter, . The conduction loss in this circuit is directly
the conduction loss is equal to the loss corresponding to the FSL computed as
output impedance. The switch-related loss of an inductor-based
converter is made up of conduction losses, due to switch on-state (33)
resistance, and switching losses during the switch state transi-
tions. Only the conduction loss will be considered here, using
The equivalent loss impedance can be directly compared
the FSL performance metric developed in
to the output impedance of the SC converter. Optimizing the
Section IV.
ratio of the two switch conductances for a given duty cycle, the
A ladder-type step-up converter [such as the one in Fig. 5(a)]
following constraint can be derived
is considered, as it uses switches most efficiently in the FSL.
Two magnetic-based converters are compared, the boost con-
verter and transformer-bridge converter, both shown in Fig. 8.
Total switch G- product is held constant for all converters, (34)
and the SC converter is assumed to operate in the FSL. Fi-
nally, all switches are sized optimally based on the optimization Since the total G- product of the switches is again con-
methods presented in this paper. All converters are designed and strained at one and each switch in the boost converter must
optimized for a given conversion ratio , and without loss of be rated for the output voltage of , the total conductance is
generality, an input voltage of 1 V is assumed. restricted to . From this constraint, the equivalent
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SEEMAN AND SANDERS: ANALYSIS AND OPTIMIZATION OF SWITCHED-CAPACITOR DC–DC CONVERTERS 849

loss impedance can be determined (note that to

achieve the correct conversion ratio):

(35)

Computing the ratio of the square of the output voltage to this

optimal output resistance yields the performance metric of the
boost circuit, . This metric is
plotted in Fig. 9.
Finally, the transformer-based direct converter in Fig. 8(b) is
considered. The transformer is assumed to be ideal and to have
an up-conversion ratio of . The output switches are all identical
and must be rated for the output voltage of V. The on-current
of these switches is equal to the output current . Likewise,
the input switches must be rated for 1 V and conduct a current Fig. 10. Simulated output impedance versus switching frequency.
of . To constrain the total G- product equal to one, the
output switches must have conductances of and the input
switches must have conductances of . The conduction loss TABLE I
SSL AND FSL VA-PRODUCTS AND IMPEDANCES
can then be calculated as FOR FIVE CONVERTERS (R AT 1 KHZ)

(36)

The resulting performance metric for this converter is then con-

stant at for any conversion ratio. This makes intuitive sense
as only the transformer turns ratio is changed to achieve dif-
ferent conversion ratios.
The conduction losses of the three converters, represented
by theperformance metric developed in switching frequency, both the SSL and FSL output impedances
Section IV, are compared in Fig. 9. The SC and boost con- can be determined and compared with those from the mathemat-
verters’ performance metrics decrease as the conversion ratio ical analysis. The converters simulated are the 1:4 (i.e., 1 V input
increases, but the SC converter approaches an asymptotic limit to 4 V output) ladder converter, 1:4 Cockcroft-Walton multi-
at (the same as the transformer-based converter), but the plier, 1:4 doubler, 1:5 Fibonacci converter, and a 1:4 series-par-
boost converter’s performance continues to decrease. allel converter, all shown in Fig. 5. The capacitors and switches
At large conversion ratios, the step-up ladder-type SC con- in all converters are optimized using the methods in this paper
verter is significantly superior to the boost converter as the using a switch GV product of 1 VA and a total capacitor energy
switches in the ladder topology block only the input voltage of 1 J. The output impedance was determined by measuring the
and most switches carry less than the input current. However, current transfer between the input and output voltage sources in
the boost converter’s switches carry the full input current and a transient simulation.
block the full output voltage. Even though the SC converter has The charge-multiplier-voltage products and output imped-
many more switches, the low working V-A product of these ances of the five converters found via the methods in Section II
switches yields a lower conduction loss than that of the boost are shown in Table I. These calculations and detailed converter
converter, with its much higher working V-A product switches. analysis are given in [8]. Fig. 10 shows the simulated impedance
In an application where switches are the limiting factor in per- of the converters between 100 Hz and 1 MHz. The symbols
formance or cost, switched-capacitor converters are evidently in the plots indicate the calculated FSL and SSL impedances,
advantageous over conventional magnetics-based dc–dc con- showing a match between the theoretical and simulated values.
verters at high or moderate conversion ratios. Five very different switched-capacitor converters were sim-
ulated for a range of frequencies encompassing both the SSL
VI. VERIFICATION BY SIMULATION asymptote and the FSL asymptote. The simulation results verify
As this analysis method is based on idealized devices, cir- that the analysis methods developed in Section II determine the
cuit-level simulation, through SPICE or spectre is appropriate correct output impedance in both asymptotes for all five con-
for verification of this analysis. Ideal capacitor and voltage-con- verters. This simulation verifies that the methods developed in
trolled resistances are used in the simulation. Parasitics, while this paper accurately predict the performance of any two-phase
an important consideration in real-world implementations, are SC converter.
not considered in this paper, and are not considered in the veri-
fication simulation. VII. EXPERIMENTAL VERIFICATION
Five step-up switched-capacitor converters have been sim- An ultra-low-power switched-capacitor power conversion in-
ulated over a range of switching frequencies. By varying the tegrated circuit (IC) has been fabricated and tested with design
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850 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 23, NO. 2, MARCH 2008

switching frequencies, parasitic losses hurt the converter’s per-

formance. The most influential parasitics, in this case the ca-
pacitor bottom-plate capacitance and drain-source capacitance,
need to be carefully considered in any realization of switched-
capacitor converters.

VIII. CONCLUSION
An analysis method has been presented to determine the
performance of any switched-capacitor power converter using
Fig. 11. 3:2 Series-parallel converter topology. easily-determined charge multiplier vectors. The capacitors
and semiconductor switches of the converter were optimized
to minimize output impedance for several conditions and con-
straints. Five separate converter topologies were considered for
their effectiveness in utilizing capacitors and switches. This
comparison allows the use of an optimal topology suited to
its application and implementation technology. Significantly,
the performance (based on conduction loss) of a ladder-type
converter was found to be superior to that of a conventional
boost converter for medium to high conversion ratios.

REFERENCES
[1] M. S. Makowski and D. Maksimovic, “Performance limits of switched-
capacitor dc–dc converters,” in IEEE Power Electron. Spec. Conf., Jun.
18–22, 1995, pp. 1215–1221.
[2] P. M. Lin and L. O. Chua, “Topological generation and analysis of
voltage multiplier circuits,” IEEE Trans. Circuits Syst., vol. 24, no. 10,
pp. 517–530, Oct. 1977.
[3] J. S. Brugler, “Theoretical performance of voltage multiplier circuits,”
IEEE J. Solid-State Circuits, vol. 6, no. 3, pp. 132–135, Jun. 1971.
[4] Z. Pan, F. Zhang, and F. Z. Peng, “Power losses and efficiency analysis
Fig. 12. Measured and calculated output voltage versus load and switching fre- of multilevel dc–dc converters,” in Proc. IEEE Appl. Power Electron.
quency. Conf., Mar. 2005, pp. 1393–1398.
[5] I. Oota, N. Hara, and F. Ueno, “A general method for deriving output
resistances of serial fixed type switched-capacitor power supplies,” in
Proc. IEEE ISCAS, May 2000, pp. 503–506.
guidance from the analysis method developed here. The design [6] G. Zhu and A. Ioinovici, “Switched-capacitor power supplies: DC
voltage ratio, efficiency, ripple, regulation,” in Proc. IEEE Int. Symp.
and experimental results of this IC are presented in [12]. The re- Circuits Syst., May 12–15, 1996, pp. 553–556.
sults from the 3:2 converter (1.2 V to 0.8 V) is presented here as [7] K. D. T. Ngo and R. Webster, “Steady-state analysis and design of a
an example circuit further verifying the calculations for a single switched-capacitor dc–dc converter,” in Proc. IEEE Power Electron.
Spec. Conf., 1992, vol. 1, pp. 378–385.
converter topology. [8] M. D. Seeman, “Analytical and Practical Analysis of Switched-Capac-
A schematic of this converter is shown in Fig. 11. It is similar itor DC–DC Converters,” Berkeley, CA, Tech. Rep. EECS-2006-11,
to the series-parallel circuit in that the capacitors are placed in 2006.
[9] L. Chua, C. Desoer, and E. Kuh, Linear and Nonlinear Circuits. New
series in one phase and parallel in the other phase. Capacitors York: McGraw Hill, 1987.
C and C both have a charge multiplier of 1/3 in this circuit and [10] J.-T. Wu and K.-L. Chang, “MOS charge pumps for low-voltage oper-
capacitor C is ignored as it is in parallel with the output. Each ation,” IEEE J. Solid-State Circuits, vol. 33, no. 4, pp. 592–597, Apr.
1998.
of the seven switches also has a charge multiplier of 1/3. In the [11] D. Maksimovic and S. Dhar, “Switched-capacitor dc–dc converters for
IC, each capacitor has a value of 1.15 nF and each switch has a low-power on-chip applications,” in Proc. IEEE Power Electron. Spec.
resistance of 4.75 . Thus, the predicted output impedances in Conf., 1999, vol. 1, pp. 54–59.
[12] M. D. Seeman, S. R. Sanders, and J. M. Rabaey, “An ultra-low-power
both limits, calculated using (9) and (14), are power management IC for wireless sensor nodes,” in Proc. IEEE
Custom Integr. Circuits Conf., Sep. 2007, pp. 567–570.

(37) Michael D. Seeman (S’03) received the B.S. degree

in electrical engineering and the B.S. degree in
physics from the Massachusetts Institute of Tech-
(38) nology, Cambridge, in 2004 and the M.S. degree
in electrical engineering from the University of
Fig. 12 shows the output of the 3–2 converter for various California, Berkeley, in 2006 where he is currently
pursuing the Ph.D. degree. His work centers on the
switching frequencies and resistive loads. The plotted curves implementation of advanced integrated switched-ca-
indicate the ideal output voltage calculated by considering a re- pacitor converters.
sistor divider between the load resistance and converter output His research interests also include low-power
analog integrated circuits and energy conversion
impedance. The data indicate that the model accurately pre- circuits for scavenged-energy wireless sensor nodes.
dicts the converter performance for low frequencies. At high Mr. Seeman is a member of Eta Kappa Nu and Phi Beta Kappa.
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SEEMAN AND SANDERS: ANALYSIS AND OPTIMIZATION OF SWITCHED-CAPACITOR DC–DC CONVERTERS 851

Seth R. Sanders (M’88) received the S.B. degrees

in electrical engineering and physics and the S.M.
and Ph.D. degrees in electrical engineering from the
Massachusetts Institute of Technology, Cambridge,
in 1981, 1985, and 1989, respectively.
He was a Design Engineer with Honeywell Test
Instruments Division, Denver, CO. Since 1989,
he has been on the faculty of the Department of
Electrical Engineering and Computer Sciences, Uni-
versity of California, Berkeley, where he is presently
a Professor. During the 1992 to 1993 academic
year, he was on industrial leave with National Semiconductor, Santa Clara,
CA. His research interests are in high frequency power conversion circuits
and components, in design and control of electric machine systems, and in
nonlinear circuit and system theory as related to the power electronics field.
He is presently actively supervising research projects in the areas of renewable
energy, novel electric machine design, and digital pulse-width modulation
strategies and associated IC designs for power conversion applications.
Dr. Sanders received the NSF Young Investigator Award in 1993 and multiple
Best Paper Awards from the IEEE Power Electronics and IEEE Industry Appli-
cations Societies. He has served as Chair of the IEEE Technical Committee on
Computers in Power Electronics, and as a Member-At-Large of the IEEE PELS
Adcom.

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