Chapter 2 Assembly Language Programming

Instruction Formats (Opcodes, Mnemonics and Operands)

An instruction is a binary pattern designed inside a microprocessor to perform a specific
function. Each instruction has two parts: one is task to be performed, called the operation code
(opcode) and second is the data to be operated on, called the operand. The operand or data can be
specified in various ways. It may include 8-bit or 16-bit data, an internal register, a memory
location, or 8-bit or 16-bit address. In some instructions, the operand is implicit.

Every instruction in 8085 is represented by an 8-bit binary value. A microprocessor executes

instruction given by the user. Instruction should be in a language known to the microprocessor.
But Microprocessor understands the language of 0’s and 1’s. This language is called Machine
Language. We write 8085 program in assembly language which microprocessor cannot
understand so, a program known as Assembler is used to convert an assembly language.
Instruction formats are divided into three types:

 One-byte instructions: A 1-byte instruction includes the opcode and the operand in the
same byte. For example MOV C, A and ADD B.

 Two-byte instructions: In a 2-byte instruction, the first byte specifies the operation code
an second byte specifies the operand. For example MVI A,08H.

 Three-byte instructions: In a 3-byte instruction, the first byte specifies the opcode and the
following the two bytes specify the 16-bit address. Note that the second byte is the low-
order address and the third byte is the higher-order address. For example JMP 2000H,
LDA D000H.

8085 Instruction Sets

The complete set of instructions which a particular computer can interpret and execute is known
as Instruction Set. The program is written using the instructions from this instruction set and the
computer fetches and executes these instructions.
These instructions can be classified into the following five functional categories:

  Data transfer (copy) Instructions

  Arithmetic Instructions
  Logical Instructions
  Branching Instructions
 Machine-control Instructions

Data Transfer Instructions: This instruction copy the contents of the source register into the
destination register. For example:

I. MOV Rd, Rs  e.g., MOV C, A where C is the destination register and A is source
Register. In the below example, Rs and Rd are all general purpose registers such as A, B,
C, D, E, H, L. The contents of the source register do not change.
Before Execution After Execution

A=08 Flag Register A=08 Flag Register

B C=00 B C=08
D E D E
H L H L
SP SP
PC PC

II. MVI R, data  e.g., MVI A, 05H where 05 is the immediate data and A is the destination
register. Here, the immediate data 05H is copied to A register.

A=00 Flag Register A=05 Flag Register

B C B C
D E D E
H L H L
SP SP
PC PC
III. MOV M, Rs  e.g., MOV M, C where C is the source register and M is the memory
pointer which is HL pair. The HL pair contains the memory address whose data is 00H
(assume). C register content is copied to HL pair content.
Before Execution After Execution

A Flag Register A Flag Register

B C=08 B C=08
D E D E
H(C0) L(00) H(C0) L(00)
SP SP
PC PC

FFFFH FFFFH

C000H 00 C000H 08

0000H 0000H

IV. MOV Rd, M  MOV C, M where C is the destination register and M is the memory
pointer which is HL pair. This case is quite reverse of the last case.
Before Execution After Execution

A Flag Register A Flag Register

B C=00 B C=08
D E D E
H=C0 L=00 H=C0 L=00
SP SP
PC PC

[C000H]
V. MVI M,data  MVI M, 10H where M is the memory pointer which is HL pair. This
instruction moves immediate data to memory. Now, by taking the address from the HL
pair, the immediate data written to this memory location.

Before execution After execution

A Flag Register A Flag Register

B C B C
D E D E
H(C0) L(00) H(C0) L(00)
SP SP
PC PC

FFFF FFFF

C000 00 C000 10

0000 0000

Here the memory contents are changed.

VI. LXI Rp, data  LXI H 3000H where 3000H is the 16-bit data and H stands for HL pair.
This instruction loads register pair with the 16-bit data. Finally we can see that H contains
30H and L contains 00H.

Before execution After execution

A Flag Register A Flag Register

B C B C
D E D E
H(05) L(00) H(30) L(00)
SP SP
PC PC
VII. LDA address  LDA D000H where D000H is the address. This instruction loads the
accumulator direct from memory location D000H.
Before execution After execution

A(50) Flag Register A(20) Flag Register

B C B C
D E D E
H L H L
SP SP
PC PC

FFFF FFFF

D000 20 D000 20

0000 0000

VIII. STA address  STA D001H where D001H is the address. This instruction stores the
accumulator direct to memory location D001H.
Before execution After execution

A(50) Flag Register A(50) Flag Register

B C B C
D E D E
H L H L
SP SP
PC PC

FFFF FFFF

D001 20 D001 50

0000 0000
IX. LHLD address  LHLD D001H where D001H is the address. This instruction loads the
HL pair direct from memory.
Before execution After execution

A(50) Flag Register A(50) Flag Register

B C B C
D E D E
H(D0) L(01) H(30) L(20)
SP SP
PC PC

FFFF FFFF

D001 20 D001 20
D002 30 D002 30

0000 0000

X. SHLD address  SHLD D001H where D001H is the address. This instruction stores the
HL pair content direct to memory location D001H& D002H.
Before execution After execution

A(50) Flag Register A(50) Flag Register

B C B C
D E D E
H(05) L(04) H(05) L(04)
SP SP
PC PC

FFFF FFFF

D001 20 D001 04
D002 30 D002 05

0000 0000
XI. LDAX Rp  LDAX B where B is the Register pair BC. This instruction load
accumulator indirect by using a memory pointer.

Before execution After execution

A(00) Flag Register A(50) Flag Register

B(D0) C(02) B(D0) C(02)
D E D E
H L H L
SP SP
PC PC

FFFF FFFF

D002 50s D002 50

00 0000

XII. STAX Rp  STAX D where D is the DE registers pair. This instruction stores the
accumulator indirect to memory pointer.
Before execution After execution

A(20) Flag Register A(20) Flag Register

B C B C
D(D0) E(01) D(D0) E(01)
H L H L
SP SP
PC PC

FFFF FFFF

D001 10 D001 20
XIII. XCHG: This instruction is used to exchange the contents of HL with DE pair. This is one
byte instruction.

Before execution After execution

A A
B C B C
D(40) E(50) D(20) E(30)
H(20) L(30) H(40) L(50)
SP SP
PC PC

Addressing Modes of 8085

The method by which the address of source of data or the address of destination of result is given
in the instruction is called Addressing Modes. The term addressing mode refers to the way in
which the operand of the instruction is specified. Intel 8085 uses the following addressing
modes:

  Direct Addressing Mode

  Register Addressing Mode
  Register Indirect Addressing Mode
  Immediate Addressing Mode
 Implicit Addressing Mode

Direct Addressing Mode: In this mode, the address of the operand is given in the instruction
itself. For example:

LDA 2500H; H Load the contents of memory location 2500 H in accumulator.

  LDA is the operation.

  2500 H is the address of source.
 Accumulator is the destination.

Register Addressing Mode: In this mode, the operand is in general purpose register. For
example:

MOV A, B; Move the contents of register B to A.

  MOV is the operation.

  B is the source of data.
 A is the destination.
Register Indirect Addressing Mode: In this mode, the address of operand is specified by a
register pair. For example:

MOV A, M; Move data from memory location specified by H-L pair to accumulator.

  MOV is the operation.

  M is the memory location specified by H-L register pair.
 A is the destination.

Immediate Addressing Mode: In this mode, the operand is specified within the instruction
itself. For example:

MVI A, 05H; Move 05 H in accumulator.

  MVI is the operation.

  05 H is the immediate data (source).
 A is the destination.

Implicit Addressing Mode: If address of source of data as well as address of destination

of result is fixed, then there is no need to give any operand along with the instruction. For
example:

CMA; Complement accumulator.

CMA is the operation.

A is the source.
A is the destination.
Arithmetic Instructions: This group of instructions performs arithmetic
operations such as addition, subtraction, increment and decrement.

I. ADD Rs  e.g., ADD B where A is the destination register and B is source Register. In
the above example, Rs is all general purpose registers such as A, B, C, D, E, H, L. The
contents of the source register do not change. A (98)  A (47) +B (51), The register A
value is added with register B value and the result goes to A register.

Before Execution After Execution

A=47 S Z AC P CY A=98 1 0 0 0 0
B=51 C B=51 C
D E D E
H L H L
SP SP
PC PC

II. ADD M  e.g., ADD M where M is the memory pointer which is HL pair. The HL pair
contains the memory address whose data is 20H (assume). A register value 10 is added
with [HL] and the results can be seen in the accumulator.

Before Execution After Execution

A=10 S Z AC P CY A=30 0 0 00 01 0 0
B C B C
D E D E
H(C0) L(00) H(C0) L(00)
SP SP
PC PC

FFFFH FFFFH

C000H 20 C000H 20

0000H 0000H
III. ADC R  ADC B where B is the source register. Here the register B value is added with
Accumulator and carry flag CY.

Before Execution After Execution

A=3F S Z AC P CY A=60 0 0 01 0 1 0 0
B=20 C B=20 C
D E D E
H L H L
SP SP
PC PC

IV. ADC M  ADC M where M is the memory pointer which is HL pair. This instruction
adds memory content with Accumulator and Carry flag CY. The final result goes to the
accumulator.
Before execution After execution

A=10 S Z AC P CY A=31 0 0 0 0 0 00 0
B C B C
D E D E
H(C0) L(02) H(C0) L(02)
SP SP
PC PC

FFFF FFFF

C002 20 C002 20

0000 0000
 V. ADI data  ADI B7H where B7H is the 8-bit data. This data is added with Accumulator
and the result goes to A register. This comes under immediate addressing mode.

Before execution After execution

A=59 S Z AC P CY A=10 0 0 010 0 0 1

B C B C
D E D E
H L H L
SP SP
PC PC

VI. ACI Data  ACI 20H where 20H is the immediate data. This is added with accumulator
and carry flag CY. The final result goes to accumulator.
Before execution After execution

A=C0 S Z AC P CY A=E0 1 0 0 0 0 0 0 0
B C B C
D E D E
H L H L
SP SP
PC PC

VII. DAD Rp  DAD B where B is Register pair BC. This BC pair is added with HL pair
value and final results goes to HL register.
Before execution After execution

A S Z AC P CY A 0 0 00 0 00 0
B=20 C=35 B=20 C=35
D E D E
H=80 L=45 H=A0 L=7A
SP SP
PC PC
VIII. SUB R  SUB B where B is the source register. This instruction subtracts the contents of
register B from the contents of accumulator and the result is placed in accumulator. The
contents of B are not altered. All fags are modified to reflect the result. The subtraction is
performed by using 2’s complement method. If carry flag CY is set the result is negative
and is in 2’s complement form. If CY is reset, the result is positive and is in normal form.
Before execution After execution

A=37H S Z AC P CY A=F7H 1 0 0 0 0 00 1
B=40H C B=40H C
D E D E
H L H L
SP SP
PC PC
In the example above, no carry is generated so CY=0. The microprocessor complements
the carry which means CY=1 which represents that the result is negative and is in 2’s
complement form.

IX. SUB M  SUB M where M is the memory pointer. This instruction subtracts the
memory location contents from accumulator.

Before execution After execution

A=50 S Z AC P CY A=30 0 00 0 0 10 0
B C B C
D E D E
H(C2) L(00) H(C2) L(00)
SP SP
PC PC

FFFF FFFF

C200 20 C200 20
C001 C201

0000 0000
X. SBB R  SBB B where B is the Source Register. This instruction subtracts register B
and borrow flag from accumulator.

Before execution After execution

A=37 S Z AC P CY A=F7 1 0 00 0 0 0 1
B=3F C B=3F C
D E D E
H L H L
SP SP
PC PC

XI. SBB M  SBB M where M is the memory pointer. This instruction subtracts memory
contents and borrow flag from accumulator.
Before execution After execution

A=20H S Z AC P CY A=D0 1 0 00 0 00 1
B C B C
D E D E
H=C2 L=00 H=C2 L=00
SP SP
PC PC

FFFF FFFF

C200 4F C200 4F

0000 0000
XII. SUI Data  SUI 50 where 50H is the immediate data. This instruction subtracts
immediate data from accumulator.

Before execution After execution

A=20H S Z AC P CY A=D0 1 0 0 0 000 1

B C B C
D E D E
H L H L
SP SP
PC PC

XIII. SBI Data  SBI 4F where 4F is immediate data. This instruction subtracts immediate
data and borrow flag from accumulator.

Before execution After execution

A=20H S Z AC P CY A=D0 1 0 00 00 0 1
B C B C
D E D E
H L H L
SP SP
PC PC

XIV. Decimal Adjust Accumulator (DAA):

i. If the value of the low order 4-bits D3-0 in the accumulator is greater than 9 or if AC
flag is set, the instruction adds 6 to the low order 4-bits of accumulator.
ii. If the value of the higher order 4-bits D7-4 in the accumulator is greater than 9 or if
carry flag is set, the instruction adds 6 to the higher order 4-bits of accumulator.

If we want to add two BCD numbers 12 and 39 and want result in BCD form.

MVI A, 12
ADI 39
DAA
When DAA is executed, it checks lower D0-D3 is greater than 9 or AC flag is set. Here the result
addition is 4B in hexadecimal where B is greater than 9 so 6 is added to the lower order 4-bits.
However, nothing is added to the higher D4-7 bits. So, the final result 51.

XV. INR R/DCR R  INR B/DCR B where B is source register. This instruction
increments/decrements the register value by 1. The below example is for increment.

Before execution After execution

A S Z AC P CY A 0 0 01 0 1 0 0
B=2F C B=30 C
D E D E
H L H L
SP SP
PC PC

XVI. INR M/DCR M where M is the memory pointer. This instruction increment/decrement
memory contents by one. The below example is for increment.

Before execution After execution

A S Z AC P CY A 0 0 0 0 01 0 0
B C B C
D E D E
H=C2 L=00 H=C2 L=00
SP SP
PC PC

C200 05 C200 06
XVII. INX Rp/DCX Rp  INX B/DCX B where BC is the register pair Rp. This instruction
increments/decrements the register pair value by 1. The below example is for increment.

Before execution After execution

A S Z AC P CY A 0 0 0 101 0 0
B=02 C=FF B=03 C=00
D E D E
H L H L
SP SP
PC PC
Logical Instructions: This group of instructions performs logical operations such
as and, or, xor etc. with the contents of accumulator.

I. ANA R  e.g., ANA B where A is the destination register and B is source Register. In
the below example, Rs is all general purpose registers such as A, B, C, D, E, H, L. The
contents of the source register do not change. A (02)  A (56) and B (82), The register A
value is anded with register B value and the result goes to A register.

Before Execution After Execution

A=56 S Z AC P CY A=02 0 0 01 0 0 0 0
B=82 C B=82 C
D E D E
H L H L
SP SP
PC PC

II. ANA M  e.g., ANA M where M is the memory pointer which is HL pair. The HL pair
contains the memory address whose data is F2H (assume). A register value 10 is added
with [HL] and the results can be seen in the accumulator.

Before Execution After Execution

A=4A S Z AC P CY A=42 0 0 0 1 0 10 0
B C B C
D E D E
H(C0) L(00) H(C0) L(00)
SP SP
PC PC

FFFFH FFFFH

C000H F2 C000H F2

0000H 0000H
III. ANI Data  ANI 0FH where A is the destination register. This instruction logically
AND the immediate data with accumulator.

Before Execution After Execution

A=F7 S Z AC P CY A=07 0 0 01 0 0 0 0
B C B C
D E D E
H L H L
SP SP
PC PC

IV. ORA R  e.g., ORA B where A is the destination register and B is source Register. In
the below example, Rs is all general purpose registers such as A, B, C, D, E, H, L. The
contents of the source register do not change. A (B7)  A (A2) or B (B5), The register A
value is anded with register B value and the result goes to A register.

Before Execution After Execution

A=A2 S Z AC P CY A=B7 1 0 0 1 0 1 0 0
B=B5 C B=B5 C
D E D E
H L H L
SP SP
PC PC

V. ORA M ORA M where M is the memory pointer which is HL pair. This instruction
does logical OR with memory content.

Before execution After execution

A=AA S Z AC P CY A=FF 1 0 0 0 0 10 0
B C B C
D E D E
H(C0) L(02) H(C0) L(02)
SP SP
PC PC
 FFFF FFFF

C002 55 C002 55

0000 0000

VI. ORI data  ORI 20H where 20H is the 8-bit data. This instruction does logically OR to
the immediate data with accumulator.

Before execution After execution

A=55 S Z AC P CY A=75 0 0 00 0 00 0
B C B C
D E D E
H L H L
SP SP
PC PC

VII. XRA R  XRA B where A is the destination register and B is the source register. This
instruction does Exclusive-OR operation with accumulator.

Before execution After execution

A=77 S Z AC P CY A=71 0 0 0 0 0 10 0
B=06 C B=06 C
D E D E
H L H L
SP SP
PC PC
VIII. XRA M  XRA M where M is the memory pointer which is HL pair. This instruction
does Exclusive-OR with memory content.

Before execution After execution

A=A5 S Z AC P CY A=F5 1 0 00 0 1 0 0
B C B C
D E D E
H(C2) L(00) H(C2) L(00)
SP SP
PC PC

FFFF FFFF

C200 50 C200 50
C001 C201

0000 0000

IX. XRI data  XRI 2FH where 2FH is the 8-bit data. This instruction does Exclusive-OR of
immediate data with accumulator.

Before execution After execution

A=75 S Z AC P CY A=5A 0 0 00 0 1 0 0
B C B C
D E D E
H L H L
SP SP
PC PC
 X. CMA  CMA where A is the Source Register. This instruction complements the
accumulator value and the result is placed in the accumulator.

Before execution After execution

A=AA S Z AC P CY A=55 0 0 00 0 0 0 0
B C B C
D E D E
H L H L
SP SP
PC PC

XI. CMC: This instruction complements the carry flag. If carry flag is set, the instruction will
reset it and carry flag is reset, the instruction will set it. Only the carry flag is
complemented. No other flags are modified.

XII. STC: This instruction sets the carry flag. It does not consider previous carry flag status.
Only sets the carry flag. Only the carry flag is set and no other flags are changed.

XIII. CMP R  CMP B where Accumulator value A is compared with B register value. The
operation of comparing is performed by subtracting register from accumulator. The
contents of register or accumulator are not changed.
The result of comparison by setting flags as follows:
If accumulator > register B: CY is set and Zero Flag is Reset.
If accumulator < register B: Zero Flag is set
If accumulator = register B: CY is set.

Before execution After execution

A=20H S Z AC P CY A=20H 0 0 0 0 0 0 0 0
B=10H C B=10H C
D E D E
H L H L
SP SP
PC PC
XIV. CMP M: This instruction compares the memory content with the accumulator. The
address of the memory location is given by HL register pair. The operation is performed
in same way as CMP R instruction. Contents of accumulator and contents of memory
location are not changed.

XV. CPI Data: This instruction compares the immediate data with the accumulator similar to
that of CMP R and the result is indicated by Z and CY flags. The accumulator contents
are not altered.

XVI. RLC: RLC refers to Rotate Accumulator Left. This instruction rotates the content of
accumulator left by 1-bit which implies it shifts the bits left by single position. D0 will be
transferred to D1 and D2 to D3 and so on. The D7 result is transferred to CY flag and Do.
This can be seen in the figure below.

CY

D7 D6 D5 D4 D3 D2 D1 D0

For Example: MVI A, 1F

RLC

Before Execution

CY

0 0 0 1 1 1 1 1
 After Execution

0 0 1 1 1 1 1 0

XVII. RRC: RRC refers to Rotate Accumulator Right. This instruction rotates the content of
accumulator right by 1-bit which implies it shifts the bits right by single position. D7 will
be transferred to D6 and D6 to D5 and so on. The D0 result is transferred to CY flag and
D7. This can be seen in the figure below.

CY

D7 D6 D5 D4 D3 D2 D1 D0

For Example:

MVI A, 1C
RRC

Before Execution

CY

0 0 0 1 1 1 0 0
 After Execution

0 0 0 0 1 1 1 0

XVIII. RAL: RAL refers to Rotate Accumulator Left through Carry. This instruction rotates the
content of accumulator left by 1-bit. D0 will be transferred to D1 and D1 to D2 and so on.
The D7 result is transferred to CY flag and CY flag result is transferred to D0. This can
be seen in the figure below.

CY

D7 D6 D5 D4 D3 D2 D1 D0

For Example:

MVI A, 1E
RAL

Before Execution

CY=1

0 0 0 1 1 1 1 0

After Execution

0 0 1 1 1 1 0 1
XIX. RAR: RAR refers to Rotate Accumulator Right through Carry. This instruction rotates the
content of accumulator right by 1-bit. D7 will be transferred to D6 and D6 to D5 and so
on. The D0 result is transferred to CY flag and CY flag result is transferred to D7. This
can be seen in the figure below.

CY

D7 D6 D5 D4 D3 D2 D1 D0

For Example:

MVI A, 0E
RAR

Before Execution

CY=1

0 0 0 0 1 1 1 0

After Execution

1 0 0 0 0 1 1 1
 Program Control Instructions: This group of instructions includes instruction
related to Stack Control and Branch Group.

Stack: It is group of memory locations in RAM defined by user. It stores data temporarily in
case there is shortage of available general purpose registers. To store the data in this stack we
push the contents of register on to stack and these register would be free to be used. After that
function is completed, the previous contents are popped from stack and stored in the register.
Similar to Program Counter, Stack Pointer (SP) is the memory pointer in the stack. It uses the
concept of LIFO. While Pushing the data in the stack area, the SP decrements after each write.
Similarly, while Poping increments the address first then pops the data.

I. PUSH Rp  e.g., PUSH B where B is the register pair BC. This instruction pushes the
contents of register pair on to the stack. The SP pushes the content of B register to the
address pointed by Stack Pointer.
Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B=20 C=30 B=20 C=30
D E D E
H L H L
SP(FFFF) SP(FFFD)
PC PC

0000H 0000H

FFFDH 88 FFFDH 88
FFFEH 9A FFFEH 30 2nd push
36 20
FFFFH FFFFH
1st push
and dec counter
After execution stack pointer
to the top location of the
content
Initially points to the bottom of the stack

**Note: Stack pointer always points to the data that is at the top of the stack after push operation.
II. POP Rp  e.g., POP D where D is the register pair DE. This instruction pop off the stack
contents to register pair. When this instruction is executed, the contents of the memory
location pointed by the stack pointer (SP) register are copied to the low order register
pair. The SP is incremented by one and the contents of that memory location are copied
to the higher order register of register pair. The SP is incremented by 1. The process of
POP is exactly opposite to that of PUSH. So, the contents stored by PUSH are taken back
using POP instructions.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D=01 E=02 D=30 E=20
H L H L
SP(FFFD)
E SP(FFFF)
PC PC

0000H 0000H

FFFDH 20 FFFDH 20
30 FFFEH 30
FFFEH
90
20 90
FFFFH FFFFH 20
III. SPHL: This instruction loads the stack pointer with HL register pair contents. When this
instruction is executed, the contents of HL pair are transferred to stack pointer register. H
register contents to high order 8-bits and L register contents to low order 8-bits. The
contents of H and L are not altered.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D E D E
H=01 L=09 H=01 L=09
SP(FFFD) SP(0109)
PC PC

IV. XTHL: This instruction exchanges the HL with top of stack. When this instruction is
executed, the contents of L register are exchanged with the stack location pointed by the
stack pointer. The contents of H register are exchanged with the next stack location
(SP+1). The contents of the stack pointer register are not altered. No flags are modified.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D E D E
H=01 L=20 H=06 L=05
SP(FFFD) SP(FFFD)
PC PC

0000H 0000H

FFFDH 05 FFFDH 20
FFFEH 06 FFFEH 01
90 90
FFFFH FFFFH
V. NOP: This instruction does no operation

When this instruction is executed no operation is performed. The instruction is fetched

and decoded, no operation is executed and microprocessor will go for the next instruction
after that. This instruction can be used as a small delay of 4T states or if you have to
delete any instruction from your program you can use NOP instead of that instruction.

VI. HLT: This instruction halts and enters wait state.

When this instruction is executed, the microprocessor completes the execution and halts
any further execution. The microprocessor enters the halt acknowledge machine cycle
and wait states are inserted in every clock period. The address and data bus are placed in
high impedance state. The contents of the registers are not modified in this state.

To come out of this state the microprocessor must be interrupted or resetted. If

interrupted, the microprocessor executes a call location. Because of call, PC contents are
stored on to stack i.e. the address of next instruction. Microprocessor completes
ISR(Interrupt Service Routine) and with return instruction it returns back to next
instruction after halt.

When the reset signal is applied, PC is loaded with 0000 and execution starts from 0000
address onwards. This instruction is generally used to terminate the program execution.
In multiple ending programs at each end this instruction can be used in order to avoid
unnecessary jumps to terminate the program.
 Branch Group:

The microprocessor executes machine codes in a sequential manner. It goes on executing

from one memory location to the next. Branch group of instruction instructs the
microprocessor to go to different memory location. It continues executing machine codes
from that new location. The address of the new memory location is either specified in the
instruction or supplied by the microprocessor or given by extra hardware. The branch
group can be divided as:

Jump Instruction:
I. JMP address
II. Conditional Jump Instructions
III. PCHL

Call and Return Instruction

I. CALL address
II. Conditional CALL instructions
III. RET
IV. Conditional RET instructions

Restart Instructions
I. RST N

I. JMP Address: This is an unconditional jump instruction where the address is specified in
the instruction. When this instruction is executed, it directs the microprocessor about the
jump and its address where the microprocessor has to transfer its control. The storing
format is Opcode, Low order address and Higher order address.

E.g: JMP C200H where JMP is the opcode, C200H is the 16-bit address.

II. Conditional JMP Instructions: In conditional jump instructions, when the condition is true
or satisfied then only the jump is made at the specified address. If the condition is false or
not satisfied it will just check and proceed further to execute the next instruction after it.
 Different available conditional jumps are as follows:

JC – Jump if carry flag is set.

JNC – Jump if carry flag is reset.
JZ – Jump if zero flag is set.
JNZ - Jump if zero flag is reset.
JP – Jump if positive i.e. sign flag is set.
JM – Jump if negative i.e. sign flag is reset.
JPE – Jump if parity even i.e. parity flag is set.
JPO – Jump if parity odd i.e. parity flag is reset.

Note: No Jump on auxiliary carry flag.

Example JZ C200 : This instruction checks the zero flag. If the zero flag is set, condition
is true and the program control is transferred to the address C200H. If zero flag is reset,
condition is false and the program control is not transferred instead it will execute the
next instruction after JZ C200.

III. PCHL: This instruction loads program counter with HL contents. The contents of H and
L registers are transferred to Program Counter. The H contents to high order 8-bits and L
contents to low order 8-bits of program counter. This instruction is equivalent to a 1byte
unconditional jump instruction. A program sequence can be changed to any location by
simply loading the H and L registers with address and by using this instruction.
Example: LXI H C200H
PCHL
The LXI H instruction initializes HL pair with C200 contents H=C2 and L=00. When
PCHL is executed HL contents are transferred to PC and PC=C200, so the next
instruction executed will be from C200 address.
IV. CALL Address: This instruction is an unconditional call subroutine. When this
instruction is executed the program sequence is transferred to the address specified in the
instruction. Before transferring the sequence the PC contents are stored on to stack i.e.
higher order byte and then lower order byte. The call instruction is used to call a
subroutine. To return back from the subroutine, the PC contents are stored on to the stack.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D E D=30 E=20
H L H L
SP(C7FF) SP(C7FD)
PC(C006) PC(C200)

0000H 0000H

C006H CD C006H CD
C007H 00 C007H 00

C200H C200H
C201H

X C7FDH
C7FFH C7FEH 06
C7FFH C0
Undefined
Example: CALL C200H or Don’t Care

C006H Opcode of Call

C007H 00H

C008H C2H

C009H Next Instruction

When this instruction is executed, program counter contents C009 will be stored on to the
stack and microprocessor starts executing instructions from C200H onwards.
 V. Condition Call Instructions: In conditional CALL instruction, when the condition is true,
then a CALL at new address is made. If the condition is false then it will not have a
CALL and will proceed for next instruction after it. Different conditional CALL
instructions available are:

CC – Call, if carry flag is set.

CNC – Call, if carry flag is reset.
CP – Call, if positive i.e. sign flag is reset.
CM - Call, if minus i.e. sign flag is set.
CPE – Call, if parity even i.e. parity flag is set.
CPO – Call, if parity odd i.e. parity flag is
reset. CZ – Call, if zero flag is set.
CNZ – Call, if zero flag is reset.

Example: CC C200H

Call if carry flag is set, the program written from address C200H onwards will be executed.
If carry flag is reset microprocessor will execute next instruction after CC C200H.
VI. RET: This instruction will return from the subroutine. When this instruction is executed
program sequence is transferred from subroutine to the calling program. The return
address is taken from stack (where the call instruction has stored its PC contents i.e.
return address) this address is loaded in PC and the program execution begins at address
taken from stack.

Before Execution After Execution

A S Z AC P CY A x x x x xx xx
B C B C
D E D=30 E=20
H L H L
SP(C7FD) SP(C7FF)
PC(C209) PC(C009)

0000H 0000H

C006H C008H
C009H
C200H
C208H
C209H
C209H RET Opcode RET Opcode
C7FDH 09
C7FEH C0
C7FDH 09 C7FFH X
C7FEH C0
VII. Conditional RET Instructions: In this type of instructions, when the condition is true, then
only the RET is made at the address given by the stack. If condition is false, it will
proceed further to execute the next instruction after it.

Different conditional RET’s available are:

RC – Return from subroutine, if carry flag is set.

RNC – Return from subroutine, if carry flag is reset.
RZ – Return from subroutine, if zero flag is set.
RNZ - Return from subroutine, if zero flag is reset.
RP - Return from subroutine, if positive i.e. if sign flag is reset.
RM - Return from subroutine, if minus i.e. if sign flag is set.
RPO- Return from subroutine, if odd parity i.e. if parity flag is reset.
RPE - Return from subroutine, if even parity i.e. if parity flag is set.

VIII. RST N: These instructions are equivalent to 1 byte CALL instruction at restart location.
The contents of the PC are saved on to stack and program jumps to the address. These
instructions can be used as software interrupts in a program to transfer program execution
to one of the 8 locations depending on which RST instruction is executed.

Restart instructions and its locations are as follows:

Instructions Restart Locations

RST 0 0000

RST 1 0008

RST 2 0010

RST 3 0018

RST 4 0020

RST 5 0028

RST 6 0030

RST 7 0038