IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION, VOL. 6, NO.

4, DECEMBER 2020 1755

A Low-THD Two-Switch PFC DCM Boost

Rectifier for Aviation Applications
Tomas Sadilek , Member, IEEE, Misha Kumar , Member, IEEE, Yungtaek Jang , Fellow, IEEE,
Peter Barbosa, Senior Member, IEEE, and Iqbal Husain , Fellow, IEEE

Abstract— In this article, a new two-switch, single-phase, Conventional continuous-conduction-mode (CCM) power-
power-factor-correction, discontinuous-conduction-mode boost factor-correction (PFC) boost rectifiers are well optimized to
rectifier that features zero-voltage switching turn on and can the line frequency of 50 or 60 Hz by employing an active
achieve less than 5% input-current total harmonic distor-
tion (THD) by injecting a simple feedforward signal obtained input current shaping control with bandwidth around 3–5 kHz
from input and output voltages to the output voltage feedback to obtain low total harmonic distortion (THD). To achieve
control is introduced. Since low THD is achieved without high- similar current shaping performance at the line frequency
bandwidth active current shaping control, the proposed topology of 800 Hz, the current control bandwidth should be designed
is suitable for modern aviation applications that require line to be around 50 kHz. However, it is not possible to achieve
frequency up to 800 Hz. The evaluation was performed on
a 320-W prototype designed to operate from 94–134-V line the high bandwidth current control with hard-switching CCM
input and deliver 220-V dc output. The prototype achieves 3.3% PFC boost rectifiers that are mostly designed to operate below
THD at full load over the line frequency range from 360 to 100-kHz switching frequency to meet the required efficiency
800 Hz and meets the required harmonic limits specified by the and thermal performance [19]–[22].
DO-160 standard that describes the environmental conditions and Recently, totem-pole bridgeless PFC rectifiers with wide
test procedures for airborne equipment.
bandgap devices operating in the critical conduction mode
Index Terms— Aviation, boost rectifier, discontinuous- were introduced [23]–[28]. To achieve low THD, zero cross-
conduction mode (DCM), power-factor correction (PFC), single ings of boost inductor current and line input voltage should be
phase, zero-voltage switching (ZVS).
properly detected without significant delay. However, by using
the existing current sensing techniques, commercially available
I. I NTRODUCTION
gate drivers with propagation delay, blanking of gate signals

I N THE aviation industry, electric power loads and source

properties are regulated by the DO-160 standard [1] that
specifies stringent harmonic limits of airborne power equip-
around zero crossings of the line voltage, and a digital
controller that has limited processing speed [29], [30], it is
virtually impossible to achieve less than 5% THD at 800-Hz
ment. Moreover, modern airborne power distribution systems line frequency.
employ line frequency up to 800 Hz to increase the perfor- In this article, a new, two-switch, single-phase, PFC,
mance of onboard generators and to reduce the size of onboard discontinuous-conduction-mode (DCM) boost rectifier that
passive elements, such as transformers and filters [2]–[7]. features ZVS turns on and can achieve less than 5%
In traditional commercial aircraft, ac–dc rectification is input-current THD by injecting a simple feedforward sig-
achieved with a multipulse autotransformer-diode-rectifier nal obtained from input and output voltages to the output
unit [8]. While this power conversion approach is reli- voltage feedback control is introduced. The converter topol-
able, it produces significant current harmonics (notably 11th, ogy is based on the three-phase Taipei rectifier introduced
13th, 23rd, and 25th orders), and its power factor is a in [31] and its variations with three-level [32] and single-
function of load [9]. Active power filtering techniques stage [33] structures. Since low THD is achieved without
explored in [10]–[13] address these power quality issues. additional high bandwidth active current shaping control,
Recently, three-phase active rectifiers have been proposed the proposed topology is suitable for modern aviation appli-
for the aviation industry to further reduce the need for a cations that require line frequency up to 800 Hz. The eval-
line-frequency transformer [14]–[18]. However, single-phase uation was performed on a 320-W prototype designed to
aviation line-frequency rectification has not yet been explicitly operate from 94–134 VRMS line input and deliver 220-V dc
explored. output. The prototype achieves at most 3.3% THD at full
Manuscript received January 21, 2020; revised March 29, 2020; accepted load over the line frequency range from 360 to 800 Hz
May 1, 2020. Date of publication May 11, 2020; date of current version and meets the required harmonic limits specified by the
October 30, 2020. (Corresponding author: Tomas Sadilek.) DO-160 standard.
Tomas Sadilek, Misha Kumar, Yungtaek Jang, and Peter Barbosa
are with the Milan M. Jovanović Power Electronics Laboratory,
Delta Electronics (Americas) Ltd., Durham, NC 27709 USA (e-mail:
[email protected]). II. T WO -S WITCH ZVS PFC DCM B OOST R ECTIFIER
Iqbal Husain is with the Department of Electrical and Computer Engineer-
ing, North Carolina State University, Raleigh, NC 27695 USA. Fig. 1 shows the proposed two-switch ZVS PFC DCM
Digital Object Identifier 10.1109/TTE.2020.2993925 boost rectifier [34]. The input of the rectifier consists of two
2332-7782 © 2020 IEEE. Personal use is permitted, but republication/redistribution requires IEEE permission.
See https://www.ieee.org/publications/rights/index.html for more information.

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 1756 IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION, VOL. 6, NO. 4, DECEMBER 2020

Fig. 1. Proposed two-switch ZVS PFC DCM boost rectifier.

Fig. 2. Simplified circuit diagram when VAN > 0 and VBN < 0.
boost inductors L 1 and L 2 coupled to input ac source Vac
and two capacitors C1 and C2 . The main purpose of adding
split input capacitors C1 and C2 is to create common point N semiconductors exhibit zero resistance, i.e., they are short
that has the medium potential of ac input source Vac . As a circuits. However, the output capacitances of the switches are
result, voltages VAN and VBN across capacitors C1 and C2 are not neglected in this analysis. The coupled inductor L C in
substantially equal to one-half of input voltage Vac and have Fig. 1 is modeled as a two-winding ideal transformer with
opposite polarities. Common point N between capacitors C1 magnetizing inductance L M and leakage inductances L LK1 and
and C2 is connected to the midpoint between switches S1 and L LK2 . Finally, since the average voltage across capacitor C R
S2 and also to the midpoint of split output capacitors C O1 is equal to output voltage VO = VO1 + VO2 , capacitor C R is
and C O2 . As a result, the potential of the midpoint of output modeled as a constant voltage source. The reference directions
capacitors C O1 and C O2 and the midpoint of switches does not of voltages and currents in the circuit diagram of the simplified
experience step changes with high dV/dt. Switches S1 and S2 rectifier shown in Fig. 2 correspond to the 180◦ segment of a
are controlled by two complementary gate signals with 50% line cycle when Vac > 0, VAN > 0, and VBN < 0.
duty cycle and a short dead time necessary to achieve ZVS To further facilitate the explanation of the operation, Fig. 3
turn on. shows the topological stages of the circuit in Fig. 2 during
As shown in Fig. 1, because the midpoint between switches a switching cycle, whereas Fig. 4 shows the power-stage key
S1 and S2 is directly connected to common point N and bridge waveforms.
diodes D1 –D4 are located between the switches and phase As can be seen from the gate-drive timing diagrams for
voltages VAN and VBN across capacitors C1 and C2 , bridge switches S1 and S2 in Fig. 4, both switches operate with 50%
diodes D1 –D4 only allow the phase voltage with positive duty cycle in an alternative fashion with the short dead time
potential to deliver current through switch S1 when it is between the turn off of switch S1 and turn on of switch S2
turned on. Similarly, the phase voltage with negative potential or vice versa. Because of this gating strategy, both switches
provides current through switch S2 when it is turned on. can achieve ZVS. To maintain ZVS with a 50% duty cycle
Therefore, when switch S1 is on, the boost inductor connected for a varying input voltage and/or output load, the proposed
to the positive phase voltage stores energy and carries positive rectifier must employ a variable switching frequency control.
current whereas, when switch S2 is ON, the other boost The minimum frequency is determined at full load and the
inductor connected to the negative phase voltage stores energy minimum input voltage, while the maximum frequency is
and carries negative current. When switch S1 is OFF, the stored determined at a light load and the maximum input voltage.
energy in the boost inductor connected to the positive phase The rectifier operates in the pulsewidth modulation (PWM)
voltage is delivered to flying capacitor C R whereas, when mode or burst mode at no load or very light load, to avoid
switch S2 is OFF, the stored energy in the boost inductor unnecessarily high-frequency operation.
connected to the negative phase voltage is delivered to flying As shown in Figs. 3(a) and 4, when switch S1 is on, inductor
capacitor C R . Because the voltage of each terminal of flying current i L1 flows through switch S1 . The slope of inductor
capacitor C R changes with high dV/dt at every switching cycle, current i L1 is equal to VAN /L 1 . The peak of the inductor current
coupled inductor L C is connected between output capacitors is approximately
C O1 and C O2 and flying capacitor C R to isolate the common- VAN TS
mode noise sources to a small area. I L1(PK) = × (1)
L1 2
where VAN is the phase voltage across the input capacitor
III. A NALYSIS OF O PERATION
C1 , and TS is the switching period. Because the dead time
To simplify the analysis of operation, it is assumed that between the turn off of switch S1 and turn on of switch
ripple voltages of the input and output filter capacitors shown S2 is very small in comparison with switching period TS ,
in Fig. 1 are negligible such that the voltage across the the effect of the dead time is neglected in (1). During the
input and output filter capacitors can be represented by period between T0 and T1 , current i O1 decreases by the rate
constant-voltage sources VAN , VBN , VO1 , and VO2 , as shown as −VO1 /(2·L M + LLK1 ) while current i O2 increases by the
in Fig. 2. In addition, it is assumed that in the on state, rate as (VCR − VO2 ) (2·L M + L LK2 ). Magnetizing current i M

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 SADILEK et al.: LOW-THD TWO-SWITCH PFC DCM BOOST RECTIFIER 1757

Fig. 3. Topological states of proposed rectifier when Vac > 0. (a) [T0 − T1 ]. (b) [T1 − T2 ]. (c) [T2 − T3 ]. (d) [T3 − T4 ]. (e) [T4 − T5 ]. (f) [T5 − T6 ]. (g) [T6 − T7 ].
(h) [T7 − T8 ].

is the difference between currents i O1 and i O2 . It should be output capacitance of switch S2 is fully discharged, and the
noted that the inductance value of coupled inductor L M is antiparallel body diode of switch S2 starts to conduct at t = T2 ,
designed to be sufficiently large such that the ripple current as shown in Figs. 3(c) and 4. Because the body diode of
of the coupled inductor does not significantly affect rectifier switch S2 is forward biased, inductor current i L2 begins to
operation. As shown in Fig. 1, the two windings of inductor increase linearly. At t = T3 , switch S2 is turned on with ZVS
L M are coupled in such a way as to cancel the magnetic fluxes and inductor current i L2 is commutated from the antiparallel
from the differential current of the two windings so that the diode of switch S2 to the switch, as shown in Fig. 3(d).
large magnetizing inductance can be obtained by a small gap This period ends when the inductor current i L1 decreases to
in the core without saturation. Since the effect of currents i O1 zero at t = T4 . To maintain DCM operation, the time period
and i O2 is negligible, they are no longer discussed, although between t = T3 and t = T4 must be less than one-half of
they are shown in topological stages in Fig. 3. switching period TS , which means that the rising slope of
At t = T1 , when switch S1 is turned off, inductor current i L1 inductor current i L1 should be smaller than its falling slope.
starts charging the output capacitance of switch S1 , as shown As a result, minimum voltage VCR(MIN) across capacitor C R ,
in Fig. 3(b). Since the switches S1 and S2 are clamped which is equal to minimum output voltage VO(MIN), should be
to capacitor voltage VCR , the output capacitance of switch √
VCR(MIN) ≥ 2 × V AN(PK) = 2 × VAC,rms (2)
S2 discharges at the same rate as the charging rate of the
output capacitance of switch S1 . This period ends when the where VAN(PK) is the peak phase voltage.

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 1758 IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION, VOL. 6, NO. 4, DECEMBER 2020

Fig. 5. Simplified control block diagram showing feedback and feedforward

control.

inductor current i L2 reaches zero at t = T8, and a new

switching cycle begins, as shown in Fig. 3(a).
As shown in the inductor current waveform in Fig. 4, when
a switch is turned on, the voltage across related boost inductor
L 1 or L 2 is always the phase voltage VAN or VBN , respectively.
When the switch is turned off, the voltage across related boost
inductor L 1 or L 2 is always respective phase voltage VAN
or VBN minus flying capacitor voltage VCR until the boost
inductor current reaches zero. As a result, averaged inductor
current I L−AVG Ts of each boost inductor, which is averaged
over a full switching cycle as described in [35], is
 √ 
Fig. 4. Key waveforms of the proposed rectifier when VAN > 0 and VBN < 0. VCR TS 2Vac,rms sinωt
I L−AVG TS (t) = √ (4)
8L 2VCR − 2Vac,rms sinωt
It also should be noted that because inductor current i L2 where L is the inductance of a boost inductor assum-
flows in the opposite direction from inductor current i L1 during ing boost inductors L 1 and L 2 having an identical value,
the time between t = T2 and t = T4 , the average current and ω is the angular frequency of the line voltage.
through switch S2 is reduced so that the switches in the √ PFC, switching period TS should be proportional to
To achieve
proposed rectifier exhibit reduced conduction losses. 2VCR − 2Vac,rms sinωt, that is,
During the period between t = T4 and t = T5 , inductor  √ 
current i L2 continues to flow through switch S2 , as shown TS (t) = K 2VCR − 2Vac,rms sinωt (5)
in Fig. 3(e). As shown in Fig. 4, the slope of inductor current where K is a constant. With the proposed control method,
i L2 during this period is equal to VBN /L 2 . The peak of the averaged inductor current I L_AVG Ts of each boost inductor
inductor current at the moment when switch S2 turns off at becomes
t = T5 is approximately
VCR · K √ 
I L_AVG TS (t) = 2Vac,rms sinωt . (6)
VBN TS 8L
I L2(PK) = × . (3) Since voltage VCR and inductance L are also constant, the
L1 2
averaged inductor current that is equal to the input current is
As can be seen in (1) and (3), the peak of each inductor proportional to the input voltage. Fig. 5 shows the simplified
current is proportional to its corresponding input voltage. control block diagram that depicts the injection of the simple
After switch S2 is turned off at t = T5 , inductor cur- feedforward signal obtained from input and output voltages to
rent i L2 starts to simultaneously charge the output capac- the output voltage feedback control. As shown in the nonlinear
itance of switch S2 and discharge the output capacitance compensator block in Fig. 5, the sensed ac input voltage is
of switch S1 , as shown in Fig. 3(f). This period ends at rectified and scaled to be subtracted from the scaled output
t = T6 when the output capacitance of switch S1 is fully dis- voltage, which creates the nonlinear term of (5). The result of
charged, and its antiparallel diode starts conducting, as shown the nonlinear compensator is multiplied with signal G of the
in Figs. 3(g) and 4. After t = T6 , switch S1 can be turned on output voltage feedback compensator. The voltage-controlled
with ZVS. In Fig. 4, switch S1 is turned on at t = T7 . As shown oscillator (VCO) generates gate signals that are alternate
in Fig. 3(h), once switch S1 is on, increasing inductor current pulses with approximately 50% duty cycle and switching
i L1 flows in the opposite direction from inductor current i L2 period TS for switches S1 and S2 , as shown in Fig. 4. Since
through switch S1, so that switch S1 carries only the difference switching period TS is proportional to the multiplier output
of current i L1 and current i L2 . This period ends when the signal with the constant VCO gain, the condition derived

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 SADILEK et al.: LOW-THD TWO-SWITCH PFC DCM BOOST RECTIFIER 1759

Fig. 6. Simplified block diagram of digital control implementation.

at (5) is met, and the proposed rectifier automatically achieves obtained from output voltage VO . Output voltage VO is scaled
PFC without active current shaping control. It should be noted and passed through an anti-aliasing filter G AAF (s) with corner
that K in (5) is equal to the multiplication of k, G, and VCO frequency f AAF = 16 kHz. This sensed and filtered signal is
gain, as shown in Fig. 5. then converted to the digital domain with the 12-b analog-to-
digital converter (ADC), which has a full-scale range of 3.3 V.
In the DSP, the signal at the output of the ADC is multiplied
IV. C ONTROL S TRUCTURE
with unscaling gain K S to obtain sensed and sampled output
The control of the prototype rectifier was implemented with voltage VO(SENS) so that the value of VO(SENS) is equal to the
TMS320F28027 DSP from TI. Since the rectifier naturally value of output voltage VO .
achieves a high-power factor without an active current shaping In the implementation in Fig. 6, the drive signals of switches
control, the control consists only of a low-bandwidth feedback S1 and S2 are generated by digital PWM (DPWM) with an
loop that varies the switching frequency to regulate the output up–down counter as a digital carrier ramp. The up–down
voltage. Switches S1 and S2 operate with variable frequency, counter is generated by counting the DSP clock period TCLK .
alternate switching pulses with a 50% duty cycle. In general, Since carrier ramp period TS = 2 · NCAR · TCLK , where NCAR
a converter with variable frequency control employs burst- is the number of clock periods, carrier ramp period TS is
mode operation at light load, in which the switching pulses are proportional to NCAR . It should be noted that in the variable
enabled and disabled at regular intervals to regulate the out- frequency control mode, carrier ramp peak NCAR is determined
put voltage. However, the burst mode operation significantly by the product of the output of voltage controller VEA and
increases the magnitude of the output voltage ripple. To reduce normalized feedforward injection signal VFI . In fact, in the
the peak–peak ripple of the output voltage at light load, PWM variable frequency mode, the output of voltage controller VEA
is employed instead of a burst mode operation. Switches S1 is equal to the output of the “calculation of switching period”
and S2 operate with constant frequency, 180◦ phase-shifted, block NCAR−AVG so that VEA(MAX) = NMAX and VEA TH
= NMIN .
variable-duty-cycle pulses. The PWM frequency is selected as Normalized feedforward injection signal VFI is calculated as
20 kHz to avoid audible noise and to limit converter losses  
2 · v O(SENS) − v ac(SENS) 
since the switches lose ZVS turn on in the PWM mode. VFI = (7)
Fig. 6 shows the simplified block diagram of the proposed KN
digital control implementation. As can be seen in Fig. 6, for where v ac(SENS) is the sensed and sampled ac input voltage
both the variable frequency control and the PWM control, whose value is equal to the ac input voltage v ac , and K N is
the switching period and the switching pulse on time are the normalization factor. The value of normalization factor
determined by output VEA of voltage controller G C . Voltage K N is calculated such that the average value of normalized
controller G C processes the error between sensed and sampled feedforward injection signal VFI over a line cycle is 1, as
output voltage VO(SENS) and reference VO(REF) . It can be seen 2 peak
from Fig. 6 that sensed and sampled output voltage VO(SENS) is K N = 2 · v O(SENS) − V (8)
π ac(SENS)
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 1760 IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION, VOL. 6, NO. 4, DECEMBER 2020

Fig. 7. Experimental waveforms of rectified ac input voltage |v ac | and the

normalized feedforward injection signal at line frequency f L = 800 Hz, VO =
220 V, and Vac = 94 VRMS . Sampling and control law calculation frequency
f CTRL is 50 kHz.

Fig. 8. Block diagram of output voltage control loop in the continuous-time

domain.
peak
where Vac(SENS)is the peak value of the sensed and sampled
ac input voltage. By using a normalized feedforward injection
signal, the steady-state value of the output of the voltage compensator, that is,
controller VEA with and without the feedforward injection will KI
be approximately the same. In addition, with the normalized G C (s) = K P + (10)
s
feedforward injection, the gain of the output voltage control
loop will not be affected, and therefore, the dynamic response where K I = 2 · π · f Z · K P and f Z is the zero of the PI com-
of the output voltage control loop will not be affected. Fig. 7 pensator. The parameters K P and K I of the PI compensator
shows the experimental waveforms of rectified ac input voltage are designed by using the SIMPLISTM commercial simulation
|v ac | and the normalized feedforward injection signal at line tool. The bode plots of plant transfer function G PL (s), loop
frequency f L = 800 Hz, VO = 220 V, and Vac = 94 VRMS . It is gain TV (s) and controller transfer function G C (s) simulated
important to note that the sampling and control law calculation when the rectifier operates from an input voltage of 115 VRMS
frequency of 50 kHz is selected to attain a sufficient number of and delivers the full power of 320 W are shown in Fig. 9.
calculations in a line cycle to achieve low THD at maximum To achieve bandwidth higher than 10 Hz and phase margin
line frequency f L(MAX) = 800 Hz. greater than 65◦ , the parameters of PI compensator, K P = 27
Furthermore, in Fig. 6, it should be noted that the maximum and K I = 2 · π · f Z · K P = 1017 s−1 , where f Z = 6 Hz,
value of NCAR , i.e., NMAX = 750, which corresponds to were selected. Since the control frequency in the prototype
minimum switching frequency f SW_MIN = 40 kHz and the circuit is f CTRL = 50 kHz, the z-domain transfer function
minimum value of NCAR , i.e., NMIN = 120 which corresponds of the output voltage controller G C (z) obtained by bilinear
to the maximum switching frequency f SW_MAX = 250 kHz. (Tustin’s) transformation is
The selection of the maximum switching frequency is to limit
z −1
the switch turn off losses, gate-driving losses, and magnetic G C (z) = 27 + 0.02034 . (11)
losses of the boost inductor. Moreover, it can guarantee suffi- 1 − z −1
cient precision of the gate signals generated by the processor. At light loads, as shown in Fig. 6, when voltage controller
The output voltage controller is designed using an analog- output VEA reaches a threshold value VEA TH
, which corre-
to-digital conversion approach, i.e., by designing controller sponds to the maximum switching frequency of 250 kHz,
G C in the s-domain (continuous-time domain) and mapping it the controller changes its control mode to the PWM mode.
into the z-domain (discrete-time domain). The continuous-time In the PWM mode, the variable duty-cycle is achieved by
domain block diagram of the output voltage control loop, varying DPWM carrier comparison level Non whose value
which is obtained from the block diagram in Fig. 6, is shown is determined by voltage controller output VEA . Non changes
in Fig. 8. The output voltage control loop gain TV (s) is equal MAX
from Non(PWM) TH
at VEA MAX
to 0 at VEA(MIN). The value of NON (PWM)
to the product of the plant transfer function G PL (s) and the peak
is determined by the peak of input voltage Vac(SENS) since
controller transfer function G C (s) and is obtained as the power level at which the control mode changes from the
variable frequency control to PWM is positively correlated
2 peak
TV (s) = G PL (s) · G C (s) = K D · K ADC · K S with Vac(SENS) , as shown in (4) (120 W at 134 VRMS , 80 W
f CLK at 115 VRMS , and 65 W at 94 VRMS ). It should be noted that
·G PS (s) · G AAF (s) · G C (s) (9) in the PWM mode, constant switching frequency f SW_PWM is
20 kHz and the corresponding carrier peak NPWM is equal to
where f CLK is the clock frequency of the processor, K D is the fCLK /(2·fSW ) = 1, 500. Also, in the PWM mode, the feedfor-
sensing gain of the output voltage, K ADC is the gain of ADC, ward injection is not applied, i.e., VFI = 1.
K S is the unscaling gain such that K S = 1/(K D · K ADC ), The drive signal of switch S1 is obtained by compar-
G PS (s) is the power-stage small-signal transfer function, and ing the carrier ramp with comparison level NCAR –Non whereas,
G AAF (s) is the transfer function of the anti-aliasing filter. the drive signal of switch S2 is obtained by directly comparing
The output voltage controller is implemented with a PI the carrier ramp with Non . In the variable frequency mode,

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 SADILEK et al.: LOW-THD TWO-SWITCH PFC DCM BOOST RECTIFIER 1761

TS = 1/ f SW = 25 μs as
 √ min 
VCR TS 2Vac,rms
L= √ ≈ 50 μH. (13)
8 · Iac(peak)
max
2VCR − 2Vac,rms
min

To obtain the desired inductance of boost inductors L 1 and

L 2 of approximately 50 μH, each inductor was built using a
pair of ferrite cores (PQ-26/20, 3C95) with 15 turns of Litz
wire (200 strands / AWG #38).

B. Switch Selection
The voltage stress of switches S1 and S2 is approximately
equal to bus voltage VCR = 220 V. Due to ZVS operation
and practically no overshoot in the voltage across switches S1
and S2 , IPP220N25NFD MOSFET (VDS = 250 V, RDS = 22
m, COSS = 299 pF, and Q RR = 623 nC) was used in this
prototype.

C. Rectifier Diode Selection

As input diodes D1 –D4 block the same voltage and conduct
the same current as of the switches, the STTH803 rectifier
was selected (VRRM = 300 V, I A = 8 A, and tRR = 625 ns).
Fig. 9. Simulated bode plots. Gain and phase of transfer function G PL (s), The crucial part of the diode selection is the tradeoff between
loop gain TV (s), and controller transfer function G C (s).
diode forward voltage drop VF and output capacitance COSS .
Diode voltage drop VF reduces power conversion efficiency
while diode output capacitance COSS resonates with the boost
switches S1 and S2 operate alternately with a 50% duty cycle
inductor since the boost inductor current is discontinuous. Due
and, therefore, Non = NCAR /2.
to the variable-frequency operation and time-varying input
voltage VAC , the number of resonant cycles is not constant,
V. D ESIGN C ONSIDERATIONS which might lead to additional line current harmonics.
Design guidelines and performance evaluation of the pro-
posed rectifier for aviation applications with the following key D. Capacitor Selection
specifications are presented. Input capacitors C1 and C2 provide filtering of the switching
1) Single-phase ac input voltage Vac : 94 – 134 VRMS. frequency ripple and facilitate phase decoupling. The current
2) Line frequency range: 360–800 Hz. rating of the capacitors is determined by the peak boost
3) THD: meets the DO-160 standard (THD less than inductor current that occurs at full load and low line. A low-
10% with a limit on each current harmonic, as shown ESR film capacitor (2.2 μF, 305 VAC ) was selected.
in Fig. 14). The peak current of the flying capacitor C R is approximately
4) PF: ≥ 0.98. equal to the peak current of the boost inductor. A film capacitor
5) Efficiency: ≥ 95% from 30% to 100% load at nominal (2.2 μF, 250 V) is placed across switches S1 and S2 . Moreover,
input voltage two additional film capacitors (1 μF, 250 V) are placed across
6) Output voltage VO : 220 V. diodes D1 and D3 and diodes D2 and D4 pairs, respectively.
7) Maximum output power PMAX : 320 W. The voltage ripple across the flying capacitors at rated power
is less than 1% of the nominal output voltage.
Finally, the output bulk capacitance was an aluminum
A. Design of Boost Inductor capacitor (2.4 mF, 320 V) sized to effectively filter out the
For the design of the boost inductor with 25% margin, line-frequency voltage ripple and to provide sufficient hold-up
the maximum value of the average boost inductor current over time for the rectifier load.
a switching period I L_AVG TS is calculated as
√ PMAX E. Input Filter Design
I L_AVG TS = Iac(peak)
max
= 2 · min · 1.25 = 6.02 A. (12) The simplified schematic of the input filter is shown
Vac,rms
in Fig. 10. The filter has two stages. The first stage is formed
To achieve the desired power density, the minimum switch- by two symmetrical differential mode filter inductors L DM1
ing frequency f SW at the maximum value of peak line current and L DM2 and input capacitors C1 and C2 . The inductance of
max
Iac(peak) is set to 40 kHz. Substituting (12) into (4), the value filter inductors L DM1 and LDM2 are equally 175 μH. Leakage
of boost inductor L can be calculated using VCR = 220 V, inductance L CM−LK of each winding of the common-mode

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 1762 IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION, VOL. 6, NO. 4, DECEMBER 2020

Fig. 10. Simplified schematic of the input filter. Currents of boost inductors
are represented as current sources.

Fig. 12. Top view of experimental prototype circuit.

Fig. 11. Schematics and component information of experimental prototype

circuit.

filter inductor and differential-mode filter capacitor CDM form

the second stage, where L CM−LK = 190 μH and capacitor
CDM = 0.1 μF. The two-stage input filter has two complex
pole pairs at 5.5 and 37 kHz.
The currents of boost inductors L 1 and L 2 are represented
as current sources i L1 and i L2 in the simplified schematic
in Fig. 10. As shown in Fig. 4, boost inductor currents
i L1 and i L2 are interleaved, i.e., they have opposite signs,
equal magnitude, and shifted phase by 180◦ concerning each
other. As a result, the minimum effective frequency of the
ripple current that should be attenuated is 80 kHz when
the rectifier operates at the minimum switching frequency
of 40 kHz. The attenuation of the input filter at 80 kHz is
approximately 63 dB.

VI. E XPERIMENTAL R ESULTS

The performance of the proposed converter, as shown
in Fig. 1, was evaluated on a 320-W prototype circuit designed
according to the procedure, and the key specifications are given Fig. 13. Measured input voltage Vac and input current IAC waveforms when
in Section IV. Fig. 11 shows the schematics and component prototype circuit delivers 320 W from 115-V input voltage with (a) 360 and
information of the prototype. Furthermore, a top view of the (b) 800 Hz, respectively.
experimental prototype circuit is shown in Fig. 12.
Fig. 13 (a) and (b) shows the measured waveforms of the
ac input voltage and input current at 360- and 800-Hz line Measured line current even harmonics are significantly below
frequencies. The measured THDs were 2.28% at 360 Hz and the DO-160 limit, and therefore, not shown in Fig. 14.
3.29% at 800 Hz, respectively. Moreover, the measured power Fig. 15 shows the measured waveforms of the gate and
factor was 0.997 at 360 Hz and 0.982 at 800 Hz, respectively. drain voltages of switch S1 and the current waveform of
Fig. 14 shows the comparisons between each harmonic boost inductor L 1 at 800-Hz line frequency and full load.
limit specified by the DO-160 standard and measured line The measured waveforms in Fig. 15 are in good agreement
current harmonic content when prototype rectifier delivers a with the ideal waveforms shown in Fig. 4. It should be noted
full load at 360- and 800-Hz line frequencies. Each mea- that switch S1 turns on when its drain voltage is substantially
sured current harmonic is well below its required limit. zero. Dead time duration is 400 ns. Due to soft switching and

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 SADILEK et al.: LOW-THD TWO-SWITCH PFC DCM BOOST RECTIFIER 1763

Fig. 17. Measured THD at Vac = 115 VRMS , VO = 220 V, and f L = 360,
500, and 800 Hz, respectively, as functions of output power.

Fig. 14. Comparisons between each harmonic limit specified by DO-160 and
measured harmonic content of line current when prototype circuit delivers
320 W from 115-V input voltage with 360 and 800 Hz. Each measured
harmonic is well below its required limit.

Fig. 18. Measured power conversion efficiency at Vac = 115 VRMS , VO =

220 V, and f L = 360, 500, and 800 Hz, respectively, as functions of output
power.

THD across the entire power range is shown in Fig. 17. It

Fig. 15. Measured waveforms of gate and drain voltages of switch S1 , current should be noted that THD increases with reduced load level
of inductor L 1 , and input current iAC . because of more pronounced nonideal circuit properties, such
as switch output capacitance COSS , diode forward voltage
drop VF , and so on. Moreover, lower power levels occur
at higher switching frequencies, where the 400-ns dead time
forms a more significant portion of the entire switching period.
Input current THD stays below 10% at all line frequencies and
input voltages as specified in Section IV for loads greater than
50% of rated power.
Power conversion efficiency as a function of load at line
frequencies of interest is shown in Fig. 18. The measured
efficiency of the prototype circuit was approximately 95.8% at
full load and nominal phase voltage of VAC of 115 VRMS . Line
frequency has no significant impact on converter efficiency.
Calculated loss distribution of the converter at nominal input
Fig. 16. Measured power factor at Vac = 115 VRMS , VO = 220 V, and voltage and full load is shown in Fig. 19. The four bridge
f L = 360, 500, and 800 Hz, respectively, as functions of output power. diodes contribute to nearly half of all losses, which is expected
since the diode voltage drop forms a significant fraction of
the input voltage. Conduction and turn-off losses of switches
a small inductive loop, there is no voltage overshoot across contribute only 0.7%. Turn-on losses of switches are zero
the switch. Switching-frequency waveforms are independent due to ZVS. The loss denoted as “other” corresponds to the
of the line frequency. As a result, similar waveforms were difference between calculated and measured losses. Losses,
measured at f L = 360 Hz. such as losses of PCB traces, additional switching losses due to
Power factors as a function of load at line frequencies nonlinear parasitic capacitances, losses induced by discharge
of 360, 500, and 800 Hz are shown in Fig. 16. Measured circuits for capacitors and voltage measurement circuits, and

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 1764 IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION, VOL. 6, NO. 4, DECEMBER 2020

Fig. 19. Estimated loss distribution for Vac = 115 VRMS , VO = 220 V, and Fig. 21. Measured waveforms of output voltage v O , phase voltage v ac , phase
PO = 320 W at f L = 800 Hz. current iAC , and boost inductor current i L1 when prototype circuit delivers
320 W from 115-VRMS input voltage. There is abrupt line frequency change
from 360 to 800 Hz.

Fig. 20. Measured power conversion efficiency at minimum (Vac = 94 VRMS ),

nominal (Vac = 115 VRMS ), and maximum (Vac = 134 VRMS ) phase voltages,
VO = 220 V, and f L = 800 Hz as functions of output power. Fig. 22. Transition from variable frequency mode to PWM mode at light load
with Vac = 115 VRMS , VO = 220 V, and f L = 360 Hz. Load is approximately
80 W. Switching frequency is 20 kHz in PWM mode.

gate driver losses, are not included in the calculated loss

model. Fig. 22 shows the measured waveforms of the rectifier
Furthermore, Fig. 20 shows the converter efficiency at during a transition from the variable frequency mode to the
800-Hz line frequency as functions of load and input voltage. PWM mode. In the PWM mode, the duty cycle of the switches
Higher input voltage (134 VRMS ) results in lower input current is adjusted by the feedback compensator to regulate the output
and, therefore, increased efficiency. Fig. 20 also shows the voltage, as shown in the control diagram in Fig. 6. It should be
region of the PWM operation. noted that the peak value of the inductor current in the PWM
Fig. 21 shows a transient response of the rectifier during mode at light loads is still smaller than the peak value of the
an abrupt line frequency change from the minimum frequency inductor current at full load. Therefore, the boost inductors
of 360 Hz to the maximum frequency of 800 Hz at nominal do not saturate at the low-frequency operation in the PWM
input voltage and rated load. The input current follows the mode. It should also be noted that the ringing of drain-to-
input voltage of the rectifier without any significant distortion. source voltage VDS of the switch shown in Fig. 22 is the result
Furthermore, there is no observable response in rectifier output of the discontinuous inductor currents. However, voltage VDS
voltage VO . is well clamped by flying capacitor voltage VCR .
As indicated by (4), the output power of the rectifier is
inversely proportional to the switching frequency. As a result, VII. C ONCLUSION
the switching frequency of the rectifier is high, and the peak- A new, two-switch, PFC, DCM boost rectifier that features
values of the inductor currents i L1 and i L2 become small to ZVS and can achieve less than 5% input-current THD at
achieve ZVS at light loads. High-frequency operation without very high line frequencies is proposed and evaluated. Since
ZVS at light loads results in significant switching losses. low THD is achieved without high-bandwidth active current
To limit the high switching frequency operation at light loads, shaping control, the proposed topology is suitable for modern
the mode of control is changed from variable frequency to aviation applications that require line frequency up to 800 Hz.
PWM if the maximum switching frequency is reached during The prototype achieves 3.3% THD at full load of 320 W and
the variable frequency mode. In the PWM mode, the rectifier nominal line input voltage 115 V over the line frequency range
operates with a constant switching frequency of 20 kHz to from 360 to 800 Hz and meets the required harmonic limits
avoid audible noise and limit switching losses. specified by the DO-160 standard.

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 SADILEK et al.: LOW-THD TWO-SWITCH PFC DCM BOOST RECTIFIER 1765

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[16] M. Silva, N. Hensgens, J. Oliver, P. Alou, O. Garcia, and J. A. Cobos,
“Isolated Swiss-forward three-phase rectifier for aircraft applications,” Tomas Sadilek (Member, IEEE) received the B.S.
in Proc. IEEE Appl. Power Electron. Conf. Expo. (APEC), Fort Worth, degree in electrical engineering from Czech Tech-
TX, USA, Mar. 2014, pp. 951–958. nical University in Prague, Prague, the Czech
[17] J. L. F. Vieira, J. A. Oliver, P. Alou, and J. A. Cobos, “Power converter Republic, in 2007, and the M.S. degree in mechan-
topologies for a high performance transformer rectifier unit in aircraft ical engineering from the University of Wisconsin–
applications,” in Proc. 11th IEEE/IAS Int. Conf. Ind. Appl., Juiz de Fora, Madison, Madison, WI, USA, in 2016.
Brazil, Dec. 2014, pp. 1–8. From 2014 to 2019, he was with Electric Power
[18] T. B. Soeiro, G. J. M. de Sousa, M. S. Ortmann, and M. L. Heldwein, Organization, General Electric Global Research,
“Three-phase unidirectional buck-type third harmonic injection rectifier Niskayuna, NY, USA. He is currently a Member
concepts,” in Proc. IEEE Appl. Power Electron. Conf. Expo. (APEC), of Research and Development Staff with the Milan
Fort Worth, TX, USA, Mar. 2014, pp. 928–934. M. Jovanović Power Electronics Laboratory, Delta
[19] S. F. Lim and A. M. Khambadkone, “A simple digital DCM control Electronics (Americas) Ltd., Durham, NC, USA. His research interests
scheme for boost PFC operating in both CCM and DCM,” IEEE Trans. include machine drive systems and power electronics, especially for electric
Ind. Appl., vol. 47, no. 4, pp. 1802–1812, Jul. 2011. propulsion traction and infrastructure applications.

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 1766 IEEE TRANSACTIONS ON TRANSPORTATION ELECTRIFICATION, VOL. 6, NO. 4, DECEMBER 2020

Misha Kumar (Member, IEEE) was born in New Peter Barbosa (Senior Member, IEEE) received the
Delhi, India. She received the B.Tech. degree in Ph.D. degree from Virginia Tech, Blacksburg, VA,
power-electrical engineering from Guru Gobind USA, in 2002.
Singh Indraprastha University, New Delhi, in 2009, From 2001 to 2003, he served as the Techni-
and the M.S.E.E degree from North Carolina State cal Director with the Center for Power Electronics
University (NCSU), Raleigh, NC, USA, in 2011. Systems, Virginia Tech. In 2003, he joined ABB
During her graduate studies, she worked as Corporate Research, Baden, Switzerland, as a Sci-
Research Assistant with the FREEDM System Cen- entist, and later as a Manager of the Power Elec-
ter, NCSU. Since 2011, she has been a Member tronics and System Applications Group. At ABB,
of Research and Development Staff with the Milan he developed innovative multilevel power converters
M. Jovanović Power Electronics Laboratory, Delta for high-power applications by introducing novel
Electronics (Americas) Ltd., Durham, NC, USA. Her current research interests hybrid multilevel power conversion concepts. Since 2008, he has been with
include analysis, design, and implementation of power converters, such as Delta Electronics, Inc., Taipei, Taiwan, where he was involved in developing
bidirectional dc–dc converters for onboard chargers and auxiliary power high-efficiency telecom power supplies and heading medium-voltage drive
modules in electric vehicle applications, single-phase and three-phase PFC products, and transferred to the Milan M. Jovanović Power Electronics
for telecom and server applications, and gradient power supply for MRI Laboratory, Delta Electronics (Americas) Ltd., Durham, NC, USA, as the
application. Director.

Iqbal Husain (Fellow, IEEE) received the Ph.D.

degree in electrical engineering from Texas A&M
University, College Station, TX, USA, in 1993.
He was with The University of Akron, Akron, OH,
USA, where he built a successful power electron-
ics and motor drives program. He was a visiting
Professor with Oregon State University, Corvallis,
Yungtaek Jang (Fellow, IEEE) was born in Seoul, OR, USA, in 2001. He is currently the Director of
South Korea. He received the B.S. degree from the FREEDM Systems Center and the ABB Distin-
Yonsei University, Seoul, in 1982, and the M.S. guished Professor with the Department of Electrical
and Ph.D. degrees from the University of Colorado and Computer Engineering, North Carolina State
at Boulder, Boulder, CO, USA, in 1991 and 1995, University, Raleigh, NC, USA. He has also developed innovative graduate
respectively, all in electrical engineering. and undergraduate courses on electric and hybrid vehicles and authored
Since 1996, he has been a Senior Member of the textbook Electric and Hybrid Vehicles: Design Fundamentals on this
Research and Development Staff with the Milan topic. His expertise is in the areas of power electronics, electric machines,
M. Jovanović Power Electronics Laboratory, Delta motor drives, and system controls. The primary applications of his work
Electronics (Americas) Ltd., Durham, NC, USA, the are in the transportation, automotive, aerospace, and power industries. His
U.S. subsidiary of Delta Electronics, Inc., Taipei, research interest is focused on power electronics integration into power and
Taiwan. He holds 30 U.S. patents. He has authored or coauthored 31 journal transportation systems.
articles in refereed journals and more than 50 technical articles in conference Dr. Husain received the 1998 IEEE-IAS Outstanding Young Member Award,
proceedings. the 2000 IEEE Third Millennium Medal, the 2004 College of Engineering
Dr. Jang received the IEEE T RANSACTIONS ON P OWER E LECTRONICS Outstanding Researcher Award, and the 2006 SAE Vincent Bendix Automo-
prize paper awards for the best paper published in 1996, 2009, and 2013, tive Electronics Engineering Award. He is the past Editor-in-Chief of the IEEE
respectively. Electrification Magazine.

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