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DAC124S085
SNAS348G – MAY 2006 – REVISED APRIL 2016

DAC124S085 12-Bit Micro Power Quad Digital-to-Analog

Converter With Rail-to-Rail Output
1 Features 3 Description
•
1 Ensured Monotonicity The DAC124S085 device is a full-featured, general-
purpose, quad, 12-bit, voltage-output, digital-to-
• Low Power Operation analog converter (DAC) that can operate from a
• Rail-to-Rail Voltage Output single 2.7-V to 5.5-V supply and consumes 1.1 mW
• Power-On Reset to 0 V at 3 V and 2.4 mW at 5 V. The DAC124S085 is
• Simultaneous Output Updating packaged in 10-pin WSON and VSSOP packages.
• Wide Power Supply Range: 2.7 V to 5.5 V The 10-pin SON package makes the DAC124S085
the smallest quad DAC in its class. The on-chip
• Industry's Smallest Package
output amplifier allows rail-to-rail output swing and the
• Power-Down Modes three-wire serial interface operates at clock rates up
• Resolution: 12 Bits to 40 MHz over the entire supply voltage range.
• INL: ±8 LSB (Maximum) Competitive devices are limited to 25-MHz clock rates
at supply voltages in the 2.7-V to 3.6-V range. The
• DNL: 0.7 to −0.5 LSB (Maximum) serial interface is compatible with standard SPI,
• Setting Time: 8.5 µs (Maximum) QSPI, MICROWIRE, and DSP interfaces.
• Zero Code Error: 15 mV (Maximum) The reference for the DAC124S085 serves all four
• Full-Scale Error: −0.75% FS (Maximum) channels and can vary in voltage between 1 V and
• Supply Power: VA, providing the widest possible output dynamic
range. The DAC124S085 has a 16-bit input shift
– Normal: 1.1 mW at 3 V or 2.4 mW at 5 V register that controls the outputs to be updated, the
(Typical) mode of operation, the power-down condition, and
– Power Down: 0.3 µW at 3 V or 0.8 µW at 5 V the binary input data. All four outputs can be updated
(Typical) simultaneously or individually depending on the
setting of the two mode of operation bits.
2 Applications
Device Information(1)
• Battery-Powered Instruments
PART NUMBER PACKAGE BODY SIZE (NOM)
• Digital Gain and Offset Adjustment VSSOP (10) 3.00 mm × 3.00 mm
• Programmable Voltage and Current Sources DAC124S085
WSON (10) 3.00 mm × 3.00 mm
• Programmable Attenuators (1) For all available packages, see the orderable addendum at
the end of the data sheet.

DNL at VA = 3 V

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
1 Features .................................................................. 1 8.4 Device Functional Modes........................................ 16
2 Applications ........................................................... 1 8.5 Programming........................................................... 16
3 Description ............................................................. 1 9 Application and Implementation ........................ 19
4 Revision History..................................................... 2 9.1 Application Information .......................................... 19
9.2 Typical Application .................................................. 19
5 Description (continued)......................................... 3
6 Pin Configuration and Functions ......................... 3 10 Power Supply Recommendations ..................... 21
10.1 Using References as Power Supplies................... 21
7 Specifications......................................................... 4
7.1 Absolute Maximum Ratings ...................................... 4 11 Layout................................................................... 23
11.1 Layout Guidelines ................................................. 23
7.2 ESD Ratings.............................................................. 4
11.2 Layout Example ................................................... 23
7.3 Recommended Operating Conditions....................... 4
7.4 Thermal Information ................................................. 5 12 Device and Documentation Support ................. 24
7.5 Electrical Characteristics........................................... 5 12.1 Device Support...................................................... 24
7.6 Timing Requirements ................................................ 7 12.2 Community Resources.......................................... 25
7.7 Typical Characteristics .............................................. 9 12.3 Trademarks ........................................................... 25
12.4 Electrostatic Discharge Caution ............................ 25
8 Detailed Description ............................................ 14
12.5 Glossary ................................................................ 25
8.1 Overview ................................................................. 14
8.2 Functional Block Diagram ....................................... 14 13 Mechanical, Packaging, and Orderable
8.3 Feature Description................................................. 15
Information ........................................................... 25

4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision F (March 2013) to Revision G Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section .................................................................................................. 1

Changes from Revision E (March 2013) to Revision F Page

• Changed layout of National Data Sheet to TI format ............................................................................................................. 1

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5 Description (continued)
A power-on reset circuit ensures that the DAC output powers up to zero volts and remains there until there is a
valid write to the device. A power-down feature reduces power consumption to less than a microWatt with three
different termination options.
The low power consumption and small packages of the DAC124S085 make it an excellent choice for use in
battery-operated equipment.
The DAC124S085 is one of a family of pin-compatible DACs, including the 8-bit DAC084S085 and the 10-bit
DAC104S085. The DAC124S085 operates over the extended industrial temperature range of −40°C to 105°C.

6 Pin Configuration and Functions

DGS Package
10-Pin VSSOP DSC Package
Top View 10-Pin WSON
Top View

VA 1 10 SCLK

VA 1 10 SCLK
VOUTA 2 9 SYNC

VOUTA 2 9 SYNC
VOUTB 3 8 DIN

VOUTB 3 ExposedPad 8 DIN

VOUTC 4 7 VREFIN

VOUTC 4 7 VREFIN
VOUTD 5 6 GND

VOUTD 5 6 GND

Pin Functions
PIN
TYPE (1) DESCRIPTION
NO. NAME
1 VA S Power supply input. Must be decoupled to GND.
2 VOUTA O Channel A analog output voltage.
3 VOUTB O Channel B analog output voltage.
4 VOUTC O Channel C analog output voltage.
5 VOUTD O Channel D analog output voltage.
6 GND G Ground reference for all on-chip circuitry.
7 VREFIN I Unbuffered reference voltage shared by all channels. Must be decoupled to GND.
Serial data input. Data is clocked into the 16-bit shift register on the falling edges of SCLK after the
8 DIN I
fall of SYNC.
Frame synchronization input for the data input. When this pin goes low, it enables the input shift
register and data is transferred on the falling edges of SCLK. The DAC is updated on the 16th clock
9 SYNC I
cycle unless SYNC is brought high before the 16th clock, in which case the rising edge of SYNC
acts as an interrupt and the write sequence is ignored by the DAC.
10 SCLK I Serial clock input. Data is clocked into the input shift register on the falling edges of this pin.
PAD Exposed die attach pad can be connected to ground or left floating. Soldering the pad to the PCB
11 G
(WSON only) offers optimal thermal performance and enhances package self-alignment during reflow.

(1) G = Ground, I = Input, O = Output, and S = Supply

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7 Specifications
7.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted) (1) (2) (3)
MIN MAX UNIT
Supply voltage, VA 6.5 V
Voltage on any input pin –0.3 6.5 V
Input current at any pin (4) 10 mA
Package input current (4) 20 mA
(5)
Power consumption at TA = 25°C See
Junction temperature, TJ 150 °C
Storage temperature, Tstg –65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(4) When the input voltage at any pin exceeds 5.5 V or is less than GND, the current at that pin must be limited to 10 mA. The 20 mA
maximum package input current rating limits the number of pins that can safely exceed the power supplies with an input current of 10
mA to two.
(5) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation is reached only when the device is operated in a severe fault
condition (that is, when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).

7.2 ESD Ratings

VALUE UNIT
(1)
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001 ±2500
V(ESD) Electrostatic discharge V
Machine model (MM) ±250

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

7.3 Recommended Operating Conditions

over operating free-air temperature range (unless otherwise noted) (1)
MIN NOM MAX UNIT
VA Supply voltage 2.7 5.5 V
VREFIN Reference voltage 1 VA V
(2)
Digital input voltage 0 5.5 V
Output load 0 1500 pF
SCLK frequency 40 MHz
TA Operating temperature –40 105 °C

(1) All voltages are measured with respect to GND = 0 V, unless otherwise specified.
(2) The inputs are protected as shown below. Input voltage magnitudes up to 5.5 V, regardless of VA, do not cause errors in the conversion
result. For example, if VA is 3 V, the digital input pins can be driven with a 5-V logic device.
I/O

TO INTERNAL
CIRCUITRY

GND

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7.4 Thermal Information

DAC124S085
THERMAL METRIC (1) DGS (VSSOP) DSC (WSON) UNIT
10 PINS 10 PINS
RθJA Junction-to-ambient thermal resistance 240 250 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 53.3 40.7 °C/W
RθJB Junction-to-board thermal resistance 78.9 23.7 °C/W
ψJT Junction-to-top characterization parameter 4.8 0.4 °C/W
ψJB Junction-to-board characterization parameter 77.6 23.8 °C/W
RθJC(bot) Junction-to-case (bottom) thermal resistance — 4.7 °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.

7.5 Electrical Characteristics

TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
STATIC PERFORMANCE
Resolution –40°C ≤ TA ≤ 105°C 12 Bits
Monotonicity –40°C ≤ TA ≤ 105°C 12 Bits
TA = 25°C ±2.4
INL Integral non-linearity LSB
–40°C ≤ TA ≤ 105°C ±8
TA = 25°C ±0.2
VA = 2.7 V to 5.5 V LSB
–40°C ≤ TA ≤ 105°C –0.5 0.7
DNL Differential non-linearity
TA = 25°C ±0.15
VA = 4.5 V to 5.5 V (2) LSB
–40°C ≤ TA ≤ 105°C ±0.5
TA = 25°C 4
ZE Zero code error IOUT = 0 mA mV
–40°C ≤ TA ≤ 105°C 15
TA = 25°C –0.1%
FSE Full-scale error IOUT = 0 mA FSR
–40°C ≤ TA ≤ 105°C –0.75%
All ones loaded TA = 25°C –0.2%
GE Gain error FSR
to DAC register –40°C ≤ TA ≤ 105°C –1%
ZCED Zero code error drift –20 µV/°C
VA = 3 V –0.7 ppm/°C
TC GE Gain error tempco
VA = 5 V –1 ppm/°C
OUTPUT CHARACTERISTICS
Output voltage range (2) –40°C ≤ TA ≤ 105°C 0 VREFIN V
High-impedance output
IOZ –40°C ≤ TA ≤ 105°C ±1 µA
leakage current (2)
VA = 3 V, IOUT = 200 µA 1.3 mV
VA = 3 V, IOUT = 1 mA 6 mV
ZCO Zero code output
VA = 5 V, IOUT = 200 µA 7 mV
VA = 5 V, IOUT = 1 mA 10 mV
VA = 3 V, IOUT = 200 µA 2.984 V
VA = 3 V, IOUT = 1 mA 2.934 V
FSO Full-scale output
VA = 5 V, IOUT = 200 µA 4.989 V
VA = 5 V, IOUT = 1 mA 4.958 V

(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing
Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
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Electrical Characteristics (continued)

TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
Output short-circuit current VA = 3 V, VOUT = 0 V, Input Code = FFFh –56 mA
IOS
(source) VA = 5 V, VOUT = 0 V, Input Code = FFFh –69 mA
Output short-circuit current VA = 3 V, VOUT = 3 V, Input Code = 000h 52 mA
IOS
(sink) VA = 5 V, VOUT = 5 V, Input Code = 000h 75 mA
Available on each DAC output,
IO Continuous output current (2) 11 mA
–40°C ≤ TA ≤ 105°C
RL = ∞ 1500 pF
CL Maximum load capacitance
RL = 2 kΩ 1500 pF
ZOUT DC output impedance 7.5 Ω
REFERENCE INPUT CHARACTERISTICS
TA = 25°C 0.2
Input range minimum V
VREFIN (3 –40°C ≤ TA ≤ 105°C 1
)
Input range maximum –40°C ≤ TA ≤ 105°C VA V
Input impedance 30 kΩ
LOGIC INPUT CHARACTERISTICS
IIN Input current (2) –40°C ≤ TA ≤ 105°C ±1 µA
TA = 25°C 0.9
VA = 3 V V
–40°C ≤ TA ≤ 105°C 0.6
VIL Input low voltage (2)
TA = 25°C 1.5
VA = 5 V V
–40°C ≤ TA ≤ 105°C 0.8
TA = 25°C 1.4
VA = 3 V V
–40°C ≤ TA ≤ 105°C 2.1
VIH Input high voltage (2)
TA = 25°C 2.1
VA = 5 V V
–40°C ≤ TA ≤ 105°C 2.4
CIN Input capacitance (2) –40°C ≤ TA ≤ 105°C 3 pF
POWER REQUIREMENTS
Supply voltage minimum –40°C ≤ TA ≤ 105°C 2.7 V
VA (3)
Supply voltage maximum –40°C ≤ TA ≤ 105°C 5.5 V
fSCLK = 30 MHz, TA = 25°C 360
output unloaded, µA
VA = 2.7 V to 3.6 V –40°C ≤ TA ≤ 105°C 485
fSCLK = 30 MHz, TA = 25°C 480
IN Normal supply current output unloaded, µA
VA = 4.5 V to 5.5 V –40°C ≤ TA ≤ 105°C 650
fSCLK = 0 MHz, output unloaded, VA = 2.7 V to 3.6 V 330 µA
fSCLK = 0 MHz, output unloaded, VA = 4.5 V to 5.5 V 440 µA
All PD modes, TA = 25°C 0.1
output unloaded,
SYNC = DIN = 0 V µA
after PD mode loaded, –40°C ≤ TA ≤ 105°C 1
Power-down supply VA = 2.7 V to 3.6 V
IPD
current (2) All PD modes, TA = 25°C 0.15
output unloaded,
SYNC = DIN = 0 V µA
after PD mode loaded, –40°C ≤ TA ≤ 105°C 1
VA = 4.5 V to 5.5 V

(3) To ensure accuracy, it is required that VA and VREFIN be well bypassed.

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Electrical Characteristics (continued)

TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
fSCLK = 30 MHz, TA = 25°C 1.1
output unloaded, mW
VA = 2.7 V to 3.6 V –40°C ≤ TA ≤ 105°C 1.7
fSCLK = 30 MHz, TA = 25°C 2.4
PN Normal supply power output unloaded, mW
VA = 4.5 V to 5.5 V –40°C ≤ TA ≤ 105°C 3.6

fSCLK = 0 MHz, VA = 2.7V to 3.6 V 1 mW

output unloaded VA = 4.5 V to 5.5 V 2.2 mW
All PD modes, output VA = 2.7 V to 3.6 V 0.3 3.6 µW
Power-down supply unloaded,
PPD
power (2) SYNC = DIN = 0 V VA = 4.5 V to 5.5 V 0.8 5.5 µW
after PD mode loaded

7.6 Timing Requirements

TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
TA = 25°C 40
fSCLK SCLK frequency MHz
–40°C ≤ TA ≤ 105°C 30
400h to C00h TA = 25°C 6
ts Output voltage settling time (2) code change µs
RL = 2 kΩ, CL = 200 pF –40°C ≤ TA ≤ 105°C 8.5
SR Output slew rate 1 V/µs
Glitch impulse Code change from 800h to 7FFh 12 nV-sec
Digital feedthrough 0.5 nV-sec
Digital crosstalk 1 nV-sec
DAC-to-DAC crosstalk 3 nV-sec
Multiplying bandwidth VREFIN = 2.5 V ± 0.1 Vpp 160 kHz
VREFIN = 2.5 V ± 0.1 Vpp
Total harmonic distortion 70 dB
input frequency = 10 kHz
VA = VREF = 3 V 6 µs
tWU Wake-up time
VA = VREF = 5 V 39 µs
TA = 25°C 25
1/fSCLK SCLK cycle time ns
–40°C ≤ TA ≤ 105°C 33
TA = 25°C 7
tCH SCLK high time ns
–40°C ≤ TA ≤ 105°C 10
TA = 25°C 7
tCL SCLK low time ns
–40°C ≤ TA ≤ 105°C 10
SYNC set-up time TA = 25°C 4
tSS ns
prior to SCLK falling edge –40°C ≤ TA ≤ 105°C 10
Data set-up time TA = 25°C 1.5
tDS ns
prior to SCLK falling edge –40°C ≤ TA ≤ 105°C 3.5
Data hold time TA = 25°C 1.5
tDH ns
after SCLK falling edge –40°C ≤ TA ≤ 105°C 3.5
SCLK fall TA = 25°C 0
tCFSR ns
prior to rise of SYNC –40°C ≤ TA ≤ 105°C 3

(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are ensured to AOQL (Average Outgoing
Quality Level).
(2) This parameter is ensured by design and/or characterization and is not tested in production.
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Timing Requirements (continued)

TA = 25°C, VA = 2.7 V to 5.5 V, VREFIN = VA, CL = 200 pF to GND, fSCLK = 30 MHz, and input code range 48 to 4047 (unless
otherwise noted).
PARAMETER TEST CONDITIONS MIN TYP (1) MAX UNIT
TA = 25°C 6
tSYNC SYNC high time ns
–40°C ≤ TA ≤ 105°C 10

FSE
4095 x VA
4096

GE = FSE - ZE

FSE = GE + ZE

OUTPUT
VOLTAGE

ZE

0
0 4095
DIGITAL INPUT CODE

Figure 1. Input and Output Transfer Characteristic

1 / fSCLK
|

SCLK 1 2 13 14 15 16

tSS tCL tCH

tSYNC
tCFSR

SYNC
|

tDH
| |

DIN DB15 DB0

tDS

Figure 2. Serial Timing Diagram

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7.7 Typical Characteristics

TA = 25°C, VREF = VA, fSCLK = 30 MHz, and input code range 48 to 4047 (unless otherwise noted)

Figure 3. INL at VA = 3 V Figure 4. INL at VA = 5 V

Figure 5. DNL at VA = 3 V Figure 6. DNL at VA = 5 V

Figure 7. INL/DNL vs VREFIN Figure 8. INL/DNL vs VREFIN

at VA = 3 V at VA = 5 V

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Typical Characteristics (continued)

TA = 25°C, VREF = VA, fSCLK = 30 MHz, and input code range 48 to 4047 (unless otherwise noted)

Figure 9. INL/DNL vs fSCLK Figure 10. INL/DNL vs VA

at VA = 2.7 V

Figure 11. INL/DNL vs Clock Duty Cycle Figure 12. INL/DNL vs Clock Duty Cycle
at VA = 3 V at VA = 5 V

Figure 13. INL/DNL vs Temperature Figure 14. INL/DNL vs Temperature

at VA = 3 V at VA = 5 V

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Typical Characteristics (continued)

TA = 25°C, VREF = VA, fSCLK = 30 MHz, and input code range 48 to 4047 (unless otherwise noted)

Figure 15. Zero Code Error vs VA Figure 16. Zero Code Error vs VREFIN

Figure 17. Zero Code Error vs fSCLK Figure 18. Zero Code Error vs Clock Duty Cycle

Figure 19. Zero Code Error vs Temperature Figure 20. Full-Scale Error vs VA

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Typical Characteristics (continued)

TA = 25°C, VREF = VA, fSCLK = 30 MHz, and input code range 48 to 4047 (unless otherwise noted)

Figure 21. Full-Scale Error vs VREFIN Figure 22. Full-Scale Error vs fSCLK

Figure 23. Full-Scale Error vs Clock Duty Cycle Figure 24. Full-Scale Error vs Temperature

Figure 25. Supply Current vs VA Figure 26. Supply Current vs Temperature

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Typical Characteristics (continued)

TA = 25°C, VREF = VA, fSCLK = 30 MHz, and input code range 48 to 4047 (unless otherwise noted)

Figure 27. 5-V Glitch Response Figure 28. Power-On Reset

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8 Detailed Description

8.1 Overview
The DAC124S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings followed by an output buffer.

8.2 Functional Block Diagram

VREFIN

DAC124S085

REF
POWER-ON
RESET 12 BIT DAC BUFFER VOUTA
12

2.5k 100k
REF

12 BIT DAC BUFFER VOUTB

12

DAC
REGISTER 2.5k 100k
REF

12 BIT DAC BUFFER VOUTC

12

2.5k 100k
12
REF

12 BIT DAC BUFFER VOUTD

12

2.5k 100k

INPUT POWER-DOWN
CONTROL CONTROL
LOGIC LOGIC

SYNC SCLK DIN

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8.3 Feature Description

8.3.1 DAC Section
The DAC124S085 is fabricated on a CMOS process with an architecture that consists of switches and resistor
strings that are followed by an output buffer. The reference voltage is externally applied at VREFIN and is shared
by all four DACs.
For simplicity, a single resistor string is shown in Figure 29. This string consists of 4096 equal valued resistors
with a switch at each junction of two resistors, plus a switch to ground. The code loaded into the DAC register
determines which switch is closed, connecting the proper node to the amplifier. The input coding is straight
binary with an ideal output voltage calculated with Equation 1.
VOUTA,B,C,D = VREFIN × (D / 4096)
where
• D is the decimal equivalent of the binary code that is loaded into the DAC register (1)
D can take on any value between 0 and 4095. This configuration ensures that the DAC is monotonic.
VA

R
To Output Amplifier

Figure 29. DAC Resistor String

8.3.2 Output Amplifiers

The output amplifiers are rail-to-rail, providing an output voltage range of 0 V to VA when the reference is VA. All
amplifiers, even rail-to-rail types, exhibit a loss of linearity as the output approaches the supply rails (0 V and VA,
in this case). For this reason, linearity is specified over less than the full output range of the DAC. However, if the
reference is less than VA, there is only a loss in linearity in the lowest codes. The output capabilities of the
amplifier are described in Electrical Characteristics.
The output amplifiers are capable of driving a load of 2 kΩ in parallel with 1500 pF to ground or to VA. The zero-
code and full-scale outputs for given load currents are available in Electrical Characteristics.

8.3.3 Reference Voltage

The DAC124S085 uses a single external reference that is shared by all four channels. The reference pin, VREFIN,
is not buffered and has an input impedance of 30 kΩ. TI recommends driving the VREFIN by a voltage source with
low-output impedance. The reference voltage range is 1 V to VA, providing the widest possible output dynamic
range.

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Feature Description (continued)

8.3.4 Power-On Reset
The power-on reset circuit controls the output voltages of the four DACs during power-up. Upon application of
power, the DAC registers are filled with zeros and the output voltages are 0 V. The outputs remain at 0 V until a
valid write sequence is made to the DAC.

8.4 Device Functional Modes

8.4.1 Power-Down Modes
The DAC124S085 has four power-down modes, two of which are identical. In power-down mode, the supply
current drops to 20 µA at 3 V and 30 µA at 5 V. The DAC124S085 is set in power-down mode by setting OP1
and OP0 to 11. Because this mode powers down all four DACs, the address bits, A1 and A0, are used to select
different output terminations for the DAC outputs. Setting A1 and A0 to 00 or 11 causes the outputs to be tri-
stated (a high impedance state). While setting A1 and A0 to 01 or 10 causes the outputs to be terminated by 2.5
kΩ or 100 kΩ to ground respectively (see Table 1).

Table 1. Power-Down Modes

A1 A0 OP1 OP0 OPERATING MODE
0 0 1 1 High-Z outputs
0 1 1 1 2.5 kΩ to GND
1 0 1 1 100 kΩ to GND
1 1 1 1 High-Z outputs
The bias generator, output amplifiers, resistor strings, and other linear circuitry are all shut down in any of the
power-down modes. However, the contents of the DAC registers are unaffected when in power down. Each DAC
register maintains its value prior to the ADC124S085 being powered down unless it is changed during the write
sequence which instructed it to recover from power down. Minimum power consumption is achieved in the
power-down mode with SYNC and DIN idled low and SCLK disabled. The time to exit power down (Wake-Up
Time) is typically tWU, which is stated in Timing Requirements.

8.5 Programming
8.5.1 Serial Interface
The three-wire interface is compatible with SPI, QSPI, and MICROWIRE, as well as most DSPs and operates at
clock rates up to 40 MHz. See Timing Requirements for information on a write sequence.
A write sequence begins by bringing the SYNC line low. Once SYNC is low, the data on the DIN line is clocked
into the 16-bit serial input register on the falling edges of SCLK. To avoid misclocking data into the shift register,
it is critical that SYNC not be brought low simultaneously with a falling edge of SCLK (see Figure 2). On the 16th
falling clock edge, the last data bit is clocked in and the programmed function (a change in the DAC channel
address, mode of operation, or register contents) is executed. At this point the SYNC line may be kept low or
brought high. Any data and clock pulses after the 16th falling clock edge are ignored. In either case, SYNC must
be brought high for the minimum specified time before the next write sequence is initiated with a falling edge of
SYNC.
Because the SYNC and DIN buffers draw more current when they are high, they must be idled low between write
sequences to minimize power consumption.

8.5.2 Input Shift Register

The input shift register, Figure 30, has sixteen bits. The first two bits are address bits. They determine whether
the register data is for DAC A, DAC B, DAC C, or DAC D. The address bits are followed by two bits that
determine the mode of operation (writing to a DAC register without updating the outputs of all four DACs, writing
to a DAC register and updating the outputs of all four DACs, writing to the register of all four DACs and updating
their outputs, or powering down all four outputs). The final twelve bits of the shift register are the data bits. The
data format is straight binary (MSB first, LSB last), with all 0s corresponding to an output of 0 V and all 1s
corresponding to a full-scale output of VREFIN – 1 LSB. The contents of the serial input register are transferred to
the DAC register on the sixteenth falling edge of SCLK (see Figure 2).

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Programming (continued)

MSB LSB
A1 A0 OP1 OP0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0

DATA BITS

0 0 DAC A 0 0 Write to specified register but do not update outputs.

0 1 DAC B 0 1 Write to specified register and update outputs.
1 0 DAC C 1 0 Write to all registers and update outputs.
1 1 DAC D 1 1 Power-down outputs.

Figure 30. Input Register Contents

Normally, the SYNC line is kept low for at least 16 falling edges of SCLK and the DAC is updated on the 16th
SCLK falling edge. However, if SYNC is brought high before the 16th falling edge, the data transfer to the shift
register is aborted and the write sequence is invalid. Under this condition, the DAC register is not updated and
there is no change in the mode of operation or in the DAC output voltages.

8.5.3 DSP or Microprocessor Interfacing

Interfacing the DAC124S085 to microprocessors and DSPs is quite simple. The following guidelines are offered
to hasten the design process.

8.5.3.1 ADSP-2101 or ADSP2103 Interfacing

Figure 31 shows a serial interface between the DAC124S085 and the ADSP-2101/ADSP2103. The DSP must be
set to operate in the SPORT Transmit Alternate Framing Mode. It is programmed through the SPORT control
register and must be configured for Internal Clock Operation, Active-Low Framing and 16-bit Word Length.
Transmission is started by writing a word to the Tx register after the SPORT mode has been enabled.

ADSP-2101/ DAC124S085
ADSP2103
TFS SYNC

DT DIN

SCLK SCLK

Figure 31. ADSP-2101/2103 Interface

8.5.3.2 80C51 or 80L51 Interface

A serial interface between the DAC124S085 and the 80C51/80L51 microcontroller is shown in Figure 32. The
SYNC signal comes from a bit-programmable pin on the microcontroller. The example shown here uses port line
P3.3. This line is taken low when data is transmitted to the DAC124S085. Because the 80C51/80L51 transmits 8-
bit bytes, only eight falling clock edges occur in the transmit cycle. To load data into the DAC, the P3.3 line must
be left low after the first eight bits are transmitted. A second write cycle is initiated to transmit the second byte of
data, after which port line P3.3 is brought high. The 80C51/80L51 transmit routine must recognize that the
80C51/80L51 transmits data with the LSB first while the DAC124S085 requires data with the MSB first.

80C51/80L51 DAC124S085
P3.3 SYNC
TXD SCLK

RXD DIN

Figure 32. 80C51/80L51 Interface

8.5.3.3 68HC11 Interface

A serial interface between the DAC124S085 and the 68HC11 microcontroller is shown in Figure 33. The SYNC
line of the DAC124S085 is driven from a port line (PC7 in the figure), similar to the 80C51/80L51.

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Programming (continued)
The 68HC11 must be configured with its CPOL bit as a zero and its CPHA bit as a one. This configuration
causes data on the MOSI output to be valid on the falling edge of SCLK. PC7 is taken low to transmit data to the
DAC. The 68HC11 transmits data in 8-bit bytes with eight falling clock edges. Data is transmitted with the MSB
first. PC7 must remain low after the first eight bits are transferred. A second write cycle is initiated to transmit the
second byte of data to the DAC, after which PC7 must be raised to end the write sequence.

68HC11 DAC124S085
PC7 SYNC
SCK SCLK

MOSI DIN

Figure 33. 68HC11 Interface

8.5.4 Microwire Interface

Figure 34 shows an interface between a Microwire compatible device and the DAC124S085. Data is clocked out
on the rising edges of the SK signal. As a result, the SK of the Microwire device must be inverted before driving
the SCLK of the DAC124S085.

MICROWIRE DAC124S085
DEVICE
CS SYNC
SK SCLK

SO DIN

Figure 34. Microwire Interface

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9 Application and Implementation

NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.

9.1 Application Information

Figure 35 is an example of the DAC124S085 in a typical application. This circuit is basic and generally requires
modification for specific circumstances.

9.2 Typical Application

9.2.1 Bipolar Operation
The DAC124S085 is designed for single-supply operation and thus has a unipolar output. However, a bipolar
output may be obtained with the circuit in Figure 35. This circuit provides an output voltage range of ±5 V. A rail-
to-rail amplifier must be used if the amplifier supplies are limited to ±5 V.
10 pF

R2

+5V
+5V R1
+ -
10 PF 0.1 PF ±5V
+
DAC124S085
-5V
SYNC
VOUT
DIN

SCLK
Copyright © 2016, Texas Instruments Incorporated

Figure 35. Bipolar Operation

9.2.1.1 Design Requirements

• The DAC124S085 uses a single supply.
• The output is required to be bipolar with a voltage range of ±5 V.
• Dual supplies are used for the output amplifier.

9.2.1.2 Detailed Design Procedure

The output voltage of this circuit for any code is found with Equation 2.
VO = (VA × (D / 4096) × ((R1 + R2) / R1) – VA × R2 / R1
where
• D is the input code in decimal form (2)
Equation 3 is calculated with VA = 5 V and R1 = R2.
VO = (10 × D / 4096) – 5 V (3)
A list of rail-to-rail amplifiers suitable for this application are indicated in Table 2.

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Table 2. Some Rail-to-Rail Amplifiers

AMP PKGS VOS (TYP) ISUPPLY (TYP)
DIP-8
LMC7111 0.9 mV 25 µA
SOT23-5
SO-8
LM7301 0.03 mV 620 µA
SOT23-5
LM8261 SOT23-5 0.7 mV 1 mA

9.2.1.3 Application Curve

5V

OUTPUT
VOLTAGE

-5V
0 4095
DIGITAL INPUT CODE

Figure 36. Bipolar Input and Output Transfer Characteristic

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10 Power Supply Recommendations

10.1 Using References as Power Supplies

While the simplicity of the DAC124S085 implies ease of use, it is important to recognize that the path from the
reference input (VREFIN) to the VOUTs has essentially zero Power Supply Rejection Ratio (PSRR). Therefore, it is
necessary to provide a noise-free supply voltage to VREFIN. To use the full dynamic range of the DAC124S085,
the supply pin (VA) and VREFIN can be connected together and share the same supply voltage. Because the
DAC124S085 consumes very little power, a reference source may be used as the reference input or the supply
voltage. The advantages of using a reference source over a voltage regulator are accuracy and stability. Some
low noise regulators can also be used. Listed below are a few reference and power supply options for the
DAC124S085.

10.1.1 LM4132
The LM4132, with its 0.05% accuracy over temperature, is a good choice as a reference source for the
DAC124S085. The 4.096-V version is useful if a 0-V to 4.095-V output range is desirable or acceptable.
Bypassing the LM4132 VIN pin with a 0.1-µF capacitor and the VOUT pin with a 2.2-µF capacitor improves
stability and reduce output noise. The LM4132 comes in a space-saving 5-pin SOT23.
Input LM4132-4.1
Voltage
C1 C2 C3
0.1 PF 2.2 PF 0.1 PF

VA VREFIN
DAC124S085
VOUT = 0V to 4.092V
SYNC

DIN

SCLK

Figure 37. LM4132 Power Supply

10.1.2 LM4050
Available with accuracy of 0.44%, the LM4050 shunt reference is also a good choice as a reference for the
DAC124S085. It is available in 4.096-V and 5-V versions and comes in a space-saving 3-pin SOT23.
Input
Voltage

R
IDAC
VZ

IZ
0.47 PF 0.1 PF

LM4050-4.1 VA VREFIN
or
LM4050-5.0 DAC124S085
VOUT = 0V to 5V
SYNC

DIN

SCLK

Figure 38. LM4050 Power Supply

The minimum resistor value in the circuit of Figure 38 must be chosen such that the maximum current through
the LM4050 does not exceed its 15-mA rating. The conditions for maximum current include the input voltage at
its maximum, the LM4050 voltage at its minimum, and the DAC124S085 drawing zero current. The maximum
resistor value must allow the LM4050 to draw more than its minimum current for regulation plus the maximum
DAC124S085 current in full operation. The conditions for minimum current include the input voltage at its
minimum, the LM4050 voltage at its maximum, the resistor value at its maximum due to tolerance, and the
DAC124S085 draws its maximum current. These conditions can be summarized with Equation 4 and Equation 5.
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Using References as Power Supplies (continued)

R(min) = (VIN(max) – VZ(min)) / IZ(max) (4)
and
R(max) = (VIN(min) – VZ(max)) / ((IDAC(max) + IZ(min))
where
• VZ(min) and VZ(max) are the nominal LM4050 output voltages ± the LM4050 output tolerance over
temperature
• IZ(max) is the maximum allowable current through the LM4050
• IZ(min) is the minimum current required by the LM4050 for proper regulation
• IDAC(max) is the maximum DAC124S085 supply current (5)

10.1.3 LP3985
The LP3985 is a low-noise, ultra-low dropout voltage regulator with a 3% accuracy over temperature. It is a good
choice for applications that do not require a precision reference for the DAC124S085. It comes in 3.0-V, 3.3-V,
and 5-V versions, among others, and sports a low 30-µV noise specification at low frequencies. Because low
frequency noise is relatively difficult to filter, this specification could be important for some applications. The
LP3985 comes in a space-saving 5-pin SOT-23 and 5-bump DSBGA packages.
Input LP3985
Voltage
1 PF 0.1 PF 0.1 PF
0.01 PF VA VREFIN

DAC124S085
VOUT = 0V to 5V
SYNC

DIN

SCLK

Figure 39. LP3985 Regulator

An input capacitance of 1 µF without any ESR requirement is required at the LP3985 input, while a 1-µF ceramic
capacitor with an ESR requirement of 5 mΩ to 500 mΩ is required at the output. Careful interpretation and
understanding of the capacitor specification is required to ensure correct device operation.

10.1.4 LP2980
The LP2980 is an ultra-low dropout regulator with a 0.5% or 1.0% accuracy over temperature, depending upon
grade. It is available in 3.0-V, 3.3-V, and 5-V versions, among others.
Input VIN VOUT
Voltage LP2980

ON /OFF 1 PF 0.1 PF

VA VREFIN

DAC124S085
VOUT = 0V to 5V
SYNC

DIN

SCLK

Figure 40. LP2980 Regulator

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Using References as Power Supplies (continued)

Like any low dropout regulator, the LP2980 requires an output capacitor for loop stability. This output capacitor
must be at least 1 µF over temperature, but values of 2.2 µF or more provides even better performance. The
ESR of this capacitor must be within the range specified in the LP2980 data sheet. Surface-mount solid tantalum
capacitors offer a good combination of small size and ESR. Ceramic capacitors are attractive due to their small
size but generally have ESR values that are too low for use with the LP2980. Aluminum electrolytic capacitors
are typically not a good choice due to their large size and have ESR values that may be too high at low
temperatures.

11 Layout

11.1 Layout Guidelines

For best accuracy and minimum noise, the printed-circuit board containing the DAC124S085 must have separate
analog and digital areas. The areas are defined by the locations of the analog and digital power planes. Both of
these planes must be placed in the same board layer. There must be a single ground plane. A single ground
plane is preferred if digital return current does not flow through the analog ground area. Frequently a single
ground plane design uses a fencing technique to prevent the mixing of analog and digital ground current.
Separate ground planes must only be used when the fencing technique is inadequate. The separate ground
planes must be connected in one place, preferably near the DAC124S085. Take special care to ensure that
digital signals with fast edge rates do not pass over split ground planes. They must always have a continuous
return path below their traces.
The DAC124S085 power supply must be bypassed with a 10-µF and a 0.1-µF capacitor as close as possible to
the device with the 0.1 µF right at the device supply pin. The 10-µF capacitor must be a tantalum type and the
0.1-µF capacitor must be a low ESL, low ESR type. The power supply for the DAC124S085 must only be used
for analog circuits.
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the
board. The clock and data lines must have controlled impedances.

11.2 Layout Example

Figure 41. DAC124S085 Layout Example

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12 Device and Documentation Support

12.1 Device Support

12.1.1 Device Nomenclature
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of
1 LSB, which is VREF / 4096 = VA / 4096.
DAC-to-DAC CROSSTALK is the glitch impulse transferred to a DAC output in response to a full-scale change
in the output of another DAC.
DIGITAL CROSSTALK is the glitch impulse transferred to a DAC output at mid-scale in response to a full-scale
change in the input register of another DAC.
DIGITAL FEEDTHROUGH is a measure of the energy injected into the analog output of the DAC from the digital
inputs when the DAC outputs are not updated. It is measured with a full-scale code change on the data bus.
FULL-SCALE ERROR is the difference between the actual output voltage with a full scale code (FFFh) loaded
into the DAC and the value of VA × 4095 / 4096.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It can be calculated from Zero and
Full-Scale Errors as GE = FSE – ZE, where GE is Gain error, FSE is Full-Scale Error and ZE is Zero Error.
GLITCH IMPULSE is the energy injected into the analog output when the input code to the DAC register
changes. It is specified as the area of the glitch in nanovolt-seconds.
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a straight line
through the input to output transfer function. The deviation of any given code from this straight line is measured
from the center of that code value. The end point method is used. INL for this product is specified over a limited
range, per Electrical Characteristics.
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is
LSB = VREF / 2n
where
• VREF is the supply voltage for this product
• "n" is the DAC resolution in bits, which is 12 for the DAC124S085 (6)
MAXIMUM LOAD CAPACITANCE is the maximum capacitance that can be driven by the DAC with output
stability maintained.
MONOTONICITY is the condition of being monotonic, where the DAC has an output that never decreases when
the input code increases.
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is
1/2 of VA.
MULTIPLYING BANDWIDTH is the frequency at which the output amplitude falls 3 dB below the input sine wave
on VREFIN with a full-scale code loaded into the DAC.
POWER EFFICIENCY is the ratio of the output current to the total supply current. The output current comes from
the power supply. The difference between the supply and output currents is the power consumed by the device
without a load.
SETTLING TIME is the time for the output to settle to within 1/2 LSB of the final value after the input code is
updated.
TOTAL HARMONIC DISTORTION (THD) is the measure of the harmonics present at the output of the DACs
with an ideal sine wave applied to VREFIN. THD is measured in dB.
WAKE-UP TIME is the time for the output to exit power-down mode. This is the time from the falling edge of the
16th SCLK pulse to when the output voltage deviates from the power-down voltage of 0 V.
ZERO CODE ERROR is the output error, or voltage, present at the DAC output after a code of 000h has been
entered.

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12.2 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.

12.3 Trademarks
E2E is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
12.4 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.

12.5 Glossary
SLYZ022 — TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.

13 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

Copyright © 2006–2016, Texas Instruments Incorporated Submit Documentation Feedback 25

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PACKAGING INFORMATION

Orderable Device Status Package Type Package Pins Package Eco Plan Lead finish/ MSL Peak Temp Op Temp (°C) Device Marking Samples
(1) Drawing Qty (2) Ball material (3) (4/5)
(6)

DAC124S085CIMM LIFEBUY VSSOP DGS 10 1000 Non-RoHS Call TI Level-1-260C-UNLIM -40 to 105 X66C
& Green
DAC124S085CIMM/NOPB ACTIVE VSSOP DGS 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X66C Samples

DAC124S085CIMMX/NOPB ACTIVE VSSOP DGS 10 3500 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X66C Samples

DAC124S085CISD/NOPB ACTIVE WSON DSC 10 1000 RoHS & Green SN Level-1-260C-UNLIM -40 to 105 X67C Samples

(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.

(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.

(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.

(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

Addendum-Page 1
 PACKAGE OPTION ADDENDUM

www.ti.com 2-Jul-2024

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

Addendum-Page 2
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL INFORMATION

REEL DIMENSIONS TAPE DIMENSIONS

K0 P1

B0 W
Reel
Diameter
Cavity A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
W Overall width of the carrier tape
P1 Pitch between successive cavity centers

Reel Width (W1)

QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE

Sprocket Holes

Q1 Q2 Q1 Q2

Q3 Q4 Q3 Q4 User Direction of Feed

Pocket Quadrants

*All dimensions are nominal

Device Package Package Pins SPQ Reel Reel A0 B0 K0 P1 W Pin1
Type Drawing Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
DAC124S085CIMM VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
DAC124S085CIMM/NOPB VSSOP DGS 10 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
DAC124S085CIMMX/ VSSOP DGS 10 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
NOPB
DAC124S085CISD/NOPB WSON DSC 10 1000 178.0 12.4 3.3 3.3 1.0 8.0 12.0 Q1

Pack Materials-Page 1
 PACKAGE MATERIALS INFORMATION

www.ti.com 9-Aug-2022

TAPE AND REEL BOX DIMENSIONS

Width (mm)
H
W

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
DAC124S085CIMM VSSOP DGS 10 1000 210.0 185.0 35.0
DAC124S085CIMM/NOPB VSSOP DGS 10 1000 210.0 185.0 35.0
DAC124S085CIMMX/ VSSOP DGS 10 3500 367.0 367.0 35.0
NOPB
DAC124S085CISD/NOPB WSON DSC 10 1000 210.0 185.0 35.0

Pack Materials-Page 2
 PACKAGE OUTLINE
DGS0010A SCALE 3.200
VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

C
5.05
TYP SEATING PLANE
4.75

A PIN 1 ID 0.1 C
AREA

8X 0.5
10
1

3.1
2.9 2X
NOTE 3 2

5
6
0.27
10X
0.17
3.1 0.1 C A B 1.1 MAX
B
2.9
NOTE 4

0.23
TYP
SEE DETAIL A 0.13

0.25
GAGE PLANE

0.7 0.15
0 -8 0.05
0.4

DETAIL A
TYPICAL

4221984/A 05/2015

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed 0.15 mm per side.
4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side.
5. Reference JEDEC registration MO-187, variation BA.

www.ti.com
 EXAMPLE BOARD LAYOUT
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
10X (0.3) SYMM (R0.05)
1 TYP
10

SYMM

8X (0.5) 5 6

(4.4)

LAND PATTERN EXAMPLE

SCALE:10X

SOLDER MASK METAL UNDER SOLDER MASK

METAL OPENING
OPENING SOLDER MASK

0.05 MAX 0.05 MIN

ALL AROUND ALL AROUND

NON SOLDER MASK SOLDER MASK

DEFINED DEFINED

SOLDER MASK DETAILS

NOT TO SCALE

4221984/A 05/2015
NOTES: (continued)

6. Publication IPC-7351 may have alternate designs.

7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.

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 EXAMPLE STENCIL DESIGN
DGS0010A VSSOP - 1.1 mm max height
SMALL OUTLINE PACKAGE

10X (1.45)
SYMM (R0.05) TYP
10X (0.3)
1
10

SYMM
8X (0.5)

5 6

(4.4)

SOLDER PASTE EXAMPLE

BASED ON 0.125 mm THICK STENCIL
SCALE:10X

4221984/A 05/2015
NOTES: (continued)

8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.

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