ESP8684 Series

Datasheet

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Ultra­Low­Power SoC with RISC­V Single­Core CPU
Supporting IEEE 802.11b/g/n (2.4 GHz Wi­Fi) and Bluetooth 5 (LE)

Including:
ESP8684H1

ESP8684H2

ESP8684H4
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Pre-release v0.4
Espressif Systems
Copyright © 2022

www.espressif.com
Product Overview

ESP8684 series of SoCs is an ultra-low-power and highly-integrated MCU-based SoC solution that supports 2.4
GHz Wi-Fi and Bluetooth® Low Energy (Bluetooth LE). The block diagram of ESP8684 series is shown
below.

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Espressif’s ESP8684 Wi-Fi + Bluetooth® Low Energy SoC

Core System Wireless MAC and RF

Baseband
2.4 GHz Balun + Switch
RISC-V

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32-bit Wi-Fi
Wi-Fi MAC
Microprocessor Baseband

2.4 GHz Receiver

RF Synthesizer
Transmitter
2.4 GHz
Bluetooth LE Link
Cache SRAM Controller

Bluetooth LE
JTAG ROM Baseband

Peripherals RTC

SPI0/1 I2C Master GPIO RTC GPIO PMU

SPI2

SiP Flash

Temperature Sensor
GDMA IN
UART

DIG ADC
Controller

RTC Super Watchdog Timer

RTC
Watchdog
Timer
RNG

Secure
Security

ECC

SHA
Boot
eFuse
Brownout
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Main System Watchdog Timer
Controller Flash Encryption

General-purpose Timer System Timer LED PWM

Modules having power in specific power modes:

Active
Active, Modem-sleep, and Light-sleep;
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All modes

Figure 1: Block diagram of ESP8684

Solution Highlights
• A complete Wi­Fi subsystem that complies • Storage capacity ensured by 272 KB of SRAM
with IEEE 802.11b/g/n protocol and supports (16 KB for cache) and 576 KB of ROM on the
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Station mode, SoftAP mode, SoftAP + Station chip.

mode, and promiscuous mode
• Reliable security features ensured by
• A Bluetooth LE subsystem that supports – Cryptographic hardware accelerators that
features of Bluetooth 5, multiple connections and support ECC, Hash and secure boot
advertising extensions.
– Random number generator
• State­of­the­art power and RF performance
– External memory encryption and decryption
• 32­bit RISC­V single­core processor with a
• Rich set of peripheral interfaces and GPIOs,
four-stage pipeline that operates at up to 120
ideal for various scenarios and complex
MHz
applications

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Features

Wi­Fi – 1 core at 120 MHz: 305.42 CoreMark; 2.55

CoreMark/MHz
• IEEE 802.11 b/g/n-compliant
• 576 KB ROM
• Supports 20 MHz bandwidth in 2.4 GHz band
• 272 KB SRAM (16 KB for cache)

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• 1T1R mode with data rate up to 72.2 Mbps
• SiP flash (see details in Chapter 1 ESP8684
• Wi-Fi Multimedia (WMM) Series Comparison)
• TX/RX A-MPDU, TX/RX A-MSDU • Access to flash accelerated by cache

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• Immediate Block ACK • Supports flash in-Circuit Programming (ICP)
• Fragmentation and defragmentation

• Transmit opportunity (TXOP)

Advanced Peripheral Interfaces

• Automatic Beacon monitoring (hardware TSF) • 14 × programmable GPIOs

• 3 × virtual Wi-Fi interfaces • Digital interfaces:

mode, and promiscuous mode

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• Simultaneous support for Infrastructure BSS in
Station mode, SoftAP mode, Station + SoftAP

Note that when ESP8684 series scans in Station

– 3 × SPI

– 2 × UART

– 1 × I2C Master
mode, the SoftAP channel will change along with – LED PWM controller, with up to 6 channels
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the Station channel
– General DMA controller (GDMA), with 1
• Antenna diversity transmit channel and 1 receive channel
• Supports external power amplifier • Analog interfaces:

– 1 × 12-bit SAR ADC, up to 5 channels

Bluetooth
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– 1 × temperature sensor
• Bluetooth LE: Bluetooth 5
• Timers:
• High power mode�20 dBm�
– 1 × 54-bit general-purpose timer
• Speed: 125 kbps, 500 kbps, 1 Mbps, 2 Mbps
– 2 × watchdog timers
• Advertising extensions
– 1 × 52-bit system timer
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• Multiple advertisement sets

• Channel selection algorithm #2 Low Power Management

• Internal co-existence mechanism between Wi-Fi
• Power Management Unit with four power modes
and Bluetooth to share the same antenna

Security
CPU and Memory
• Secure boot
• 32-bit RISC-V single-core processor, up to 120
MHz • Flash encryption

• CoreMark® score: • 1024-bit OTP, up to 256 bits for use

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 • Cryptographic hardware acceleration: – SHA Accelerator (FIPS PUB 180-4)

– ECC • Random Number Generator (RNG)

Applications (A Non­exhaustive List)

With ultra-low power consumption, ESP8684 is an ideal choice for IoT devices in the following areas:

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• Smart Home • Health Care

– Light control – Health monitor

– Smart button – Baby monitor

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– Smart plug • Smart Agriculture

– Indoor positioning – Smart greenhouse

• Industrial Automation – Smart irrigation

– Industrial robot – Agriculture robot

– Industrial field bus • Retail and Catering

• Consumer Electronics

– Smart watch and bracelet

– Over-the-top (OTT) devices

IN – POS machines

– Service robot

• Generic Low-power IoT Sensor Hubs

– Logger toys and proximity sensing toys • Generic Low-power IoT Data Loggers
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Contents

Contents

Product Overview 1
Solution Highlights 1
Features 2
Applications 3

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1 ESP8684 Series Comparison 8
1.1 ESP8684 Series Nomenclature 8

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1.2 Comparison 8

2 Pin Definition 9
2.1 Pin Layout 9
2.2 Pin Description 9
2.3 Power Scheme 10
2.4 Strapping Pins 12

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3.1
Functional Description
Radio and Wi-Fi
3.1.1
3.1.2
2.4 GHz Receiver
2.4 GHz Transmitter
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3.1.3 Clock Generator 14
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3.1.4 Wi-Fi Radio and Baseband 15
3.1.5 Wi-Fi MAC 15
3.1.6 Networking Features 15
3.2 Bluetooth LE 15
3.2.1 Bluetooth LE Radio and PHY 16
3.2.2 Bluetooth LE Link Layer Controller 16
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3.3 CPU and Memory 16

3.3.1 CPU 16
3.3.2 Internal Memory 17
3.3.3 Address Mapping Structure 17
3.3.4 Cache 17
3.4 System Clocks 18
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3.4.1 CPU Clock 18

3.4.2 RTC Clock 18
3.5 Digital Peripherals 18
3.5.1 General Purpose Input / Output Interface (GPIO) 18
3.5.2 Serial Peripheral Interface (SPI) 19
3.5.3 Universal Asynchronous Receiver Transmitter (UART) 20
3.5.4 I2C Interface 20
3.5.5 LED PWM Controller 20
3.5.6 General DMA Controller 20
3.6 Analog Peripherals 21
3.6.1 Analog-to-Digital Converter (ADC) 21

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Contents

3.6.2 Temperature Sensor 21

3.7 Timers 21
3.7.1 General Purpose Timer 21
3.7.2 System Timer 21
3.7.3 Watchdog Timers 22
3.8 Low Power Management 22
3.9 Cryptographic Hardware Accelerators 22

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3.10 Physical Security Features 22
3.11 Peripheral Pin Configurations 23

4 Electrical Characteristics 24

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4.1 Absolute Maximum Ratings 24
4.2 Recommended Operating Conditions 24
4.3 DC Characteristics (3.3 V, 25 °C) 24
4.4 ADC Characteristics 25
4.5 Current Consumption 25
4.6 Wi-Fi Radio 26
4.6.1 Wi-Fi RF Transmitter (TX) Specifications 26

4.7
4.6.2
Bluetooth LE Radio
4.7.1
4.7.2
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Wi-Fi RF Receiver (RX) Specifications

Bluetooth LE RF Transmitter (TX) Specifications

Bluetooth LE RF Receiver (RX) Specifications
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5 Package Information 32
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Revision History 33

Solutions, Documentation and Legal Information 34

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List of Tables

List of Tables
1 ESP8684 Series Member Comparison 8
2 Pin Description 9
3 Description of ESP8684 Series Power-up and Reset Timing Parameters 12
4 Strapping Pins 12
5 Parameter Descriptions of Setup and Hold Times for the Strapping Pins 13

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6 IO MUX Pin Functions 19
7 Peripheral Pin Configurations 23
8 Absolute Maximum Ratings 24

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9 Recommended Operating Conditions 24
10 DC Characteristics (3.3 V, 25 °C) 24
11 ADC Characteristics 25
12 Current Consumption Depending on RF Modes 25
13 Current Consumption Depending on Work Modes (except Modem-sleep) 26
14 Current Consumption in Modem-sleep Mode 26
15 Wi-Fi Frequency 26
16 TX Power with Spectral Mask and EVM Meeting 802.11 Standards 26
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TX EVM Test
RX Sensitivity
Maximum RX Level
RX Adjacent Channel Rejection
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21 Bluetooth LE Frequency 28
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22 Transmitter Characteristics - Bluetooth LE 1 Mbps 28
23 Transmitter Characteristics - Bluetooth LE 2 Mbps 28
24 Transmitter Characteristics - Bluetooth LE 125 Kbps 29
25 Transmitter Characteristics - Bluetooth LE 500 Kbps 29
26 Receiver Characteristics - Bluetooth LE 1 Mbps 29
27 Receiver Characteristics - Bluetooth LE 2 Mbps 30
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28 Receiver Characteristics - Bluetooth LE 125 Kbps 31

29 Receiver Characteristics - Bluetooth LE 500 Kbps 31
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List of Figures

List of Figures
1 Block diagram of ESP8684 1
2 ESP8684 Series Nomenclature 8
3 ESP8684 Pin Layout (Top View) 9
4 ESP8684 Series Power Scheme 11
5 ESP8684 Series Power-up and Reset Timing 11

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6 Setup and Hold Times for the Strapping Pins 13
7 Address Mapping Structure 17
8 QFN56 (7×7 mm) Package 32

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1 ESP8684 Series Comparison

1 ESP8684 Series Comparison

1.1 ESP8684 Series Nomenclature

ESP8684 H x

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Flash

Flash temperature
H: High temperature
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Figure 2: ESP8684 Series Nomenclature

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1.2 Comparison

Table 1: ESP8684 Series Member Comparison

Ordering Code SiP Flash Ambient Temperature (°C) Package (mm)

ESP8684H1 1 MB –40 ∼ 105 QFN24 (4*4)
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ESP8684H2 2 MB –40 ∼ 105 QFN24 (4*4)

ESP8684H4 4 MB –40 ∼ 105 QFN24 (4*4)
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2 Pin Definition

2 Pin Definition

2.1 Pin Layout

22 XTAL_N
23 XTAL_P

19 U0RXD
20 U0TXD
24 VDDA

21 VDDA

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ANT 1 18 GPIO18

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VDDA3P3 2 17 VDD3P3_CPU

VDDA3P3 3 16 GPIO10

GPIO0 4 15 GPIO9

ESP8684
GPIO1

GPIO2
5

6
IN MTDI 10

25 GND
VDD3P3_RTC 11

MTCK 12
14 GPIO8

13 MTDO
7

9
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CHIP_EN

GPIO3

MTMS

Figure 3: ESP8684 Pin Layout (Top View)

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2.2 Pin Description

Table 2: Pin Description

Name No. Type Power Domain Function

ANT 1 I/O — RF input and output
VDDA3P3 2 PA — Analog power supply
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VDDA3P3 3 PA — Analog power supply

GPIO0 4 I/O/T VDD3P3_RTC GPIO0, ADC1_CH0
GPIO1 5 I/O/T VDD3P3_RTC GPIO1, ADC1_CH1
GPIO2 6 I/O/T VDD3P3_RTC GPIO2, ADC1_CH2, FSPIQ
High: on, enables the chip.
CHIP_EN 7 I VDD3P3_RTC Low: off, the chip powers off.
Note: Do not leave the CHIP_EN pin floating.
GPIO3 8 I/O/T VDD3P3_RTC GPIO3, ADC1_CH3
MTMS 9 I/O/T VDD3P3_RTC MTMS, GPIO4, ADC1_CH4, FSPIHD
MTDI 10 I/O/T VDD3P3_RTC MTDI, GPIO5, FSPIWP

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2 Pin Definition

Name No. Type Power Domain Function

VDD3P3_RTC 11 PD — Input power supply for RTC
MTCK 12 I/O/T VDD3P3_CPU MTCK, GPIO6, FSPICLK
MTDO 13 I/O/T VDD3P3_CPU MTDO, GPIO7, FSPID
GPIO8 14 I/O/T VDD3P3_CPU GPIO8
GPIO9 15 I/O/T VDD3P3_CPU GPIO9
GPIO10 16 I/O/T VDD3P3_CPU GPIO10, FSPICS0

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VDD3P3_CPU 17 PD — Input power supply for digital IO
GPIO18 18 I/O/T VDD3P3_CPU GPIO18
U0RXD 19 I/O/T VDD3P3_CPU U0RXD, GPIO19

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U0TXD 20 I/O/T VDD3P3_CPU U0TXD, GPIO20
VDDA 21 PA — Analog power supply
XTAL_N 22 — — External crystal output
XTAL_P 23 — — External crystal input
VDDA 24 PA — Analog power supply
GND 25 G — Ground
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PA : analog power supply; PD : power supply for digital IO; I: input; O: output; T: high impedance.
2

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Pin functions in bold font are the default pin functions.
The pin function in this table refers only to some fixed settings and do not cover all cases for signals
that can be input and output through the GPIO matrix.

2.3 Power Scheme

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Digital pins of ESP8684 are divided into two different power domains:

• VDD3P3_CPU

• VDD3P3_RTC

VDD3P3_CPU is the input power supply for digital IO and digital system.
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VDD3P3_RTC is the input power supply for RTC, RTC IO, and digital system.

The power scheme diagram is shown in Figure 4.

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2 Pin Definition

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IN
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Figure 4: ESP8684 Series Power Scheme

Notes on CHIP_EN:

Figure 5 shows the power-up and reset timing of ESP8684 series. Details about the parameters are listed in
Table 3.
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t0 t1

2.8 V

VDDA,
VDDA3P3,
VDD3P3_RTC,
VDD3P3_CPU
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VIL_nRST
CHIP_EN

Figure 5: ESP8684 Series Power­up and Reset Timing

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2 Pin Definition

Table 3: Description of ESP8684 Series Power­up and Reset Timing Parameters

Min
Parameter Description (µs)
Time between bringing up the VDDA, VDDA3P3, VDD3P3_RTC, and
t0 50
VDD3P3_CPU rails, and activating CHIP_EN
Duration of CHIP_EN signal level < VIL_nRST (refer to its value in
t1 50

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Table 10) to reset the chip

2.4 Strapping Pins

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ESP8684 series has two strapping pins:

• GPIO8

• GPIO9

Software can read the values of GPIO8 and GPIO9 from GPIO_STRAPPING field in GPIO_STRAP_REG
register.

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During the chip’s power-on reset, RTC watchdog reset, and brownout reset, the latches of the strapping pins
sample the voltage level as strapping bits of ”0” or ”1”, and hold these bits until the chip is powered down or shut
down.

By default, GPIO9 is connected to the internal weak pull-up resistor. If GPIO9 is not connected or connected to
an external high-impedance circuit, the latched bit value will be ”1”
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To change the strapping bit values, you can apply the external pull-down/pull-up resistances, or use the host
MCU’s GPIOs to control the voltage level of these pins when powering on ESP8684.

After reset, the strapping pins work as normal-function pins.

Table 4 lists detailed booting configurations of the strapping pins.

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Table 4: Strapping Pins

Booting Mode 1
Pin Default SPI Boot Download Boot
GPIO8 N/A Don’t care 1
Internal weak
GPIO9 1 0
pull-up
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Enabling/Disabling ROM Messages Print During Booting

Pin Default Functionality
When the value of eFuse field EFUSE_UART_PRINT_CONTROL is
0 (default), print is enabled and not controlled by GPIO8.
GPIO8 N/A 1, if GPIO8 is 0, print is enabled; if GPIO8 is 1, it is disabled.
2, if GPIO8 is 0, print is disabled; if GPIO8 is 1, it is enabled.
3, print is disabled and not controlled by GPIO8.
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The strapping combination of GPIO8 = 0 and GPIO9 = 0 is invalid and will trigger unexpected be-
havior.

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2 Pin Definition

Figure 6 shows the setup and hold times for the strapping pins before and after the CHIP_EN signal goes high.
Details about the parameters are listed in Table 5.

t0 t1

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VIL_nRST
CHIP_EN

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VIH

Strapping pin

Figure 6: Setup and Hold Times for the Strapping Pins

Parameter
t0
Description
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Table 5: Parameter Descriptions of Setup and Hold Times for the Strapping Pins

Setup time before CHIP_EN goes from low to high

Min
(ms)
0
t1 Hold time after CHIP_EN goes high 3
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3 Functional Description

3 Functional Description
This chapter describes the functions of ESP8684.

3.1 Radio and Wi­Fi

The ESP8684 series radio consists of the following blocks:

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• 2.4 GHz receiver

• 2.4 GHz transmitter

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• bias and regulators

• balun and transmit-receive switch

• clock generator

3.1.1 2.4 GHz Receiver

The 2.4 GHz receiver demodulates the 2.4 GHz RF signal to quadrature baseband signals and converts them to

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the digital domain with two high-resolution, high-speed ADCs. To adapt to varying signal channel conditions,
ESP8684 series integrates RF filters, Automatic Gain Control (AGC), DC offset cancelation circuits, and
baseband filters.

3.1.2 2.4 GHz Transmitter

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The 2.4 GHz transmitter modulates the quadrature baseband signals to the 2.4 GHz RF signal, and drives the
antenna with a high-powered CMOS power amplifier. The use of digital calibration further improves the linearity of
the power amplifier.

Additional calibrations are integrated to cancel any radio imperfections, such as:

• carrier leakage
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• I/Q amplitude/phase matching

• baseband nonlinearities

• RF nonlinearities

• antenna matching

These built-in calibration routines reduce the cost, time, and specialized equipment required for product
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testing.

3.1.3 Clock Generator

The clock generator produces quadrature clock signals of 2.4 GHz for both the receiver and the transmitter. All
components of the clock generator are integrated into the chip, including inductors, varactors, filters, regulators
and dividers.

The clock generator has built-in calibration and self-test circuits. Quadrature clock phases and phase noise are
optimized on chip with patented calibration algorithms which ensure the best performance of the receiver and the
transmitter.

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3 Functional Description

3.1.4 Wi­Fi Radio and Baseband

The ESP8684 series Wi-Fi radio and baseband support the following features:

• 802.11b/g/n

• 802.11n MCS0-7 that supports 20 MHz bandwidth

• 802.11n 0.4 µs guard interval

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• data rate up to 72.2 Mbps

• RX STBC (single spatial stream)

• adjustable transmitting power

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• antenna diversity
ESP8684 series supports antenna diversity with an external RF switch. This switch is controlled by one or
more GPIOs, and used to select the best antenna to minimize the effects of channel imperfections.

3.1.5 Wi­Fi MAC

ESP8684 series implements the full 802.11 b/g/n Wi-Fi MAC protocol. It supports the Basic Service Set (BSS)

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STA and SoftAP operations under the Distributed Control Function (DCF). Power management is handled
automatically with minimal host interaction to minimize the active duty period.

The ESP8684 series Wi-Fi MAC applies the following low-level protocol functions automatically:

• 3 × virtual Wi-Fi interfaces

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• infrastructure BSS in Station mode, SoftAP mode, Station + SoftAP mode, and promiscuous mode

• RTS protection, CTS protection, Immediate Block ACK

• fragmentation and defragmentation

• TX/RX A-MPDU, TX/RX A-MSDU

• transmit opportunity (TXOP)

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• Wi-Fi multimedia (WMM)

• CCMP, TKIP, WEP, BIP, WPA2-PSK/WPA2-Enterprise, and WPA3-PSK/WPA3-Enterprise

• automatic beacon monitoring (hardware TSF)

3.1.6 Networking Features

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Espressif provides libraries for TCP/IP networking and other networking protocols over Wi-Fi. TLS 1.0, 1.1 and
1.2 is also supported.

3.2 Bluetooth LE
ESP8684 series includes a Bluetooth Low Energy subsystem that integrates a hardware link layer controller, an
RF/modem block and a feature-rich software protocol stack. It supports the core features of Bluetooth 5.

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3 Functional Description

3.2.1 Bluetooth LE Radio and PHY

Bluetooth Low Energy radio and PHY in ESP8684 series support:

• 1 Mbps PHY

• 2 Mbps PHY for higher data rates

• coded PHY for longer range (125 Kbps and 500 Kbps)

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• listen before talk (LBT), implemented in hardware

3.2.2 Bluetooth LE Link Layer Controller

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Bluetooth Low Energy Link Layer Controller in ESP8684 series supports:

• LE advertising extensions, to enhance broadcasting capacity and broadcast more intelligent data

• multiple advertisement sets

• simultaneous advertising and scanning

• multiple connections in simultaneous central and peripheral roles

• adaptive frequency hopping and channel assessment

• LE channel selection algorithm #2

• connection parameter update

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• high duty cycle non-connectable advertising
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• LE privacy 1.2

• LE data packet length extension

• link layer extended scanner filter policies

• low duty cycle directed advertising

• link layer encryption

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• LE Ping

3.3 CPU and Memory

3.3.1 CPU
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ESP8684 series has a low-power 32-bit RISC-V single-core microprocessor with the following features:

• four-stage pipeline that supports a clock frequency of up to 120 MHz

• RV32IMC ISA

• 32-bit multiplier and 32-bit divider

• up to 32 vectored interrupts at seven priority levels

• up to 2 hardware breakpoints/watchpoints

• JTAG for debugging

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3 Functional Description

3.3.2 Internal Memory

ESP8684’s internal memory includes:

• 576 KB of ROM: for booting and core functions.

• 272 KB of on­chip SRAM: for data and instructions. Of the 272 KB SRAM, 16 KB is configured for cache.

• 1 Kbit of eFuse: 256 bits are reserved for your data, such as encryption key and device ID.

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• SiP flash : See details in Chapter 1 ESP8684 Series Comparison.

3.3.3 Address Mapping Structure

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IN
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Figure 7: Address Mapping Structure

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Note:
The memory space with gray background is not available for use.

3.3.4 Cache
ESP8684 series has an four-way set associative cache. This cache is read-only and has the following
features:

• size: 16 KB

• block size: 32 bytes

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3 Functional Description

• critical word first and early restart

3.4 System Clocks

3.4.1 CPU Clock
The CPU clock has three possible sources:

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• external main crystal clock

• fast RC oscillator (typically about 17.5 MHz, and adjustable)

• PLL clock

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The application can select the clock source from the three clocks above. The selected clock source drives the
CPU clock directly, or after division, depending on the application. Once the CPU is reset, the default clock
source would be the external main crystal clock divided by 2.

Note:
ESP8684 is unable to operate without an external main crystal clock.

3.4.2 RTC Clock

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The RTC slow clock is used for RTC counter, RTC watchdog and low-power controller. It has two possible
sources:
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• internal slow RC oscillator (typically about 136 kHz, and adjustable)

• internal fast RC oscillator divided clock (derived from the fast RC oscillator divided by 256)

The RTC fast clock is used for RTC peripherals and sensor controllers. It has two possible sources:

• external main crystal clock divided by 2

• internal fast RC oscillator clock (typically about 17.5 MHz, and adjustable)
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3.5 Digital Peripherals

3.5.1 General Purpose Input / Output Interface (GPIO)
ESP8684 has 14 GPIO pins which can be assigned various functions by configuring corresponding registers.
Besides digital signals, some GPIOs can be also used for analog functions, such as ADC.
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All GPIOs have selectable internal pull-up or pull-down, or can be set to high impedance. When these GPIOs are
configured as an input, the input value can be read by software through the register. Input GPIOs can also be set
to generate edge-triggered or level-triggered CPU interrupts. All digital IO pins are bi-directional, non-inverting
and tristate, including input and output buffers with tristate control. These pins can be multiplexed with other
functions, such as the UART, SPI, etc. For low-power operations, the GPIOs can be set to holding state.

The IO MUX and the GPIO matrix are used to route signals from peripherals to GPIO pins. Together they provide
highly configurable I/O. Using GPIO Matrix, peripheral input signals can be configured from any IO pins while
peripheral output signals can be configured to any IO pins. Table 6 shows the IO MUX functions of each
pin.

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3 Functional Description

Table 6: IO MUX Pin Functions

Name No. Function 0 Function 1 Function 2 Reset Notes

GPIO0 4 GPIO0 GPIO0 — 0 R
GPIO1 5 GPIO1 GPIO1 — 0 R
GPIO2 6 GPIO2 GPIO2 FSPIQ 1 R
GPIO3 8 GPIO3 GPIO3 — 1 R

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MTMS 9 MTMS GPIO4 FSPIHD 1 R
MTDI 10 MTDI GPIO5 FSPIWP 1 R
MTCK 12 MTCK GPIO6 FSPICLK 1* —
MTDO 13 MTDO GPIO7 FSPID 1 —

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GPIO8 14 GPIO8 GPIO8 — 1 —
GPIO9 15 GPIO9 GPIO9 — 3 —
GPIO10 16 GPIO10 GPIO10 FSPICS0 1 —
GPIO18 18 GPIO18 GPIO18 — 0 —
U0RXD 19 U0RXD GPIO19 — 3 —
U0TXD 20 U0TXD GPIO20 — 4 —

Reset

The default configuration of each pin after reset:

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• 0 - input disabled, in high impedance state (IE = 0)

• 1 - input enabled, in high impedance state (IE = 1)

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• 2 - input enabled, pull-down resistor enabled (IE = 1, WPD = 1)

• 3 - input enabled, pull-up resistor enabled (IE = 1, WPU = 1)

• 4 - output enabled, pull-up resistor enabled (OE = 1, WPU = 1)

• 1* - When the value of eFuse bit EFUSE_DIS_PAD_JTAG is

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0, input enabled, pull-up resistor enabled (IE = 1, WPU = 1)

1, input enabled, in high impedance state (IE = 1)

We recommend pulling high or low GPIO pins in high impedance state to avoid unnecessary power
consumption. You may add pull-up and pull-down resistors in your PCB design referring to Table 10, or enable
internal pull-up and pull-down resistors during software initialization.

Notes
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• R - These pins have analog functions.

3.5.2 Serial Peripheral Interface (SPI)

ESP8684 series features three SPI interfaces (SPI0, SPI1, and SPI2). SPI0 and SPI1 can be configured to
operate in SPI memory mode and SPI2 can be configured to operate in general-purpose SPI mode.

• SPI Memory mode

In SPI memory mode, SPI0 and SPI1 interface with SiP flash. Data is transferred in bytes. Up to four-line
STR reads and writes are supported. The clock frequency is configurable to a maximum of 60 MHz in STR

Espressif Systems 19 ESP8684 Datasheet (Pre-release v0.4)

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3 Functional Description

mode.

• SPI2 General­purpose SPI (GP­SPI) mode

When SPI2 acts as a general-purpose SPI, it can operate in master and slave modes. SPI2 supports
two-line full-duplex communication and single-/two-/four-line half-duplex communication in both master
and slave modes. The host’s clock frequency of SPI2 is configurable. Data is transferred in bytes. The
clock polarity (CPOL) and phase (CPHA) are also configurable. The SPI2 interface can connect to GDMA.

Y
In master or slave mode, the clock frequency is 40 MHz at most, and the four modes of SPI transfer format
are supported.

3.5.3 Universal Asynchronous Receiver Transmitter (UART)

AR
ESP8684 series has two UART interfaces, i.e. UART0 and UART1, which support IrDA and asynchronous
communication (RS232 and RS485) at a speed of up to 2.5 Mbps. The UART controller provides hardware flow
control (CTS and RTS signals) and software flow control (XON and XOFF).

3.5.4 I2C Interface

ESP8684 series has an I2C bus master interface. The I2C interface supports:

• standard mode (100 Kbit/s)

• fast mode (400 Kbit/s)

IN
• up to 800 Kbit/s (constrained by SCL and SDA pull-up strength)

• 7-bit and 10-bit addressing mode

IM
• double addressing mode

• 7-bit broadcast address

You can configure instruction registers to control the I2C interface for more flexibility.

3.5.5 LED PWM Controller

EL

The LED PWM controller has the following features:

• Six identical, independent PWM generators (i.e. channels) that generate digital waveforms

• Configurable waveform periods and duty cycle

• Maximum PWM resolution: 18 bits

PR

• PWM signal output in low-power mode (Light-sleep mode)

• Automatic duty cycle fading - gradual increase/decrease of PWM duty cycle, which is useful for the LED
RGB color-gradient generator.

3.5.6 General DMA Controller

ESP8684 series has a general DMA controller (GDMA) with two independent channels, i.e. one transmit channel
and one receive channel. These two channels are shared by peripherals with DMA feature. The GDMA controller
implements a fixed-priority scheme among these channels, whose priority can be configured.

Espressif Systems 20 ESP8684 Datasheet (Pre-release v0.4)

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3 Functional Description

The GDMA controller controls data transfer using linked lists. It allows peripheral-to-memory and
memory-to-memory data transfer at a high speed. All channels can access internal RAM.

Peripherals on ESP8684 series with DMA feature are SPI2 and SHA.

3.6 Analog Peripherals

3.6.1 Analog­to­Digital Converter (ADC)

Y
ESP8684 series integrates a 12-bit SAR ADC, which supports measurements on 5 channels.

For ADC characteristics, please refer to Table 11.

AR
3.6.2 Temperature Sensor
The temperature sensor generates a voltage that varies with temperature. The voltage is internally converted via
an ADC into a digital value.

The temperature sensor has a range of –40 °C to 125 °C. It is designed primarily to sense the temperature
changes inside the chip. The temperature value depends on factors like microcontroller clock frequency or I/O
load. Generally, the chip’s internal temperature is higher than the operating ambient temperature.

3.7 Timers
3.7.1 General Purpose Timer
IN
ESP8684 series is embedded with a 54-bit general-purpose timer, which is based on a 16-bit prescaler and a
IM
54-bit auto-reload-capable up/down-timer.

The timers’ features are summarized as follows:

• a 16-bit clock prescaler, from 2 to 65536

• a 54-bit time-base counter programmable to be incrementing or decrementing

EL

• able to read real-time value of the time-base counter

• halting and resuming the time-base counter

• programmable alarm generation

• level interrupt generation

PR

3.7.2 System Timer

ESP8684 series integrates a 52-bit system timer, which has two 52-bit counters and three comparators. The
system timer has the following features:

• counters with a fixed clock frequency of 16 MHz

• three types of independent interrupts generated according to alarm value

• two alarm modes: target mode and period mode

• 52-bit target alarm value and 26-bit periodic alarm value

• automatic reload of counter value

Espressif Systems 21 ESP8684 Datasheet (Pre-release v0.4)

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3 Functional Description

• counters can be stalled if the CPU is stalled or in OCD mode

3.7.3 Watchdog Timers

The ESP8684 series contains two watchdog timers: one in general-purpose timer group (called Main System
Watchdog Timer, or MWDT) and one in the RTC module (called the RTC Watchdog Timer, or RWDT).

During the flash boot process, RWDT and MWDT are enabled automatically in order to detect and recover from

Y
booting errors.

Watchdog timers have the following features:

• four stages, each with a programmable timeout value. Each stage can be configured, enabled and

AR
disabled separately

• interrupt, CPU reset, or core reset for MWDT upon expiry of each stage; interrupt, CPU reset, core reset, or
system reset for RWDT upon expiry of each stage

• 32-bit expiry counter

• write protection, to prevent RWDT and MWDT configuration from being altered inadvertently

• flash boot protection

watchdog will reboot the entire main system.

3.8 Low Power Management

IN
If the boot process from an SPI flash does not complete within a predetermined period of time, the
IM
With the use of advanced power-management technologies, ESP8684 series can switch between different
power modes.

• Active mode: CPU and chip radio are powered on. The chip can receive, transmit, or listen.

• Modem-sleep mode: The CPU is operational and the clock speed can be reduced. Wireless base band,
and radio are disabled, but wireless connection can remain active.
EL

• Light-sleep mode: The CPU is paused. Any wake-up events (MAC, host, RTC timer, or external interrupts)
will wake up the chip. Wireless connection can remain active.

• Deep-sleep mode: CPU and most peripherals are powered down. Only the PMU in RTC power
management unit is powered on. For more details, please refer to Figure 1.

For power consumption in different power modes, please refer to Table 13.
PR

3.9 Cryptographic Hardware Accelerators

ESP8684 series is equipped with hardware accelerators of general algorithms, such as:

• SHA1/SHA224/SHA256 (FIPS PUB 180-4)

• ECC

3.10 Physical Security Features

• SiP flash encryption (AES-XTS algorithm) with software inaccessible key prevents unauthorized readout of
your application code or data.

Espressif Systems 22 ESP8684 Datasheet (Pre-release v0.4)

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3 Functional Description

• Secure boot feature uses a hardware root of trust to ensure only signed firmware can be booted.

3.11 Peripheral Pin Configurations

Table 7: Peripheral Pin Configurations

Interface Signal Pin Function

Y
ADC ADC1_CH0 GPIO0 One 12-bit SAR ADC
ADC1_CH1 GPIO1
ADC1_CH2 GPIO2
ADC1_CH3 GPIO3

AR
ADC1_CH4 MTMS
JTAG MTDI MTDI JTAG for software debugging
MTCK MTCK
MTMS MTMS
MTDO MTDO
UART U0RXD_in Any GPIO pins Two UART channels with hardware flow control
U0CTS_in
U0DSR_in
U0TXD_out
U0RTS_out
U0DTR_out
IN
U1RXD_in
IM
U1CTS_in
U1DSR_in
U1TXD_out
U1RTS_out
U1DTR_out
I2C I2CEXT0_SCL_in Any GPIO pins One I2C channel in slave or master mode
EL

I2CEXT0_SDA_in
I2CEXT0_SCL_out
I2CEXT0_SDA_out
LED PWM ledc_ls_sig_out0~5 Any GPIO pins Six independent PWM channels
SPI2 FSPICLK_in/_out_mux Any GPIO pins • Master mode and slave mode of SPI, Dual
FSPICS0_in/_out SPI, Quad SPI, and QPI
FSPICS1~5_out • Connection to external flash, RAM, and
PR

FSPID_in/_out other SPI devices

FSPIQ_in/_out • Four modes of SPI transfer format
FSPIWP_in/_out • Configurable SPI frequency
FSPIHD_in/_out • 64-byte FIFO or GDMA buffer

Espressif Systems 23 ESP8684 Datasheet (Pre-release v0.4)

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4 Electrical Characteristics

4 Electrical Characteristics
The values presented in this section are preliminary and may change with the final release of this
datasheet.

4.1 Absolute Maximum Ratings

Y
Stresses beyond the absolute maximum ratings listed in the table below may cause permanent damage to the
device. These are stress ratings only, and do not refer to the functional operation of the device.

Table 8: Absolute Maximum Ratings

AR
Symbol Parameter Min Max Unit
VDDA3P3, VDDA, VDD3P3_RTC, Voltage applied to power supply pins
–0.3 3.6 V
VDD3P3_CPU per power domain
1
Ioutput Cumulative IO output current — 730 mA
TST ORE Storage temperature –40 150 °C
1
The chip worked properly after a 24-hour test in ambient temperature at 25 °C, and the IOs in two domains

IN
(VDD3P3_RTC, VDD3P3_CPU) output high logic level to ground.

4.2 Recommended Operating Conditions

Table 9: Recommended Operating Conditions

IM
Symbol Parameter Min Typ Max Unit
VDDA3P3, VDDA,
VDD3P3_RTC, Voltage applied to power supply pin 3.0 3.3 3.6 V
1
VDD3P3_CPU
IV DD 2 Current delivered by external power supply 0.5 — — A
EL

TA Operating ambient temperature -40 — 105 °C

1
To write eFuse, VDD3P3_CPU should not be higher than 3.3 V.
2
If you use a single power supply, the recommended output current is 500 mA or more.

4.3 DC Characteristics (3.3 V, 25 °C)

PR

Table 10: DC Characteristics (3.3 V, 25 °C)

Symbol Parameter Min Typ Max Unit

CIN Pin capacitance — 2 — pF
1 1
VIH High-level input voltage 0.75 × VDD — VDD + 0.3 V
1
VIL Low-level input voltage –0.3 — 0.25 × VDD V
IIH High-level input current — — 50 nA
IIL Low-level input current — — 50 nA
2 1
VOH High-level output voltage 0.8 × VDD — — V
2 1
VOL Low-level output voltage — — 0.1 × VDD V

Espressif Systems 24 ESP8684 Datasheet (Pre-release v0.4)

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4 Electrical Characteristics

High-level source current (VDD1= 3.3 V,

IOH — 40 — mA
VOH >= 2.64 V, PAD_DRIVER = 3)
Low-level sink current (VDD1= 3.3 V, VOL =
IOL — 28 — mA
0.495 V, PAD_DRIVER = 3)
RP U Pull-up resistor — 45 — kΩ
RP D Pull-down resistor — 45 — kΩ
1 1

Y
VIH_nRST Chip reset release voltage 0.75 × VDD — VDD + 0.3 V
1
VIL_nRST Chip reset voltage –0.3 — 0.25 × VDD V
1
VDD is the I/O voltage for a particular power domain of pins.
2
VOH and VOL are measured using high-impedance load.

AR
4.4 ADC Characteristics

Table 11: ADC Characteristics

Symbol Parameter Min Max Unit

DNL (Differential nonlinearity)1

INL (Integral nonlinearity)

Sampling rate
Wi-Fi off
—
IN
ADC connected to an external
100 nF capacitor; DC signal input;
ambient temperature at 25 °C;
–3

–9

— 100
3

9
LSB

LSB

kSPS 2
ATTEN0 0 1050 mV
IM
ATTEN1 0 1350 mV
Effective Range
ATTEN2 0 2000 mV
ATTEN3 0 3300 mV
1
To get better DNL results, you can sample multiple times and apply a filter, or calculate the average value.
2
kSPS means kilo samples-per-second.
EL

4.5 Current Consumption

The current consumption measurements are taken with a 3.3 V supply at 25 °C of ambient temperature at the RF
port. All transmitters’ measurements are based on a 100% duty cycle.

Table 12: Current Consumption Depending on RF Modes

PR

Work mode Description Peak

(mA)
802.11b, 1 Mbps, @22 dBm 370
TX 802.11g, 54 Mbps, @20 dBm 300
Active (RF working) 802.11n, HT20, MCS7, @19 dBm 280
RX 802.11b, HT20 62

Espressif Systems 25 ESP8684 Datasheet (Pre-release v0.4)

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4 Electrical Characteristics

Note:
Current consumption measurements for RX 802.11g/n are not ready yet and will be published later.

Table 13: Current Consumption Depending on Work Modes (except Modem­sleep)

Work mode Description Typ Unit

Light-sleep — 130 µA

Y
Deep-sleep Only RTC timer is powered on 5 µA
Power off CHIP_PU is set to low level, and the chip is powered off 1 µA

AR
Table 14: Current Consumption in Modem­sleep Mode

Frequency Typ
Work mode (MHz) Description (mA)
WFI (Wait-for-Interrupt) 12.63
80
CPU run at full speed 15.01
Modem-sleep1
WFI (Wait-for-Interrupt) 13.81
120

2
IN
CPU run at full speed

When Wi-Fi is enabled, the chip switches between Active and Modem-sleep modes. Therefore, current
consumption changes accordingly.
In Modem-sleep mode, the CPU frequency changes automatically. The frequency depends on the CPU
17.39

load and the peripherals used.

IM
3
In practice, the power consumption might be different depending on which peripherals are enabled.

4.6 Wi­Fi Radio

Table 15: Wi­Fi Frequency

EL

Min Typ Max

Parameter
(MHz) (MHz) (MHz)
Center frequency of operating channel 2412 — 2484

4.6.1 Wi­Fi RF Transmitter (TX) Specifications

PR

Table 16: TX Power with Spectral Mask and EVM Meeting 802.11 Standards

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps — 22.0 —
802.11b, 11 Mbps — 22.0 —
802.11g, 6 Mbps — 22.0 —
802.11g, 54 Mbps — 20.0 —
802.11n, HT20, MCS0 — 21.0 —
802.11n, HT20, MCS7 — 19.0 —

Espressif Systems 26 ESP8684 Datasheet (Pre-release v0.4)

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4 Electrical Characteristics

Table 17: TX EVM Test

Min Typ SL1

Rate
(dB) (dB) (dB)
802.11b, 1 Mbps, @22 dBm — –24.5 –10
802.11b, 11 Mbps, @22 dBm — –24.5 –10
802.11g, 6 Mbps, @22 dBm — –20.0 –5

Y
802.11g, 54 Mbps, @20 dBm — –26.5 –25
802.11n, HT20, MCS0, @21 dBm — –22.0 –5
802.11n, HT20, MCS7, @19 dBm — –29.5 –27
1

AR
SL stands for standard limit value.

4.6.2 Wi­Fi RF Receiver (RX) Specifications

Table 18: RX Sensitivity

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps
802.11b, 2 Mbps
802.11b, 5.5 Mbps
802.11b, 11 Mbps
IN —
—
—
—
–100.0
–97.0
–95.0
–90.5
—
—
—
—
IM
Table 19: Maximum RX Level

Min Typ Max

Rate
(dBm) (dBm) (dBm)
802.11b, 1 Mbps — 5 —
802.11b, 11 Mbps — 5 —
EL

Table 20: RX Adjacent Channel Rejection

Min Typ Max

Rate
(dB) (dB) (dB)
802.11b, 1 Mbps — 35 —
PR

802.11b, 11 Mbps — 35 —

Note:
Wi-Fi RF receiver performance for 802.11g/n are not ready yet and will be published later.

Espressif Systems 27 ESP8684 Datasheet (Pre-release v0.4)

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4 Electrical Characteristics

4.7 Bluetooth LE Radio

Table 21: Bluetooth LE Frequency

Min Typ Max

Parameter
(MHz) (MHz) (MHz)
Center frequency of operating channel 2402 — 2480

Y
4.7.1 Bluetooth LE RF Transmitter (TX) Specifications

AR
Table 22: Transmitter Characteristics ­ Bluetooth LE 1 Mbps

Parameter Description Min Typ Max Unit

RF transmit power RF power control range –24.00 3 21.00 dBm
Max |fn |n=0, 1, 2, ..k — 2.00 — kHz
Max |f0 − fn | — 1.00 — kHz
Carrier frequency offset and drift
Max |fn − fn−5 | — 1.00 — kHz
|f1 − f0 | — 0.50 — kHz

Modulation characteristics
∆ f 1avg IN
Min ∆ f 2max (for at least
99.9% of all ∆ f 2max )
∆ f 2avg /∆ f 1avg
—

—
249.00

246.00

1.10
—

—
kHz

kHz

—
± 2 MHz offset — –32.00 — dBm
IM
In-band spurious emissions ± 3 MHz offset — –38.00 — dBm
± > 3 MHz offset — –41.00 — dBm

Table 23: Transmitter Characteristics ­ Bluetooth LE 2 Mbps

Parameter Description Min Typ Max Unit

EL

RF transmit power RF power control range –24.00 3 21.00 dBm

Max |fn |n=0, 1, 2, ..k — 1.00 — kHz
Max |f0 − fn | — 3.00 — kHz
Carrier frequency offset and drift
Max |fn − fn−5 | — 1.20 — kHz
|f1 − f0 | — 2.40 — kHz
∆ f 1avg — 498.00 — kHz
PR

Min ∆ f 2max (for at least

Modulation characteristics — 589.00 — kHz
99.9% of all ∆ f 2max )
∆ f 2avg /∆ f 1avg — 1.20 — —
± 4 MHz offset — –40.00 — dBm
In-band spurious emissions ± 5 MHz offset — –43.00 — dBm
± > 5 MHz offset — –44.00 — dBm

Espressif Systems 28 ESP8684 Datasheet (Pre-release v0.4)

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4 Electrical Characteristics

Table 24: Transmitter Characteristics ­ Bluetooth LE 125 Kbps

Parameter Description Min Typ Max Unit

RF transmit power RF power control range –24.00 3 21.00 dBm
Max |fn |n=0, 1, 2, ..k — 0.50 — kHz
Max |f0 − fn | — 0.70 — kHz
Carrier frequency offset and drift
|fn − fn−3 | — 0.20 — kHz
|f0 − f3 |

Y
— 0.70 — kHz
∆ f 1avg — 248.00 — kHz
Modulation characteristics Min ∆ f 1max (for at least
— 224.00 — kHz
99.9% of all∆ f 2max )

AR
± 2 MHz offset — –32.00 — dBm
In-band spurious emissions ± 3 MHz offset — –38.00 — dBm
± > 3 MHz offset — –41.00 — dBm

Table 25: Transmitter Characteristics ­ Bluetooth LE 500 Kbps

Parameter Description Min Typ Max Unit

RF transmit power

Carrier frequency offset and drift

Max |f0 − fn |
|fn − fn−3 |
IN
RF power control range
Max |fn |n=0, 1, 2, ..k
–24.00
—
—
—
0.50
0.70
0.20
3 21.00
—
—
—
dBm
kHz
kHz
kHz
|f0 − f3 | — 0.70 — kHz
IM
∆ f 2avg — 273.00 — kHz
Modulation characteristics Min ∆ f 2max (for at least
— 243.00 — kHz
99.9% of all ∆ f 2max )
± 2 MHz offset — –32.00 — dBm
In-band spurious emissions ± 3 MHz offset — –38.00 — dBm
± > 3 MHz offset — –41.00 — dBm
EL

4.7.2 Bluetooth LE RF Receiver (RX) Specifications

Table 26: Receiver Characteristics ­ Bluetooth LE 1 Mbps

Parameter Description Min Typ Max Unit

PR

Sensitivity @30.8% PER — — –99 — dBm

Maximum received signal @30.8% PER — — 8 — dBm
Co-channel C/I F = F0 MHz — 8 — dB
F = F0 + 1 MHz — -1 — dB
F = F0 – 1 MHz — -3 — dB
F = F0 + 2 MHz — –26 — dB
F = F0 – 2 MHz — –28 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –34 — dB
F = F0 – 3 MHz — –33 — dB
F > F0 + 3 MHz — –33 — dB
Cont’d on next page

Espressif Systems 29 ESP8684 Datasheet (Pre-release v0.4)

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4 Electrical Characteristics

Table 26 – cont’d from previous page

Parameter Description Min Typ Max Unit
F > F0 – 3 MHz — –31 — dB
Image frequency — — –33 — dB
F = Fimage + 1 MHz — –32 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –34 — dB
30 MHz ~ 2000 MHz — –23 — dBm

Y
2003 MHz ~ 2399 MHz — –30 — dBm
Out-of-band blocking performance
2484 MHz ~ 2997 MHz — –10 — dBm
3000 MHz ~ 12.75 GHz — –17 — dBm

AR
Intermodulation — — –31 — dBm

Table 27: Receiver Characteristics ­ Bluetooth LE 2 Mbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –95.5 — dBm
Maximum received signal @30.8% PER — — 8 — dBm
Co-channel C/I F = F0 MHz — 9 — dB
IN
F = F0 + 2 MHz
F = F0 – 2 MHz
F = F0 + 4 MHz
F = F0 – 4 MHz
—
—
—
—
–11
–7
–35
–30
—
—
—
—
dB
dB
dB
dB
Adjacent channel selectivity C/I
F = F0 + 6 MHz — –35 — dB
IM
F = F0 – 6 MHz — –29 — dB
F > F0 + 6 MHz — –39 — dB
F > F0 – 6 MHz — –33 — dB
Image frequency — — –35 — dB
F = Fimage + 2 MHz — –35 — dB
Adjacent channel to image frequency
F = Fimage – 2 MHz — –11 — dB
EL

30 MHz ~ 2000 MHz — –30 — dBm

2003 MHz ~ 2399 MHz — –34 — dBm
Out-of-band blocking performance
2484 MHz ~ 2997 MHz — –19 — dBm
3000 MHz ~ 12.75 GHz — –28 — dBm
Intermodulation — — –33 — dBm
PR

Espressif Systems 30 ESP8684 Datasheet (Pre-release v0.4)

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4 Electrical Characteristics

Table 28: Receiver Characteristics ­ Bluetooth LE 125 Kbps

Parameter Description Min Typ Max Unit

Sensitivity @30.8% PER — — –106.5 — dBm
Maximum received signal @30.8% PER — — 8 — dBm
Co-channel C/I F = F0 MHz — 3 — dB
F = F0 + 1 MHz — -7 — dB

Y
F = F0 – 1 MHz — -5 — dB
F = F0 + 2 MHz — –35 — dB
F = F0 – 2 MHz — –34 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –38 — dB

AR
F = F0 – 3 MHz — –37 — dB
F > F0 + 3 MHz — –41 — dB
F > F0 – 3 MHz — –45 — dB
Image frequency — — –41 — dB
F = Fimage + 1 MHz — –43 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –38 — dB

Parameter
Sensitivity @30.8% PER —
IN
Table 29: Receiver Characteristics ­ Bluetooth LE 500 Kbps

Description Min
—
Typ
–102.5
Max
—
Unit
dBm
Maximum received signal @30.8% PER — — 8 — dBm
IM
Co-channel C/I F = F0 MHz — 4 — dB
F = F0 + 1 MHz — -6 — dB
F = F0 – 1 MHz — -5 — dB
F = F0 + 2 MHz — –29 — dB
F = F0 – 2 MHz — –32 — dB
Adjacent channel selectivity C/I
F = F0 + 3 MHz — –31 — dB
EL

F = F0 – 3 MHz — –36 — dB
F > F0 + 3 MHz — –34 — dB
F > F0 – 3 MHz — –33 — dB
Image frequency — — –34 — dB
F = Fimage + 1 MHz — –37 — dB
Adjacent channel to image frequency
F = Fimage – 1 MHz — –31 — dB
PR

Espressif Systems 31 ESP8684 Datasheet (Pre-release v0.4)

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5 Package Information

5 Package Information

Y
AR
IN
IM
·

Figure 8: QFN56 (7×7 mm) Package

Note:
EL

• All dimensions are in millimeters (mm).

• The pins of the chip are numbered in a clockwise direction from Pin 1 in the top view;

• For information about tape, reel, and product marking, please refer to Espressif Chip-Packing Information.
PR

Espressif Systems 32 ESP8684 Datasheet (Pre-release v0.4)

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Revision History

Revision History

Date Version Release notes

2021-11-30 v0.1 Preliminary release
2021-12-22 v0.2 Updated section Applications
2022-01-28 v0.4 Updated Electrical Characteristics and Package Information

Y
AR
IN
IM
EL
PR

Espressif Systems 33 ESP8684 Datasheet (Pre-release v0.4)

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Solutions, Documentation and Legal Information

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• Courses
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• Videos
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Y
• Certificates Products
• Notification Subscription • SoCs

AR
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Developer Zone

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IN • Tools

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Espressif Systems 34 ESP8684 Datasheet (Pre-release v0.4)

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AR
IN
IM
EL

Disclaimer and Copyright Notice

Information in this document, including URL references, is subject to change without notice.
PR

ALL THIRD PARTY’S INFORMATION IN THIS DOCUMENT IS PROVIDED AS IS WITH NO

WARRANTIES TO ITS AUTHENTICITY AND ACCURACY.
NO WARRANTY IS PROVIDED TO THIS DOCUMENT FOR ITS MERCHANTABILITY, NON-
INFRINGEMENT, FITNESS FOR ANY PARTICULAR PURPOSE, NOR DOES ANY WARRANTY
OTHERWISE ARISING OUT OF ANY PROPOSAL, SPECIFICATION OR SAMPLE.
All liability, including liability for infringement of any proprietary rights, relating to use of information
in this document is disclaimed. No licenses express or implied, by estoppel or otherwise, to any
intellectual property rights are granted herein.
The Wi-Fi Alliance Member logo is a trademark of the Wi-Fi Alliance. The Bluetooth logo is a
registered trademark of Bluetooth SIG.
All trade names, trademarks and registered trademarks mentioned in this document are property
www.espressif.com of their respective owners, and are hereby acknowledged.
Copyright © 2022 Espressif Systems (Shanghai) Co., Ltd. All rights reserved.
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