LTM4619

Dual, 26VIN, 4A DC/DC

µModule Regulator
Features Description
n Complete Standalone Power Supply The LTM®4619 is a complete dual 4A or single 8A step-
n Wide Input Voltage Range: 4.5V to 26.5V down DC/DC µModule® (micromodule) regulator. Included
(EXTVCC Available for VIN ≤ 5.5V) in the package are the switching controller, power FETs,
n Dual 180° Out-of-Phase Outputs with 4A DC inductor, and all support components. Operating over
Typical, 5A Peak Output Current for Each input voltage ranges of 4.5V to 26.5V, the LTM4619 sup-
n Dual Outputs with 0.8V to 5V Range ports two outputs with voltage ranges of 0.8V to 5V, each
n Output Voltage Tracking set by a single external resistor. Its high efficiency design
n ±1.5% Maximum Total DC Output Error delivers 4A continuous current (5A peak) for each output.
n Current Mode Control/Fast Transient Response
High switching frequency and a current mode architecture
n Power Good
enable a very fast transient response to line and load
n Phase-Lockable Fixed Frequency 250kHz to 780kHz
changes without sacrificing stability. The two outputs
n On Board Frequency Synchronization
are interleaved with 180° phase to minimize the ripple
n Parallel Current Sharing
noise and reduce the I/O capacitors. The device supports
n Selectable Burst Mode® Operation
frequency synchronization and output voltage tracking for
n Output Overvoltage Protection
supply rail sequencing. Burst Mode operation or pulse-
n 15mm × 15mm × 2.82mm LGA Package
skipping mode can be selected for light load operations.
Fault protection features include overvoltage protection,
Applications overcurrent protection and foldback current limit for
n Telecom and Networking Equipment short-circuit protection.
n Servers The low profile package (2.82mm) enables utilization of
n Storage Cards unused space on the bottom of PC boards for high density
n ATCA Cards point of load regulation. The power module is offered in
n Industrial Equipment a 15mm × 15mm × 2.82mm LGA package. The LTM4619
n Point of Load Regulation is RoHS compliant with Pb-free finish.
L, LT, LTC, LTM, Linear Technology, the Linear logo, Burst Mode and µModule are registered
trademarks and LTpowerCAD is a trademark of Linear Technology Corporation. All other
trademarks are the property of their respective owners.

Typical Application
Dual 4A 3.3V/2.5V DC/DC µModule Regulator Efficiency and Power Loss at 12V input
95 2.0

90 EFFICIENCY
MODE/PLLIN INTVCC
5.5V TO 26.5V VIN FREQ/PLLFLTR
10µF 28k 19.1k 85 1.5
×2 VFB1 VFB2
POWER LOSS (W)
EFFICIENCY (%)

80
22pF COMP1 COMP2 22pF
VOUT1 LTM4619 VOUT2 75 1.0
VOUT1 VOUT2
2.5V/4A 3.3V/4A
100µF TK/SS1 TK/SS2 100µF 70
POWER LOSS
0.1µF RUN1 RUN2 0.1µF 65 0.5
PGOOD EXTVCC 60 2.5VOUT
SGND PGND 3.3VOUT
4619 TA01a 55 0
0 0.5 1 1.5 2 2.5 3 3.5 4
LOAD CURRENT (A)
4619 TA01b

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LTM4619
Absolute Maximum Ratings Pin Configuration
(Note 1)
VIN.............................................................. –0.3V to 28V TK/SS2 VFB2
TOP VIEW
COMP2 COMP1 VFB1 TK/SS1
INTVCC, PGOOD, RUN1, RUN2, EXTVCC....... –0.3V to 6V
VFB1, VFB2.................................................. –0.3V to 2.7V M
VIN

COMP1, COMP2 (Note 4)........................... –0.3V to 2.7V

L

K
MODE/PLLIN, TK/SS1, TK/SS2, RUN2
J
FREQ/PLLFLTR

FREQ/PLLFLTR...................................... –0.3V to INTVCC EXTVCC

H
SGND RUN1

VOUT1, VOUT2................................................... 0.8V to 5V SW2

G
SW1

Internal Operating Temperature Range PGOOD

F
MODE/PLLIN

(Note 2)................................................... –40°C to 125°C INTVCC

E

Maximum Reflow Body Temperature..................... 245°C D

Storage Temperature Range................... –55°C to 125°C C

GND

VOUT2 VOUT1
B

1 2 3 4 5 6 7 8 9 10 11 12

LGA PACKAGE
144-LEAD (15mm × 15mm × 2.82mm)
TJMAX = 125°C, θJA = 13.4°C/W, θJCbottom = 6°C/W, θJCtop = 16°C/W, θJB ≈ θJCbottom,
θJB + θBA = 13.4° C/W, θJA DERIVED FROM 95mm × 76mm PCB WITH 4 LAYERS WEIGHT = 1.7g

Order Information
PART NUMBER PAD OR BALL FINISH PART MARKING* PACKAGE MSL TEMPERATURE RANGE
DEVICE FINISH CODE TYPE RATING (SEE NOTE 2)

LTM4619EV#PBF Au (RoHS) LTM4619V e4 LGA 3 –40°C to 125°C

LTM4619IV#PBF Au (RoHS) LTM4619V e4 LGA 3 –40°C to 125°C
Consult Marketing for parts specified with wider operating temperature • Recommended LGA and BGA PCB Assembly and Manufacturing
ranges. *Device temperature grade is indicated by a label on the shipping Procedures:
container. Pad or ball finish code is per IPC/JEDEC J-STD-609. www.linear.com/umodule/pcbassembly
• Terminal Finish Part Markings: • LGA and BGA Package and Tray Drawings:
www.linear.com/leadfree http://www.linear.com/packaging

Electrical Characteristics The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 19.
Specified as each channel. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VIN(DC) Input DC Voltage VIN ≤ 5.5V, Connect VIN and INTVCC Together l 4.5 26.5 V
VOUT1, 2(RANGE) Output Voltage Range VIN = 5.5V to 26.5V l 0.8 5.0 V
VOUT1, 2(DC) Output Voltage CIN = 10µF ×1, COUT = 100µF Ceramic, 100µF POSCAP,
RSET = 28.0kΩ
VIN = 12V, VOUT = 2.5V, IOUT = 0A 2.483 2.52 2.557 V
VIN = 12V, VOUT = 2.5V, IOUT = 4A l 2.470 2.52 2.570 V
Input Specifications
VIN(UVLO) Undervoltage Lockout Thresholds VINTVCC Rising 2.00 2.2 2.35 V
VINTVCC Falling 1.85 2.0 2.15 V
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 LTM4619
Electrical Characteristics The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 19.
Specified as each channel. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
IINRUSH(VIN) Input Inrush Current at Start-Up IOUT = 0A, CIN = 10µF, COUT = 100µF, VOUT = 2.5V
VIN = 12V 0.25 A
IQ(VIN) Input Supply Bias Current VIN = 12V, VOUT1 = 2.5V, Switching Continuous 30 mA
VIN = 12V, VOUT2 = 2.5V, Switching Continuous 30 mA
VIN = 26.5V, VOUT1 = 2.5V, Switching Continuous 40 mA
VIN = 26.5V, VOUT2 = 2.5V, Switching Continuous 40 mA
Shutdown, RUN = 0, VIN = 20V 40 µA
IS(VIN) Input Supply Current VIN = 12V, VOUT = 2.5V, IOUT = 4A 0.97 A
VIN = 26.5V, VOUT = 2.5V, IOUT = 4A 0.480 A
INTVCC Internal VCC Voltage VIN = 12V, VRUN > 2V, No Load 4.8 5 5.2 V
EXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive l 4.5 4.7 V
Output Specifications
IOUT1, 2(DC) Output Continuous Current Range VIN = 12V, VOUT = 2.5V (Note 5) 0 4 A
ΔVOUT1(LINE) Line Regulation Accuracy VOUT = 2.5V, VIN from 6V to 26.5V 0.15 0.3 %
VOUT(NOM) IOUT = 0A For Each Output l 0.25 0.5 %

ΔVOUT2(LINE) Line Regulation Accuracy VOUT = 2.5V, VIN from 6V to 26.5V 0.15 0.3 %
VOUT(NOM) IOUT = 0A For Each Output l 0.25 0.5 %

ΔVOUT1(LOAD) Load Regulation Accuracy For Each Output, VOUT = 2.5V, 0A to 4A (Note 5) l 0.6 0.8 ±%
VOUT1(NOM) VIN = 12V

ΔVOUT2(LOAD) Load Regulation Accuracy For Each Output, VOUT = 2.5V, 0A to 4A (Note 5) l 0.6 0.8 ±%
VOUT2(NOM) VIN = 12V

VOUT1, 2(AC) Output Ripple Voltage IOUT = 0A, COUT = 100µF X5R Ceramic
VIN = 12V, VOUT = 2.5V 20 mV
VIN = 26.5V, VOUT = 2.5V 25 mV
fS Output Ripple Voltage Frequency IOUT = 2A, VIN = 12V, VOUT = 2.5V 780 kHz
FREQ/PLLFLTR = INTVCC
ΔVOUTSTART Turn-On Overshoot COUT = 100µF X5R Ceramic, VOUT = 2.5V, IOUT = 0A
VIN = 12V 10 mV
VIN = 26.5V 10 mV
tSTART Turn-On Time COUT = 100µF X5R Ceramic, VOUT = 2.5V, IOUT = 0A
Resistive Load,
VIN = 12V 0.250 ms
VIN = 26.5V 0.130 ms
ΔVOUTLS Peak Deviation for Dynamic Load Load: 0% to 50% to 0% of Full Load
COUT = 100µF X5R Ceramic,VOUT = 2.5V, VIN = 12V 15 mV
tSETTLE Settling Time for Dynamic Load Load: 0% to 50% to 0% of Full Load
Step COUT = 100µF X5R Ceramic,VOUT = 2.5V, VIN = 12V 10 µs
IOUTPK Output Current Limit COUT = 100µF X5R Ceramic,
VIN = 6V, VOUT = 2.5V 12 A
VIN = 26.5V, VOUT = 2.5V 11 A
Control Section
VFB1, VFB2 Voltage at VFB Pin IOUT = 0A, VOUT = 2.5V 0.792 0.8 0.808 V
l 0.788 0.8 0.810
ITK/SS1, 2 Soft-Start Charge Current VTK/SS = 0V, VOUT = 2.5V 0.9 1.3 1.7 µA
DFMAX Maximum Duty Factor In Dropout (Note 4) 97 %
tON(MIN) Minimum On-Time (Note 4) 90 ns

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LTM4619
electrical characteristics The l denotes the specifications which apply over the full internal
operating temperature range (Note 2), otherwise specifications are at TA = 25°C, VIN = 12V. Per typical application in Figure 19.
Specified as each channel. (Note 3)
SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fNOM Nominal Frequency VFREQ = 1.2V 450 500 550 kHz
fLOW Lowest Frequency VFREQ = 0V 210 250 290 kHz
fHIGH Highest Frequency VFREQ ≥ 2.4V 700 780 860 kHz
RMODE/PLLIN MODE/PLLIN Input Resistance 250 kΩ
IFREQ Frequency Setting
Sinking Current fMODE > fOSC –13 µA
Sourcing Current fMODE < fOSC 13 µA
VRUN1, 2 RUN Pin ON/OFF Threshold RUN Rising 1.1 1.22 1.35 V
RUN Falling 1.02 1.14 1.27 V
RFB1, RFB2 Resistor Between VOUT and VFB 60.1 60.4 60.7 kΩ
Pins for Each Channel
VPGL PGOOD Voltage Low IPGOOD = 2mA 0.1 0.3 V
IPGOOD PGOOD Leakage Current VPGOOD = 5V ±2 µA
ΔVPGOOD PGOOD Range VFB Ramping Negative –5 –7.5 –10 %
VFB Ramping Positive 5 7.5 10 %

Note 1: Stresses beyond those listed under Absolute Maximum Ratings internal operating temperature range. Note that the maximum ambient
may cause permanent damage to the device. Exposure to any Absolute temperature consistent with these specifications is determined by specific
Maximum Rating condition for extended periods may affect device operating conditions in conjunction with board layout, the rated package
reliability and lifetime. thermal resistance and other environmental factors.
Note 2: The LTM4619E is guaranteed to meet performance specifications Note 3: The two outputs are tested separately and the same testing
over the 0°C to 125°C internal operating temperature range. Specifications condition is applied to each output.
over the full –40°C to 125°C internal operating temperature range are Note 4: 100% tested at wafer level only.
assured by design, characterization and correlation with statistical process Note 5: See Output Current Derating curves for different VIN, VOUT and TA.
controls. The LTM4619I is guaranteed to meet specifications over the full

Typical Performance Characteristics (Refer to Figures 19 and 20)

Efficiency vs Load Current with Efficiency vs Load Current with

5VIN (f = 500kHz for 0.8VOUT, 12VIN (f = 500kHz for 1.2VOUT and Efficiency vs Load Current with
1.2VOUT and 1.5VOUT) 1.5VOUT) 24VIN (f = 500kHz for 1.5VOUT)
95 95 95
3.3VOUT 5VOUT
90 5VOUT
90 2.5VOUT 90 3.3VOUT
3.3VOUT 2.5VOUT 85
85 85
1.2VOUT 80
1.5VOUT
EFFICIENCY (%)
EFFICIENCY (%)

EFFICIENCY (%)

80 80 75
1.5VOUT 1.2VOUT 2.5VOUT
0.8VOUT 1.5VOUT
75 75 70

70 65
70
60
65 65
55
60 60 50
55 55 45
0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4 0 0.5 1 1.5 2 2.5 3 3.5 4
LOAD CURRENT (A) LOAD CURRENT (A) LOAD CURRENT (A)
4619 G01 4619 G02 4619 G03

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 LTM4619
Typical Performance Characteristics (Refer to Figures 19 and 20)

1.2V Output Transient Response 1.5V Output Transient Response 2.5V Output Transient Response

IOUT IOUT IOUT

1A/DIV 1A/DIV 1A/DIV

VOUT VOUT VOUT

50mV/DIV 50mV/DIV 50mV/DIV

100µs/DIV 4619 G04

100µs/DIV 4619 G05
100µs/DIV 4619 G06

6VIN 1.2VOUT AT 2A/µs LOAD STEP 6VIN 1.5VOUT AT 2A/µs LOAD STEP 6VIN 2.5VOUT AT 2A/µs LOAD STEP
f = 780kHz f = 780kHz f = 780kHz
COUT 2× 22µF, 6.3V X5R CERAMIC COUT 2× 22µF, 6.3V X5R CERAMIC COUT 2× 22µF, 6.3V X5R CERAMIC
COUT 1× 330µF, 6.3V SANYO POSCAP COUT 1× 330µF, 6.3V SANYO POSCAP COUT 1× 330µF, 6.3V SANYO POSCAP

3.3V Output Transient Response Start-Up, IOUT = 0A Start-Up, IOUT = 4A

IOUT VIN VIN

1A/DIV 1V/DIV 1V/DIV

VOUT
50mV/DIV IIN IIN
0.5A/DIV 0.5A/DIV
100µs/DIV 4619 G07
20ms/DIV 4619 G08
20ms/DIV 4619 G09

6VIN 3.3VOUT AT 2A/µs LOAD STEP VIN = 12V, VOUT = 2.5V, IOUT = 0A VIN = 12V, VOUT = 2.5V,
f = 780kHz COUT = 2× 22µF 10V IOUT = 4A RESISTIVE LOAD
COUT 2× 22µF, 6.3V X5R CERAMIC AND 1× 100µF 6.3V CERAMIC CAPs COUT = 2× 22µF 10V,
COUT 1× 330µF, 6.3V SANYO POSCAP CSOFTSTART = 0.1µF AND 1× 100µF 6.3V CERAMIC CAPs
USE RUN PIN TO CONTROL START-UP CSOFTSTART = 0.1µF
USE RUN PIN TO CONTROL START-UP

Short Circuit, IOUT = 0A Short Circuit, IOUT = 4A

VOUT VOUT
1V/DIV 1V/DIV

IIN
0.5A/DIV
IIN
0.5A/DIV
50µs/DIV 4619 G10
50µs/DIV 4619 G11

VIN = 12V, VOUT = 2.5V, IOUT = 0A VIN = 12V, VOUT = 2.5V, IOUT = 4A
COUT = 2× 22µF 10V, COUT = 2× 22µF 10V,
AND 1× 100µF 6.3V CERAMIC CAPs AND 1× 100µF 6.3V CERAMIC CAPs

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LTM4619
Pin Functions
PACKAGE ROW AND COLUMN LABELING MAY VARY FREQ/PLLFLTR (J8): Frequency Selection Pin. An internal
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE lowpass filter is tied to this pin. The frequency can be
LAYOUT CAREFULLY.
selected from 250kHz to 780kHz by varying the DC volt-
VIN (J1 to J3, J10 to J12, K1 to K4, K9 to K12, L1 to L5, age on this pin from 0V to 2.4V. The nominal frequency
L8 to L12, M1 to M12): Power Input Pins. Apply input setting is 500kHz. Frequency selection can be modified as
voltage between these pins and PGND pins. Recommend long as the inductor ripple current is less ≈40% to 50%
placing input decoupling capacitance directly between VIN at the output current
pins and PGND pins. For VIN < 5.5, tie VIN and INTVCC
together. 1  VOUT 
1– V
FREQ  VIN  OUT
VOUT1, VOUT2 (A10 to D10, A11 to D11, A12 to D12, A1 to IRIPPLE =
D1, A2 to D2, A3 to D3): Power Output Pins. Apply output L
load between these pins and PGND pins. Recommend Where FREQ is selected operating frequency and L is
placing output decoupling capacitance directly between the inductor value. Leave this pin floating when external
these pins and PGND pins. synchronization is used.
PGND (H1, H2, H4, H9, H11, H12, G1 to G12, F1 to F5, TK/SS1, TK/SS2 (K8, K5): Output Voltage Tracking and
F7 to F12, E1 to E12, D4 to D9, C4 to C9, B4 to B9, A4 to Soft-Start Pins. Internal soft-start currents of 1.3µA charge
A9): Power ground pins for both input and output returns. the soft-start capacitors. See the Applications Information
INTVCC (F6): Internal 5V Regulator Output. This pin is for section to use the tracking function.
additional decoupling of the 5V internal regulator. VFB1, VFB2 (K7, K6): The negative input of the error
EXTVCC (J4): External Power Input to Controller. When amplifier. Internally, this pin is connected to VOUT with
EXTVCC is higher than 4.7V, the internal 5V regulator is a 60.4k precision resistor. Different output voltages can
disabled and external power supplies current to reduce be programmed with an additional resistor between VFB
the power dissipation in the module. This will improve the and SGND pins. See the Applications Information section
efficiency more at high input voltages. for details.
SGND (J6, J7, H6, H7): Signal Ground Pin. Return ground COMP1, COMP2 (L7, L6): Current Control Threshold and
path for all analog and low power circuitry. Tie a single Error Amplifier Compensation Point. The module has been
connection to PGND in the application. internally compensated for most I/O ranges.
MODE/PLLIN (H8): Mode selection or external synchroniza- PGOOD (H5): Output Voltage Power Good Indicator. Open
tion pin. Tying this pin high enables pulse-skipping mode. drain logic output that is pulled to ground when the output
Tying this pin low enables force continuous operation. voltage is not within ±7.5% of the regulation point.
Floating this pin enables Burst Mode operation. A clock RUN1, RUN2 (J9, J5): Run Control Pins. 0.5µA pull-up
on the pin will force the controller into the continuous currents on these pins turn on the module if these pins
mode of operation and synchronize the internal oscillator. are floating. Forcing either of these pins below 1.2V will
The suitable synchronizable frequency range is 250kHz to shut down the corresponding outputs. An additional 4.5µA
780kHz subject to inductor ripple current limits described pull-up current is added to this pin, once the RUN pin rises
in the FREQ/PLLFLTR pin section. The external clock input above 1.2V. Also, active control or pull-up resistors can
high threshold is 1.6V, while the input low threshold is 1V. be used to enable the RUN pin. The maximum voltage is
6V on these pins.
SW1, SW2 (H10, H3): Switching Test Pins. These pins
are provided externally to check the operation frequency.

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 LTM4619
Simplified Block Diagram
INTERNAL VIN
FILTER 4.5V TO 26.5V*
1.5µF
+
CIN
INTVCC
M1
PGOOD PGND
SW1
MODE/PLLIN VOUT1
L1 2.5V/4A
EXTVCC
M2 1.5µH
+
VIN 10µF COUT1
TK/SS1

CSS1 PGND
R1
RUN1
60.4k
COMP1
R2 VFB1
INTERNAL RSET1
 R2  POWER 28k
 R1+ R2  • VIN COMP 1.5µF
CONTROL
= UVLO THRESHOLD = 1.22V TK/SS2
M3
PGND
CSS2
SW2
RUN2 VOUT2
3.3V/4A
COMP2 L2 +
M4 1.5µH 10µF COUT2
INTERNAL PGND
COMP
60.4k
FREQ
VFB2
INTERNAL RSET2
FILTER 19.1k
SGND

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*USE EXTVCC FOR VIN ≤ 5.5V, OR TIE VIN AND EXTVCC TOGETHER FOR VIN ≤ 5.5V

Figure 1. Simplified LTM4619 Block Diagram

Decoupling Requirements TA = 25°C. Use Figure 1 configuration.

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

External Input Capacitor Requirement
CIN (VIN = 4.5V to 26.5V, VOUT1 = 2.5V, VOUT2 = 3.3V) IOUT1 = 4A, IOUT2 = 4A 10 µF
External Output Capacitor Requirement
COUT1 (VIN = 4.5V to 26.5V, VOUT1 = 2.5V, VOUT2 = 3.3V) IOUT1 = 4A 200 µF
COUT2 IOUT2 = 4A 200 µF

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LTM4619
Operation
The LTM4619 is a dual-output standalone non-isolated Internal overvoltage and undervoltage comparators pull
switching mode DC/DC power supply. It can deliver up to the open-drain PGOOD output low if the output feedback
4A (DC current) for each output with few external input and voltage exits a ±7.5% window around the regulation point.
output capacitors. This module provides precisely regulated The power good pin is disabled during start-up.
output voltages programmable via external resistors from
Pulling the RUN pin below 1.2V forces the controller into
0.8VDC to 5.0VDC over 4.5V to 26.5V input voltages. The
its shutdown state, by turning off both MOSFETs. The
typical application schematic is shown in Figure 19. TK/SS pin is used for programming the output voltage
The LTM4619 has integrated constant frequency current ramp and voltage tracking during start-up. See the Ap-
mode regulators and built-in power MOSFET devices with plications Information section.
fast switching speed. The typical switching frequency is The LTM4619 is internally compensated to be stable over
780kHz. To reduce switching noise, the two outputs are all operating conditions. LTpowerCAD™ is available for
interleaved with 180° phase internally and can be synchro- transient and stability analysis. The VFB pin is used to
nized externally using the MODE/PLLIN pin.
program the output voltage with a single external resistor
With current mode control and internal feedback loop to ground. Multiphase operation can be easily employed
compensation, the LTM4619 module has sufficient stabil- with the synchronization.
ity margins and good transient performance with a wide
High efficiency at light loads can be accomplished with
range of output capacitors, even with all ceramic output
selectable Burst Mode operation or pulse-skipping mode
capacitors.
using the MODE/PLLIN pin. Efficiency graphs are provided
Current mode control provides cycle-by-cycle fast current for light load operations in the Typical Performance Char-
limit and current foldback in a short-circuit condition. acteristics section.

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 LTM4619
Applications Information
The typical LTM4619 application circuit is shown in Without considering the inductor ripple current, for each
Figure 19. External component selection is primarily deter- output, the RMS current of the input capacitor can be
mined by the maximum load current and output voltage. estimated as:
IOUT(MAX)
Output Voltage Programming ICIN(RMS) = • D•(1−D)
η
The PWM controller has an internal 0.8V reference voltage.
As shown in the block diagram, a 60.4k internal feedback In the above equation, η is the estimated efficiency of the
resistor RFB connects VOUT to VFB pin. The output voltage power module. The bulk capacitor can be a switcher-rated
will default to 0.8V with no feedback resistor. Adding a aluminum electrolytic capacitor or a polymer capacitor. One
resistor RSET from VFB pin to SGND programs the output 10µF ceramic input capacitor is typically rated for 2A of
voltage: RMS ripple current, so the RMS input current at the worst
case for each output at 4A maximum current is about 2A.
60.4k +RSET
VOUT = 0.8V • If a low inductance plane is used to power the device, then
RSET two 10µF ceramic capacitors are enough for both outputs
or equivalently at 4A load and no external input bulk capacitor is required.
60.4k Output Capacitors
RSET =
 VOUT 
 – 1 The LTM4619 is designed for low output voltage ripple
0.8V  noise. The bulk output capacitors defined as COUT are
chosen with low enough effective series resistance (ESR)
Table 1. RSET Resistor Table vs Various Output Voltages
to meet the output voltage ripple and transient require-
VOUT (V) 0.8 1.2 1.5 1.8 2.5 3.3 5
ments. COUT can be a low ESR tantalum capacitor, a low
RSET (kΩ) Open 121 68.1 48.7 28.0 19.1 11.5
ESR polymer capacitor or ceramic capacitor. The typical
output capacitance range for each output is from 47µF
Input Capacitors
to 220µF. Additional output filtering may be required by
The LTM4619 module should be connected to a low AC- the system designer. If further reduction of output ripple
impedance DC source. Two 1.5µF input ceramic capacitors or dynamic transient spikes is required, LTpowerCAD is
are included inside the module. Additional input capacitors available for stability analysis. Multiphase operation will
are needed if a large load is required up to the 4A level. reduce effective output ripple as a function of the num-
A 47µF to 100µF surface mount aluminum electrolytic ber of phases. Application Note 77 discusses this noise
capacitor can be used for more input bulk capacitance. reduction versus output ripple current cancellation, but
This bulk capacitor is only needed if the input source im- the output capacitance should be considered carefully as
pedance is compromised by long inductive leads, traces a function of stability and transient response. LTpowerCAD
or not enough source capacitance. calculates the output ripple reduction as the number of
For a buck converter, the switching duty-cycle can be implemented phases increased by N times.
estimated as:
VOUT
D=
VIN

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LTM4619
applications information
Mode Selections and Phase-Locked Loop Frequency Selection
The LTM4619 can be enabled to enter high efficiency The switching frequency of the LTM4619’s controllers
Burst Mode operation, constant-frequency pulse-skipping can be selected using the FREQ/PLLFLTR pin. If the
mode, or forced continuous conduction mode. To select MODE/PLLIN pin is not being driven by an external clock
the forced continuous operation, tie the MODE/PLLIN pin source, the FREQ/PLLFLTR pin can be set from 0V to 2.4V to
to a DC voltage below 0.8V. To select pulse-skipping mode program the controller’s operating frequency from 250kHz
of operation, tie the MODE/PLLIN pin to INTVCC. To select to 780kHz using a voltage divider to INTVCC (see Figure
Burst Mode operation, float the MODE/PLLIN pin. 20). The typical frequency is 780kHz. If the output is too
low or the minimum on-time is reached, the frequency
Frequency Synchronization needs to decrease to enlarge the turn-on time. Otherwise,
A phase-lock loop is available on the LTM4619 to syn- a significant amount of cycle skipping can occur with cor-
chronize the internal clock to an external clock source respondingly larger current and voltage ripple.
connected on the MODE/PLLIN pin. The clock high level
900
needs to be higher than 1.6V and the clock low level needs
to be lower than 1V. The frequency programming voltage 800

SWITCHING FREQUENCY (kHz)

and or the programming voltage divider must be removed 700

from the FREQ/PLLFLTR pin when synchronizing to an 600

external clock. The FREQ/PLLFLTR pin has the required 500

onboard PLL filter components for clock synchronization. 400

The LTM4619 will default to forced continuous mode while 300

being clock synchronized. Channel 1 is synchronized to 200
the rising edge on the external clock, and channel 2 is 180 100
degrees out-of-phase with the external clock. 0
0 0.5 1 1.5 2 2.5
FREQ/PLLFLTR PIN VOLTAGE (V) 4619 F02

Figure 2. Switching Frequency vs FREQ/PLLFLTR Pin Voltage

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Applications Information
Soft-Start and Tracking Output voltage tracking can be programmed externally
using the TK/SS pin. The master channel is divided down
The LTM4619 has the ability to either soft-start by itself
with an external resistor divider that is the same as the
with a capacitor or track the output of another channel or
slave channel’s feedback divider to implement coincident
external supply. When one particular channel is configured
tracking. The LTM4619 uses an accurate 60.4k resistor
to soft-start by itself, a capacitor should be connected to
internally for the top feedback resistor. Figure 3 shows an
its TK/SS pin. This channel is in the shutdown state if its
example of coincident tracking. Figure 4 shows the output
RUN pin voltage is below 1.2V. Its TK/SS pin is actively
voltages with coincident tracking.
pulled to ground in this shutdown state.
Once the RUN pin voltage is above 1.2V, the channel pow-  R1
VSLAVE =  1+  • VTRACK
ers up. A soft-start current of 1.3µA then starts to charge  R2 
its soft-start capacitor. Note that soft-start or tracking is VTRACK is the track ramp applied to the slave’s TK/SS2
achieved not by limiting the maximum output current of pin. VTRACK has a control range of 0V to 0.8V. When the
the controller but by controlling the output ramp voltage master’s output is divided down with the same resistor
according to the ramp rate on the TK/SS pin. Current values used to set the slave’s output, then the slave will
foldback is disabled during this phase to ensure smooth coincident track with the master until it reaches its final
soft-start or tracking. The soft-start or tracking range is value. The master will continue to its final value from the
defined to be the voltage range from 0V to 0.8V on the slave’s regulation point.
TK/SS pin. The total soft-start time can be calculated as:
Ratiometric modes of tracking can be achieved by select-
0.8V •CSS ing different divider resistors values to change the output
tSOFT-START =
1.3µA tracking ratio. The master output must be greater than the
slave output for the tracking to work. Master and slave
data inputs can be used to implement the correct resistors
values for coincident or ratiometric tracking.

VIN MODE/PLLIN INTVCC

5.5V TO VIN FREQ/PLLFLTR
28V
CIN VFB1 VFB2
R3 R4 MASTER OUTPUT
C2 C3
19.1k COMP1 COMP2 28k
22pF 22pF
VOUT1 LTM4619 V VOUT2
VOUT1 OUT2 2.5V
3.3V
COUT1 TK/SS1 TK/SS2 COUT2 SLAVE OUTPUT
OUTPUT
C1 VOLTAGE
0.1µF RUN1 RUN2
VOUT1
PGOOD EXTVCC
SGND PGND R1
4619 F03
60.4k

R2
28k 4619 F04
TIME

Figure 3. Example of Coincident Tracking Figure 4. Coincident Tracking

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LTM4619
applications information
0.60
1-PHASE
0.55 2-PHASE
3-PHASE
4-PHASE
0.50 6-PHASE

0.45

0.40
RMS INPUT RIPPLE CURRENT
DC LOAD CURRENT

0.35

0.30

0.25

0.20

0.15

0.10

0.05

0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN) 4619 F05

Figure 5. Normalized Input RMS Ripple Current vs Duty Cycle for One to Six Phases

1.00
0.95 1-PHASE
2-PHASE
0.90 3-PHASE
0.85 4-PHASE
6-PHASE
0.80
0.75
PEAK-TO-PEAK OUTPUT RIPPLE CURRENT

0.70
0.65
0.60
0.55
0.50
DIr

0.45
0.40
0.35
0.30
0.25
RATIO =

0.20
0.15
0.10
0.05
0
0.1 0.15 0.2 0.25 0.3 0.35 0.4 0.45 0.5 0.55 0.6 0.65 0.7 0.75 0.8 0.85 0.9
DUTY CYCLE (VOUT/VIN) 4619 F06

Figure 6. Normalized Output Ripple Current vs Duty Cycle, Dlr = VOUT T/L
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 LTM4619
Applications Information
Multiphase Operation RUN Pin
Multiphase operation with multiple LTM4619 devices in The RUN pins can be used to enable or sequence the
parallel will lower the effective input RMS ripple current particular regulator channel. The RUN pins have their own
as well as the output ripple current due to the interleaving internal 0.5µA current source to pull up the pin to 1.2V, and
operation of the regulators. Figure 5 provides a ratio of then the current increases to 4.5µA above 1.2V. Careful
input RMS ripple current to DC load current as a function consideration is needed to assure that board contamination
of duty cycle and the number of paralleled phases. Choose or residue does not load down the 0.5µA pull-up current.
the corresponding duty cycle and the number of phases Otherwise active control to these pins can be used to en-
to get the correct ripple current value. For example, the able the regulators. A voltage divider can be used from
2-phase parallel for one LTM4619 design provides 8A VIN to set an enable point that can also be used as a UVLO
at 2.5V output from a 12V input. The duty cycle is DC = feature for the regulator. The resistor divider needs to be
2.5V/12V = 0.21. The 2-phase curve has a ratio of ~0.25 low enough resistance to swamp out the pull-up current
for a duty cycle of 0.21. This 0.25 ratio of RMS ripple cur- sources to prevent unintended activation of the device.
rent to a DC load current of 8A equals ~2A of input RMS See the Simplified Block Diagram.
ripple current for the external input capacitors.
Power Good
The effective output ripple current is lowered with mul-
tiphase operations as well. Figure 6 provides a ratio of The PGOOD pin is connected to the open drain of an internal
peak-to-peak output ripple current to the normalized N-channel MOSFET. The MOSFET turns on and pulls the
output ripple current as a function of duty cycle and the PGOOD pin low when either VFB pin voltage is not within
number of paralleled phases. Choose the corresponding ±7.5% of the 0.8V reference voltage. The PGOOD pin is
duty cycle and the number of phases to get the correct also pulled low when either RUN pin is below 1.2V or when
output ripple current ratio value. If a 2-phase operation the LTM4619 is in the soft-start or tracking phase. When
is chosen at 12VIN to 2.5VOUT with a duty cycle of 21%, the VFB pin voltage is within the ±7.5% requirement, the
then 0.6 is the ratio of the normalized output ripple cur- MOSFET is turned off and the pin is allowed to be pulled
rent to inductor ripple DIr at zero duty cycle. This leads up by an external resistor to a source of up to 6V. The
to ~1.3A of the effective output ripple current ΔIL if the PGOOD pin will flag power good immediately when both
DIr is at 2.2A. Refer to Application Note 77 for a detailed VFB pins are within the ±7.5% window. However, there is
explanation of the output ripple current reduction as a an internal 17µs power bad mask when either VFB goes
function of paralleled phases. out of the ±7.5% window.
The output ripple voltage has two components that are
related to the amount of bulk capacitance and effective
series resistance (ESR) of the output bulk capacitance.
Therefore, the output ripple voltage can be calculated with
the known effective output ripple current. The equation:
ΔVOUT(P-P) ≈ ΔIL/(8 • f • N • COUT) + ESR • ΔIL
where f is frequency and N is the number of parallel phases.

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LTM4619
applications information
INTVCC and EXTVCC Fault Conditions: Current Limit and Overcurrent
Foldback
The INTVCC is the internal 5V regulator that powers the
LTM4619 internal circuitry and drives the power MOSFETs. The LTM4619 has a current mode controller, which inher-
The input voltage of the LTM4619 must be 6V or above ently limits the cycle-by-cycle inductor current not only in
for the INTVCC to regulate to the proper 5V level due to steady-state operation, but also in transient.
the internal LDO dropout from the input voltage. For ap- To further limit current in the event of an overload condi-
plications that need to operate below 6V input, then the tion, the LTM4619 provides foldback current limiting. If the
input voltage can be connected directly to the EXTVCC output voltage falls by more than 50%, then the maximum
pin to bypass the LDO dropout concern, or an external output current is progressively lowered to one-third of its
5V supply can be used to power the EXTVCC pin when full current limit value. Foldback current limiting is disabled
the input voltage is at high end of the supply range to during soft-start and tracking up.
reduce power dissipation in the module. For example the
dropout voltage for 24V input would be 24V – 5V = 19V. Thermal Considerations and Output Current Derating
This 19V headroom then multiplied by the power MOSFET
drive current of ~15mA would equal ~0.3W additional The thermal resistances reported in the Pin Configuration
power dissipation. So utilizing an external 5V supply on section of the data sheet are consistent with those param-
the EXTVCC would improve design efficiency and reduce eters defined by JESD51-12 and are intended for use with
device temperature rise. finite element analysis (FEA) software modeling tools that
leverage the outcome of thermal modeling, simulation,
Slope Compensation and correlation to hardware evaluation performed on a
µModule package mounted to a hardware test board.
The module has already been internally compensated for The motivation for providing these thermal coefficients
all output voltages. LTpowerCAD is available for control is found in JESD51-12 (“Guidelines for Reporting and
loop optimization. Using Electronic Package Thermal Information”).
Burst Mode Operation and Pulse-Skipping Mode Many designers may opt to use laboratory equipment
and a test vehicle such as the demo board to predict the
The LTM4619 regulator can be placed into high efficiency µModule regulator’s thermal performance in their appli-
power saving modes at light load condition to conserve cation at various electrical and environmental operating
power. The Burst Mode operation can be selected by float- conditions to compliment any FEA activities. Without FEA
ing the MODE/PLLIN pin, and pulse-skipping mode can be software, the thermal resistances reported in the Pin Con-
selected by pulling the MODE/PLLIN pin to INTVCC. Burst figuration section are, in and of themselves, not relevant to
Mode operation offers the best efficiency at light load, but providing guidance of thermal performance; instead, the
output ripple will be higher and lower frequency ranges derating curves provided in this data sheet can be used
are capable which can interfere with some systems. Pulse- in a manner that yields insight and guidance pertaining to
skipping mode efficiency is not as good as Burst Mode one’s application-usage, and can be adapted to correlate
operation, but this mode only skips pulses to save efficiency thermal performance to one’s own application.
and maintains a lower output ripple and a higher switch-
The Pin Configuration section gives four thermal coeffi-
ing frequency. Burst Mode operation and pulse-skipping
cients explicitly defined in JESD51-12; these coefficients
mode efficiencies can be reviewed in graph supplied in
are quoted or paraphrased in the following:
the Typical Performance Characteristics section.

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 LTM4619
applications information
1 θJA, the thermal resistance from junction to ambient, is As a practical matter, it should be clear to the reader that
the natural convection junction-to-ambient air thermal no individual or sub-group of the four thermal resistance
resistance measured in a one cubic foot sealed enclo- parameters defined by JESD51-12 or provided in the
sure. This environment is sometimes referred to as Pin Configuration section replicates or conveys normal
“still air” although natural convection causes the air to operating conditions of a µModule regulator. For example,
move. This value is determined with the part mounted in normal board-mounted applications, never does 100%
to a 95mm × 76mm PCB with four layers. of the device’s total power loss (heat) thermally con-
duct exclusively through the top or exclusively through
2 θJCbottom, the thermal resistance from junction to the bottom of the µModule package—as the standard defines
bottom of the product case, is determined with all of for θJCtop and θJCbottom, respectively. In practice, power
the component power dissipation flowing through the loss is thermally dissipated in both directions away from
bottom of the package. In the typical µModule regulator, the package—granted, in the absence of a heat sink and
the bulk of the heat flows out the bottom of the pack- airflow, a majority of the heat flow is into the board.
age, but there is always heat flow out into the ambient
environment. As a result, this thermal resistance value Within the LTM4619, be aware there are multiple power
may be useful for comparing packages but the test devices and components dissipating power, with a con-
conditions don’t generally match the user’s application. sequence that the thermal resistances relative to different
junctions of components or die are not exactly linear with
3 θJCtop, the thermal resistance from junction to top of respect to total package power loss. To reconcile this
the product case, is determined with nearly all of the complication without sacrificing modeling simplicity—but
component power dissipation flowing through the top of also not ignoring practical realities—an approach has been
the package. As the electrical connections of the typical taken using FEA software modeling along with laboratory
µModule regulator are on the bottom of the package, it testing in a controlled-environment chamber to reason-
is rare for an application to operate such that most of ably define and correlate the thermal resistance values
the heat flows from the junction to the top of the part. supplied in this data sheet: (1) Initially, FEA software is
As in the case of θJCbottom, this value may be useful used to accurately build the mechanical geometry of the
for comparing packages but the test conditions don’t LTM4619 and the specified PCB with all of the correct
generally match the user’s application. material coefficients along with accurate power loss source
4 θJB, the thermal resistance from junction to the printed definitions; (2) this model simulates a software-defined
circuit board, is the junction-to-board thermal resistance JEDEC environment consistent with JESD51-12 to predict
where almost all of the heat flows through the bottom power loss heat flow and temperature readings at different
of the µModule package and into the board, and is really interfaces that enable the calculation of the JEDEC-defined
the sum of the θJCbottom and the thermal resistance of thermal resistance values; (3) the model and FEA software
the bottom of the part through the solder joints and a is used to evaluate the LTM4619 with heat sink and airflow;
portion of the board. The board temperature is measured (4) having solved for and analyzed these thermal resis-
tance values and simulated various operating conditions
a specified distance from the package.
in the software model, a thorough laboratory evaluation
A graphical representation of the aforementioned ther- replicates the simulated conditions with thermocouples
mal resistances is given in Figure 7; blue resistances are within a controlled-environment chamber while operat-
contained within the µModule regulator, whereas green ing the device at the same power loss as that which was
resistances are external to the µModule package. simulated. The outcome of this process and due diligence
yields the set of derating curves shown in this data sheet.

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LTM4619
applications information
JUNCTION-TO-AMBIENT THERMAL RESISTANCE COMPONENTS

JUNCTION-TO-CASE (TOP) CASE (TOP)-TO-AMBIENT

RESISTANCE RESISTANCE

JUNCTION-TO-BOARD RESISTANCE
JUNCTION AMBIENT

JUNCTION-TO-CASE CASE (BOTTOM)-TO-BOARD BOARD-TO-AMBIENT

(BOTTOM) RESISTANCE RESISTANCE RESISTANCE

4619 F07
µMODULE DEVICE

Figure 7. Graphical Representation of JESD51-12 Thermal Coefficients

The 1.5V and 3.3V power loss curves in Figures 8 and 9 1.5V power loss curve at 5A, and the 1.35 multiplying
can be used in coordination with the load current derating factor at 120°C ambient. If the 95°C ambient temperature
curves in Figures 10 to 17 for calculating an approximate is subtracted from the 120°C junction temperature, then
ΘJA thermal resistance for the LTM4619 with various heat the difference of 25°C divided by 1.83W equals a 13.6°C/W
sinking and airflow conditions. The power loss curves are ΘJA thermal resistance. Table 2 specifies a 13.4°C/W value
taken at room temperature, and are increased with a 1.35 which is pretty close. The airflow graphs are more accurate
multiplicative factor at 120°C. The derating curves are plot- due to the fact that the ambient temperature environment is
ted with CH1 and CH2 in parallel single output operation controlled better with airflow. As an example in Figure 14,
starting at 8A of load with low ambient temperature. The the load current is derated to 5A at ~95°C with 400LFM of
output voltages are 1.5V and 3.3V. These are chosen to airflow and the power loss for the 12V to 3.3V at 5A output
include the lower and higher output voltage ranges for cor- is ~2.5W. The 2.5W loss is calculated with the ~1.85W room
relating the thermal resistance. Thermal models are derived temperature loss from the 12V to 3.3V power loss curve at
from several temperature measurements in a controlled 5A, and the 1.35 multiplying factor at 120°C ambient. If the
temperature chamber along with thermal modeling analysis. 95°C ambient temperature is subtracted from the 120°C
The junction temperatures are monitored while ambient junction temperature, then the difference of 25°C divided
temperature is increased with and without airflow. The by 2.5W equals a 10°C/W θJA thermal resistance. Table 2
specifies a 9.7°C/W value which is pretty close. Tables 2
power loss increase with ambient temperature change
and 3 provide equivalent thermal resistances for 1.5V and
is factored into the derating curves. The junctions are
3.3V outputs with and without airflow and heat sinking.
maintained at ~120°C maximum while lowering output
current or power while increasing ambient temperature. The derived thermal resistances in Tables 2 and 3 for the
The decreased output current will decrease the internal various conditions can be multiplied by the calculated
module loss as ambient temperature is increased. power loss as a function of ambient temperature to derive
temperature rise above ambient, thus maximum junction
The monitored junction temperature of 120°C minus
temperature. Room temperature power loss can be derived
the ambient operating temperature specifies how much
from the efficiency curves and adjusted with the above
module temperature rise can be allowed. As an example in
Figure 12, the load current is derated to 5A at ~95°C with ambient temperature multiplicative factors. The printed
no air or heat sink and the power loss for the 12V to 1.5V circuit board is a 1.6mm thick four layer board with two
at 5A output is about 1.83W. The 1.83W loss is calculated ounce copper for the two outer layers and one ounce
with the 1.35W room temperature loss from the 12V to copper for the two inner layers. The PCB dimensions are
95mm × 76mm. The BGA heat sinks are listed in Table 3.
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 LTM4619
applications information
Table 2. 1.5V Output
DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEATSINK ΘJA (°C/W)
Figures 10, 12 6, 12 Figure 8 0 none 13.4
Figures 10, 12 6, 12 Figure 8 200 none 11.2
Figures 10, 12 6, 12 Figure 8 400 none 9.7
Figures 11, 13 6, 12 Figure 8 0 BGA Heatsink 12.6
Figures 11, 13 6, 12 Figure 8 200 BGA Heatsink 10.0
Figures 11, 13 6, 12 Figure 8 400 BGA Heatsink 9.6

Table 3. 3.3V Output

DERATING CURVE VIN (V) POWER LOSS CURVE AIRFLOW (LFM) HEATSINK ΘJA (°C/W)
Figures 14, 16 12, 24 Figure 9 0 none 13.4
Figures 14, 16 12, 24 Figure 9 200 none 11.2
Figures 14, 16 12, 24 Figure 9 400 none 9.7
Figures 15, 17 12, 24 Figure 9 0 BGA Heatsink 12.6
Figures 15, 17 12, 24 Figure 9 200 BGA Heatsink 10.0
Figures 15, 17 12, 24 Figure 9 400 BGA Heatsink 9.6

HEATSINK MANUFACTURER PART NUMBER WEBSITE

Aavid Thermalloy 375424B00034G www.aavidthermalloy.com
Cool Innovations 4-050503P to 4-050508P www.coolinnovations.com

3.0 4.5

4.0
2.5
3.5

3.0
POWER LOSS (W)

2.0
POWER LOSS (W)

2.5
1.5
2.0

1.0 1.5

1.0
0.5
6V LOSS 0.5 12V LOSS
12V LOSS 24V LOSS
0 0
0 2 4 6 8 0 2 4 6 8
LOAD CURRENT (A) LOAD CURRENT (A)
4619 F08 4619 F09

Figure 8. Power Loss at 1.5V Output Figure 9. Power Loss at 3.3V Output

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LTM4619
applications information
8 8

7 7

6 6
LOAD CURRENT (A)

LOAD CURRENT (A)

5 5

4 4

3 3

2 2
6VIN TO 1.5VOUT 0LFM 6VIN TO 1.5VOUT 0LFM
1 6VIN TO 1.5VOUT 200LFM 1 6VIN TO 1.5VOUT 200LFM
6VIN TO 1.5VOUT 400LFM 6VIN TO 1.5VOUT 400LFM
0 0
70 75 80 85 90 95 100 105 110 115 70 75 80 85 90 95 100 105 110 115
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4619 F10 4619 F11

Figure 10. 6VIN to Figure 11. 6VIN to 1.5VOUT

1.5VOUT without Heat Sink with Heat Sink

8 8 8

7 7 7

6 6 6

LOAD CURRENT (A)

LOAD CURRENT (A)

LOAD CURRENT (A)

5 5 5

4 4 4

3 3 3

2 2 2
12VIN TO 1.5VOUT 0LFM 12VIN TO 1.5VOUT 0LFM 12VIN TO 3.3VOUT 0LFM
1 12VIN TO 1.5VOUT 200LFM 1 12VIN TO 1.5VOUT 200LFM 1 12VIN TO 3.3VOUT 200LFM
12VIN TO 1.5VOUT 400LFM 12VIN TO 1.5VOUT 400LFM 12VIN TO 3.3VOUT 400LFM
0 0 0
70 75 80 85 90 95 100 105 110 115 70 75 80 85 90 95 100 105 110 115 60 65 70 75 80 85 90 95 100 105 110
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4619 F12 4619 F13 4619 F14

Figure 12. 12VIN to 1.5VOUT Figure 13. 12VIN to 1.5VOUT Figure 14. 12VIN to 3.3VOUT
without Heat Sink with Heat Sink without Heat Sink

8 8 8

7 7 7

6 6 6
LOAD CURRENT (A)

LOAD CURRENT (A)

LOAD CURRENT (A)

5 5 5

4 4 4

3 3 3

2 2 2
12VIN TO 3.3VOUT 0LFM 24VIN TO 3.3VOUT 0LFM 24VIN TO 3.3VOUT 0LFM
1 12VIN TO 3.3VOUT 200LFM 1 24VIN TO 3.3VOUT 200LFM 1 24VIN TO 3.3VOUT 200LFM
12VIN TO 3.3VOUT 400LFM 24VIN TO 3.3VOUT 400LFM 24VIN TO 3.3VOUT 400LFM
0 0 0
60 65 70 75 80 85 90 95 100 105 110 40 50 60 70 80 90 100 40 50 60 70 80 90 100
AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C) AMBIENT TEMPERATURE (°C)
4619 F15 4619 F16 4619 F17

Figure 15. 12VIN to 3.3VOUT Figure 16. 24VIN to 3.3VOUT Figure 17. 24VIN to 3.3VOUT
with Heat Sink without Heat Sink with Heat Sink

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 LTM4619
Applications information
Safety Considerations • Place high frequency ceramic input and output capaci-
tors next to the VIN, PGND and VOUT pins to minimize
The LTM4619 modules do not provide galvanic isolation
high frequency noise.
from VIN to VOUT. There is no internal fuse. If required,
a slow blow fuse with a rating twice the maximum input • Place a dedicated power ground layer underneath the
current needs to be provided to protect each unit from unit.
catastrophic failure.
• To minimize the via conduction loss and reduce module
Layout Checklist/Example thermal stress, use multiple vias for interconnections
between top layer and other power layers.
The high integration of LTM4619 makes the PCB board
layout very simple and easy. However, to optimize its electri- • Do not put vias directly on the pads.
cal and thermal performance, some layout considerations • Use a separated SGND ground copper area for com-
are still necessary. ponents connected to signal pins. Connect the SGND
to PGND underneath the unit.
• Use large PCB copper areas for high current path, includ-
ing VIN, PGND, VOUT1 and VOUT2. It helps to minimize • Decouple the input and output grounds to lower the
the PCB conduction loss and thermal stress. output ripple noise.
Figure 18 gives a good example of the recommended layout.
TOP VIEW

PGND VIN PGND

L
CIN2 CIN1
K

1 2 3 4 5 6 7 8 9 10 11 12

COUT2 COUT1

VOUT2 PGND VOUT1

Figure 18. Recommended PCB Layout

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LTM4619
Typical Applications

VIN MODE/PLLIN INTVCC

4.5V TO 26.5V VIN FREQ/PLLFLTR
CIN 11.5k 19.1k
10µF VFB1 VFB2
×2 C1 C2
22pF COMP1 COMP2 22pF
VOUT1 VOUT2
VOUT1 VOUT2
5V/4A LTM4619 3.3V/4A
COUT1 COUT2
100µF TK/SS1 TK/SS2 100µF
0.1µF RUN1 RUN2 0.1µF

100k R1 (OPT*)
INTVCC PGOOD EXTVCC VIN
SGND PGND
PGOOD 4619 F19

*STUFF WITH A 0Ω RESISTOR FOR 4.5V < VIN < 5.5V

Figure 19. Typical 4.5V to 26.5V Input, 5V and 3.3V Outputs at 4A Design

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 LTM4619
TYPICAL applications
EXTERNAL 5V SUPPLY FOR
INPUT VOLTAGE BELOW 5.5V
R1 R2
MODE/PLLIN INTVCC EXTVCC 3.83k 1.21k
VIN
4.5V TO VIN FREQ/PLLFLTR
CIN 121k 68.1k
26.5V 10µF VFB1 VFB2
×2 C1 C2
22pF COMP1 COMP2 22pF
VOUT1 VOUT2
VOUT1 VOUT2 1.5V/4A
1.2V/4A LTM4619
COUT1 COUT2
100µF TK/SS1 TK/SS2 100µF
×2 0.1µF RUN1 RUN2 0.1µF ×2

100k
INTVCC PGOOD
SGND PGND
4619 F20
PGOOD

Figure 20. Typical 4.5V to 26.5V Input, 1.2V and 1.5V

Outputs at 4A Design with Adjusted Frequency at 500kHz

MODE/PLLIN EXTVCC INTVCC

VIN
VIN FREQ/PLLFLTR
6V TO
CIN
26.5V COMP1 VFB1
10µF
C1
COMP2 VFB2 51pF R1
TK/SS1 LTM4619 VOUT1 5.76k

TK/SS2 VOUT2 VOUT2

C3 C4
+ C5
5V/8A
0.1µF PGOOD RUN2 100µF 330µF
RUN1
SGND PGND
4619 F21

Figure 21. Output Paralleled LTM4619 Module for 5V Output at 8A Design

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For more information www.linear.com/LTM4619 21

LTM4619
TYPICAL applications
CLOCK SYNC, 0° PHASE

VIN MODE/PLLIN INTVCC

6V TO 26.5V VIN FREQ/PLLFLTR
+ CIN1 CIN2
330µF 10µF VFB1 VFB2
2x R3 C10 C11 R4
11.5k 22pF COMP1 COMP2 22pF 19.1k
VOUT2
VOUT1 LTM4619
VOUT1 VOUT2 3.3V/4A
5V/4A + C2 C3 VOUT1 C4 + C5
22µF TK/SS1 TK/SS2 22µF
220µF 220µF
C1 R1
0.1µF RUN1 RUN2
60.4k
PGOOD EXTVCC
2 PHASE OSCILLATOR SGND PGND R2
19.1k
V+ OUT1 ON/OFF
C3 GND LTC6908-2 OUT2
R9 0.1µF CLOCK SYNC, 90° PHASE
143k SET MOD
MODE/PLLIN INTVCC
VIN FREQ/PLLFLTR

VFB1 VFB2
R7 C12 C13 R8
28k 22pF COMP1 COMP2 22pF 48.7k
VOUT4
VOUT3 LTM4619
VOUT1 VOUT2 1.8V/4A
2.5V/4A + C9 C8 VOUT1 VOUT1 C6 + C7
22µF TK/SS1 TK/SS2 22µF
220µF 220µF
R10 R5
RUN1 RUN2
60.4k 60.4k
PGOOD EXTVCC
R11 SGND PGND R6
28k 4619 F22
48.7k

Figure 22. 4-Phase, Four Outputs (5V, 3.3V, 2.5V and 1.8V) with Tracking

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22 For more information www.linear.com/LTM4619

 LTM4619
Package Description
PACKAGE ROW AND COLUMN LABELING MAY VARY
AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
LAYOUT CAREFULLY.
Pin Assignment Table 4
(Arranged by Pin Function)

PIN NAME PIN NAME PIN NAME PIN NAME

A1 VOUT2 D1 VOUT2 G1 PGND K1 VIN
A2 VOUT2 D2 VOUT2 G2 PGND K2 VIN
A3 VOUT2 D3 VOUT2 G3 PGND K3 VIN
A4 PGND D4 PGND G4 PGND K4 VIN
A5 PGND D5 PGND G5 PGND K5 TK/SS2
A6 PGND D6 PGND G6 PGND K6 VFB2
A7 PGND D7 PGND G7 PGND K7 VFB1
A8 PGND D8 PGND G8 PGND K8 TK/SS1
A9 PGND D9 PGND G9 PGND K9 VIN
A10 VOUT1 D10 VOUT1 G10 PGND K10 VIN
A11 VOUT1 D11 VOUT1 G11 PGND K11 VIN
A12 VOUT1 D12 VOUT1 G12 PGND K12 VIN
B1 VOUT2 E1 PGND H1 PGND L1 VIN
B2 VOUT2 E2 PGND H2 PGND L2 VIN
B3 VOUT2 E3 PGND H3 SW2 L3 VIN
B4 PGND E4 PGND H4 PGND L4 VIN
B5 PGND E5 PGND H5 PGOOD L5 VIN
B6 PGND E6 PGND H6 SGND L6 COMP2
B7 PGND E7 PGND H7 SGND L7 COMP1
B8 PGND E8 PGND H8 MODE/PLLIN L8 VIN
B9 PGND E9 PGND H9 PGND L9 VIN
B10 VOUT1 E10 PGND H10 SW1 L10 VIN
B11 VOUT1 E11 PGND H11 PGND L11 VIN
B12 VOUT1 E12 PGND H12 PGND L12 VIN
C1 VOUT2 F1 PGND J1 VIN M1 VIN
C2 VOUT2 F2 PGND J2 VIN M2 VIN
C3 VOUT2 F3 PGND J3 VIN M3 VIN
C4 PGND F4 PGND J4 EXTVCC M4 VIN
C5 PGND F5 PGND J5 RUN2 M5 VIN
C6 PGND F6 INTVCC J6 SGND M6 VIN
C7 PGND F7 PGND J7 SGND M7 VIN
C8 PGND F8 PGND J8 FREQ/PLLFLTR M8 VIN
C9 PGND F9 PGND J9 RUN1 M9 VIN
C10 VOUT1 F10 PGND J10 VIN M10 VIN
C11 VOUT1 F11 PGND J11 VIN M11 VIN
C12 VOUT1 F12 PGND J12 VIN M12 VIN

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For more information www.linear.com/LTM4619 23

24
LGA Package
144-Lead (15mm × 15mm × 2.82mm)
(Reference LTC DWG # 05-08-1816 Rev C) DETAIL A
SEE NOTES
3x, C (0.22 x45°) 7
A 12 11 10 9 8 7 6 5 4 3 2 1
aaa Z
LTM4619

b L

H
MOLD
CAP SUBSTRATE
G
F
D
F
H1
H2
E
Package Description

Z
D

bbb Z
DETAIL B
C

B
e
PIN “A1” 0.630 ±0.025 SQ. 143x
A
CORNER eee S X Y
4 X DIA 0.630
SEE NOTES b e PAD 1
E Y
DETAIL B 3 G
PACKAGE TOP VIEW PACKAGE SIDE VIEW

aaa Z
PACKAGE BOTTOM VIEW

NOTES:
DETAIL A 1. DIMENSIONING AND TOLERANCING PER ASME Y14.5M-1994
2. ALL DIMENSIONS ARE IN MILLIMETERS

0.0000

6.9850
5.7150
4.4450
3.1750
1.9050
0.6350
0.6350
1.9050
3.1750
4.4450
5.7150
6.9850
3 BALL DESIGNATION PER JESD MS-028 AND JEP95
6.9850 4 DETAILS OF PIN #1 IDENTIFIER ARE OPTIONAL,
DIMENSIONS
BUT MUST BE LOCATED WITHIN THE ZONE INDICATED.
5.7150 SYMBOL MIN NOM MAX NOTES THE PIN #1 IDENTIFIER MAY BE EITHER A MOLD OR
A 2.72 2.82 2.92 MARKED FEATURE

For more information www.linear.com/LTM4619

4.4450
b 0.60 0.63 0.66
5. PRIMARY DATUM -Z- IS SEATING PLANE
3.1750 D 15.00
E 15.00 6. THE TOTAL NUMBER OF PADS: 144
1.9050
e 1.27 7 PACKAGE ROW AND COLUMN LABELING MAY VARY
0.6350 F 13.97
! AMONG µModule PRODUCTS. REVIEW EACH PACKAGE
0.0000 LAYOUT CAREFULLY
G 13.97
0.6350
H1 0.27 0.32 0.37
1.9050 H2 2.45 2.50 2.55
3.1750
aaa 0.15
bbb 0.10
4.4450
eee 0.05
5.7150 TOTAL NUMBER OF LGA PADS: 144
LTMXXXXXX
µModule
6.9850
COMPONENT
PIN “A1”
SUGGESTED PCB LAYOUT
TOP VIEW
TRAY PIN 1
BEVEL
PACKAGE IN TRAY LOADING ORIENTATION LGA 144 1112 REV C

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 LTM4619
Revision History (Revision history begins at Rev B)

REV DATE DESCRIPTION PAGE NUMBER

B 08/13 Added “or single 8A” to Description 1
Changed MODE to MODE/PLLIN 8
Changed GND to PGND 22
Added Design Resources 24
C 05/14 Update Order Information Table 2
Update thermal resistance figures 2, 17
Update Thermal Considerations Section 14, 15, 16

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Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-
For more
tion that the interconnection information
of its circuits www.linear.com/LTM4619
as described herein will not infringe on existing patent rights. 25
LTM4619
Package Photograph

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Design Resources
SUBJECT DESCRIPTION
µModule Design and Manufacturing Resources Design: Manufacturing:
• Selector Guides • Quick Start Guide
• Demo Boards and Gerber Files • PCB Design, Assembly and Manufacturing Guidelines
• Free Simulation Tools • Package and Board Level Reliability
µModule Regulator Products Search 1. Sort table of products by parameters and download the result as a spread sheet.
2. Search using the Quick Power Search parametric table.

TechClip Videos Quick videos detailing how to bench test electrical and thermal performance of µModule products.
Digital Power System Management Linear Technology’s family of digital power supply management ICs are highly integrated solutions that
offer essential functions, including power supply monitoring, supervision, margining and sequencing,
and feature EEPROM for storing user configurations and fault logging.

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26 Linear Technology Corporation

LT 0514 REV C • PRINTED IN USA

1630 McCarthy Blvd., Milpitas, CA 95035-7417

For more information www.linear.com/LTM4619
(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com/LTM4619  LINEAR TECHNOLOGY CORPORATION 2009