DEPARTMENT OF COMPUTER ENGINEERING

Subject: Microprocessor
Class: SE A/B/C Div: A/B/C Semester: IV

Questions on Module-4

1. Discuss in brief the protection mechanism of 80386DX (5M, May-2023)

2. Explain the Register organization of 80386 (10M, May-2023)
3. Differentiate between real Mode, Virtual Mode and Protected Mode of
80386 Processor (5M, Dec-2022)
4. Explain the segment descriptor of 80386 processor (10M, Dec-2022)
5. Explain the FLAG Register of 80386 Processor (10M, Dec-2022)
6. Explain descriptors and paging mechanism in protected mode of 80386
(10M, May-2022)
7. Explain the protection mechanism of 80386 with diagram (10M, May-
2022)
8. Draw and explain the internal architecture of 80386 microprocessor?
(5M, May-2021)
9. Explain the operating modes of 80386? (5M, May-2021)
1. & 7. Discuss in brief the protection mechanism of 80386DX (5M, May-
2023)
When you are trying to access a memory location, the first thing that happens
is address translation, so during address translation protection mechanism
takes place
There are three checks in protection:
1. Limit Check: Here the offset is compared with the limit of the segment.
80386 works on 32-bit no’s, it also works on 16 bit no’s and 8 bit no’s
8 bit: Mov CL,[2000] : Here you are trying to access only location 2000, if the
limit is also 2000, then also it is fine, you are accessing the last location of the
segment Offset ≤ Limit
16 bit: Mov CX,[2000] : Here if the limit is 2000 and you are trying to access
location 2000 and 2001,then there is a problem, so for 16-bit operations Offset
≤ Limit-1
32 bit: Mov ECX,[2000] : Here you want to access 4 memory locations. so
for 32-bit operations Offset ≤ Limit-3
2. Type Check: Suppose you have given your address in DS and ESI, so you
want to access data segment and that segment has a descriptor. In the
descriptor, the type field is S=0 → System segment, S=1 → User segment.
Here S=1, E=0, ED=0, W=0 →User segment, data segment , Read operation.
This is called type check

S E ED W

E C R

3. Privilege Check: PL0 →Highest; PL3 → Lowest, access is given

outwards, i.e. PL0 can access PL0,PL1,PL2,PL3.
Your program PL is compared with the segment PL that you want to access
Requester Privilege Level(RPL): Your privilege is given in the segment
register (last 2 bits) and the segment privilege level that you want to access is
given in the descriptor(DPL)
CPL: Actually, the program that you are writing is a code segment and this
code segment has a descriptor and hence descriptor privilege level(DPL). So
this DPL of the code segment is your actual privilege level(RPL). CPL is
present in current code segment descriptor.
Rules for access: Target DPL ≥ 𝑀𝑎𝑥(𝐶𝑃𝐿, 𝑅𝑃𝐿)𝑜𝑟 Target DPL ≥ 𝐸𝑃𝐿
2. Explain the Register organization of 80386 (10M, May-2023)
3. Differentiate between real Mode, Virtual Mode and Protected Mode of
80386 Processor (5M, Dec-2022)
 Real Mode Protected Mode

16- bit operations, Default mode 32- bit operations, Protected mode
after reset entered after making LSB of CR0
(PE=1)

Four 16-bit General Purpose Four 32-bit General Purpose

registers(AX,BX,CX,DX) registers(EAX,EBX,ECX,EDX)

Flag Register: 16-bit Flag Register: 32-bit(EFLAG)

Control register: Only LSB of CR0 All four control registers are available
is available in real mode CR0,CR1,CR3,CR4

PA = Seg Add X 10H + Offset add Complex segment and page

translation

16 bit offset, therefore maximum 32 bit offset, therefore maximum size

size of Segment is 64 KB of Segment is 4 GB

Memory range: Size of memory Total physical memory 232 = 4 GB

available in real mode is 1MB and
has address range 00000H
……FFFFFH, just like in 8086

In the Virtual mode of 80386 we can go to Virtual 8086 mode by making

VM bit in flag register equal to 1, here 8086 programs can run and by making
VM=0, we can go back to protected mode.

4. Explain the segment descriptor of 80386 processor (10M, Dec-2022)

• Solution: The virtual address is given by a segment register(16) and an offset
register(32)
• First the segment register is examined. It gives a 13 bit selector which leads to
a descriptor in LDT or in GDT, depending upon the Ti bit. If Ti=1 then LDT,
if Ti=0 then GDT
• Using the specified selector the descriptor is accessed from LDT or GDT
• This descriptor is copied into an on chip segment descriptor cache. It is of 8
bytes.
• There is a bit “P” in the descriptor . If P=1, the segment is present in the
physical memory
 • Then the base address (Starting address) of the segment is available in the
descriptor. If P = 0 the segment is not present in the physical memory
• Now the memory management unit copies the segment from virtual memory
to physical memory makes the “p” bit = 1 in the descriptor and stores its base
address into the descriptor for further use.

Bit Name Function

Position

7 P(Present) P=1 : Segment is present in Physical memory

P=0 : Segment is not present in Physical memory

6-5 Descriptor It gives the privilege level of the segment that we

Privilege access
Level(DPL-
0,1,2,3)
4 Segment S=1 ; Code or data segment(programmer)
Descriptor(S)
S=0 ; System Segment

3 Executable(E) E=0 descriptor type is data segment If data

seg(S=1,
E=0)
ED ED = 1 ; Stack segment
ED = 0 ; Data segment
2

W W=1 ; You can Read and write

W=0 ; You can only Read
1

3 Executable(E) E=1 ; Code segment If code

seg(S=1,
2 C(Confirmati C =1 ; It allows invert access for privilege level E=1)
on) momentarily

1 R(Readable) R=1 ; Read and Execute

R=0 : Execute

0 Accessed A=1 ; Segment has been accessed

A=0 ; Segment has not been accessed

5. Explain the FLAG Register of 80386 Processor (10M, Dec-2022)

As seen from the diagram, the lower 12 bits(11….0) of EFLAGS are same as
those in 8086. These are the only flags available when 𝜇𝑃 is in real Mode.
The additional 5 Flags are only available once 𝜇𝑃 enters protected mode by
making PE bit =1, in CR0 register.
• Virtual 8086 Mode: This flag is used to make 80386 operate in virtual
Mode(V86). If VM = 1, enter virtual 8086 mode. V86
mode is basically used to run 8086 programs in a faster environment of 80386
using multitasking and protection. V86 mode can only be entered if 𝝁𝑷 is
working in Protected Mode. Once in virtual 8086 Mode, we can return back
to protected Mode by making VM = 0. A special program called Virtual
8086 Monitor is responsible for switching back and forth between Protected
mode and real mode.
• RF(Resume Flag): Resume Flag is useful during debugging. If RF = 1,
then any debug fault in the next instruction will be ignored. RF is
automatically reset after the next instruction. In 80386 𝜇𝑃, some fault
handlers(ISRs) return back to the same instruction that caused the fault instead
of returning back to the next instruction. By keeping RF=1, we ensure that the
program resumes after such a fault instead of repeatedly generating breakpoint
faults on the same instruction
• NT (Nested Task): This flag applies to protected mode. NT is set to indicate
that the execution of this task is nested within another task. If set , it indicates
that the current nested ttask’s Task State Segment(TSS) has a valid back link
to the previous task’s TSS.

6. Explain descriptors and paging mechanism in protected mode of 80386

(10M, May-2022)
The virtual memory space is divided into equal size blocs of 4 KB called “Pages”
The physical memory (RAM) is also divided into equal size blocks of 4KB called
“Page Frames”
As physical memory is of 4GB and page size is 4KB there are total ( No. of Pages
4𝐺𝐵
= = 1MB), 1million(220) pages in the physical memory
4𝐾𝐵

A page from virtual memory is loaded into any available page frame of physical
memory
Since a page of virtual memory can be loaded into any page of physical memory, a
“page table” is required to give the mapping between virtual memory page number
and physical memory page frame number.
Page table tells which page of virtual memory is present in which page frame of
physical memory
4𝐺𝐵
But as there are too many page frames( No. of frames = 4𝐾𝐵 = 1MB), to search
any page frame from 1MB of frames it will take long time
Therefore there are 1K(210) page entries in a page table and there are 1 K (210)
such page tables
Each page table is of 4KB and has 1K “Page Table Entries”(PTEs) each of size 4
bytes. Each PTE gives information about a page frame
The PTE has following information: 20 bit page frame address: Gives the upper
20 bits of the starting address of the page frame, lower 12 bits are 0….0, as the
page is of 4 KB and starts from a 4KB aligned location, these 20 bits are used to
give the information about access and privilege
D: Dirty bit indicates whether the page has been modified(1) or not(0)
A: Access bit tells whether the page has been accessed or not(1= accessed)
U/S: User or supervisor and R/W: Read or Read and Write give protection
information
If P=1 then the page is present and the 20 bit address field is valid, else the page is
not present
Information about all the page tables is stored in the “Page Directory”
The page directory is of 4KB and has 1K”Page Directory Entries”(PDEs) each of size
4 bytes, each PDE gives information about page table
• The PDE has following information: 20 bit page table address: Gives the
upper 20 bits of the starting address of the page table, lower 12 bits are 0….0,
as the page is of 4 KB and starts from a 4KB aligned location
• D: Dirty bit indicates whether the page has been modified(1) or not(0)
• A: Access bit tells whether the page has been accessed or not(1= accessed)
• U/S: User or supervisor and R/W: Read or Read and Write give protection
information
• If P=1 then the page is present and the 20 bit address field is valid, else the
page is not present
• The page directory is of 4KB and begins from a 4 KB aligned location
• The address of the page directory is given by the PDBR(Page Directory Base
Register) field in CR3

8. Draw and explain the internal architecture of 80386 microprocessor?

(5M, May-2021)
80386 is 32 bit µP / 32 bit ALU, it has 32 bit data bus (4 Memory Banks), 32
bit address bus and 232 = 4 GB memory and Clock: 16MHz, 20 MHz, 25
MHz, 33 MHz It can operates at SX (single Execution Speed) => 16 bit data
bus and DX (Double Execution speed) => 32 bit data bus. It works in 3
stage pipeline (Fetch + Decode + Execute) , 64TB Virtual Memory,
Segmentation, Paging and Protection Mechanism (PL0, PL1, PL2, PL3) also
Dedicated hardware for Multi-tasking (windows want a multi-tasking
environment). The architecture of 80386 is as shown below:

BUS INTERFACE UNIT

• The bus unit is responsible for transferring data in and out of the 𝜇𝑃
• It is connected to the external memory and I/O devices using the
system bus 80386 (Address + Data + Control)
• It gets request from prefetch Unit for fetching instruction and from
execution Unit for transferring data.
• If both request occur simultaneously preference is given to Execution
unit.
Prefetch Unit
• The prefetch unit fetches further instructions in advance to implement
pipelining
• It fetches the next 16 bytes of the program and stores it into the
prefetch queue
• It refills the queue when at least 4 bytes are empty as 80386 has a 32
bit data bus
• During a branch, the instructions in the queue are invalid and hence
are discarded.
Decode Unit
 • 80386 𝜇𝑃 has a separate unit for decoding instructions called the
Decode unit
• It decode the next 3 instructions and keep them ready in the decode
queue.
• The decoded instructions are stored in Micro-Coded form
• During the branch, the instructions in the queue are invalid and hence
discarded
Execution Unit
• Execution unit performs the main task of executing instructions
• Normally execution requires Arithmetic or logical operations performed
by a 32-bit ALU
• It also has dedicated circuits for 32 bit multiplication and division
• A 64 bit barrel shifter is also provided for faster shifts during
multiplication and division
• Operands for the ALU can either be provided in the instruction, or can be
taken from memory or could be taken from the 32-bit registers like
EAX,EBX etc.
• Additionally there is a 32-bit flag register(EFLAG) giving the status of the
current result
Memory Unit
• The memory unit converts Virtual address (Logical address)to physical
address
• 80386 implements 64 TBytes of Virtual memory using segmentation and
paging. Hence the memory unit is sub-divided into Segmentation unit and
Paging Unit
• Segmentation is compulsory, while Paging is optional
• The Segmentation unit converts Logical address into a Linear address
• The Paging unit converts a Linear address into a Physical address.
• If paging is not used, then Linear address itself is the Physical address

9. Explain the operating modes of 80386? (5M, May-2021)

 80386 can operate in 3 modes
1. Real Mode
2. Protected mode
3. Virtual Mode
1. Real Mode: It is the default mode selected when 80386 is reset. In real
mode, 80386 does not behave like a 80386 but it behaves like a 8086, it just
works like a fast 8086 due to 20 MHz clock of 80386. All the registers are just
like 8086, even the memory used is only 1MB, just like 8086. PA = Segment
address X 10H + Offset address. This mode is basically used to run BIOS on
reset.
80386 starts in real mode and it creates the environment for protected mode
i.e. it initializes all the registers and tables like GDT,LDT page table etc. so
that the protected mode can work
Once the required registers are initialized, we can switch to protected mode
by making the protection Enable (PE bit) =1 in CR0(Control register 0)
We can’t switch back to real mode from protected mode. But we can go to
Virtual 8086 mode by making VM bit in flag register 1, here 8086 programs
can run and by making VM=0, we can go back to protected mode

• 80386 𝜇𝑃 provides a very advanced mode of operations called the protected

Mode. In protected Mode, 80386 𝜇𝑃 provides dedicated hardware to prevent
user programs from affecting other user programs and also safeguards the
operating system from being affected by user programs.
• There are four privilege levels, assigned to programs and data to define their
privileges.
• Level 0: This level is assigned to the operating system Kernal(Main part
of the operating system). It is the most privileged level. Any program at this
level can access all the data at any privilege level, whereas a data at this
privilege level can only be accessed by a program at privilege level 0.
• Level 1: This level is assigned to the system Services such as File
Handling, Device Drivers. It is the second most privilege level. Any
program at this level can access the data at any privilege level which is lower
than this level(numerically higher), whereas a data at this privilege level can
only be accessed by a program at privilege level 0 or privilege level 1.
• Level 2: This level is assigned to the Custom Extensions of the OS. It is
the third most privilege level. Any program at this level can access the data
at any privilege level which is lower than this level(numerically higher),
whereas a data at this privilege level can only be accessed by a program at
privilege level 0 or privilege level 0,1 or 2.
• Level 3: This level is assigned to all the user Application and Programs. It
is the least privilege level. Any program at this level can normally access the
data at privilege level 0, whereas a data at this privilege level can only be
accessed by a program at privilege level 0 or privilege level 0…3.