Lab 03
Layout of Basic Gates and a Complex Gate using CMOS 0.25
micron Technology in Microwind.
1. Objectives
In this lab students will design and implement the layouts of
different CMOS gates, which includes NAND, AND NOR, OR and a Complex Gate. The
tool used in this lab is Microwind.
The tasks given in the lab include,
• Design of CMOS NAND, AND, NOR, OR Gates and a Complex Gate.
• Layout Design using the tool.
• Gate delay, area, power and current analysis and the effects of transistor
sizing on these parameters.
Tool used: Microwind
2. Lab Description:
a) NAND Gate
As per discussion and design on white board in the Lab, a NAND gate can be
implemented using four FETS i.e. two pFETs and two nFETs as the inputs of the gate
is two. pFETs are connected in parallel while nFETs are connected in series, Vdd is
supplied to the parallel combination of pFETs while the series combination of nFETs
is grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output
f is obtained from the common junction of these series and parallel combinations as
illustrated in NAND circuit under the heading of Design Diagram/Circuit.
b) NOR Gate
As per discussion and design on white board in the Lab, a NOR gate can be
implemented using four FETS i.e. two pFETs and two nFETs as the inputs of the gate
is two. pFETs are connected in series while nFETs are connected in parallel, Vdd is
supplied to theseries combination of pFETs while the parallel combination of nFETs
is grounded. Inputs a & b are applied to the gate terminals of all FETs, and the output
f is obtained from thecommon junction of these parallel and series combinations as
illustrated in NOR circuit under the heading of Design Diagram/Circuit.
c) Complex Gate
The expression for the complex gate is given as under
As per discussion and design on white board in the Lab, this complex gate can be
implemented as under
For pFETs Array
Group1: Three pFETs with inputs “c”, “d” and “d” at its gate terminals are connected in
parallel.
Group2: Two pFETs with inputs “a” and “d” are in parallel and is connected in series
with Group1
For nFETs Array
Group1: Three nFETs with inputs “c”, “d” and “d” at its gate terminals are connected in
series.
Group2: Two nFETs with inputs “a” and “d” are in series and is connected in parallel
with Group1
Design/ Diagram/Circuit
(a) Symbol, Truth Table and CMOS circuit of NAND Gate
(b) Symbol, Truth Table and CMOS circuit of NOR Gate
(c) Expression and CMOS circuit of a Complex Gate
1. Open Microwind and select the foundry cmos025.
2. Save the design as “Save as” as “Lab03”, and save the design frequently during the
Lab session.
3. Draw the layout of nMOS using MOS Generator
4. Draw the layout of pMOS using MOS Generator by setting the appropriate width of
pMOS.
5. Connect the two transistors using Metal 1 as per design.
6. Draw the rails of V DD and ground rails above and below.
7. Connect the nWell to V DD
8. Check the design using DRC for any design rule violation and correct the design in
case of error, again run the DRC and check for errors. Or run the DRC after each change
in the layout.
9. Check for Electrical connections to be valid.
10. Add inputs and outputs to the design; also add virtual capacitance at the output in
your design.
11. Simulate the Design. Observe the values of configuration delay, gate delay, power,
current, VTC, and area.
12. Repeat the design using for different values of transistor’s dimensions, supply
voltages. And observe the changes in configuration delay, gate delay, power, current,
VTC, and area carefully. Make a conclusion of your observations.
5. Lab Tasks:
Task 1: Design the layout of 2- Input NAND Gate.
Task 2: Design the layout of 2- Input AND Gate, Simulate the Design. Observe the
values of configuration delay, gate delay, power, current, VTC, and area.
Task 3: Design the layout of 2- Input NOR Gate, Simulate the Design. Observe the
values of configuration delay, gate delay, power, current, VTC, and area.
Task 4: Design the layout of 2- Input OR Gate, Simulate the Design. Observe the
values of configuration delay, gate delay, power, current, VTC, and area.
Task 5: Design the layout of Complex Gate, Simulate the Design. Observe the values
of configuration delay, gate delay, power, current, VTC, and area..
