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STLD Imp For 3-4-5 Uni

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Siva Nagendra
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50 views1 page

STLD Imp For 3-4-5 Uni

Uploaded by

Siva Nagendra
Copyright
© © All Rights Reserved
We take content rights seriously. If you suspect this is your content, claim it here.
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Important Questions for STLD (UNIT-III,IV&V)

Short Answer Questions:


1. What is a PLD? What is the principal advantage of a PLD?
2. Draw the state diagram of modulo-4 up/down counter
3. Define encoder? List out the applications of it?
4. Explain the operation of a SR flip-flop?
5. What is the mealy machine?
6. Realize a single bit comparator?
7. What are the advantages and disadvantages of using a PROM as a PLD?
8. Draw and explain active low S-R latch
9. What is the Moore machine?
10. Why a multiplexer is called a data selector? Draw the 2x1 MUX.
11. Draw the basic architecture of a PAL?
12. What are the various methods used for triggering flip-flops? Explain with examples.
13. Compare the Moore and Mealy machines?
14. Define combinational circuit?
15. What is PAL?
16. List out the application of counters?
17. List out the applications of multiplexers.
18. Design a 4*2 PROM with AND-OR gates.
19. Draw the circuit diagram of a shift register and list its types
20. What is Mealy state diagram?
21. What is an excess-3 adder circuit and draw its logic diagram?
22. Write the need for preset and clear inputs.
23. Define state assignment.
24. Define state reduction.
25. Give the comparison between PROM, PLA and PAL
Essay Answer Questions
1. What is decoder? Construct 3*8 decoder using logic gates and truth tables.
2. Explain the operation of carry look-a-head adder.
3. Explain the operation of priority encoder with a neat diagram.
4. Implement the following switching function F(A,B,C,D)=Σm(0,2,3,6,8,9,12,14) using the multiplexer
5. Realize the function f(A,B,C,D) = ∑ (1,2,5,8,10,14)+d (6,7,15) using i) 8:1 MUX ii) 4:1 MUX
6. Implement the following multiple output combinational logic circuit using a 4 line to 16 line decoder:
F1= ∑m (0, 1, 4, 7, 12, 14, 15) F2= ∑m (1, 3, 6, 9, 12)
F3= ∑m (2, 3, 7, 8, 10) F4= ∑m (1, 3, 5)
7. Draw the logic diagram of a 2 to 4 line decoder using NOR gates including an enable input
8. Design an arithmetic circuit that adds 2 binary digits. The circuit should have 2 outputs, one for the sum and the other for
the carry. Implement the same in a PAL
9. Perform the realization of half adder and full adder using decoders and logic gates.
10. Derive the PLA programming table for the combinational circuit that squares a 3-bit number
11. Implement f(A,B,C,D)=Σ(0,1,3,5,6,8,9,11,12,13) using PROM and explain its procedure.
12. Define finite state machine? Explain about it.
13. Draw the circuit diagram of 4-bit Johnson counter using D-flip flop and explain its operation with the help of bit pattern.
14. Explain the analysis of clocked sequential circuits.
15. Draw a state diagram of a sequence detector which can detect 110.
16. Implement f(A,B,C,D)=Σ(0,1,4,5,6,9,10,12,13,15) using PLA and explain its procedure.
17. Draw the logic diagram of a JK flip-flop and using excitation table explain its operation.
18. Draw and explain in detail about registers.
19. Draw and explain the logic diagram of Moore model
20. Derive the PLA programming table for the combinational circuit that squares a 3-bit number
21. Write the conversion procedure of the flip-flops. Convert T flip-flop to JK flip flop
22. Explain the state reduction technique.
23. Draw and explain 4-bit universal shift register.
24. Design a sequence detector circuit to detect a serial input sequence of 1010.it should produce an output 1 when the input
pattern has been detected.
25. Design a sequence detector circuit to detect a serial input sequence

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