‘Winter Semester Examination ~ Dec - 2019 DR. BABASAHEB AMBEDKAR TECHNOLOGICAL UNIVERSITY, LONERE — RAIGAD -402 103) (Branch: B.Tech. (Computer Engineering ) jem: Subject with Subject Code: omputer Architecture & Organization[BTCOC304] Marks:60 IDate:- 17-12-2019 [Time: 3 Hrs linstruetions to the Student LEach question carries 12 marks. 2. Attempt any five questions of the following. 3, Illustrate your answers with neat sketches, diagram ete., wherever necessary. 4, If some part or parameter is noticed to be missing, you may appropriately assume it and should mention | it clearly. va i Q.1 [Solve any following questions. / (A) |What, in general terms, is the distinction between computer organization and computer} 06 farchitecture? __ I |B) [Explain the computer: the top level structure with structural component with neat sketch | 06 diagram. _ — - ~ @2Z_ [Attempt the following questions. (A) [Enlist and explain any two addressing modes. Given the following memory values anda one-| 06 | iddress machine with an accumulator, what values do the following instructions load into the | laccumutator? Word 20 contains 40. * Word 30 contains 50, * Word 40 contains 60 * Word 50 contains 70 | LOAD IMMEDIATE 20 | LOAD DIRECT 20 | | LOAD INDIRECT 20 | LOAD IMMEDIATE 30 Z (8) 1. [Convert the following instruction into Accumulator based CPU, Register based CPU. | 03 |__| Instruction:(A*B)-(R+Z)T 7 = j | TL [is RISC better than CISC? Mlustrate your answer with example of processor. B Q3__|Attempt the following questions. i= — (A) (Given x = 1011 and y = 1001 in twos complement notation (i.e., x = -5, y =~ 7), draw and pera -ompute the product p = x * y with Booth’s algorithm flowchart. | {B) Show how the following floating-point additions are performed (where significants are fa (C1B384B90A6F2E4613757ABODIDSBDDB[runcated to 4 decimal digits). Show the results in normalized form a, $.566 x10 * 7.777 « 10° b, 3.344 x10! + 8.877 x10? ¢.6.21%10°#8.877%10! [Attempt the following ques [What are the differences among direct mapping, associative mapping, and set-associative mapping?A set-associative cache consists of 64 lines, or slots, divided into four-line sets. Main {memory contains 4K blocks of 128 words each, Show the format of main memory addresses. ja 06 [Elaborate the concept of SRAM and DRAM memory with typical memory cell structure. 06 \Attempt the following questions. (A) |What is the overall function of a processor's control unit?A stack is implemented.show the sequence of micro-operations for popping: pushing the stack PUSH 10 PUSH 70 uss ‘ADD USH 20 sus MUL (B) Q6 |What is the difference between a hardwired implementation and a microprogrammed iplementation of a control unit? 06 [Attempt any (wo questions. (A) (B) lin virtually all systems that include DMA modules, DMA access to main memory is givei priority than CPU access to main memory. Why? 06 |What is the meaning of each of the four states in the MESI protocol? Can you foresee any [problem with the write-once cache approach on bus-based multiprocessors? If so, suggest a Ksolution, © lHow does instruction pipelining enhance system performance? Elaborate your answer using IRISC instruction stages. 06 pers aeeeanaaeanaaTeRNaTE (C7BS84B90A6F2E4613757AB6DID6BDDB.