AOZ5310NQI

High-Current, High-Performance
DrMOS Power Module

General Description Features

The AOZ5310NQI is a high efficiency synchronous buck • 2.5 V to 18 V power supply range
power stage module consisting of two asymmetrical • 4.5 V to 5.5 V driver supply range
MOSFETs and an integrated driver. The MOSFETs are
individually optimized for operation in the synchronous
• 60 A continuous output current
buck configuration. The High-Side MOSFET is optimized to - Up to 80 A for 10 ms on pulse
achieve low capacitance and gate charge for fast switching - Up to 120 A for 10 µs on pulse
with low duty cycle operation. The Low-Side MOSFET has • Up to 2MHz switching operation
ultra low ON resistance to minimize conduction loss. • 3V / 5V PWM / Tri-State input compatible

The AOZ5310NQI uses a PWM input for accurate control of • Under-Voltage Lockout protection
the power MOSFETs switching activities, is compatible with • SMOD# control for Diode Emulation / CCM operation
3V and 5V (CMOS) logic and supports Tri-State PWM. • Low Profile 5x5 QFN-31L package

A number of features are provided making the AOZ5310NQI

a highly versatile power module. The boot- strap switch Applications
is integrated in the driver. The Low-Side MOSFET can be
driven into diode emulation mode to provide asynchronous
• Memory and graphic cards

operation and improve light-load performance. The pin-out

• VRMs for motherboards
is also optimized for low parasitics, keeping their effects to • Point of load DC/DC converters
a minimum.

Typical Application
2.5V ~ 18V

VIN

VCC BOOT

HS CBOOT CIN
THWN Driver

Driver PHASE
PWM Logic
DISB# L1 VOUT
Controller and VSWH
Delay
SMOD#
LS
Driver COUT
PWM
GL

AGND
VCC PVCC PGND

CVCC
5V CPVCC PGND

Rev. 2.0 November 2023 www.aosmd.com Page 1 of 18

 AOZ5310NQI

Ordering Information
Part Number Ambient Temperature Range Package Environmental
AOZ5310NQI -40 °C to 125 °C QFN5x5-31L RoHS

AOS products are offered in packages with Pb-free plating and compliant to RoHS standards.
Please visit https://aosmd.com/sites/default/files/media/AOSGreenPolicy.pdf for additional information.

Pin Configuration

THWN

VSWH

VSWH

VSWH
DISB#

PGND
PVCC

GL
31 30 29 28 29 26 25 25

PWM 1 GL 23 VSWH

SMOD# 2 22 VSWH
PGND
VCC 3 21 VSWH

AGND 4 20 VSWH

BOOT 5 19 VSWH

NC 6 PGND 18 VSWH

PHASE 7 VIN 17 VSWH

VIN 8 16 VSWH

9 10 11 12 13 14 15
VIN

VIN

VIN

PGND

PGND

PGND

PGND

QFN5x5-31L
(Top Transparent View)

Rev. 2.0 November 2023 www.aosmd.com Page 2 of 18

 AOZ5310NQI

Pin Description
Pin Number Pin Name Pin Function
PWM input signal from the controller IC. When DISB#=0V, the internal resistor divider will be
1 PWM
disconnected and this pin will be at high impedance.
Pull low to enable Discontinuous Mode of Operation (DCM), Diode Emulation or Skip Mode. There
2 SMOD#
is an internal pull-down resistor to AGND.
5V Bias for Internal Logic Blocks. Ensure to position a 1µF MLCC directly between VCC and AGND
3 VCC
(Pin 4).
4 AGND Signal Ground.
High-Side MOSFET Gate Driver supply rail. Connect a 100nF ceramic capacitor between BOOT
5 BOOT
and the PHASE (Pin 7).
6 NC Internally connected to VIN paddle. It can be left floating (no connect) or tied to VIN.
7 PHASE This pin is dedicated for bootstrap capacitor AC return path connection from BOOT (Pin 5).
8, 9, 10, 11 VIN Power stage High Voltage Input (Drain connection of High-Side MOSFET).
12, 13, 14, 15 PGND Power Ground pin for power stage (Source connection of Low-Side MOSFET).
16, 17, 18, 19, Switching node connected to the Source of High-Side MOSFET and the Drain of Low-Side
20, 21, 22, 23, VSWH MOSFET. These pins are used for Zero Cross Detection and Anti-Overlap Control as well as main
24, 25, 26 inductor terminal.
27 GL Low-Side MOSFET Gate connection. This is for test purposes only.
Power Ground pin for High-Side and Low-Side MOSFET Gate Drivers. Ensure to connect 1µF
28 PGND
directly between PGND and PVCC (Pin 29).
5V Power Rail for High-Side and Low-Side MOSFET Drivers. Ensure to position a 1µF MLCC
29 PVCC
directly between PVCC and PGND (Pin 28).
Thermal warning indicator. This is an open−drain output. When the temperature at the driver IC die
30 THWN
reaches the Over Temperature Threshold, this pin is pulled low.
Output disable pin. When this pin is pulled to a logic low level, the IC is disabled. There is an
31 DISB#
internal pull−down resistor to AGND.

Rev. 2.0 November 2023 www.aosmd.com Page 3 of 18

 AOZ5310NQI

Functional Block Diagram

VCC PVCC BOOT VIN

SMOD# ZCD Select REF/BIAS

UVLO
Level HS
Gate
Shifter Driver
Boot HS

Sequencing
PHASE
HS Gate
And PHASE Check VSWH
Driver
Enable Propagation Logic
DISB# Delay Control LS Min On
LS
Control Logic ZCD
VCC
ZCD Detect

PWM LS Gate
Tri-State PVCC
PWM
PWM Tri-State LS
Logic Gate
Driver GL
Thermal
Monitor PGND

THWN AGND

Rev. 2.0 November 2023 www.aosmd.com Page 4 of 18

 AOZ5310NQI

Absolute Maximum Ratings Recommended Operating Conditions

Exceeding the Absolute Maximum ratings may damage the The device is not guaranteed to operate beyond the
device. Maximum Recommended Operating Conditions.

Parameter Rating Parameter Rating

Low Voltage Supply (VCC, PVCC) -0.3 V to 7 V High Voltage Supply (VIN) 2.5 V to 18 V
High Voltage Supply (VIN) -0.3 V to 30 V Low Voltage/ MOSFET Driver Supply
4.5 V to 5.5 V
(VCC, PVCC)
Control Inputs
-0.3 V to (VCC+0.3 V)
(PWM, SMOD#, DISB#) Control Inputs
0 V to VCC
(PWM, FCCM, REFIN, VOS)
Output (THWN) -0.3 V to (VCC+0.3 V)
Output (TMON/FLT, IMON) 0 V to VCC
Bootstrap Voltage DC (BOOT-PGND) -0.3 V to 28 V
Operating Frequency 200 kHz to 2 MHz
Bootstrap Voltage Transient(1)
-8 V to 35 V
(BOOT-PGND)
Bootstrap Voltage DC
-0.3 V to 7 V
(BOOT-PHASE/VSWH)
BOOT Voltage Transient(1)
-0.3V to 9 V
(BOOT-PHASE/VSWH)
Switch Node Voltage DC
-0.3 V to 23 V
(PHASE/VSWH)
Switch Node Voltage Transient(1)
-8 V to 31 V
(PHASE/VSWH)
Phase Node Voltage Transient (2ns) -18V
Phase Node Voltage Distortion time 2ns
VIN-PHASE Voltage Transient (2ns) -8V to 38V
VIN-PHASE Voltage Distortion time 2ns
(PGND-0.3 V) to
Low-Side Gate Voltage DC (GL)
(PVCC+0.3 V)
Low-Side Gate Voltage Transient(2) (PGND-2.5 V) to
(GL) (PVCC+0.3 V)
VSWH Current DC 60 A
VSWH Current 10 ms Pulse 80 A
VSWH Current 10 µs Pulse 120 A

Storage Temperature (TS) -65°C to +150°C

Max Junction Temperature (TJ) 150°C

ESD Rating(3) 2 kV

Notes:
1. Peak voltages can be applied for 10 ns per switching cycle.
2. Peak voltages can be applied for 20 ns per switching cycle.
3. Devices are inherently ESD sensitive, handling precautions are
required. Human body model rating: 1.5 Ω in series with 100 pF.

Rev. 2.0 November 2023 www.aosmd.com Page 5 of 18

 AOZ5310NQI

Electrical Characteristics(4)
TA = 25°C to 125°C. Typical values reflect 25°C ambient temperature; VIN = 12 V, VCC = PVCC = DISB# = 5 V, unless
otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit
General
VVIN Power Stage Power Supply 2.5 18 V
VCC Low Voltage Bias Supply PVCC = VCC 4.5 5.5 V

RθJC(5) Reference to High-Side MOSFET

temperature rise 2.5 °C/W
Thermal Resistance
RθJA(5) Fsw = 300 kHz, AOS Demo Board 12.5 °C/W

Input Supply and UVLO

VCC_UVLO VCC Rising 3.4 3.8 4.2 V
Under-Voltage Lockout
VCC_HYST VCC Hysteresis 400 mV
DISB# = 0V 1
SMOD# = 5V, PWM = 0V 550
IVCC Control Circuit Bias Current µA
SMOD# = 0V, PWM = 0V 535
SMOD# = 0V, PWM =1.65V 430
PWM = 400 kHz, 20% Duty Cycle 20 mA
IPVCC Drive Circuit Operating Current
PWM = 1MHz, 20% Duty Cycle 50 mA
PWM Input
VPWMH Logic High Input Voltage 2.7 V
VPWML Logic Low Input Voltage 0.72 V
IPWM_SRC PWM = 0V -150 µA
PWM Pin Input Current
IPWM_SNK PWM = 3.3V 150 µA
VTRI PWM Tri-State Window 1.35 1.95 V
VPMW_FLOAT PWM Tri-State Voltage Clamp PWM = Floating 1.65 V
DIST# Input
VDISB#_ON Enable Input Voltage 2.0 V
VDISB#_OFF Disable Input Voltage 0.8 V
RDISB# DISB# Input Resistance Pull-Down Resistor 850 kΩ
SMOD# Input
VSMOD#_H Logic High Input Voltage 2.0 V
VSMOD#_L Logic Low Input Voltage 0.8 V
RSMOD# SMOD# Input Resistance Pull-Down Resistor 850 kΩ
Gate Driver Timing
tPDLU PWM to High-Side Gate PWM: H → L, VSWH: H → L 30
tPDLL PWM to Low-Side Gate PWM: L → H, GL: H → L 25
ns
tPDHU Low-side to High-Side Gate Deadtime GL: H → L, GH(6): L → H 15
tPDHL High-Side to Low-side Gate Deadtime VSWH: H → 1V, GL: L → H 13

Rev. 2.0 November 2023 www.aosmd.com Page 6 of 18

 AOZ5310NQI

Electrical Characteristics(4)
TA = 25°C to 125°C. Typical values reflect 25°C ambient temperature; VIN = 12 V, VCC = PVCC = DISB# = 5 V, unless
otherwise specified.
Symbol Parameter Conditions Min Typ Max Unit

t TSSHD PWM: L → VTRI, GL: H → L and

Tri-State Shutdown Delay 25
PWM: H → VTRI, VSWH: H → L

t TSEXIT PWM: VTRI → H, VSWH: L → H PWM:

Tri-State Propagation Delay 35
VTRI → L, GL: L → H ns
tLGMIN LS Minimum On Time SMOD# = L 350

DtDL Variations of Width Difference

tDL = tPDLL + tPDHU - tPDLU -2.5 0 2.5
between PWM and VSWH
Thermal Notification(5)
TJTHWN Junction Thermal Threshold Temperature Rising 150 °C
TJHYST Junction Thermal Hysteresis 30 °C
VTHWN THWN Pin Output Low ITHWN = 0.5mA 60 mV
RTHWN THWN Pull-Down Resistance 120 Ω

Notes:
4. All voltages are specified with respect to the corresponding AGND pin.
5. Characterization value. Not tested in production.
6. GH is an internal pin.

Rev. 2.0 November 2023 www.aosmd.com Page 7 of 18

 AOZ5310NQI

Table 1. Input Control Truth Table

DISB# SMOD# PWM(7) GH (Not a Pin) GL
L X X L L
H L H H L
H, Forward IL
H L H to Tri-State L
L, Reverse IL
H L L to Tri-State L L
H L L L H
H H H H L
H H L L H
H H Tri-State L L

Note:
7. Diode emulation mode is activated when SMOD# is LOW and PWM transition from HIGH to Tri-State.
Zero Cross Detection (ZCD) at IL*Rdson(LS) = 1mV to turn off GL

Timing Diagrams

VPWMH

PWM
VPWML
tPDLL
tPDHL

GL

1V 1V

tPDLU

90%

VSWH tPDHU
1V 1V

Figure 1. PWM Logic Input Timing Diagram

Rev. 2.0 November 2023 www.aosmd.com Page 8 of 18

 AOZ5310NQI

Timing Diagrams (cont.)

PWM VTRI

tTSSHD tTSSHD tTSSHD tTSSHD

GL

tTSEXIT TTSEXIT tTSEXIT tTSEXIT

VSWH

Figure 2. PWM Tri-State Hold Off and Exit Timing Diagram

Rev. 2.0 November 2023 www.aosmd.com Page 9 of 18

 AOZ5310NQI

Typical Characteristics
TA = 25 °C, VIN = 12 V, VOUT = 1.0V, PVCC = VCC = 5 V, unless otherwise specified.

94 8

7
92 VIN=12V, VOUT=0.9V, Fsw=500kHz
6

Power Loss (W)

Efficiency (%)

5
90
4
88 3

2
86
1
VIN=12V, VOUT=0.9V, Fsw=500kHz
84 0
5 10 15 20 25 30 35 40 5 10 15 20 25 30 35 40
Load Current (A) Load Current (A)

Figure 3. Efficiency vs. Load Current Figure 4. Power Loss vs. Load Current

600 4.0

580 3.5

560 3.0
PVCC Current (uA)

PWM Voltage (V)

Logic High Threshold

540 2.5

520 2.0
Tri-state Window
500 1.5

480 1.0
Logic Low Threshold
460 0.5

440 0.0
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)

Figure 5. Supply Current (IPVCC) vs. Temperature Figure 6. PWM Threshold vs. Temperature

1.8 3.7

1.7 3.6
Rising Threshold
1.6 3.5
SMOD# Voltage (V)

Logic High Threshold

VCC Voltage (V)

1.5 3.4

1.4 3.3

1.3 3.2
Logic Low Threshold Falling Threshold
1.2 3.1

1.1 3.0

1.0 2.9
-50 -25 0 25 50 75 100 125 150 -50 -25 0 25 50 75 100 125 150
Temperature (°C) Temperature (°C)
Figure 7. SMOD# Threshold Figure 8. UVLO (VCC) Threshold
vs. Temperature vs. Temperature

Rev. 2.0
1.0 November 2023
2020 www.aosmd.com Page 10 of 18
 AOZ5310NQI

Typical Characteristics
TA = 25 °C, VIN = 12 V, VOUT = 1.0V, PVCC = VCC = 5 V, unless otherwise specified.
1.8 4.0

1.7 3.5

1.6 3.0 Logic HighThreshold

DISB# Voltage (V)

PWM Voltage (V)

Logic High Threshold
1.5 2.5

1.4 2.0
Tri-state Window
1.3 1.5
Logic Low Threshold
1.2 1.0

1.1 0.5 Logic Low Threshold

1.0 0.0
-50 -25 0 25 50 75 100 125 150 4.2 4.4 4.6 4.8 5 5.2 5.4 5.6 5.8
Temperature (°C) VCC Voltage (V)
Figure 9. DISB# Threshold Figure 10. PWM Threshold
vs. Temperature vs. VCC Voltage

Rev. 2.0 November 2023 www.aosmd.com Page 11 of 18

 AOZ5310NQI

Application Information Disable (DISB#) Function

The AOZ5310NQI can be enabled and disabled through
AOZ5310NQI is a fully integrated power module designed DISB# (Pin 31). The driver output is disabled when DISB#
to work over an input voltage range of 2.5V to 18V with input is connected to AGND. The module would be in
a separate 5V supply for gate drive and internal control standby mode with low quiescent current of less than 1uA.
circuitry. The MOSFETs are individually optimized for The module will be active when DISB# is connected to VCC
efficient operation on both High-Side and Low-Side for a Supply. The driver output will follow PWM input signal. A
low duty cycle synchronous buck converter. High current weak pull-down resistor is connected between DISB# and
MOSFET Gate Drivers are integrated in the package to AGND.
minimize parasitic loop inductance for optimum switching
efficiency. Power up sequence design must be implemented to ensure
proper coordination between the module and external PWM
Powering the Module and the Gate Drives controller for soft start and system enable/disable. It is
An external supply PVCC = 5V is required for driving the recommended that the AOZ5310NQI should be disabled
MOSFETs. The MOSFETs are designed with optimally before the PWM controller is disabled. This would make
customized gate thresholds voltages to achieve the most sure AOZ5310NQI will be operating under the recommended
advantageous compromise between fast switching speed conditions.
and minimal power loss. The integrated gate driver is
capable of supplying large peak current into the Low-Side Input Voltage VIN
MOSFET to achieve fast switching. A ceramic bypass AOZ5310NQI is rated to operate over a wide input range from
capacitor of 1µF or higher is recommended from PVCC 2.5V to 18V. For high current synchronous buck converter
(Pin 29) to PGND (Pin 28). The control logic supply VCC applications, large pulse current at high frequency and high
(Pin 3) can be derived from the gate drive supply PVCC current slew rates (di/dt) will be drawn by the module during
(Pin 29) through an RC filter to bypass the switching noise normal operation. It is strongly recommended to place a
(See Typical Application Circuit). bypass capacitor very close to the package leads at the
input supply (VIN). Both X7R or X5R quality surface mount
The boost supply for driving the High-Side MOSFET is ceramic capacitors are suitable.
generated by connecting a small capacitor (100nF) between
the BOOT (Pin 5) and the switching node PHASE (Pin 7). The High-Side MOSFET is optimized for fast switching by
It is recommended that this capacitor CBOOT should be using low gate charges (QG) device. When the module is
connected to the device across Pin 5 and Pin 7 as close as operated at high duty cycle ratio, conduction loss from the
possible. A bootstrap switch is integrated into the device High-Side MOSFET will be higher. The total power loss for
to reduce external component count. An optional resistor the module is still relatively low but the High-Side MOSFET
RBOOT in series with CBOOT between 1Ω to 5Ω can be higher conduction loss may have higher temperature. The
used to slow down the turn on speed of the High-Side two MOSFETs have their own exposed pads and PCB
MOSFET to achieve both short switching time and low copper areas for heat dissipation. It is recommended that
VSWH switching node spikes at the same time. worst case junction temperature be measured for both High-
Side MOSFET and Low-Side MOSFET to ensure that they
Under-voltage Lockout are operating within Safe Operating Area (SOA).
AOZ5310NQI starts up to normal operation when VCC
rises above the Under-Voltage LockOut (UVLO) threshold PWM Input
voltage. The UVLO release is set at 3.5V typically. Since the AOZ5310NQI is compatible with 3V and 5V (CMOS) PWM
PWM control signal is provided from an external controller or logic. Refer to Figure 1 for PWM logic timing and propagation
a digital processor, extra caution must be taken during start delays diagram between PWM input and the MOSFET gate
up. AOZ5310NQI must be powered up before PWM input drives. AOZ5310NQI is compatible with 3V and 5V (CMOS)
is applied. PWM logic. Refer to Figure 1 for PWM logic timing and
propagation delays diagram between PWM input and the
Normal system operation begins with a soft start sequence MOSFET gate drives.
by the controller to minimize in-rush current during start up.
Powering the module with a full duty cycle PWM signal may The PWM is also compatible with Tri-State input. When
lead to many undesirable consequences due to excessive the PWM output from the external PWM controller is in high
power. AOZ5310NQI provides some protections such as impedance or not connected both High-Side and Low-Side
UVLO and thermal monitor. For system level protection, MOSFETs are turned off and VSWH is in high impedance
the PWM controller should monitor the current output and state. Table 2 shows the thresholds level for high-to-low and
protect the load under all possible operating and transient low-to-high transitions as well as Tri-State window.
conditions.

Rev. 2.0 November 2023 www.aosmd.com Page 12 of 18

 AOZ5310NQI

There is a Holdoff Delay between the corresponding PWM MOSFET. An internal shoot through protection scheme
Tri-State signal and the MOSFET gate drivers to prevent is implemented to ensure that both MOSFETs cannot be
spurious triggering of Tri-State mode which may be caused turned on at the same time. The operation of PWM signal
by noise or PWM signal glitches. The Holdoff Delay is transition is illustrated as below.
typically 25ns.
1) PWM from logic Low to logic High
Table 2. PWM Input and Tri-State Threshold
Threshold VPWMH VPWML VTRIH VTRIL When the falling edge of Low-Side Gate Driver output GL
goes below 1V, the blanking period is activated. After a pre-
AOZ5310NQI 2.7 V 0.72 V 1.35 V 1.95 V determined value (tPDHU), the complementary High-Side
Note: Gate Driver output GH is turned on.
8. See Figure 2 for propagation delays and Tri-State window.
2) PWM from logic High to logic Low
Diode Mode Emulation of Low-Side MOSFET (SMOD#)
When the falling edge of switching node VSWH goes below
AOZ5310NQI can be operated in the diode emulation or 1V, the blanking period is activated. After a pre-determined
pulse skipping mode using SMOD# (Pin 2). This enables the value (tPDHL), the complementary Low-Side Gate Driver
converter to operate in asynchronous mode during start up, output GL is turned on
light load or under pre-bias conditions.
This mechanism prevents cross conduction across the input
When SMOD# is high, the module will operate in Continuous bus line VIN and PGND. The anti-overlap circuit monitors
Conduction Mode (CCM). The Driver logic will use the the switching node VSWH to ensure a smooth transition
PWM signal and generate both the High-Side and Low-Side between the two MOSFETs under any load transient
complementary gate drive outputs with minimal anti-overlap conditions.
delays to avoid cross conduction.
Thermal Warning (THWN)
When SMOD# is low, the module can operate in
Discontinuous Conduction Mode (DCM). The High-Side The driver IC temperature is internally monitored and an
MOSFET gate drive output is not affected but Low-Side thermal warning flag at THWN (Pin 30) is asserted if it exceeds
MOSFET will enter diode emulation mode. See Table 1 for 150°C. This warning flag is reset when the temperature drop
all truth table for DISB#, SMOD# and PWM inputs. back to 120°C. THWN is an open drain output that is pulled
to AGND to indicate an over-temperature condition. It should
Gate Drives be connected to VCC through a resistor for monitoring
AOZ5310NQI has an internal high current high speed driver purpose. The device will not power down during the over
that generates the floating gate driver for the High-Side temperature condition.
MOSFET and a complementary driver for the Low-Side

Rev. 2.0 November 2023 www.aosmd.com Page 13 of 18

 AOZ5310NQI

PCB Layout Guideline

AOZ5310NQI is a high current module rated for operation
up to 2MHz. This requires fast switching speed to keep the
switching losses and device temperatures within limits. An
integrated gate driver within the package eliminates driver-
to-MOSFET gate pad parasitic of the package or on PCB.

To achieve high switching speeds, high levels of slew

rate (dv/dt and di/dt) will be present throughout the power
train which requires careful attention to PCB layout to
minimize voltage spikes and other transients. As with any
synchronous buck converter layout, the critical requirement
is to minimize the path of the primary switching current loop
formed by the High-Side MOSFET, Low-Side MOSFET, and
the input bypass capacitor CIN. The PCB design is greatly Figure 11. Top Layer of Demo Board. VIN, VSWH, and
simplified by the optimization of the AOZ5310NQI pin out. PGND Copper Planes.
The power inputs of VIN and PGND are located adjacent to As the primary and secondary (complimentary) AC current
each other and the input bypass capacitors CIN should be loops move through VIN to VSWH and through PGND to
placed as close as possible to these pins. The area of the VSWH, large positive and negative voltage spike appear at
secondary switching loop is formed by Low-Side MOSFET, the VSWH terminal which are caused by the large internal
output inductor L1, and output capacitor COUT is the next di/dt produced by the package parasitic. To minimize the
critical requirement. This requires second layer or “Inner effects of this interference at the VSWH terminal, at which
1” to be the PGND plane. VIAs should then be placed near the main inductor L1 is mounted, size just enough for the
PGND pads. inductor to physically fit. The goal is to employ the least
amount of copper area for this VSWH terminal, only enough
While AOZ5310NQI is a highly efficient module, it is still so the inductor can be securely mounted.
dissipating significant amount of heat under high power
conditions. Special attention is required for thermal To minimize the effects of switching noise coupling to the
design. MOSFETs in the package are directly attached rest of the sensitive areas of the PCB, the area directly
to individual exposed pads (VIN and PGND) to simplify underneath the designated VSWH pad or inductor terminal
thermal management. Both VIN and VSWH pads should is voided and the shape of this void is replicated descending
be attached to large areas of PCB copper. Thermal relief down through the rest of the layers. Refer to Figure 12.
pads should be placed to ensure proper heat dissipation to
the board. An inner power plane layer dedicated to VIN,
typically the high voltage system input, is desirable and VIAs
should be provided near the device to connect the VIN pads
to the power plane. Significant amount of heat can also be
dissipated through multiple PGND pins. A large copper area
connected to the PGND pins in addition to the system ground
plane through VIAs will further improve thermal dissipation.

As shown on Figure. 11, the top most layer of the PCB should
comprise of wide and exposed copper area for the primary
AC current loop which runs along VIN pad originating from
the input capacitors C10, C11 and C12 that are mounted
to a large PGND pad. They serve as thermal relief as heat
flows down to the VIN exposed pad that fan out to a wider
area. Adding VIAs will only help transfer heat to cooler
regions of the PCB board through the other layers beneath
but serve no purpose to AC activity as all the AC current
sees the lowest impedance on the top layer only. Figure 12. Bottom Layer PCB Layout. VSWH Copper
Plane Voided on Descending Layers.

Rev. 2.0 November 2023 www.aosmd.com Page 14 of 18

 AOZ5310NQI

Positioning VIAs through the landing pattern of the VIN and optimal thermal relief, it is recommended to fill the PGND
PGND thermal pads will help quickly facilitate the thermal and VIN exposed landing pattern with 10mil diameter
build up and spread the heat much more quickly towards the VIAs. 10mil diameter is a commonly used via diameter as
surrounding copper layers descending from the top layer. it is optimally cost effective based on the tooling bit used
(See RECOMMENDED LANDING PATTERN AND VIA in manufacturing. Each VIA is associated with a 20 mil
PLACEMENT section). diameter keep out. Maintain a 5 mil clearance (127 um)
around the inside edge of each exposed pad in an event
The exposed pads dimensional footprint of the 5x6 QFN of solder overflow, potentially shorting with the adjacent
package is shown on the package dimensions page. For expose thermal pad.

Rev. 2.0 November 2023 www.aosmd.com Page 15 of 18

 AOZ5310NQI

Package Dimensions, QFN5x5A-31L

RECOMMENDED LAND PATTERN

UNIT: mm
NOTE
CONTROLLING DIMENSION IS MILLIMETER.
CONVERTED INCH DIMENSIONS ARE NOT NECESSARILY EXACT.

Rev. 2.0 November 2023 www.aosmd.com Page 16 of 18

 AOZ5310NQI

Tape and Reel Dimensions, QFN5x5A-31L

Rev. 2.0 November 2023 www.aosmd.com Page 17 of 18

 AOZ5310NQI

Part Marking

AOZ5310NQI
(QFN5x5)

DNN0
Part Number Code
Y W LT

Year & Week Code Assembly Lot Code & Assembly Site

LEGAL DISCLAIMER
Applications or uses as critical components in life support devices or systems are not authorized. Alpha and Omega
Semiconductor does not assume any liability arising out of such applications or uses of its products. AOS reserves
the right to make changes to product specifications without notice. It is the responsibility of the customer to evaluate
suitability of the product for their intended application. Customer shall comply with applicable legal requirements,
including all applicable export control rules, regulations and limitations.

AOS’s products are provided subject to AOS’s terms and conditions of sale which are set forth at:
http://www.aosmd.com/terms_and_conditions_of_sale

LIFE SUPPORT POLICY

ALPHA AND OMEGA SEMICONDUCTOR PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL
COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS.
As used herein:
1. Life support devices or systems are devices or systems 2. A critical component in any component of a life support,
which, (a) are intended for surgical implant into the body or device, or system whose failure to perform can be
(b) support or sustain life, and (c) whose failure to perform reasonably expected to cause the failure of the life support
when properly used in accordance with instructions for use device or system, or to affect its safety or effectiveness.
provided in the labeling, can be reasonably expected to
result in a significant injury of the user.

Rev. 2.0 November 2023 www.aosmd.com Page 18 of 18