Ver1.

1.8 cm (Type 0.71) Active Matrix Color OLED Panel

ECX335AF
1. Description

The ECX335AF is a 1.8 cm (type 0.71) diagonal, 1920(RGB) × 1080 dots active matrix color OLED panel module using
single crystal silicon transistors. This panel incorporates panel driver and logic driver, and realizes small size, light weight
and high definition.
(Applications: View finders, head mounted displays, very small monitors etc.)

2. Features

◆ Small size high definition type 0.70 display dots: 1920 (RGB)×1080 = 6.22 M dots
◆ High contrast
◆ Wide color reproduction range
◆ High-speed response
◆ Thin type and light weight
◆ Power saving function
◆ Up/down and/or right/left inverse display function
◆ Orbit supported

3. Element Structure

Active matrix color OLED display element with on-chip driver using single crystal silicon transistors

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4. System Block Diagram

Details of “T-con”
T-Con

XCLR System Reset

8 10 10 10 10 8
Sub-Contrast
VSS Sub-Bright
VSS
R R
8 10 10 10 10 8
Signal Sub-Contrast Sub-Bright Signal
LVDS Contrast Bright Dither
Controll G G output
8 10 10 10 10 8
Sub-Contrast Sub-Bright
B B
Sync

RGB data
XCS
Timing Pulse
XSCK H Driver
Serial Register Timing
SI I/F Controll Generator
Write
Read Timing Pulse
SO
V Driver

Pre-set mode
registers
Display
OTP
VS
HS

LV1/10 Clk_Gen

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5. Pin Description

5.1 Pin Assignment

5.2 Pin description (LVDS input)

Pin No. Equivalent
Symbol Type Description
(FPC Side) circuit
1 VCATH Power Supply EL cathode power supply

2 VCATH Power Supply EL cathode power supply

3 VCCP_O Power Supply VCCP power supply ※8

4 VCCP_I Power Supply VCCP power supply

5 VCCP_I Power Supply VCCP power supply

6 VDD2 Power Supply 10V power supply

7 VDD2 Power Supply 10V power supply

8 VSS Power Supply GND

9 VSS Power Supply GND

10 VSS Power Supply GND

11 VSS Power Supply GND

12 VDD1 Power Supply 1.8V power supply

13 VDD1 Power Supply 1.8V power supply

Serial communication
14 XCS Input ※1
Chip select
Serial communication
15 XSCK Input ※1
Serial clock
Serial communication
16 SI Input ※1
Data input
Serial communication
17 SO Output ※2
Data output

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Pin No. Equivalent

Symbol Type Description
(FPC Side) circuit
Power save communication enable
18 PSCNT Input ※1
Connect to GND
19 XCLR Input System reset ※1

20 TEST Output Test pin (no connect) ※3

21 TEST - Test pin (connect to GND)

22 TEST Input Test pin (connect to GND) ※4

23 TEST Input Test pin (connect to GND) ※5

24 TEST Input Test pin (connect to GND) ※1

25 TEST Input / Output Test pin (connect to GND) ※4

26 TEST Output Test pin（no connect） ※1

27 VDD1IF Power Supply 1.8V power supply for LVDS

28 VSSIF Power Supply GND for LVDS

29 TEST Input Test pin (connect to GND) ※6

30 TEST Input Test pin (connect to GND) ※6

31 LV1A Input LVDS clock ※6

32 LV1B Input LVDS clock ※6

33 LV2A Input LVDS data input ※6

34 LV2B Input LVDS data input ※6

35 LV3A Input LVDS data input ※6

36 LV3B Input LVDS data input ※6

37 LV4A Input LVDS data input ※6

38 LV4B Input LVDS data input ※6

39 LV5A Input LVDS data input ※6

40 LV5B Input LVDS data input ※6

41 VDD1IF Power Supply 1.8V power supply for LVDS

42 VSSIF Power Supply GND for LVDS

43 TEST Input Test pin (connect to GND) ※6

44 TEST Input Test pin (connect to GND) ※6

45 VSSIF Power Supply GND for LVDS

46 VDD1IF Power Supply 1.8V power supply for LVDS

47 LV9A Input LVDS data input ※6

48 LV9B Input LVDS data input ※6

49 LV8A Input LVDS data input ※6

50 LV8B Input LVDS data input ※6

51 LV7A Input LVDS data input ※6

52 LV7B Input LVDS data input ※6

53 LV6A Input LVDS data input ※6

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Pin No. Equivalent

Symbol Type Description
(FPC Side) circuit
54 LV6B Input LVDS data input ※6

55 LV10A Input LVDS clock ※6

56 LV10B Input LVDS clock ※6

57 TEST Input Test pin (connect to GND) ※6

58 TEST Input Test pin (connect to GND) ※6

59 VSSIF Power Supply GND for LVDS

60 VDD1IF Power Supply 1.8V power supply for LVDS

61 TEST Output Test pin (no connect) ※1

62 IFSW Input Interface select pin (connect to GND） ※1

63 VDD1 Power Supply 1.8V power supply

64 VDD1 Power Supply 1.8V power supply

65 VSS Power Supply GND

66 VSS Power Supply GND

67 TEST Input Test pin (connect to GND) ※7

68 VCAL Output Output of temperature sensing circuit ※8

69 R_IB Input / Output Bias current adjustment resistance connect pin ※8

70 VREF Output VREF voltage ※8

71 VG255 Output Gamma top voltage ※8

72 VG0 Output Gamma bottom voltage ※8

73 VOFS Output Vofs voltage ※8

74 VSS Power Supply GND

75 VSS Power Supply GND

76 VDD2 Power Supply 10V power supply

77 VDD2 Power Supply 10V power supply

78 VCCP_I Power Supply VCCP power supply

79 VCCP_I Power Supply VCCP power supply

80 VCATH Power Supply EL cathode power supply

81 VCATH Power Supply EL cathode power supply

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5.3 Equivalent Circuits

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5.4 Peripheral Circuit

Regarding power supply capacitor connections, mount an approximately 2.2 µF to 10 µF capacitor for each power supply.
Insufficient capacitance may affect the picture quality.

※This circuit is a typical example illustrating the operation of the devices. Sony cannot assume responsibility for any
problems arising out of the use of the circuit.

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6. Absolute Maximum Ratings

Item Symbol Min. Maximum Ratings Unit

1.8V power supply VDD1 -0.3 2.0 V

1.8V power supply (IF) VDD1IF -0.3 2.5 V

10 V power supply VDD2 -0.3 12.0 V

EL cathode voltage Vcath -0.3 0.3 V

Logic input voltage ※ Vi -0.3 VDD1+0.3 V

IF input voltage ※※ ViIF -0.3 VDD1IF+0.3 V

Storage temperature Tpnl -30 +80 °C

※ Pin no. 14,15,16,18,19,22,23,24 & 62

※※ Pin no. 29 to 40,43,44 & 47 to 58

7. Recommended Operating Conditions

Item Symbol Min. Typ. Max. Unit

1.8V power supply VDD1 1.62 1.8 1.98 V

1.8V power supply (IF) VDD1IF 1.62 1.8 1.98 V

10 V power supply VDD2 9.7 10.0 10.3 V

EL cathode voltage Vcath -0.3 0 0.3 V

Operating temperature range Tpnl 0 70 °C

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8. Electrical Characteristics

8.1. DC Characteristics

Item Symbol Conditions Min. Typ. Max. Unit

High-level input voltage VIH 0.7VDD1 VDD1 V

Low-level input voltage VIL 0 0.3VDD1 V

Logic High -level
VOH VDD1 - 0.5 V
Output voltage
Logic Low -level
VOL 0.5 V
Output voltage

8.2. AC Characteristics

Item Symbol Conditions Min. Typ. Max. Unit

XSCK frequency f_XSCK 0.8 2.5 MHz

XCS setup time st_XCS 0.4 µs

XCS hold time hd_XCS 0.2 µs

SI setup time st_SI 0.2 µs

SI hold time hd_SI 0.2 µs

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8.3. LVDS I/F Specifications

◆Resolution :Full-HD 1920x1080
◆Frame Rate :60Hz
◆Gradation :8bit
◆Number of pairs :Clk: 2pairs, Data:8pairs

8.4. DC Characteristics

Item Symbol Min. Typ. Max. Unit

Voltage range (*) Vi 890 1550 mV

Common Mode Voltage Vic 1040 1400 mV

Each DATA-DATA and DATA-CLK Vic difference ⊿Vic 35 mV

Differential Input Voltage Vid 130 300 mV

Each DATA-DATA and DATA-CLK Vid difference ⊿Vid 35 mV

Driver-receiver ground potential difference Vgpd 50 mV

(*)Assumed driver output differential voltage =180mV

8.5. LVDS AC Characteristics

Item Symbol Min. Typ. Max. Unit

Tx Timing Budget tTOP -250 0 250 psec

Tx tLVT tLVT 300 500 600 psec

Odd and Even clock skew OESKEW 0 500 psec

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8.6 Power Consumption

Typ. (*) Unit

Item Symbol Condition
200 120 90 Standby cd/m2

VDD1 power consumption PDD1 30 30 30 0.4 mW

VDD1=1.8V
VDD1IF power consumption PDD1IF VDD2=10V 80 80 80 0 mW
VDD2 power consumption PDD2 LVDS input 440 360 330 0 mW
Tpnl=40°C
Total power consumption PDDTTL 550 470 440 0.4 mW

*: All white raster display, Clock frequency = 148.5MHz, Frame rate = 60Hz

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9. Power Supply Sequence

To avoid panel breakdown caused by excessive current flow into the internal circuit, power supply sequence written
below should be kept.

9.1 Sequence Diagram

Data

Serial Serial Serial Serial Serial Serial Serial Serial Serial

Address
Setting① Setting② Setting③ Setting④ Setting⑤ Setting⑥ Setting⑦ Setting⑧ Setting⑨

0x00 0x0F 0x0E

0x01 0x01 0x00

0x02 0x40

0x03 0xA0 0x20

0x04 0x5F 0x3F

0x6D 0x04 0x00

0x6F 0x03 0x00

0x71 0x4E 0x46 0x00

0x72 0x4E 0x46 0x00

9.2. Power On Sequence

1. Set XCLR to low and turn on 1.8V power supply.
2. After completion of 1.8 V power supply rising, set XCLR to high, then the panel changes to the power-saving mode.
3. Perform the serial setting ①
4. Perform power-save 0 (PS0) off serial setting ②, then perform power-save 1 (PS1) off serial setting ③ at an interval
of > 200μs.
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5. After serial setting ③ completion, perform the serial setting ④ at an interval of > 4XVD.
6. After serial setting ④ completion, perform the serial setting ⑤ at an interval of > 1XVD.
7. After serial setting ⑤ completion, perform the serial setting ⑥ at an interval of > 1XVD.
8. After serial setting ⑥ completion, perform the serial setting ⑦ within V-blanking period just after 1V period from
serial setting ⑥.
*Complete turning on of 10V power supply within 3 XVD periods after power saving mode off setting ③, while the order
of turning on of 1.8V and 10V power supply is not restricted.

9.3. Power Off Sequence

1. Perform PS0 on and PS1 on serial setting to enter power-saving mode.
2. After power-saving mode starts, set XCLR to low and turn off 1.8V and 10V power supplies.
*Turning off of 1.8V and 10V power supplies should be done after completion of setting XCLR to low, while the order of
turning off of 1.8V and 10V power supply is not restricted.

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10. Description of Function

10.1. Serial Communication

10.1.1. Register Map

Addr. DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 Initial
0 +0x00 RGB_YCB YCB_DEC * * DWN RGT MCLKPOL PS0 0E
1 +0x01 VCAL_MON CALSEL[1:0] YCB_P * * * PS1 00
2 +0x02 * * * ORBIT_H[4:0] 00
3 +0x03 * * * ORBIT_V[4:0] 00
4 +0x04 * * * * * * * * 1F
5 +0x05 * * * * DITHERON LUMINANCE[2:0] 00
6 +0x06 * * * * * * * * 00
7 +0x07 * * * * * * * * 00
8 +0x08 * * * * * OTPCALDAC_REGDIS * OTPDG_REGDIS 00
9 +0x09 * * * * * * * * 56
A +0x0A * * * * * * * * 00
B +0x0B * * * * * * * * 00
C +0x0C * * * * * * * * 00
D +0x0D * * * * * * * * 00
E +0x0E * * * * * * * * 00
F +0x0F * * * * * * * * 00
10 +0x10 * * * * * * * * 00
11 +0x11 * * * * * * * * 00
12 +0x12 * * * * * * * * 00
13 +0x13 * * * * * * * * 00
14 +0x14 CONT[7:0] 00
15 +0x15 CONT[8] RCONT[6:0] C0
16 +0x16 * GCONT[6:0] 40
17 +0x17 * BCONT[6:0] 40
18 +0x18 BRT[7:0] 80
19 +0x19 * RBRT[6:0] 40
1A +0x1A * GBRT[6:0] 40
1B +0x1B * BBRT[6:0] 40
1C +0x1C * * * * * * * * 10
1D +0x1D CALDAC[7:0] 80
1E +0x1E * * * * * * * * 40
1F +0x1F * * * * * * * * 10
20 +0x20 H_ACT_U[7:0] 60
21 +0x21 H_ACT_U[8] V_ACT_D[10:8] * H_ACT_D[10:8] 44
22 +0x22 H_ACT_D[7:0] 20
23 +0x23 V_ACT_U[7:0] 29
24 +0x24 V_ACT_D[7:0] 61
25 +0x25 * * * * * * * * 00
26 +0x26 * * * * * * * * 04
27 +0x27 * * * * * * * * 4C
28 +0x28 * DE_D[10:8] * DE_U[10:8] 40
29 +0x29 DE_U[7:0] 58
2A +0x2A DE_D[7:0] 28
2B +0x2B * * * * * * * * 04
2C +0x2C * * * * * * * * 65
2D +0x2D * WSST1_D[10:8] * WSST1_U[10:8] 00
2E +0x2E WSST1_U[7:0] 18
2F +0x2F WSST1_D[7:0] 19
30 +0x30 * WSST2_D[10:8] * WSST2_U[10:8] 44
31 +0x31 WSST2_U[7:0] 0D
32 +0x32 WSST2_D[7:0] 0E

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33 +0x33 * * * * * * * * 80
34 +0x34 * * * * * * * * 00
35 +0x35 * * * * * * * * 24
36 +0x36 WSEN1_U[7:0] DD
37 +0x37 * * * * * * * WSEN1_U[8] 00
38 +0x38 WSEN1_W[7:0] 01
39 +0x39 * * * * * WSEN2_U[10:8] 04
3A +0x3A WSEN2_U[7:0] 35
3B +0x3B WSEN2_W[7:0] 07
3C +0x3C WSEN3_U[7:0] 5D
3D +0x3D WSEN3_W[7:0] 0A
3E +0x3E DSEN_U[7:0] B6
3F +0x3F * * * DESN_U[8] * DSEN_W[10:8] 03
40 +0x40 DSEN_W[7:0] 8D
41 +0x41 * * VCK_W[9:8] * * VCK_U[9:8] 00
42 +0x42 VCK_U[7:0] 01
43 +0x43 VCK_W[7:0] 7B
44 +0x44 * * * * * * SGSELREF_U[9:8] 00
45 +0x45 SIGSELREF_U[7:0] 17
46 +0x46 SIGSELREF_W[7:0] 76
47 +0x47 * * * * SIGSELOFS_U[3:0] 00
48 +0x48 SIGSELOFS_W[7:0] 76
49 +0x49 * * SIGSEL_W[9:8] SIGSEL_U[3:0] 00
4A +0x4A SIGSEL_W[7:0] 5A
4B +0x4B * * * * * * SELREF_U[9:8] 00
4C +0x4C SELREF_U[7:0] 0A
4D +0x4D SELREF_W[7:0] 5D
4E +0x4E SELOFS_U[7:0] 0A
4F +0x4F SELOFS_W[7:0] 5D
50 +0x50 * * SEL_W[9:8] * * SEL_U[9:8] 00
51 +0x51 SEL_U[7:0] 0A
52 +0x52 SEL_W[7:0] 41
53 +0x53 * * * * * * * * 00
54 +0x54 * * * * * * * * 51
55 +0x55 * * * * * * * * 0A
56 +0x56 * * * * * * * * 38
57 +0x57 * AZEN_D[10:8] * * * AZEN_U[8] 40
58 +0x58 AZEN_U[7:0] 62
59 +0x59 AZEN_D[7:0] 2F
5A +0x5A * * * * * * * * 00
5B +0x5B * * * * * * * * 76
5C +0x5C * * * * * * * * 00
5D +0x5D * * * * * * * * 01
5E +0x5E * * * * * * * * 0B
5F +0x5F * * * * * * * * 00
60 +0x60 * * * * * * * * 01
61 +0x61 * * * * * * * * A0
62 +0x62 * * * * * * * * 00
63 +0x63 * * * * * * * * 02
64 +0x64 * * * * * * * * 0F
65 +0x65 * * * * * * * * 00
66 +0x66 * * * * * * * * 00
67 +0x67 * * * * * * * * 00
68 +0x68 * * * * * * * * 00
69 +0x69 * * * * * * * * 00
6A +0x6A * * * * * * * * 00
6B +0x6B * * * * * * * * 00
6C +0x6C * * * * * * * * 00

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6D +0x6D 120MODE * * * * * * * 00
6E +0x6E * * * * * * * * E8
6F +0x6F * * * * * * * * 00
70 +0x70 * * * * * * * * 00
71 +0x71 * * * * * * * * 00
72 +0x72 * * * * * * * * 00
73 +0x73 * * * * * * * * 00
74 +0x74 * * * * * * * * 00
75 +0x75 * * * * * * * * 00
76 +0x76 * * * * * * * * 00
77 +0x77 * * * * * * * * 00
78 +0x78 * * * * * * * * 00
79 +0x79 * * * * * * * * 00
7A +0x7A * * * * * * * * 00
7B +0x7B * * * * * * * * 00
7C +0x7C * * * * * * * * 00
7D +0x7D * * * * * * * * 30
7E +0x7E * * * * * * * * 00
7F +0x7F * * * * * * * * 00
80 +0x80 * * * * * * * RD_ON 00
81 +0x81 RD_ADDR[7:0] 00
* Setting values are separately presented.

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10.1.2. Description of Register

Related
Register Bits V sync Function
Items
Power save mode
9.2
PS0 1 0:Power save on
9.3
1:Power save off
MCLK polarity
MCLKPOL 1 0: Negative －
1: Positive
RGT 1 Selection of rightward / leftward scan 10.4
DWN 1 Selection of upward / down ward scan 10.4
YCB_DEC 1 Selection of YCbCr / YPbPr conversion 10.2
RGB_YCB 1 Selection of RGB / YCbCr (YPbPr) format 10.2
IF block output control
9.2
PS1 1 0: off (PS1 on)
9.2
1: output (PS1 off)
YCB_P 1 Selection of YCbCr (YPbPr) input pattern 10.2
CALSEL 2 VCAL output selection 10.5
VCAL_MON 1 Temperature sensing circuit monitoring on / off 10.5
ORBIT_H 5 ○ Horizontal orbit adjustment 10.10.1
ORBIT_V 5 ○ Vertical orbit adjustment 10.10.2
LUMINANCE 3 Luminance and white chromaticity preset mode selection 10.6
DITHERON 1 Dithering On/Off 10.9
OTPDG_REGDIS 1 White chromaticity preset mode on / off 10.6
OTPCALDAC_REGDIS 1 Luminance preset mode on / off 10.6

CONT 9 Contrast adjustment 10.8.1

RCONT 7 R sub-contrast adjustment 10.8.1

GCONT 7 G sub-contrast adjustment 10.8.1

BCONT 7 B sub-contrast adjustment 10.8.1

BRT 8 Brightness adjustment 10.8.2

RBRT 7 R sub-brightness adjustment 10.8.2

GBRT 7 G sub-brightness adjustment 10.8.2

BBRT 7 B sub-brightness adjustment 10.8.2

CALDAC 8 Manual luminance adjustment 10.7

H_ACT_U 9 Timing setting register ( setting value separately presented) 10.3
H_ACT_D 11 Timing setting register ( setting value separately presented) 10.3
V_ACT_U 8 Timing setting register ( setting value separately presented) 10.3
V_ACT_D 11 Timing setting register ( setting value separately presented) 10.3
DE_U 11 Timing setting register ( setting value separately presented) 10.3
DE_D 11 Timing setting register ( setting value separately presented) 10.3
WSST1_U 11 Timing setting register ( setting value separately presented) 10.3
WSST1_D 11 Timing setting register ( setting value separately presented) 10.3
WSST2_U 11 Timing setting register ( setting value separately presented) 10.3

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Related
Register Bits V sync Function
Items
WSST2_D 11 Timing setting register ( setting value separately presented) 10.3
WSEN1_U 9 Timing setting register ( setting value separately presented) 10.3

WSEN1_W 8 Timing setting register ( setting value separately presented) 10.3

WSEN2_U 11 Timing setting register ( setting value separately presented) 10.3

WSEN2_W 8 Timing setting register ( setting value separately presented) 10.3

WSEN3_U 8 Timing setting register ( setting value separately presented) 10.3

WSEN3_W 8 Timing setting register ( setting value separately presented) 10.3

DSEN_U 9 Timing setting register ( setting value separately presented) 10.3

DSEN_W 11 Timing setting register ( setting value separately presented) 10.3

VCK_U 10 Timing setting register ( setting value separately presented) 10.3

VCK_W 10 Timing setting register ( setting value separately presented) 10.3

SIGSELREF_U 10 Timing setting register ( setting value separately presented) 10.3

SIGSELREF_W 8 Timing setting register ( setting value separately presented) 10.3

SIGSELOFS_U 4 Timing setting register ( setting value separately presented) 10.3

SIGSELOFS_W 8 Timing setting register ( setting value separately presented) 10.3

SIGSEL_U 4 Timing setting register ( setting value separately presented) 10.3

SIGSEL_W 10 Timing setting register ( setting value separately presented) 10.3

SELREF_U 10 Timing setting register ( setting value separately presented) 10.3

SELREF_W 8 Timing setting register ( setting value separately presented) 10.3

SELOFS_U 8 Timing setting register ( setting value separately presented) 10.3

SELOFS_W 8 Timing setting register ( setting value separately presented) 10.3

SEL_U 10 Timing setting register ( setting value separately presented) 10.3

SEL_W 10 Timing setting register ( setting value separately presented) 10.3

AZEN_U 9 Timing setting register ( setting value separately presented) 10.3

AZEN_D 11 Timing setting register ( setting value separately presented) 10.3

RD_ON 1 Register read on / off 10.1.4

RD_ADDR 8 Register read address setting 10.1.4

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10.1.3. Serial I/F Write Access

Serial communication of normal / burst transfer, LSB first is supported for write operation.
Input the address of the objective register from SI pin (#16), then input the data to the address.
The timing of write access is shown below.

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10.1.4 Serial I/F Read Access

Serial communication of normal / burst transfer, LSB first is supported for read operation.

◆Register Settings

Address Register name Bits Function

Register read on / off
0x80 RD_ON 1 0: Off (default)
1: On

0x81 RD_ADDR 8 Register read address setting

Set RD_ON to 1, and then perform 2 times serial communication.

1st: Write the address of the objective register to RD_ADDR.
2nd: Read the data of the objective register from SO pin ( #17) after accessing to the RD_ADDR.
The timing of read access is shown below.

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10.2. Video Signal Transfer Format

Set the registers appropriately for the video signal transfer format according to the table below.

◆Register Settings

Address Register name Bits Function

Selection of RGB / YCbCr (YPbPr) format
0x00 RGB_YCB 1 0: RGB (default)
1: YCbCr and YPbPr
Selection of YCbCr / YPbPr conversion
0x00 YCB_DEC 1 0: YCbCr (BT. 601) (default)
1: YPbPr (BT. 709)
Selection of YCbCr (YPbPr) input pattern
0x01 YCB_P 1 0: Cb and Pb first (default)
1: Cr and Pr first

◆Register settings for each video signal transfer formats when YCB_DEC=0.
*Cb and Cr are replaced by Pb and Pr respectively when YCB_DEC=1.

Register settings
Video signal transfer format
RGB_YCB YCB_P

0 －

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Register settings
Video signal transfer format
RGB_YCB YCB_P

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10.3. Input Signal Data Format

Set the panel timing registers appropriately for the input signal data format.

◆Register Settings

Address Register name Bits Function

0x20 H_ACT_U Timing setting registers.
| | Should be set appropriately for the input signal data format.
0x59 AZEN_D Setting values are separately presented.

◆Panel Display Modes and Input Supported Formats

①Full-HD ②Full-HD ③Full-HD

59.94Hz / 60Hz Frame Rate 50Hz Frame Rate 47.952Hz / 48Hz Frame Rate

Panel Display Mode

Input Supported Format

H 1920 1920 1920

Active
V 1080 1080 1080

H 2200 2640 2750

Total
V 1125 1125 1125

H 88 528 638
FP
V 4 4 4

H 44 44 44
SYNC
V 5 5 5

H 148 148 148

BP
V 36 36 36

H 192 192 192

BP+SYNC
V 41 41 41

fv Hz 59.95 / 60 50 47.952 / 48

Th μs 14.830 / 14.815 17.778 18.537 / 18.519

Clock MHz 148.35 / 148.5 148.5 148.35 / 148.5

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10.4. Up/down and/or Right/left Inversion Function

Up/down and right/left inverse display of the panel are set by the registers RGT and DWN, respectively.

◆Register settings

Address Register Bits Setting Value

Selection of rightward / leftward scan
0x00 RGT 1 0: Leftward scan
1: Rightward scan (Default)
Selection of upward / downward scan
0x00 DWN 1 0: Upward scan
1: Downward scan (Default)

81 Pin 1 Pin 81 Pin 1 Pin

RGT=1

RGT=0

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10.5. Luminance Temperature Compensation Function

Organic EL panels have characteristics such that the luminance changes according to the temperature.

This product has a function that compensates the temperature dependence of the panel luminance.

◆Register Settings

Address Register name Bits Function

Display on/off when temperature sensor monitoring
0x01 VCAL_MON 1 0: on (Default)
1: off
VCAL output selection
00: (default)
0x01 CALSEL[1:0] 2
01: V1 output
10: V2 output

◆Method of Checking the Panel Temperature

The temperature sensor output voltage can be output from VCAL pin (#68).
Set the register VCAL_MON to 1: valid, set the register CALSEL as noted above, and read the V1 and V2 outputs. The
temperature can be calculated by subtracting V1 from V2.

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10.6. Luminance and White Balance Preset Mode

This product has 3 luminance and white balance preset modes.

By selecting the mode according to the register LUMINNACE, the luminance and the white chromaticity are adjusted to

preset value.

Register Settings

Address Register name Number of bits Function

Luminance adjustment
0x08 OTPCALDAC_REGDIS 1 0: Preset mode valid
1: Preset mode invalid (CALDAC adjustment)
White chromaticity adjustment
0x08 OTPDG_REGDIS 1 0: Preset mode valid
1: Preset mode invalid (CONT/BRT adjustment)
Luminance and white chromaticity preset mode selection
2: 90cd/m2, (0.313,0.329)
0x05 LUMINANCE[2:0] 3
0: 120cd/m2, (0.313,0.329)
3: 200cd/m2, (0.313,0.329)

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 ECX335AF

10.7. Luminance adjustment function

Manual luminance adjustment is performed by CALDAC register.

This function is valid when OTPCALDAC_REGDIS=1.

◆Register settings

Address Register name Bits Function

Luminance adjustment
0x08 OTPCALDAC_REGDIS 1 0: Preset mode valid
1: Preset mode invalid (CALDAC adjustment)
Luminance adjustment
0×1D CALDAC[7:0] 8 setting value: 1 to 255 (in decimal notation)
Default :128

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 ECX335AF

10.8. White Balance Adjustment Function

10.8.1. Contrast / Sub Contrast
RGB simultaneous and R, G and B separate contrast adjustment.
This function is valid when OTPDG_REGDIS=1.

 Register Settings

Address Register name Number of bits Function

White chromaticity adjustment
0x08 OTPDG_REGDIS 1 0: Preset mode valid
1: Preset mode invalid (CONT and R/G/BCONT adjustment)
0x14, 0x15 CONT 9 To RGB input signal, × 0 ... × 1 (Default) ... × 1.99

0x15 RCONT 7 Sets R relative to CONT to × 0.75 ... × 1 (Default) ... × 1.24

0x16 GCONT 7 Sets G relative to CONT to × 0.75 ... × 1 (Default) ... × 1.24

0x17 BCONT 7 Sets B relative to CONT to ×0.75 ... × 1 (Default) ... ×1.24

◆Contrast Adjustment
R, G and B are adjusted simultaneously relative to the input signal using the register CONT. The setting value is 0 to 511
(decimal notation).

CONT setting value 0 … 128 … 256 (Default) … 384 … 511

Gain (to input) ×0 … × 0.5 … ×1 … × 1.5 … × 1.99

256 200

192 150
Luminance [cd/m2]
Output gray level

128 100

64 50

0 0
0 64 128 192 256 0 64 128 192 256
Input gray level Input gray level

◆Sub Contrast Adjustment

R, G and B are adjusted separately using the registers RCONT, GCONT and BCONT, respectively.
The R, G and B gains can be set separately relative to the main CONT setting. The setting range is 0 to 127 (decimal
notation).

R/G/BCONT setting value 0 … 32 … 64 (Default) … 96 … 127

Gain (to CONT) × 0.75 … × 0.875 … ×1 … × 1.125 … × 1.24

256 256

192 192
Output gray level
Output gray level

128 128

64 64

0 0
0 64 128 192 256 0 64 128 192 256
Input gray level Input gray level

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 ECX335AF

10.8.2. Bright/Sub Bright

RGB simultaneous and R, G and B separate brightness adjustment.
This function is valid when OTPDG_REGDIS=1.

Register Settings

Address Register name Number of bits Function

White chromaticity adjustment
0x08 OTPDG_REGDIS 1 0: Preset mode valid
1: Preset mode invalid (BRT and R/G/BBRT adjustment)
0x18 BRT 8 To RGB input signal, -64 ... 0 (Default) ... +63 gradations

0x19 RBRT 7 Sets R relative to BRT to-32 ... 0 (Default) ... +31 gradations

0x1A GBRT 7 Sets G relative to BRT to-32 ... 0 (Default) ... +31 gradations

0x1B BBRT 7 Sets B relative to BRT to-32 ... 0 (Default) ... +31 gradations

◆Brightness Adjustment
R, G and B are adjusted simultaneously relative to the input signal using register BRT. The setting value is 0 to 255
(decimal notation).

BRT setting value 0 … 64 … 128(Default) … 192 … 255

Output gradations(to input) -64 … -32 … 0 … +32 … +63

256 200

lt)
fau

192 150
(de
Luminance [cd/m2]
Output gray level

28
25

4
=6
=1
T=

128 100
T
BR

BR
BR

64 50

0 0
0 64 128 192 256 0 64 128 192 256
Input gray level Input gray level

◆Sub Brightness Adjustment

R, G and B are adjusted separately using registers RBRT, GBRT and BBRT, respectively.
The R, G and B adjustments can be set separately relative to the main BRT setting. The setting range is 0 to 127
(decimal notation).

R/G/BBRT setting value 0 … 32 … 64 (Default) … 96 … 127

Output gradations (to BRT) -32 … -16 … 0 … +16 … +31

256 256

192 192
Output gray level

Output gray level

128 128

64 64

0 0
0 64 128 192 256 0 64 128 192 256
Input gray level Input gray level

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 ECX335AF

10.9. Dithering Function

This function expresses simulated gradations between the original gradations by using FRC.
This is used to interpolate gradations that decrease due to contrast or brightness adjustment.

◆Register Settings

Address Register name Bits Function

Dithering processing
0x05 DITHERON 1 0: Off
1: On

10.9.1. FRC (Frame Rate Control)

Simulated colors are expressed making use of frame rate and image lag effect of human eyes. When two colors are
switching alternately in high-speed, it looks an intermediate color for human eyes. Three simulated colors can be added
to original colors by changing data in 4-frame cycle making use of this property (2 bit FRC).

FRC simulated color image when noticing arbitral one pixel is shown below.

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 ECX335AF

10.10. Orbit Function

The image data start position can be changed. This enables reducing of the noticeability of local drops in luminance.

Max. 15 pixel shift

Full pixel area
1950(H) x 1110(V)

Max. 15 pixel shift Active area Max. 15 pixel shift

1920(H) x 1080(V)

Max. 15 pixel shift

◆Register Settings

Address Register name Bits Function

Horizontal orbit adjustment
0x02 ORBIT_H[4:0] 5 -15 to 0 to +15,
Default: 0
Vertical orbit adjustment
0x03 ORBIT_V[4:0] 5 -15 to 0 to +15,
Default: 0

10.1. Horizontal Display Position Shift

Change the display start position using the register ORBIT_H. The variable range is ± 15 pixels.

ORBIT_H setting value -15 … -1 0 (Default) 1 … 15

Leftward … Leftward Center Rightward … Rightward
Number of pixels shifted
15-pixel 1-pixel 1-pixel 15-pixel

10.2. Vertical Display Position Shift

The display start position is changed by the register ORBIT_V The variable range is ± 15 pixels.

ORBIT_V setting value -15 … -1 0 (Default) 1 … 15

Upward … Upward Center Downward … Downward
Number of pixels shifted
15-pixels 1-pixel 1-pixel 15-pixel

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 ECX335AF

11. Pixel Alignment

1110 pixels

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 ECX335AF

12. Optical Characteristics

12.1. Optical Characteristics

Item Symbol Min. Typ. Max. Unit

Mode 2 L2 76 90 104 Cd/m2
Luminance Mode 0 L0 102 120 138 Cd/m2
Mode 3 L3 170 200 230 Cd/m2
W2x 0.298 0.313 0.328 CIE
Mode 2
W2y 0.314 0.329 0.344 CIE
White W0x 0.298 0.313 0.328 CIE
Mode 0
chromaticity W0y 0.314 0.329 0.344 CIE
W3x 0.298 0.313 0.328 CIE
Mode 3
W3y 0.314 0.329 0.344 CIE
Rx 0.635 0.655 0.675 CIE
R
Ry 0.310 0.330 0.350 CIE
Monochrome Gx 0.255 0.275 0.295 CIE
G
chromaticity Gy 0.625 0.645 0.665 CIE
Bx 0.127 0.147 0.167 CIE
B
By 0.045 0.065 0.085 CIE
Contrast CR 10,000 ― ―

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 ECX335AF

12.2. Measurement System・Measurement Method

Measurement temperature: Tpnl = 40°C
Measurement point: One point on the screen center
Regisiter setting: OTPCALDAC_REGDIS = 0、OTPDG_REGDIS = 0

Item Pattern / Gray level Register setting Method

L2,W2x,W2y LUMINANCE = 2
Luminance / R=255
White L0,W0x,W0y White raster G=255 LUMINANCE = 0 Measured by system A
chromaticity B=255
L3,W3x,W3y LUMINANCE = 3

Rx,Ry Red raster R=255

Monochrome
Gx,Gy Green raster G=255 Measured by system A
chromaticity
Bx,By Blue raster B=255
White:
R=255
G=255
White & black B=255 Measured by system A
Contrast CR LUMINANCE = 3
raster Black: Contrast = white / black
R=0
G=0
B=0

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 ECX335AF

13. Package Outline (Nagasaki 200mm wafer)

(Unit：mm)

See details: pin bock

Light emission

Weight: 2.0g
Item

FPC
Reinforcing Plate

Frame

Stiffner

Product name: ECX335AF

Details: pin bock

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 ECX335AF

Package Outline (Kumamoto 300mm wafer) Tentative

(Unit：mm)

See details : pin bock

Light emission

Weight : 2.0g

Item

FPC
Reinforcing Plate

Frame

Stiffner

Product name : ECX 335 AF

Details : pin bock

36
 ECX335AF

14. Recommended Items

14.1. Suppression of the Panel Temperature

Organic EL panel temperatures rise due to power consumption (heat generation) by the EL emissive layer and the silicon
drive board. A rise in the panel temperature may affect the drop in luminance over time.
The rise in panel temperature can be suppressed by establishing a thermal connection between the rear surface (silicon
board surface) of the panel and metal (chassis, frame, etc.) in the panel mount area.

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 ECX335AF

15. Notes on Handling

15.1. Static charge prevention

Be sure to take the following protective measures. Organic EL panels are easily damaged by static charges.
(1) Use non-chargeable gloves, use bare hands.
(2) Use a wrist strap when handling.
(3) Do not touch any electrodes of the panel.
(4) Wear non-chargeable clothes and conductive shoes.
(5) Install grounded conductive mats on the working floor and working table.
(6) Keep the panel away from any charged materials.

15.2. Protection from dust and dirt

(7) Operate in a clean environment.
(8) Do not touch the panel surface. The surface is easily scratched.
When cleaning, use a clean-room wiper with isopropyl alcohol. Be careful not to leave stains on the surface.
(9) Use ionized air to blow dust off the panel surface.

15.3. Others
(10) Do not hold the flexible board or twist or bend it because the flexible board connection block is easily affected by
twisting.
(11) The minimum fold radius of the flexible board is 1 mm.
(12) Do not drop the panel.
(13) Do not twist or bend the panel.
(14) Keep the panel away from heat sources.
(15) Do not dampen the panel with water or other solvents.
(16) Do not store or use the panel (module) at high temperatures or high humidity,
as this may affect the characteristics.
(17) When disposing of this panel, handle it as industrial waste and comply with related regulations.
(18) Do not store or use the panel in reactive chemical substance (including alcohol) environments, as this may affect
the performance.
(19) This panel is delivered packed in a degassed aluminum laminated bag.
When storing this panel after unsealing the bag, put it into the aluminum laminated bag again and seal it with tape
with the opening folded after inserting desiccants.

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