APM81911

40 V, 3 A, Synchronous Buck Regulator Module

with Low EMI and 6 µA Quiescent Current

FEATURES AND BENEFITS DESCRIPTION

• AEC-Q100 Grade 1 qualified The APM81911 is a highly integrated, 3 A, low EMI, DC-
• ClearPower module DC/DC converter with internal DC buck regulator module that satisfies demanding power
passive components delivery requirements. The APM81911 includes a high-per-
• VIN Range: 3.5 to 36 V operating, 40 V transient formance DC-DC regulator IC, two capacitors, and an induc-
• VOUT: 0.8 to 24 V, ±1.5% accuracy, ‒40°C to 150°C tor in a compact 4 mm × 6 mm QFN package. The module
• Up to 3 A of continuous output current includes all the control and protection circuitry necessary
• Ultra-Low EMI design and selectable spread spectrum to produce a robust and scalable DC-DC regulator solution
to easily pass CISPR25 Class 5 with ±1.5% output voltage accuracy over the full operating
• Low-Power (LP) mode: 6 µA IQ from VIN at no load, temperature range.
automatic transition from LP to PWM mode The fixed frequency, peak current mode control is program-
• Fixed Frequency PWM (fOSC): 1 MHz to 2.4 MHz, mable from 1 MHz to 2.4 MHz, ensuring rapid response to
programmable load and line transients. A 2.15 MHz PWM switching fre-
• Synchronization (1 MHz to 2.4 MHz): PLL-based, quency is programmed by connecting the FSET pin to VCC.
fSYNC can be above or below fOSC The VIN and BOOT pin bypass capacitors are integrated
• CLKOUT: Phase-shifted clock output for reduced EMI in into the module to greatly reduce noise-generating hot loops
multi-converter systems which significantly improves radiated EMI. Spread spectrum
• Accurate enable input threshold operation (dithering) is available to further reduce EMI. The
• Overvoltage, pulse-by-pulse current limit, hiccup mode APM81911-1 part variant is available for applications where
short-circuit, and thermal protections dithering is not desired.
• Robust FMEA: pin open/short and component faults
The Low Power (LP) mode maintains the output voltage at
APPLICATIONS: no-load or very light load conditions while drawing only
microamps from VIN. At no-load, the APM81911 draws
• Infotainment • ADAS
only 6 µA. The transition between PWM and LP modes
• Navigation systems • Industrial systems
is automatic in response to the load demand. PWM-only
PACKAGE: operation is available to prevent pulse skipping at light load
32-pin QFN conditions.
4 mm × 6 mm × 2.1 mm Continued on next page...
with wettable flank
(suffix NB)
Not to scale

PWM/AUTO BIAS
APM81911 BOOT
EN PGOOD
47nF PGOOD
SYNCIN 3.0A Buck Switcher
VOUT VOUT
VIN
1.5µH RFB1
CIN 47nF FB CO
RFB2
GND PWM
Controller SW
PGND CFF

VCC

SS
CLKOUT
FSET
COMP
CZ CP

RZ

Figure 2: APM81911 Radiated

Emissions from 150 kHz to 30 MHz
Figure 1: APM81911 Typical Application Circuit
(Monopole Antenna)

APM81911-DS, Rev. 2 May 18, 2023

MCO-0001354
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

DESCRIPTION (continued) Table of Contents

Features and Benefits............................................................ 1
The APM81911 can synchronize to an external clock signal
Description........................................................................... 1
with frequency ranging from 1 MHz to 2.4 MHz applied to the Applications.......................................................................... 1
SYNC_IN pin. The APM81911 provides a CLKOUT pin so Package.............................................................................. 1
“downstream” regulators can easily be interleaved and dithered Typical Application Circuit....................................................... 1
Selection Guide.................................................................... 2
via their synchronization inputs.
Absolute Maximum Ratings.................................................... 2
The APM81911 includes adjustable soft-start, an open-drain Thermal Characteristics......................................................... 2
Pinout Diagram and Terminal List............................................ 3
power good output, and a low shutdown current of 1 µA. The ac-
Functional Block Diagram...................................................... 4
curate enable input allows for programmable turn-on and turn-off Electrical Characteristics........................................................ 5
thresholds. EMI/EMC Performance Characteristics.................................... 9
Functional Description......................................................... 10
Extensive protection features of the APM81911 include pulse-by- Protection Features............................................................. 14
pulse current limit, hiccup mode short-circuit protection, BOOT Application Information........................................................ 16
open/short voltage protection, VIN undervoltage lockout, VOUT over- Application Schematic and Recommended External Components... 23
Power Dissipation and Thermal Calculations.......................... 24
voltage protection, and thermal shutdown. The APM81911 is offered
PCB Layout Guidelines........................................................ 25
in a thermally enhanced, 4 mm × 6 mm × 2.1 mm 32-pin wettable Package Outline Drawing and Recommended PCB Footprint... 27
flank QFN package (suffix “NB”) with exposed power pads. Revision History.................................................................. 29

SELECTION GUIDE
Part Number Dither Description Packing [1] Lead Finish
APM81911KNBJSR Enabled 32-pin wettable flank QFN package 3000 pieces
Matte Tin
APM81911KNBJSR-1 Disabled with thermal pad per 13-inch reel

[1] Contact Allegro for additional packing options.

ABSOLUTE MAXIMUM RATINGS [1]

Characteristic Symbol Notes Rating Unit
VIN, VEN,
VIN, EN, PGOOD, BIAS –0.3 to 40 V
VPGOOD, VBIAS
VOUT VOUT –0.3 to 24 V
Continuous –0.3 [2] to VIN + 0.3 V
SW VSW
VIN ≤ 36 V, t < 50 ns –1.0 to VIN + 2 V
Continuous VSW – 0.3 to VSW + 3.5 V
BOOT VBOOT
t < 1 ms VSW – 0.3 to VSW + 7.0 V
All other pins –0.3 to 5.5 V
Operating Junction Temperature TJ(max) –40 to 150 °C
Storage Temperature TSTG –55 to 150 °C
[1] Stresses beyond those listed in this table may cause permanent damage to the device. The absolute maximum ratings are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated in the Electrical Characteristics table is not implied. Expo-
sure to absolute-maximum-rated conditions for extended periods may affect device reliability.
[2] This voltage is a function of temperature.

THERMAL CHARACTERISTICS [1]: May require derating at maximum conditions; see application section
Characteristic Symbol Test Conditions* Value Unit
Package Thermal Resistance RθJA On 4-layer PCB based on JEDEC standard 48 °C/W
[1] Additional thermal information available on the Allegro website.

2
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

PINOUT DIAGRAM AND TERMINAL LIST

QFN-32 Pinout Diagram Terminal List
Number Name Function
PCB schematic and layout library files
available for download on the APM81911 1, 2, 3, 30, 31, 32 VOUT Power output of buck regulator. Connect output filter capacitor from this pin to GND.
product page 5, 6, 7 PGND Power ground pins for the lower MOSFET, gate driver, and BOOT charge circuit.
Power input for the control circuits and the drain of the internal high-side N-channel
MOSFET. A high-quality ceramic capacitor should be connected directly between VIN and
VOUT
VOUT
VOUT

9, 10 VIN
SW
SW

PGND with short and wide PCB traces to minimize EMI. The package pinout is designed
32 31 30 28 27 with this consideration.
VOUT 1 EN/UV is an input to a hysteretic comparator with an accurate 1.2 V (typical) threshold.
VOUT 2 25 BOOT A voltage on EN/UV above the nominal 1.2 V threshold enables the APM81911. Once
VOUT enabled, the EN/UV comparator has a typical hysteresis of 300 mv. Once enabled, if EN/
VOUT 3
11 EN/UV UV is lowered below 0.9 V (typical), the APM81911 will enter the shutdown state, stop
switching and draw only 1 uA (typical) from Vin. Connect EN/UV directly to VIN for “always-
PGND 5 22 BIAS on” applications. When EN is not connected directly to VIN, the rising edge of EN must be
compatible to a digital signal.
PGND 6 PGND 21 PGOOD
PGND Soft-start pin. Connect a capacitor, CSS, from this pin to GND to set the startup time. This
7 20 GND 12 SS capacitor also determines the hiccup period during overcurrent. Connect SS directly to VCC
19 COMP to program a fixed 880 µs (typical) startup time.

VIN 9 18 VCC Frequency setting pin. A resistor, RFSET, from this pin to GND sets the base oscillator
VIN
13 FSET frequency, fOSC. Connect FSET directly to VCC to program a fixed 2.15 MHz (typical)
VIN 10 17 CLKOUT
frequency.
11 12 13 14 15 16
Feedback, negative input to the error amplifier. Connect a resistor divider from the
14 FB
FSET
FB
PWM/AUTO
SYNCIN
EN/UV
SS

regulators output, VOUT, to this pin to program the output voltage.

Dual function pin: High/Low. Setting this pin high forces PWM mode. Setting this pin low
15 PWM/AUTO
allows AUTO changeover between PWM and LP mode based on the load current.
Triple function pin: High/Low/ExtClock. Setting this pin high sets CLKOUT to the internal
oscillator frequency (fOSC) but with 180-degree phase shift. Setting this pin low disables
16 SYNCIN the CLKOUT pin. Applying an external clock forces PWM mode, synchronizes the PWM
switching frequency to the external clock, adds dithering, and sets CLKOUT to the same
dithered frequency but with 180-degree phase shift. See Table 3 for details.
Clock output pin. Frequency dithering is added to this pin. The exact functionality of this pin
17 CLKOUT is dependent on the status of the SYNCIN pin, see Table 1 and the description for SYNCIN
for additional details.
Internal voltage regulator bypass capacitor pin. Connect a 4.7 µF capacitor from this pin to
18 VCC
PGND and place it very close to the APM81911.
Output of the error amplifier and compensation node for the current-mode control loop.
19 COMP
Connect a series RC network from this pin to GND for loop compensation.
20 GND Analog ground pin.
Power good output signal. This pin is an open-drain output that transitions from low to high
impedance after the output has maintained regulation for tdPG(SU). If the output voltage is out
21 PGOOD
of range (undervoltage or overvoltage), this pin will be low impedance. Connect a resistor
from PGOOD to VCC for PGOOD to report a logic low when out of regulation.
Output voltage sense pin. This pin should be connected to the output of the regulator.
22 BIAS Voltage at this pin sets the internal slope compensation. It also supplies the internal circuitry
when output voltage is high enough.
This pin supplies the gate drive for the buck coverter’s high-side N-channel MOSFET. An
25 BOOT
internal 47 nF ceramic capacitor connects this pin to SW. Leave this pin open.
27, 28 SW Switching node of the buck converter. Leave this pin open.
Exposed VIN, VOUT, and PGND exposed pads should be soldered to their respective traces for
–
PADS enhanced thermal dissipation.

3
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

FUNCTIONAL BLOCK DIAGRAM

VIN
BIAS
VIN CBYP
VCC LD
UVLO
3.55V
3.3V
BIAS >3.15V EN
REGOK 0.8V BOOT REG BOOT
LDO BG
1.2V

BOOT FAULT
VCC Current
REGOK
2.5V Sense Amp
EN ENd Gcs

REGOK
tDIS

UVLO
1.2V CBOOT

OCL
ENd
FB
Div 2 or 4
Start up or Hiccup toff SWGNDSC
VCC
Protec�on & Fault VINSWSC

FSET PLL+
FBUV

FBOV

OSC
Dither SW
TSD
SYNCIN HD

CLK
VOUT
CLKOUT PWM PWM/LP
T/2 Control
Slope COMP
VOUT Logic VCC
Compensation
Ramp LD
FAULT

PWM/ MODE Offset

AUTO
MODE

SLEEP

PGND

0.74V
GND
FBUV

PGOOD
OCL

FBOV
0.88V
Delay Over Current
Hiccup, Dropout, Stop- Clamp Error Amp
Start Recovery, Fault,
FB
Start-up 0.8V
SS SS

LP Comparator
Comparator MODE SS
Offset
FB
LP
SLEEP Clamp
0.804V

MODE COMP

Figure 3: Functional Block Diagram

4
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

ELECTRICAL CHARACTERISTICS: Valid at 3.5 V ≤ VIN ≤ 36 V, −40°C ≤ TJ ≤ 150°C, unless otherwise noted
Characteristics Symbol Test Conditions Min. Typ. Max. Unit
INPUT VOLTAGE SPECIFICATIONS
Input Voltage Range [2] VIN VIN must first rise above VUVLO(ON,MAX) 3.5 − 36 V
UVLO Start VUVLO(ON) VIN rising 3.35 3.55 3.8 V
UVLO Stop VUVLO(OFF) VIN falling 3.1 3.3 3.5 V
UVLO Hysteresis VUVLO(HYS) − 250 − mV
INPUT SUPPLY CURRENT
Input Shutdown Current [1] IIN(SD) VIN = 12 V, VEN = 0 V, VSW = VIN, TJ = 25°C [3] − 1 2.9 µA
Input Current, PWM Mode [1] IIN(PWM) VIN = 12 V, VEN = 2 V, no load, no switching − 5 6.5 mA
VIN = 12 V, IOUT = 0 µA, TJ = 25°C,
− 6 − µA
BIAS connected to VOUT
3.3 VOUT LP Input Current [3][4] ILP(3.3V)
VIN = 12 V, IOUT = 50 µA, TJ = 25°C,
− 24.3 − µA
BIAS connected to VOUT
VIN = 12 V, IOUT = 0 µA, TJ = 25°C,
− 7.5 − µA
BIAS connected to VOUT
5.0 VOUT LP Input Current [3][4] ILP(5.0V)
VIN = 12 V, IOUT = 50 µA, TJ = 25°C,
− 40 − µA
BIAS connected to VOUT
REGULATION ACCURACY (FB PIN)
Feedback Voltage Accuracy VFB –40°C < TJ < 150°C, VIN ≥ 3.5 V 788 800 812 mV
SWITCHING FREQUENCY AND DITHERING (FSET PIN)
FSET connected to VCC 1.98 2.15 2.42 MHz
RFSET = 34 kΩ 0.90 1.00 1.10 MHz
PWM Switching Frequency fOSC RFSET = 71.5 kΩ 450 500 550 kHz
RFSET = 86.6 kΩ 360 410 460 kHz
External clock on SYNCIN pin at fSW(SYNC) − fSW(SYNC) − kHz
Dropout Switching Frequency [3] fSW(DO) − fOSC / 2 − kHz
APM81911KNJSR − ±5 ±6.5 % fOSC
PWM Frequency Dither Range fDITH(RNG)
APM81911KNJSR-1 − 0 − % fOSC
PWM Dither Modulation Frequency fDITH(FREQ) − ±0.5 − % fOSC
PULSE-WIDTH MODULATION (PWM) TIMING AND CONTROL
Minimum SW On-Time tON(MIN) VIN = 12 V, IOUT = 0.7 A, VBOOT – VSW = 3.3 V − 60 90 ns
Minimum SW Off-Time tOFF(MIN) VIN = 12 V, IOUT = 0.7 A − 55 75 ns
COMP to SW Current Gain gmPOWER − 5.0 − A/ V
PWM Ramp Offset VPWM(OFFS) − 650 − mV
LOW POWER (LP) MODE
LP Output Voltage Ripple [3][4] ΔVOUT(LP) LP Mode, 8 V < VIN < 16 V, COUT = 47 µF − 65 − mV

Continued on the next page…

5
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, −40°C ≤ TJ ≤ 150°C, unless otherwise noted
INTERNAL MOSFET PARAMETERS
TJ = 25°C [3], VBOOT – VSW = 3.3 V, IDS = 1 A − 115 140 mΩ
High-Side On Resistance RDS(ON)HS
TJ = 150°C, VBOOT – VSW = 3.3 V, IDS = 1 A − − 230 mΩ
TJ = 25°C [3], VIN ≥ 4.5 V, IDS = 1 A − 85 115 mΩ
Low-Side On Resistance RDS(ON)LS
TJ = 150°C, VIN ≥ 4.5 V, IDS = 1 A − − 195 mΩ
High-Side Leakage Current [3] ILKG(HS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 0 V − − 3.5 µA
Low-Side Leakage Current [3] ILKG(LS) TJ = 25°C, VIN = 12 V, VEN = 0 V, VSW = 12 V − − 1.5 µA
Gate Drive Non-Overlap Time [3] tNO VBOOT – VSW = 3.3 V − 1.5 4 ns
Switch Node Rising Slew Rate SRHS 12 V < VIN < 16 V, VBOOT – VSW = 3.3 V − 7 − V/ns
MOSFET CURRENT PROTECTION THRESHOLDS
High-Side Current Limit ILIM(HS) tON = tON(MIN) 4.0 4.5 5.0 A
Low-Side Negative Current Limit ILIM(LS) − 2.0 − A
SYNCHRONIZATION INPUT (SYNC IN PIN)
Synchronization Frequency Range fSW(SYNC) 1 − 2.5 MHz
SYNCIN Duty Cycle DCSYNC 20 50 70 %
SYNCIN Pulse-Width tPW(SYNC) 80 − − ns
VSYNC(HI) VSYNC(IN) rising − 1.35 1.5 V
SYNCIN Voltage Thresholds
VSYNC(LO) VSYNC(IN) falling 0.8 1.2 − V
SYNCIN Hysteresis VSYNC(HYS) VSYNC(HI) ‒ VSYNC(LO) − 150 − mV
SYNCIN Pin Current ISYNC VSYNC(IN) = 5 V − 1 − µA
CLOCK OUTPUT (CLK OUT PIN)
SYNCIN to CLKOUT Delay ФSYNC(CLK) RFSET = 14.3 kΩ, VSYNC(HI) = 3.3 V − 1/(2fOSC)±70 − ns
VCLK(OUT,H) VCC = 3.3 V 2.2 − − V
CLKOUT Output Voltage
VCLK(OUT,L) VCC = 3.3 V − − 0.6 V
ERROR AMPLIFIER (COMP PIN)
Feedback Input Bias Current [1] IFB VFB = 800 mV –50 – –10 nA
Open Loop Voltage Gain AVOL − 60 − dB
VFB > 400 mV 500 750 1000 μA / V
Transconductance gm
0 V < VFB < 400 mV 270 400 540 μA / V
Output Current IEA − ±75 − μA
COMP Pull-Down Resistance RCOMP FAULT = 1 or HICCUP = 1 − 1 − kΩ

Continued on the next page…

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Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, −40°C ≤ TJ ≤ 150°C, unless otherwise noted
SOFT-START (SS PIN)
Startup (Source) Current ISS HICCUP = FAULT = 0 −30 −20 −10 µA
Hiccup (Sink) Current IHIC HICCUP = 1 1 2.2 5 µA
Soft-Start Delay Time [3] tdSS CSS = 22 nF − 440 − µs
Soft-Start Ramp Time [3] tSS CSS = 22 nF − 880 − µs
FAULT/HICCUP Reset Voltage VSS(RST) VSS falling due to HICCUP or FAULT − 200 275 mV
Hiccup OCP (and LP) Counter
VHIC/LP(EN) VSS rising − 2.3 − V
Enable Threshold
0 V < VFB < 100 mV − fOSC / 8 − kHz
100 mV < VFB < 200 mV − fOSC / 4 − kHz
Soft-Start Frequency Foldback fSW(SS)
200 mV < VFB < 400 mV − fOSC / 2 − kHz
400 mV < VFB − fOSC − kHz
Maximum Voltage VSS(MAX) VEN = 0 V or FAULT without HICCUP − VCC − V
Pull-Down Resistance RSS(FLT) − 2 − kΩ
HICCUP MODE COUNTS
High-Side Overcurrent Count HICOC After VSS > VHIC/LP(EN) − 120 − fOSC counts
SW Short-to-Ground Count HICSW(GND) − 3 − fOSC counts
BOOT Short-Circuit Count HICBOOT(SC) − 120 − fOSC counts
BOOT Open-Circuit Count [3] HICBOOT(OC) − 7 − fOSC counts
OUTPUT VOLTAGE PROTECTION THRESHOLDS (V FB, OV, UV)
VFB OV PWM Threshold VFB(OV) VFB rising 840 860 880 mV
VFB OV PWM Hysteresis VFB(OV,HYS) VFB falling, relative to VFB(OV) − 10 − mV
VFB UV PWM Threshold VFB(UV) VFB falling 710 740 770 mV
VFB UV PWM Hysteresis VFB(UV,HYS) VFB rising, relative to VFB(UV) − 10 − mV
VFB UV LP Mode Threshold [3] VFB(UV,LP) VFB falling 665 700 735 mV
POWER GOOD OUTPUT (PGOOD PIN)
PGOOD Startup (SU) Delay tdPG(SU) Increasing VFB due to startup − 30 − µs
PGOOD Undervoltage (UV) Delay tdPG(UV) Decreasing VFB 80 120 − µs
PGOOD Overvoltage (OV) Delay tdPG(OV) After overvoltage event − 240 − fOSC cycles
PGOOD Low Output Voltage VPG(L) IPGOOD = 5 mA − 200 400 mV
PGOOD Leakage [1] IPG(LKG) VPGOOD = 5.5 V − − 2 µA
PWM/AUTO INPUT
PWM/AUTO High Threshold VHI(PWM) VPWM/AUTO rising 1.8 2.0 2.5 V
PWM/AUTO Low Threshold VLO(PWM) VPWM/AUTO falling 0.6 0.8 1.0 V
PWM/AUTO low, VSS > VHIC/LP(EN),
PWM to LP Transition Delay [3] tdPWM(LP) − 7.5 − ms
PGOOD high

Continued on the next page…

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Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

ELECTRICAL CHARACTERISTICS (continued): Valid at 3.5 V ≤ VIN ≤ 36 V, −40°C ≤ TJ ≤ 150°C, unless otherwise noted
ENABLE VOLTAGE INPUT (EN PIN)
EN High Threshold VEN(HI) VEN rising 1.15 − 1.35 V
EN Input Hysteresis VEN(HYS) VEN(HI) – VEN(LO) 200 300 400 mV
Disable Delay DISDLY VEN transitions low to when SW stops switching − 120 − fOSC cycles
EN Pin Input Current IEN VEN = 5 V − 2 − µA
BOOT REGULATOR (BOOT PIN)
BOOT Charging Frequency fBOOT − fOSC − kHz
BOOT Voltage VBOOT VIN = 12 V, VBIAS = 0 V, VBOOT – VSW − 3.3 3.6 V
INTERNAL REGULATOR (VCC PIN)
BIAS Disconnected VCC1 6 V < VIN < 36 V, VBIAS = 0 V 3.25 3.45 3.65 V
VBIAS = 3.3 V 2.85 3.2 3.29 V
BIAS Connected VCC2
6 V < VBIAS < 36 V 3 3.35 3.75 V
BIAS Input Voltage Range VBIAS 3.15 − 36 V
BIAS OVERVOLTAGE PROTECTION (BIAS PIN)
VBIASOV(FBLO) VFB ≤ 200 mV − − 7.5 V
BIAS Overvoltage Protection
VBIASOV(FBHI) VFB = 800 mV 24.6 − 27.5 V
THERMAL SHUTDOWN
TJ rising, PWM stops immediately and COMP
Thermal Shutdown Threshold [3] TSD 155 170 − °C
and SS are pulled low
Thermal Shutdown Hysteresis [3] TSD(HYS) TJ falling, relative to TSD − 20 − °C

[1] Negative current is defined as coming out of the node or pin, positive current is defined as going into the node or pin.
[2] Thermally limited depending on input voltage, duty cycle, regulator load currents, PCB layout, and airflow.
[3] Ensured by design and characterization, not production tested.
[4] Must use component values shown in Table 3, Recommended External Component Values.

8
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

EMI/EMC PERFORMANCE CHARACTERISTICS

VIN = 12 V, VOUT = 5 V, fSW = 2.15 MHz

Conducted Emissions (150 kHz to 30 MHz) Radiated Emissions (150 kHz to 30 MHz) (Monopole)

Radiated Emissions (30 MHz to 330 MHz) Radiated Emissions (30 MHz to 330 MHz)
(Horizontal Biconical) (Vertical Biconical)

NOTE: Allegro is not an accredited EMC laboratory. The information presented here is for reference only.

9
Allegro MicroSystems
955 Perimeter Road
Manchester, NH 03103-3353 U.S.A.
www.allegromicro.com
 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

FUNCTIONAL DESCRIPTION
Overview Synchronization (SYNCIN) and
The APM81911 is a wide input voltage (3.5 to 36 V) synchronous Clock Output (CLKOUT)
PWM buck regulator that integrates low RDS(on) high-side and The Phase-Locked Loop (PLL) in the APM81911 allows its
low-side N-channel MOSFETs. A low DCR inductor and two internal oscillator to be synchronized to an external clock applied
capacitors (VIN capacitor and BOOT capacitor) are also integrated on the SYNCIN pin. If the SYNCIN pin is driven by an external
in the APM81911’s compact 4 mm × 6 mm × 2.1 mm package. The clock, the APM81911 will be forced to operate in PWM mode,
APM81911 employs peak current mode control to provide superior with synchronized switching frequency, overriding the mode
line and load regulation, cycle-by-cycle current limit, fast transient selection on the PWM/AUTO pin. The external clock must sat-
response, and simple compensation. The features of the APM81911 isfy the pulse-width, duty cycle, and rise/fall time requirements
include ultra-low IQ LP mode, extremely low minimum on-time, shown in the Electrical Characteristics table. If the SYNCIN pin
maximized duty cycle for low dropout operation, and pre-bias is continuously pulled high, the APM81911 outputs a 180-degree
startup capability. phase-shifted internal oscillator clock on the CLKOUT pin, so
Protection features of the APM81911 include VIN undervoltage “downstream” APM81911 devices can be easily interleaved via
lockout, cycle-by-cycle overcurrent protection, BOOT over- their synchronization inputs. Figure 5 shows the usage of mul-
voltage and undervoltage protection, hiccup mode short-circuit tiple APM81911 devices in master-follower configuration. If the
protection, overvoltage protection, and thermal shutdown. In SYNCIN pin is continuously pulled low, the device disables the
addition, the APM81911 provides open-circuit, adjacent pin CLKOUT pin. The internal switching frequency dithering can be
short-circuit, and pin-to-ground short-circuit protection. disabled by pulling the CLKOUT pin high on APM81911 devices
or by using the APM81911-1.
Reference Voltage
Transconductance Error Amplifier
The APM81911 incorporates an internal precision reference
that allows output voltages as low as 0.8 V. The accuracy of the The transconductance error amplifier’s primary function is to con-
internal reference is ±1.5% across –40°C to 150°C. The output trol the regulator’s output voltage. The error amplifier is a three-
voltage of the regulator is programmed with a resistor divider terminal input device with two positive inputs and one negative
between VOUT and the FB pin of the APM81911. input, as shown in Figure 4. The negative input is simply con-
nected to the FB pin and is used to sense the feedback voltage for
Internal VCC Regulator regulation. The error amplifier performs an “analog OR” selection
VCC is used as power supply for internal control circuitry and between its positive inputs and operates according to the positive
low-side MOSFET driver. APM81911 consists of two internal input with the lowest potential. The two positive inputs are used for
low dropout regulators, VIN LDO and VBIAS LDO, to generate soft-start and steady-state regulation. The error amplifier regulates
VCC voltage. VIN LDO is powered from the input voltage to gen- to the soft-start pin voltage minus 400 mV during startup and to the
erate 3.5 V for VCC supply during power up, soft-start and PWM internal reference (VREF) during normal operation.
mode. VBIAS LDO uses the VBIAS pin, connected to VOUT, as
400 mV
a supply to generate VCC voltage in LP mode to reduce current
consumption from VIN.
–
Oscillator/Switching Frequency SS Pin + Error Amplifier

The PWM switching frequency of the APM81911 is adjustable +

from 1 MHz to 2.4 MHz by programming the internal clock + Comp

frequency of the oscillator by connecting an FSET resistor from Pin
VREF + –
the FSET pin to GND. The internal clock has an accuracy of 800 mV –
about ±10% over the operating temperature range. Usually, an
FSET resistor with ±1% tolerance is recommended. A graph of
switching frequency versus FSET resistor value is shown in the
PWM Switching Frequency (RFSET) section. The APM81911 will FB Pin
suspend operation if the FSET pin is shorted to GND or left open.
Figure 4: APM81911 Error Amplifier

10
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

Ultra-Low Quiescent Current Low Power (LP) Mode Integrated Passive Components
The APM81911 operates in ultra-low IQ LP mode when PWM/ The APM81911 module integrates a high-performance DC-DC
AUTO pin is pulled to logic low. If the PWM/ AUTO pin transi- regulator IC, a low DCR inductor, and two ceramic capacitors in
tions from logic high to logic low while output is in regulation, a compact 4 mm × 6 mm × 2.1 mm package:
the device waits for 7 clock cycles before entering the LP mode. • Inductor = 1.5 μH ±20% at 1 MHz, DCR= 52 mΩ
This delay provides adequate filtering to ensure no noise tran-
sients forces the device to erroneously enter LP mode. • VIN capacitor (CVIN) = 47 nF

When LP mode is selected, the APM81911 operates in continu- • BOOT capacitor (CBOOT) = 47 nF
ous conduction PWM Mode until peak inductor current decreases The bootstrap capacitor is connected between the BOOT and SW
to IPEAK(LP). When peak inductor current falls below IPEAK(LP), pins to provide floating gate drive to the high-side MOSFET,
the LP comparator monitors FB node and regulates the output while the VIN capacitor is used to bypass high di/dt input ripple
voltage in hysteretic manner. The reference for the LP compara- current, minimizing the EMI.
tor is calibrated approximately 0.5% above the PWM regulation
point. The transition point from PWM to LP mode is defined by
Soft-Start (Startup) and Inrush Current Control
the input voltage, output voltage and inductor value. The soft-start function controls the inrush current at startup. The
soft-start pin (SS) is connected to GND via a capacitor. When
When voltage on the COMP pin falls to the voltage correspond-
the APM81911 is enabled and all faults are cleared, the SS pin
ing to the ultra-low IQ peak current threshold value, an internal
sources the charging current ISS and the voltage on the soft-start
clamp prevents the COMP voltage from falling further. This
capacitor CSS starts ramping upward from 0 V. When the voltage
results in a momentary rise in the FB voltage beyond the LP com-
at the soft-start pin exceeds the soft-start offset voltage (SS Off-
parator upper threshold which causes the LP comparator to trip.
set), typically 400 mV, the error amplifier will ramp up its output
Once the LP comparator trips, the device enters a coast period
voltage above the PWM Ramp Offset. At this instant, the top and
during which MOSFET switching is terminated and the associ-
bottom MOSFETs will begin switching. There is a small delay
ated control circuitry is also shut down. This ensures a very low (tdSS) from the moment EN pin transitions high to the moment
quiescent current is drawn from the input. soft-start voltage reaches 400 mV to initiate PWM switching.
The coast period terminates once the FB voltage falls below the Immediately after the start of PWM switching, the error amplifier
LP comparator lower threshold. The device will fully power-up will regulate the voltage at the FB pin to the soft-start pin voltage
after approximately a 2.5 μs delay and the high-side MOSFET is minus approximately 400 mV. During the active portion of soft-
repeatedly turned on, operating at the PWM switching frequency start, the voltage at the SS pin will rise from 400 mV to 1.2 V
until the voltage at the FB pin rises again above the LP compara- (a difference of 800 mV), the voltage at the FB pin will rise from
tor threshold. The rate of rise of output voltage is determined by 0 V to 800 mV, and the regulator output voltage will rise from
the input voltage, output voltage, inductor value, output capaci- 0 V to the set voltage determined by the feedback resistor divider.
tance, and load.
During startup, PWM switching frequency is reduced to 25% of
Dropout fSW while FB is below 200 mV. If FB voltage is above 200 mV
The APM81911 is designed to operate at extremely wide duty but below 400 mV, the switching frequency is 50% of fSW. At
cycles to minimize any reduction in output voltage during drop- the same time, the transconductance of the error amplifier, gm,
out conditions such as cold crank (where the input voltage drops is reduced to half of nominal value when FB is below 400 mV.
to a certain value). When FB is above 400 mV, the switching frequency will be
fSW and the error amplifier gain will be the nominal value. The
Power MOSFETs reduced switching frequency and error amplifier gain are neces-
The APM81911 includes a 115 mΩ (typ), high-side N-channel sary to help improve output regulation and stability when VOUT is
MOSFET and a 85 mΩ (typ), low-side N-channel MOSFET to very low. During low VOUT, the PWM control loop requires on-
provide synchronous rectification. When the APM81911 is dis- time near the minimum controllable on-time and very low duty
abled via the EN input being low or a fault condition, its output cycles that are not possible at the nominal switching frequency.
stage is tri-stated by turning off both the high-side and low-side When the voltage at the soft-start pin reaches approximately
MOSFETs. 1.2 V, the error amplifier will switch over and begin regulating

11
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

the voltage at the FB pin to the fixed internal bandgap reference down, the PGOOD is designed to operate in the correct state
voltage of 800 mV. The voltage at the soft-start pin will con- down to a very low input voltage.
tinue to rise to the internal LDO regulator output voltage. If the
APM81911 is disabled or a fault occurs, the internal fault latch Current Sense Amplifier
is set and the capacitor at the SS pin is discharged to ground very The APM81911 incorporates a high-bandwidth current sense
quickly through a 2 kΩ pull-down resistor. The device will clear amplifier to monitor the current through the top MOSFET. This
the internal fault latch when the voltage at the SS pin decays to current signal is used to regulate the peak current when the top
approximately 200 mV. However, if the device enters hiccup MOSFET is turned on. The current signal is also used by the pro-
mode, the capacitor at the SS pin is slowly discharged through tection circuitry for the cycle-by-cycle current limit and hiccup
a current sink, IHIC. Therefore, the soft-start capacitor CSS not mode short-circuit protection.
only controls the startup time but also the time between soft-start
attempts in hiccup mode. Pulse-Width Modulation (PWM)
Pre-Biased Startup The APM81911 employs fixed-frequency, peak current mode
control to provide excellent load and line regulation, fast transient
If the output of the buck regulator is pre-biased at a certain output
response, and simple compensation. A high-speed comparator and
voltage level, the APM81911 will modify the normal startup
control logic are included in the APM81911. The inverting input
routine to prevent discharging the output capacitors. As described
of the PWM comparator is connected to the output of the error
in the Soft-Start (Startup) and Inrush Current Control section,
amplifier. The non-inverting input is connected to the sum of the
the error amplifier usually becomes active when the voltage at
current sense signal, the slope compensation signal, and a DC
the soft-start pin exceeds 400 mV. If the output is pre-biased, the
PWM Ramp offset voltage (Ramp Offset).
voltage at the FB pin will be non-zero. The device will not start
switching until the voltage at SS pin rises to approximately VFB At the beginning of each PWM cycle, the CLK signal sets
+ 400 mV. From then on, the error amplifier becomes active, the the PWM flip flop, the bottom MOSFET is turned off, the top
voltage at the COMP pin rises, PWM switching starts, and VOUT MOSFET is turned on, and the inductor current increases. When
will ramp upward from the pre-bias level. the voltage at the non-inverting input of the PWM comparator
rises above the error amplifier output COMP, the PWM flip flop
PGOOD Output is reset, the top MOSFET is turned off, the bottom MOSFET is
The APM81911 provides a Power Good (PGOOD) status signal turned on, and the inductor current decreases. Since the PWM
to indicate if the output voltage is within the regulation limits. flip flop is reset, the dominant error amplifier may override the
Since the PGOOD output is an open-drain output, an external CLK signal in certain situations.
pull-up resistor must be used as shown in the applications sche-
matic. PGOOD transitions high when the output voltage, sensed Frequency Dither
at the FB pin, is within regulation. In addition to EMI-aware PCB layout, extensive filtering,
During startup, the PGOOD signal exhibits an additional delay of controlled switch node transitions, and shielding, switching
tdPG(SU) after FB pin voltage reaches the regulation voltage. This frequency dithering is an effective way to mitigate EMI concerns
delay helps to filter out any glitches on the FB pin voltage. in switching power supplies. Frequency dither helps to mini-
mize peak emissions by spreading the emissions across a wide
The PGOOD output is pulled low if either an undervoltage or range of frequencies. The APM81911 provides frequency dither
overvoltage condition occurs or the APM81911 junction tempera- by spreading the switching frequency ±5% using a triangular
ture exceeds thermal shutdown threshold (TSD). The PGOOD modulated wave of 0.5% switching frequency (see Table 1: PWM
overvoltage and undervoltage comparators incorporate a small Frequency, CLKOUT, and Dithering Settings)
amount of hysteresis (VFB(OV,HYS)), VFB(UV,HYS)) to prevent
chattering and deglitch filtering (tdPG(UV), tdPG(OV)) to eliminate The APM81911 can add dither to the external clock applied on
false triggering. For other faults, PGOOD depends on the output the SYNC pin. This unique feature allows the minimizing of
voltage. electromagnetic emissions even when the device is using external
clock.
It is important that the correct status of PGOOD is reported
during either the input supply ramp up or ramp down. During a With a factory trim option, there is the possibility to disable the
supply ramp up, the PGOOD is designed to operate in the correct frequency dither scheme. This option could be used in master-
state from a very low input voltage. Also, during supply ramp follower configuration to avoid double-dithering.

12
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

Table 1: PWM Frequency, CLKOUT, and Dithering Settings

PWM Frequency and Dithering CLKOUT Frequency and Dithering
Dither Dither Dither Dither
SW
Device SYNCIN Frequency Modulation Frequency Frequency Modulation
Frequency
Range Frequency Range Frequency
Low fOSC Disabled/Off None None
±0.05 × fOSC ±0.005 × fOSC
APM81911KNBJSR High fOSC fOSC + 180° ±0.05 × fOSC ±0.005 × fOSC
fSYNC fSYNC ±0.05 × fOSC ±0.005 × fOSC fSYNC + 180° ±0.05 × fOSC ±0.005 × fOSC
Low fOSC Disabled/Off
APM81911KNBJSR-1 High fOSC Dither Disabled fOSC + 180° Dither Disabled
fSYNC fSYNC fSYNC + 180°
Low fOSC
APM81911KNBJSR
with CLKOUT pulled to High fOSC Dither Disabled None None None
VCC
fSYNC fSYNC

fSYNC ± fDITHER + 180°

VO2
SW2
APM81911
fSYNC ± fDITHER Follower
With Dither
Disabled
(APM81911KNBJSR-1
VO1 Option)
SW1
SYNCIN

APM81911
Master fSYNC ± fDITHER + 180°
fSYNC ± fDITHER + 180°
VO3
fSYNC SW3
SYNCIN CLKOUT APM81911
Follower
With Dither
Disabled
(APM81911KNBJSR-1
Option)

SYNCIN

Figure 5: Master-Follower Configuration with APM81911KNBJSR-1 Option

Follower devices can be APM81911-1, or APM81911 with CLKOUT tied to VCC

13
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

PROTECTION FEATURES

The APM81911 was designed to satisfy the most demanding also enables a small current sink connected to the SS pin (IHIC). This
automotive and non-automotive applications. In this section, a causes the voltage at the soft-start pin to slowly ramp downward.
description of each protection feature is described and Table 2 When the voltage at the soft-start pin decays to a low enough level
summarizes the protections and their operation. (VSS(RST), 200 mV), the hiccup latch is cleared, and the current sink
is turned off. At this instant, the SS pin will begin to source current
Undervoltage Lockout (UVLO) (ISS) and the voltage at the SS pin will ramp upward.
An undervoltage lockout (UVLO) comparator in the APM81911 This marks the beginning of a new, normal soft-start cycle as
monitors the voltage at the VIN pin and keeps the regulator described earlier. When the voltage at the soft-start pin exceeds
disabled if the voltage is below the start threshold (VUVLO(ON), the error amp voltage by approximately 400 mV, the error
VIN rising) or the stop threshold (VUVLO(OFF), VIN falling). The amplifier will force the voltage at the COMP pin to quickly slew
UVLO comparator incorporates some hysteresis (VUVLO(HYS)) upward and PWM switching will resume.
to help prevent on-off cycling of the regulator due to resistive or
inductive drops in the VIN path during heavy loading or during If the short circuit/overload at the regulator output persists, another
startup. hiccup cycle will occur. Hiccups will repeat until the short cir-
cuit/overload is removed or the converter is disabled. If the short
Pulse-by-Pulse Peak Current Protection (PCP) circuit/overload is removed, the device will soft-start normally and
The APM81911 monitors the current in the high-side MOSFET, the output voltage will automatically recover to the desired level.
and if the peak MOSFET current exceeds the pulse-by-pulse Thus, hiccup mode is a very effective protection for the short-cir-
overcurrent limit ILIM(HS), the upper MOSFET is turned off and cuit/overload condition. It avoids false trigger during short duration
the bottom MOSFET is turned on until the start of the next clock short-circuit/overload. On the other hand, for the extended short-
pulse from the oscillator. The device includes leading edge blank- circuit/overload duration, the reduced average power dissipation
ing to prevent false triggering of pulse-by-pulse current protec- with hiccup mode of operation helps in lowering the temperature
tion when the upper MOSFET is turned on. rise of the device and enhancing the system reliability.

Overcurrent Protection (OCP) and Hiccup Mode Note that OCP is the only fault that results in hiccup mode being
ignored while VSS < 2.3 V.
An OCP counter and hiccup mode circuit protect the buck regula-
tor when the output of the regulator is shorted to ground or when Bias Overvoltage Monitoring
the load is too high. When the soft-start ramp is active (t < tSS), The APM81911 includes an always-on overvoltage protection
the OCP hiccup counter is disabled. The following two conditions circuit on the BIAS pin that monitors for an output overvoltage
must be met for the OCP counter to be enabled and begin counting: condition. This circuit allows for overvoltage protection even
• SS pin voltage, VSS > VHIC/LP(EN) (2.3 V), and when the connection to FB is lost or shorted to ground. The BIAS
overvoltage threshold adjusts with the voltage at FB, decreasing
• COMP pin voltage, VCOMP clamped at its maximum voltage. the overvoltage threshold in events such as when FB is shorted to
As long as these two conditions are met, the OCP counter remains ground. During an overvoltage event the controller tries to reduce
enabled and will count pulses from the overcurrent comparator. If the output overvoltage by terminating the high-side MOSFET
the COMP voltage decreases (OCP = 0), the OCP counter is cleared. switching and pulsing the low side MOSFET with minimum off-
Otherwise, if the OCP counter reaches 120 clock counts, PWM time (tOFF(min)) until FB returns to regulation. The APM81911 waits
switching ceases, a hiccup latch is set, and the COMP pin is quickly for tdPG(OV) (240 clock cycles) before pulling the PGOOD low. The
pulled down by a relatively low resistance (1 kΩ). The hiccup latch device returns to regulation when the fault condition is removed.

14
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

side MOSFET, the device enables the hiccup latch and attempts
to restart after hiccup latch is cleared. If the short to ground is
25
removed, the regulator will automatically recover; otherwise, the
device continues hiccupping. Unlike other hiccup mode protec-
tions, the SW pin protection is not delayed until soft-start is
20
completed, i.e., VSS > 2.3 V.
BIAS OV Treshold (V)

Pin-to-Ground and Pin-to-Pin Short Protections

15
The APM81911 is designed to satisfy the most demanding
automotive applications. For example, the device has been care-
10
fully designed to withstand a short circuit to ground at each pin
7 without causing any damage to the IC.
5
In addition, care was taken when defining the device pinouts to
optimize protection against pin-to-pin adjacent short circuits. For
0 example, logic pins and high-voltage pins are separated as much
0 100 200 300 400 500 600 700 800
FB Voltage (V)
as possible. Inevitably, some low-voltage pins are located adja-
cent to high voltage pins, but in these instances, the low-voltage
Figure 6: BIAS Overvoltage Threshold vs. FB Pin Volt- pins are designed to withstand increased voltages, with clamps
age and/or series input resistance, to prevent damage to the device.
SW Pin Protection Thermal Shutdown (TSD)
Unlike most regulators, the APM81911 protects itself when the The APM81911 monitors internal junction temperature and shuts
SW pin is shorted to ground. If the SW pin is shorted to ground, down the IC by disabling the switching pulses of high- and low-
there will be a very high current in the high-side MOSFET when side MOSFETs if the junction temperature exceeds the Thermal
it is turned on. The APM81911 incorporates an internal secondary Shutdown Threshold TSD. Also, to prepare for a restart, the inter-
current protection to detect this unusually high current and turns nal soft-start voltage (VSS) and the voltage at the COMP pin are
off the high-side MOSFET if the high current persists for more pulled low until VSS < VSS(RST). TSD is a non-latched fault, so the
than two consecutive switching cycles. After turning off the high- device automatically recovers.

Table 2: Summary of APM81911 Fault Modes and Operation

High Side Low-Side
Fault Mode Hiccup PGOOD Reset Condition
MOSFET MOSFET
VIN Undervoltage NO Off Off Low VIN above UVLO
Turned On if BOOT Short / Overcurrent
Output Short / Overcurrent YES after 120 pulses Off Low
Voltage is too low removed
SW short to GND (HS OCP) YES after 2 pulses Off Off Low Short removed
Output Overvoltage NO Off Pulsed with Minimum tOFF Low VOUT within operative range
Output Undervoltage NO Switching with Minimum tOFF Low VOUT within operative range
FSET shorted to GND NO Off Off Low FSET short removed
Thermal Shutdown NO Off Off Low Part cools down

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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

APPLICATION INFORMATION

PWM Switching Frequency (RFSET) If an external clock fSYNC is used for synchronization, the base
switching frequency should be chosen such that pulse skipping
The PWM switching frequency is set by connecting a resistor
will not occur at the maximum synchronized switching frequency
from the FSET pin to signal ground. Figure 7 shows the relation-
(i.e., 1.5 × fSYNC should be less than the frequency fSW in Equa-
ship between the typical switching frequency (y-axis) and the
tion 2).
FSET resistor (x-axis). For a required switching frequency (fSW),
the FSET resistor value can be calculated as follows:
40
Equation 1:
37037 35
RFSET = – 2.96
fSW 30

where fSW is in kHz and RFSET is in kΩ.

Input Voltage (V)

25

3000 20

15 Typical PWM Operating Area

(kHz)

2500
10
SW

2000 VOUT = 3.3 V

5
Switching Frequency, f

VOUT = 5 V

1500
0
1000 1500 2000 2500
Switching Frequency (kHz)
1000

Figure 8: Input Voltage Limit To Prevent Pulse Skipping

500
Output Voltage Setting
0 The output voltage of the APM81911 is determined by connect-
10 14 18 22 26 30 34 ing a resistive feedback divider (RFB1, RFB2) from the output
FSET Resistor, R FSE T
(k ) node (VOUT) to the FB pin as shown in Figure 7. The feedback
resistors must satisfy the ratio shown in Equation 3 to produce
Figure 7: PWM Switching Frequency vs. RFSET the desired output voltage (VOUT).
Power Switch Minimum On-Time Equation 3:
While choosing the PWM switching frequency, the designer RFB1 V
= OUT – 1.0
should be aware of the minimum controllable on-time, tON(MIN), RFB2 0.8
of the APM81911. If the required on-time of the system is less 1% resistors are recommended to maintain the output voltage
than the minimum controllable on-time, pulse skipping will occur accuracy. There are tradeoffs while choosing the value of the
and the output voltage will have increased ripple. The PWM feedback resistors. If the series combination (RFB1 + RFB2) is too
switching frequency should be calculated using Equation 2, low, the light load efficiency of the regulator will be reduced.
where VOUT is the output voltage, tON(MIN) is the minimum So, to maximize the efficiency, it is best to choose large values
controllable on-time of the device (see Electrical Characteristics for feedback resistors. On the other hand, large values of feed-
table), and VIN(MAX) is the maximum required operational input back resistors increase the parallel combination (RFB1||RFB2) and
voltage (not the peak surge voltage). makes the regulator more susceptible to noise coupling onto the
Equation 2: FB pin.
VOUT The FB pin leakage current also has an impact on the output volt-
fSW <
tON(MIN) × VIN(MAX) age accuracy of the regulator. A small amount of leakage current,

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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

IFB, flowing into the FB pin increases the output voltage beyond the ESR or the total impedance is clearly documented in the
the set regulation voltage. The output voltage of the regulator capacitor datasheet. Also, ESR of electrolytic capacitors usually
accounting for the FB pin leakage current is given by: increases significantly at cold ambient temperatures, as much as
Equation 4: 10 times, which increases the output voltage ripple and, in most
cases, reduces the stability of the system.
RFB1
VOUT = VFB × ⎛ 1 + ⎞ + IFB × RFB1 The transient response of the regulator depends on the quantity
RFB2
⎝ ⎠ and type of output capacitors. In general, minimizing the ESR of
Output Capacitors (CO) the output capacitance will result in a better transient response.
The ESR can be minimized by simply adding more capacitors in
The output capacitor of switching regulators filter the output parallel or by using higher quality capacitors. At the instant of a
voltage to provide an acceptable level of ripple on the output fast load transient (high diO/dt), the change in the output voltage,
voltage, and they also store energy to help maintain voltage regu- using electrolytic output capacitors, is:
lation during a load transient. The voltage rating of the output
capacitors must support the output voltage with sufficient design Equation 8:
diO
margin. ∆VOUT = ∆ILO × ESRCO + × ESLCO
dt
The output voltage ripple (ΔVOUT) is a function of the output When ceramic capacitors are used in the output, the output
capacitor parameters: CO, ESRCO, and ESLCO: voltage deviation during load transients depends on the bulk
Equation 5: output capacitance along with various other factors. To calculate
VIN – VOUT ∆ILO the bulk ceramic capacitance required, the entire load transient
∆VOUT = ∆ILO × ESRCO + × ESLCO + duration can be divided into two stages: large signal and small
LO 8 × fSW × CO
signal. During large signal load transients, immediately after the
The type of output capacitors determines which terms of Equa- transient event, the output voltage deviates from the nominal
tion 5 are dominant. For ceramic output capacitors, ESRCO and value due to large mismatch in the load current requirement and
ESLCO are virtually zero, so the output voltage ripple will be the inductor current. The output voltage deviation during this
dominated by the third term of Equation 5. The value of CO can interval is maximum and depends on output inductor, bulk output
be calculated as: capacitance, and closed-loop crossover frequency. For designs
Equation 6: with higher crossover frequency, the controller typically saturates
∆ILO the duty cycle, i.e., either minimum or maximum. For a chosen
CO ≥ output inductor and crossover frequency values, the output volt-
8 × fSW × ∆VOUT age deviation can be minimized by increasing the output bulk
Voltage ripple of a regulator using ceramic output capacitors capacitance. In the case of a buck converter, operating with a low
can be reduced by increasing the total capacitance, reducing the duty cycle, the step-down load transient is more severe and hence
inductor current ripple, or increasing the switching frequency. For the output capacitance should be determined for this scenario.
electrolytic output capacitors, the value of capacitance will be The bulk ceramic output capacitance required is given by:
relatively high, so the third term in Equation 5 will be very small Equation 9:
and the output voltage ripple will be determined primarily by the ∆IO2 × LO
first two terms: CO(bulk) =
2 × VOUT × ∆VOUT(spec)
Equation 7:
VIN – VOUT where ΔIO is the magnitude of the change in the load current,
∆VOUT = ∆ILO × ESRCO + × ESLCO ΔVOUT(spec) is the maximum allowed output voltage deviation
LO during load transient event. Gradually, as the mismatch between
Voltage ripple of a regulator using electrolytic output capacitors the load current and the inductor current becomes small, the
can be reduced by decreasing the equivalent ESRCO and ESLCO output voltage deviation also reduces, resembling a small signal
by using a high-quality capacitor, adding more capacitors in par- transient event. Eventually, during small signal transient interval,
allel, or reducing the inductor current ripple. the error amplifier brings the output voltage back to its nominal
As the ESR of some electrolytic capacitors can be quite high, value. The speed with which the error amplifier brings the output
Allegro recommends choosing a quality capacitor for which voltage back into regulation depends mainly on the loop cross-

17
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

over frequency. A higher crossover frequency usually results in a

shorter time to return to the nominal set voltage.
Output Voltage Ripple – Ultra-Low IQ LP Mode
After choosing output capacitor(s), it is important to calculate the
output voltage ripple (VPP(LP)) during ultra-low IQ LP mode. With
ceramic output capacitors, the output voltage ripple in PWM mode
is usually negligible, but this is not the case during LP mode.
In LP mode, the peak inductor current during on-time of the high-
side switch is limited to IPEAK(LP). Also, in LP mode, the low-side
switch is constantly turned off thereby forcing the regulator to oper-
ate in Discontinuous Conduction Mode (DCM) in order to reduce
switching losses. A LP comparator monitors the output voltage on
the internal feedback node and allows the regulator to switch until
the internal feedback voltage is 0.5% greater than its nominal value
(0.8 V). When internal feedback voltage is greater than 0.804 V, the
APM81911 coasts by terminating the switching pulses. Figure 9: Output Voltage Ripple in LP Mode
During coasting, device shuts down most of its internal control During on-time interval, the length of the time for the inductor
circuitry to ensure very low quiescent current is drawn from the current to rise from 0 A to IOUT is:
input. The number of switching pulses, in LP mode, required
Equation 13:
to coast the device depends on various factors including input
voltage, output voltage, load current, output inductor and output IOUT × LO
t1 =
capacitor. If APM81911 starts coasting after a single switching VIN – VOUT – IPEAK × (RDS(ON)HS + LO(DCR))
L
pulse, then the output voltage ripple would be dictated by this During off-time interval, the length of the time for the inductor
single pulse. The peak inductor current (IPEAK ) is given by: current to fall from IOUT to 0 A is:
L
Equation 10: Equation 14:
IPEAK(LP)
IPEAK = IOUT × LO
L S × LO
1+ E t2 =
VIN – VOUT VOUT
where IPEAK(LP) is the peak inductor current, specified in the Given the peak inductor current (IPEAK ) and the rise and fall
L
Electrical Characteristics table, at which device enters LP mode. times (tON and tOFF) for the inductor current, the output voltage
Referring to Figure 49, on-time and off-time calculations are ripple for a single switching pulse can be calculated as follows:
given as: Equation 15:
Equation 11: IPEAK – IOUT
L
IPEAK × LO VPP(LP) = × (tON + tOFF – t1 – t2)
L 2 × COUT
tON =
VIN – VOUT – IPEAK × (RDS(ON)HS + LO(DCR)) Input Capacitors
L
Equation 12: Three factors should be considered when choosing the input
IPEAK × LO capacitors. First, the capacitors must be chosen to support the
L
tOFF = maximum expected input surge voltage with adequate design
VOUT
margin. Second, the capacitor RMS current rating must be higher
where RDS(ON)HS is the on-resistance of internal high-side MOS- than the expected RMS input current to the regulator. Third, the
FET and LO(DCR) is the DC resistance of the output inductor, LO. capacitors must have enough capacitance and a low enough ESR
to limit the input voltage dV/dt to much less than the hysteresis
of the UVLO circuitry (250 mV nominal) at maximum loading

18
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

and minimum input voltage. The input capacitors must deliver an A good design should consider the DC bias effect on a ceramic
RMS current (IRMS) given by: capacitor: as the applied voltage approaches the rated value, the
Equation 16: capacitance value decreases. This effect is very pronounced with
the Y5V and Z5U temperature characteristic devices (as much
IRMS = IOUT × √ D × (1 – D) as 90% reduction), so these types should be avoided. The X5R,
where D is the duty cycle X7R, and X8R type capacitors should be the primary choices due
to their stability versus both DC bias and temperature.
Equation 17:
VOUT The APM81911 integrates a 47 nF X8R input capacitor. In addi-
D≈ tion to the recommended ceramic input capacitance and 47 nF
VIN integrated ceramic capacitor, an aluminum electrolytic capacitor
Figure 1010 shows the normalized input capacitor RMS current of at least 47 µF is recommended at the input to help dampen
versus duty cycle. To use this graph, simply find the operational transient events. The electrolytic capacitor is used to meet load-
duty cycle (D) on the x-axis and determine the input/output cur- transient response requirements and to avoid input voltage oscil-
rent multiplier on the y-axis. For example, at a 20% duty cycle, lation due to the negative input impedance of the DC-DC regula-
the input/output current multiplier is 0.40. Therefore, if the tor. While the integrated ceramic capacitor is used to bypass high
regulator is delivering 1.0 A of steady-state load current, the input di/dt input ripple current.
capacitor(s) must support 0.40 × 1.0 A or 0.4 A RMS.
Soft-Start and Hiccup Mode Timing (CSS)
The input capacitor(s) must limit the voltage deviations at the
The soft-start time of the APM81911 is determined by the
VIN pin to significantly less than the device UVLO hysteresis
value of the capacitance (CSS) at the soft-start pin. When the
during maximum load and minimum input voltage condition.
APM81911 is enabled, the SS pin sources the charging current
The following equation allows to calculate the minimum input
ISS, and the voltage across the soft-start capacitor CSS starts
capacitance required:
ramping upward from 0 V. PWM switching will begin after the
Equation 18: voltage across CSS exceeds 400 mV. The soft-start delay (tdSS)
IOUT × D × (1 – D) can be calculated using the following equation:
CIN ≥
0.85 × fSW × ∆VIN(MIN) Equation 19:
where ΔVIN(MIN) is chosen to be much less than the hysteresis CSS
tdSS = 0.4 × ⎛ ⎞
of the VIN UVLO comparator (ΔVIN(MIN) ≤ 150 mV is recom- ⎝
ISS ⎠
mended), and fSW is the nominal PWM frequency. The D × (1–D)
term in Equation 18 has an absolute maximum value of 0.25 at If the device is starting with a very heavy load, a very fast soft-
50% duty cycle. start time may cause the regulator to exceed the pulse-by-pulse
overcurrent threshold. This occurs because the sum of the full
load current, the inductor ripple current, and the additional cur-
rent required to charge the output capacitors,
Equation 20:
VOUT
ICO = CO × ,
tSS
is higher than the pulse-by-pulse current threshold. This phenom-
enon is more pronounced when using high value electrolytic-type
output capacitors. To avoid prematurely triggering hiccup mode,
the soft-start capacitor (CSS) should be calculated according to
equation below:
Equation 21:
ISS × VOUT × CO
CSS ≥
0.8× ICO
Figure 10: Normalized Input Capacitor Ripple
where VOUT is the output voltage, CO is the output capacitance,
versus Duty Cycle

19
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

ICO is the amount of current allowed to charge the output capaci-

tance during soft-start (0.1 A < ICO < 0.3 A is recommended). The 3 T AMBIENT
soft-start time (tSS) can be calculated as below: 25 C
85 C
Equation 22: 2.5 105 C
CSS 125 C
tSS = 0.8 × ⎛ ⎞

⎝
ISS ⎠ 2

Max Load (A)

Higher values of ICO result in faster soft-start times. However,
1.5
lower values of ICO ensure that hiccup mode is not falsely trig-
gered. Allegro recommends starting the design with an ICO of
1
0.1 A and increasing it only if the soft-start time is too slow. If a
non-standard capacitor value for CSS is calculated, the next larger
value should be used. 0.5

When the device is in hiccup mode, the soft-start capacitor is

0
used as a timing capacitor and sets the hiccup period. The soft- 10 12 14 16 18 20 22 24 26 28 30 32 34 36
start pin charges the soft-start capacitor with ISS during a startup VIN (V)

attempt and discharges the same capacitor with IHIC between

startup attempts. Because the ratio of ISS:IHIC is approximately Figure 12: APM81911 Maximum Output Current Derating
4:1, the time between hiccups will be about four times as long as with VOUT = 5 V, fSW = 2.15 MHz
the startup time. Therefore, the effective duty cycle will be very Compensation Components (RZ, CZ, CP, and CFF)
low, and the junction temperature will be kept low.
The objective of the selection of the compensation components is
Output Current Derating to ensure adequate stability margins to avoid instability issues, to
The APM81911 output maximum current derates with increased maintain a high loop gain at DC to achieve excellent output volt-
ambient temperature. The figures below show the maximum age regulation, and to obtain a high loop bandwidth for superior
output current over temperature using the APEK81911KNB-01-T transient response. To a first order, the closed-loop model of a
evaluation board, with a large copper area for VOUT, 2 oz copper peak current mode-controlled regulator can be broken into two
on the outer layers, and 1oz copper on the inner layers. Refer to blocks as shown in Figure 133.
the evaluation board user manual for more information about the
evaluation board layout and performance.

3 T
AMBIENT

25 C
85 C
2.5 105 C
125 C

2
Max Load (A)

1.5

0.5

0
10 12 14 16 18 20 22 24 26 28 30 32 34 36
VIN (V)

Figure 11: APM81911 Maximum Output Current Derating Figure 13: Power Stage and Error Amplifier
with VOUT = 3.3 V, fSW = 2.15 MHz

20
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

The power stage includes the output filter capacitor(s), CO, the A feedforward capacitor (CFF) can be connected in parallel with
equivalent load, RL and the inner current loop which consists of RFB1 to increase phase margin and loop crossover frequency for
the PWM modulator and the integrated output inductor, LO. The improving transient response of the regulator. The addition of
inner current loop, with a first-order approximation, can be effec- CFF results in an additional zero and pole in the compensation
tively modelled as a trans-conductance amplifier which converts network and boosts the loop phase at the crossover frequency. In
the control voltage (VC) from the error amplifier to a peak output general, CFF should be less than 25 pF. While large value of CFF
inductor current with an equivalent gain gmPOWER. Although, the increases the loop crossover frequency and reduces the phase
peak current through the inductor is being controlled, neglect- margin, very small value of CFF will not have any effect. Optimal
ing the inductor ripple current, it is acceptable to replace it with value of CFF can be calculated from the following equation.
output current IOUT. Equation 26:
From a small-signal point of view, the current mode control loop 1
behaves like a current source and therefore the power inductor CFF =
2 × π × RFB1 × fC
can be ignored. The output capacitor integrates the ripple current
through the inductor, effectively forming a single pole with the
output load. A control-to-output transfer function between the
control voltage (VC), output of the error amplifier in the feed-
back loop, and the regulator output voltage (VOUT) describes the
dynamics of the power stage. The DC gain of the power stage,
i.e., control-to-output transfer function, is given by
Equation 23:
GDC(CO) = gmPOWER × RL Figure 14: Feedback Divider with Feedforward Capacitor
where gmPOWER is the equivalent gain of the inner current loop Error Amplifier
(specified in the Electrical Characteristics table) and RL is the
load resistance. The error amplifier, as a part of the output voltage feedback loop,
comprises a transconductance amplifier with an external Type-II
The control-to-output transfer function has a pole fP(CO), formed compensation formed by RZ-CZ-CP network. A Type-II compen-
by the output capacitance (CO) and load resistance (RL), located sated error amplifier introduces two poles and a zero. The place-
at: ment of these poles and zero should be such that the closed-loop
Equation 24: system has sufficient stability margins and high bandwidth (loop
1 crossover frequency) and provides optimal transient response.
fP(CO) =
2 × π × RL × CO The DC gain of the feedback loop, including the error amplifier
The control-to-output transfer function has a zero fZ(CO), formed and the feedback resistor divider is given by:
by the output capacitance (CO) and its associated ESR, located at: Equation 27:
Equation 25: RFB2 VFB
GDC(FB) = AVOL × = AVOL ×
1 RFB1 + RFB2 VOUT
fZ(CO) =
2 × π × ESR × CO where AVOL is the open-loop DC gain of the error amplifier
For a design with very low-ESR type output capacitors (such as (specified in the Electrical Characteristics table).
ceramic or OSCON output capacitors), the ESR zero, fZ(CO), is The DC gain of the error amplifier is 65 dB (equivalent to 1778)
usually at a very high frequency so it can be ignored. On the other and with a gm value of 750 μA/V, the effective output impedance,
hand, with high-ESR electrolytic output capacitors, the ESR zero RO, of the amplifier is:
falls below or near the 0 dB crossover frequency of the closed loop,
hence it should be cancelled by the pole formed by the CP capacitor Equation 28:
and the RZ resistor discussed and identified later as fP2(EA). 1778
RO = = 2.37 MΩ
750 × 10–6

21
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

Typically, RO ≫ RZ and CZ ≫ CP, which simplifies the derivation the range fSW/20 < fC < fSW/10. A higher value of fC generally
of the transfer function of the Type-II compensated error ampli- provides a better transient response, while a lower value of fC
fier. The transfer function has a (very) low frequency pole fP1(EA) generally makes it easier to obtain higher gain and phase margins.
dominated by the error amplifier output impedance RO and the 2. Calculate the RZ resistor value. This sets the system band-
compensation capacitor CZ: width (fC):
Equation 29: Equation 32:
1 VOUT 2 × π × CO
fP1(EA) = RZ = fC × ×
2 × π × RO × CZ
VFB gmPOWER ×gm
The transfer function of the Type-II compensated error amplifier
3. Calculate the range of values for the CZ capacitor. Use the
also has a zero at frequency fZ(EA) caused by the resistor RZ and
following:
the capacitor CZ:
Equation 33:
Equation 30:
4 14
1 < CZ <
fZ(EA) = 2 × π × RZ × fC 2 × π × RZ × 1.5 × fP(CO)
2 × π × RZ × CZ
Lastly, the transfer function of the Type-II compensated error To maximize system stability, i.e., high gain and phase margins,
amplifier has a (very) high frequency pole fP2(EA) dominated by use a higher value of CZ. To optimize transient recovery time,
the resistor RZ resistor and the capacitor CP: although at the expense of low stability margins, use a lower
value of CZ.
Equation 31:
4. Calculate the frequency of the ESR zero fZ(CO) formed by
1
fP2(EA) = the output capacitor(s) by using Equation 25 (repeated here):
2 × π × RZ × CP
1
Although there are many different approaches for designing the fZ(CO) =
2 × π × ESR × CO
feedback loop, a good design approach attempts to maximize the
closed-loop system stability, while providing a high bandwidth If fZ(CO) is at least one decade higher than the target crossover
and optimized transient response. A generalized tuning procedure frequency fC, then fZ(CO) can be ignored. This is usually the case
is presented below to systematically determine the values of com- for a design using ceramic output capacitors. Use Equation 31
pensation components (RZ, CZ, and CP) in the feedback loop. to calculate the value of CP by setting fP2(EA) to either 5 × fC or
fSW/2, whichever is higher.
A Generalized Tuning Procedure Alternatively, if fZ(CO) is near or below the target crossover
frequency fC, then use Equation 31 to calculate the value of CP by
1. Choose the system bandwidth (fC). This is the frequency at setting fP2(EA) equal to fZ(CO). This is usually the case for a design
which the magnitude of the gain crosses 0 dB. Recommended using high ESR electrolytic output capacitors.
values for fC, based on the PWM switching frequency, are in

22
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

APPLICATION SCHEMATIC AND RECOMMENDED EXTERNAL COMPONENTS

PWM/AUTO BIAS
APM81911 BOOT
EN PGOOD
47nF PGOOD
SYNCIN 3.0A Buck Switcher
VOUT VOUT
VIN
1.5µH RFB1
CIN 47nF FB CO
RFB2
GND PWM
Controller SW
PGND CFF

VCC

SS
CLKOUT
FSET
COMP
CZ CP

RZ

Figure 15: Applications Schematic showing component locations

Table 3: Recommended External Components Value

COMP Components FB Components
VOUT fOSC CIN(MIN) [1] CO [1]
RZ CZ CP CFF RFB1 RFB2
5.0 V 2.15 MHz 7 µF 24 µF 13.3 kΩ 1 nF Not Mounted 10 pF 732 kΩ 137 kΩ
3.3 V 2.15 MHz 7 µF 24 µF 13.3 kΩ 1 nF Not Mounted 10 pF 301 kΩ 95.3 kΩ

[1] Input
and output minimum capacitance values reflect total effective capacitance requirement over temperature and DC bias. Use high quality
ceramic capacitors with an appropriate voltage and temperature rating to ensure sufficient total effective capacitance.

Note: These values are provided for reference. It is the responsibility of the customer to verify proper performance across all operating corners in the
final application.

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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

POWER DISSIPATION AND THERMAL CALCULATIONS

The total power dissipated in the APM81911 is the sum of the where IOUT is the regulator output current, ΔILO is the peak-to-
power dissipated from the VIN supply current (PIN), the power peak inductor ripple current, RDS(ON)H is the on-resistance of the
dissipated due to the switching of the high-side power MOS- high-side MOSFET, RDS(ON)L is the on-resistance of the low-side
FET (PSWH), the power dissipated due to the conduction of rms MOSFET.
current in the high-side MOSFET (PCH) and low-side MOSFET
(PCL), power dissipated due to the low-side MOSFET body diode The power dissipated in the low-side MOSFET body diode dur-
conduction during the non-overlap time (PNO) and the power dis- ing the non-overlap time can be calculated as follows:
sipated by both high-side and low-side gate drivers (PDRIVER). Equation 38:
The power dissipated from the VIN supply current (with BIAS pin PNO = VSD × IOUT × 2 × tNO × fSW
open) can be calculated using Equation 34:
where VSD is the source-to-drain voltage of the low-side MOS-
Equation 34: FET (typically 0.60 V), and tNO is the non-overlap time.
PIN = VIN × IIN(PWM) + (VIN – VGS) × fSW The power dissipated in the internal gate drivers can be calculated
where VIN is the input voltage, IIN(PWM) is the input quiescent using Equation 39:
current drawn by the APM81911 in PWM mode (see Electrical
Equation 39:
Characteristics table), VGS is the MOSFET gate drive voltage,
and fSW is the PWM switching frequency. PDRIVER = VGS × fSW
The power dissipated by the high-side MOSFET during PWM where VGS is the gate drive voltage.
switching can be calculated using Equation 35: Finally, the total power dissipated in the APM81911 is given by:
Equation 35:
Equation 40:
PSWH = (VIN × IOUT × (tr + tf) × fSW) / 2
PTOTAL = PIN + PSW + PCH + PCL + PNO + PDRIVER
where VIN is the input voltage, IOUT is the regulator output cur-
rent, fSW is the PWM switching frequency, tr and tf are the rise The average junction temperature (TJ) can be calculated as follows.
and fall times measured at the switch node. Equation 41:
The exact rise and fall times at the SW node will depend on the TJ = PTOTAL × RθJA + TA
external components and PCB layout, so each design should be
where PTOTAL is the total power dissipated from Equation 40,
measured at full load.
RθJA is the junction-to-ambient thermal resistance (42°C/W on a
The power dissipated in the high-side MOSFET while it is con- 4-layer PCB), and TA is the ambient temperature.
ducting can be calculated using Equation 36:
RθJA includes the thermal impedance from junction to case, RθJC
Equation 36:
and the thermal impedance from case to ambient, RθCA. RθCA is
PCH = IRMS(H)2 × RDS(ON)H =
generally determined by the amount of copper that is used under-
VOUT ⎞ ∆ILO2 ⎞ neath and around the device on the printed circuit board.
⎛ × ⎛IOUT2 × × RDS(ON)H
⎝ VIN ⎠ ⎝ 12 ⎠ The maximum allowed power dissipation depends on how effi-
Similarly, the conduction losses dissipated in the low-side MOS- ciently heat can be transferred from the junction to the ambient
FET while it is conducting can be calculated by the following air, i.e., minimizing the RθJA. As with any regulator, there are
equation: limits to the amount of heat that can be dissipated before risking
Equation 37: thermal shutdown. There are tradeoffs between ambient operat-
PCL = IRMS(L)2 × RDS(ON)L = ing temperature, input voltage, output voltage, output current,
switching frequency, PCB thermal resistance, airflow, and other
VOUT ⎞ ∆ILO2 ⎞ nearby heat sources. Even a small amount of airflow will reduce
1–
⎛ × ⎛IOUT2 × × RDS(ON)L
⎝ VIN ⎠ ⎝ 12 ⎠ the junction temperature considerably.

24
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

PCB LAYOUT GUIDELINES

The APM81911 is designed to minimize electromagnetic (EM) • Voltage divider must be placed as close as possible to GND
emissions when proper PCB layout techniques are adopted. A and FB pins in order to minimize the offset and gain error due
good PCB layout is also critical for the APM81911 to provide to the parasitic resistance of the PCB traces.
clean and stable output voltages. Design guidelines for EMI/ • If a RFSET resistor is used, place it as close as possible to the
EMC-aware PCB layout and minimum RθJA are presented below. FSET pin.
Figure 166 shows a typical application schematic of a synchro-
nous buck regulator IC with critical power paths/loops. • The output voltage sense trace should be routed as close as
possible to the load to obtain the best load regulation.
• Place the ceramic input capacitors as close as possible to the
VIN pin and PGND pins to make the loop area minimal, and • Allegro recommends a 4-layer PCB. Heavier copper layers,
the traces of the input capacitors to VIN pin should be short reduced material between layers and a good amount of thermal
and wide to minimize the inductance. This critical loop is vias are the keys to improved thermal performance. Use TOP
shown as trace 1 in Figure 166. The bulk/electrolytic input layer for routing high-current traces, layer 2 for a solid GND
capacitor can be located further away from VIN pin. The input plane, layer 3 for most other routing, BOT layer for solid GND
capacitors and APM81911 IC should be on the same side of plane or optionally other components without low-impedance
the board with traces on the same layer. traces constraints—the PGOOD pull-up resistor could be on
the BOT plane if desired.
• The loop from the input supply and capacitors, through the
high-side MOSFET, into the output capacitor via the VOUT • If a two-layer only (TOP and BOT) PCB is mandatory, place
pins, and back to ground should be minimized with relatively all the components on the TOP layer and limit the routing only
wide traces. to the top layer. Use BOT layer as GND plane.
When the high-side MOSFET is off, free-wheeling current • When connecting the input and output ceramic capacitors,
flows from ground, through the synchronous low-side use multiple vias to GND planes and place the vias as close
MOSFET. as possible to the pads of the components. Do not use thermal
• Place the output capacitors relatively close to the output pins, reliefs around the pads for the input and output ceramic
VOUT. Ideally, the output capacitors and the APM81911 capacitors.
should be on the same layer. Connect the output capacitors • To minimize thermal resistance (RθJA), extend ground planes
with a fairly wide trace. The output capacitors must use a on TOP layer as much as possible and use plenty of thermal
ground plane to make a very low-inductance connection to the vias to connect them to GND plane in BOT layer.
PCB GND. These critical connections are shown as trace 2 in
• To minimize PCB losses and improve system efficiency, the
Figure 166.
power traces should be as wide as possible.
• Compensation network must be as close as possible to GND
and COMP pins.

25
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

PWM/AUTO BIAS
APM81911 BOOT
EN PGOOD
47nF PGOOD
SYNCIN 3.0A Buck Switcher
VOUT VOUT
VIN
2
1.5µH RFB1
CIN 1 47nF FB
RFB2
2 CO
GND PWM
Controller SW
PGND CFF

VCC

SS
CLKOUT
FSET
COMP
CZ CP

RZ

Figure 16: PCB Layout Critical Paths

26
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

PACKAGE OUTLINE DRAWING AND RECOMMENDED PCB FOOTPRINT

PRELIMINARY
For Reference Only; Not for Tooling Use
(Reference DWG-0000753, Rev. 2, incl. Appendix APM81911)
Dimensions in millimeters
Exact case and lead configuration at supplier discretion within limits shown

TOP VIEW BOTTOM VIEW

INDEX AREA
2.00 × 3.00
4.00 BSC A (0.625)
B
32 27 28 30 31 32
2× (0.30) (0.625)
1 1
2 25 2
1.45 ±0.10 2.85 ±0.10
4× (0.45) 3
(0.475)
135°

6.00 BSC 3× (1.46) 22 5

21 1.84 ±0.10 6
1.25 ±0.10
20 7
19 8× (0.30)
1.33 ±0.10
0.10 C

0.75 ±0.10 18 135° 9

17 10
6× (0.35)
16 15 14 13 12 11
2×

(0.404)
2× 0.10 C 0.25
24× 0.25 ±0.05
0.10 M C A B
SIDE VIEW 0.05 M C
0.065 C
Standard Branding Reference View
2.095 ±0.065
C
SEATING
PLANE XXXXXX
0.00
24× 0.05 Date Code
Detail A
0.08 C Lot Number

DETAIL A

0.100 REF 0.295 TYP Line 1: Part Number

Terminal Line 2: Logo A, 4-Digit Date Code
Thickness
Line 3: Characters 5, 6, 7, 8 of Assembly Lot Number

Center aligned
Plated Pin 1 dot top left
0.050 REF
Area
0.400

Figure 17: 32-Lead 4 mm × 6 mm QFN (Suffix NB)

27
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

PCB Footprint – Copper PCB Footprint – Paste

4.80
4.80

0.30 0.70 1.05 0.95

0.90

1.20 1.95
2.85 1.45 2.90

45°
2.43 1.20

6.80 6.80
1.30
2.85
0.70
0.70
2.85 0.80
R0.05

0.10 2.60 0.45

0.75
0.15
0.40 0.90
0.85 × 16 0.85 × 26
0.50 TYP 0.50
R0.05 0.30 × 26
0.30 × 26

PCB Footprint – Soldermask

2.64

1.40

1.43 0.85

SOLDERMASK
OPENING

0.50 0.05 MAX

METAL

Figure 18: Recommended PCB Footprint

Altium and Cadence schematic and layout library files for the APM81911 are provided on the APM81911 product page on Allegromicro.com.

28
Allegro MicroSystems
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 40 V, 3 A, Synchronous Buck Regulator Module
APM81911 with Low EMI and 6 µA Quiescent Current

Revision History
Number Date Description
– February 23, 2023 Initial release
Updated Droput Switching Frequency footnote in Characterstics table (page 5); updated test
1 March 14, 2023
conditions of Bias Overvoltage Protection in Electrical Characteristics table (page 8)
2 May 18, 2023 Updated package image (page 1)

Copyright 2023, Allegro MicroSystems.

Allegro MicroSystems reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit
improvements in the performance, reliability, or manufacturability of its products. Before placing an order, the user is cautioned to verify that the
information being relied upon is current.
Allegro’s products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of
Allegro’s product can reasonably be expected to cause bodily harm.
The information included herein is believed to be accurate and reliable. However, Allegro MicroSystems assumes no responsibility for its use; nor
for any infringement of patents or other rights of third parties which may result from its use.
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