Study Material For AEC For BL 4, 5, 6
Study Material For AEC For BL 4, 5, 6
CO2 Design and analyze various rectifiers, amplifier circuits and oscillators.
CO3 Understand the functioning of OP-AMP and design OP-AMP based circuits.
Reference Books:
1. Microelectronic Circuit- Analysis & Design, Rashid, Cenage Learning.
2.Electronic Circuits: Discrete & Integrated, 3rd Edition, Schilling & Belove, Mc Graw Hill
Company.
3. Electronic principles, 6th Edition, Malvino, Mc Graw Hill Company.
4.Operational Amplifier & Linear IC’s, Bell, Oxford University Press.
5.2000 Solved Problems in Electronics, Jimmie J. Cathey, Mc Graw Hill Inc.
6.Electronic Devices -System & Application, Robert Diffenderfer, Cengage Learning.
7.Op- Amps & Linear Integrated Circuits, Ravi Raj Dudeja & Mohan Dudeja, Umesh
Publication
CO-PO Mapping:
CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 PO10 PO1 PO1
1 2
CO1: 3 3 1 1 1 3
1
CO2: 3 3 2 2 2 1 1 3
CO3: 3 3 3 3 3 2 1 1 1 3 3
CO4: 3 3 2 1 3
3, 2, 1: - Indicate strong (3), medium (2) and weak (1) correlation respectively.
Program Outcomes (PO)
1. Engineering knowledge: Apply the knowledge of mathematics, science, engineering
fundamentals, and an engineering specialization to the solution of complex engineering problems.
2. Problem analysis: Identify, formulate, research literature, and analyse complex engineering
problems reaching substantiated conclusions using first principles of mathematics, natural
sciences, and engineering sciences.
3. Design/development of solutions: Design solutions for complex engineering problems and
design system components or processes that meet the specified needs with appropriate
consideration for the public health and safety, and the cultural, societal, and environmental
considerations.
4. Conduct investigations of complex problems: Use research-based knowledge and research
methods including design of experiments, analysis and interpretation of data, and synthesis of the
information to provide valid conclusions.
5. Modern tool usage: Create, select, and apply appropriate techniques, resources, and modern
engineering and IT tools including prediction and modelling to complex engineering activities with
an understanding of the limitations.
6. The engineer and society: Apply reasoning informed by the contextual knowledge to assess
societal, health, safety, legal and cultural issues and the consequent responsibilities relevant to the
professional engineering practice.
7. Environment and sustainability: Understand the impact of the professional engineering
solutions in societal and environmental contexts, and demonstrate the knowledge of, and need for
sustainable development.
8. Ethics: Apply ethical principles and commit to professional ethics and responsibilities and
norms of the engineering practice.
9. Individual and teamwork: Function effectively as an individual, and as a member or leader in
diverse teams, and in multidisciplinary settings.
10. Communication: Communicate effectively on complex engineering activities with the
engineering community and with society at large, such as, being able to comprehend and write
effective reports and design documentation, make effective presentations, and give and receive
clear instructions.
11. Project management and finance: Demonstrate knowledge and understanding of the
engineering and management principles and apply these to one’s own work, as a member and
leader in a team, to manage projects and in multidisciplinary environments.
12. Life-long learning: Recognize the need for and have the preparation and ability to engage in
independent and life-long learning in the broadest context of technological change.
Lesson Plan
Schmitt Trigger.
23 4
Module 1
1. (Create), 10 Marks
To design a common-emitter (CE) amplifier with the given parameters, we can utilize the h-parameter
model. The h-parameters for the CE configuration are as follows:
hfe: Current gain of the transistor in the common-base configuration. hie: Input impedance of the transistor
in the common-base configuration. hoe: Output admittance of the transistor in the common-base
configuration. hre: Feedback factor of the transistor in the common-base configuration.
Here's how you can design the CE amplifier:
Step 1: Determine the required current gain (hfe) and input impedance (hie) based on the specifications.
Step 2: Choose a transistor that satisfies the desired hfe and hie values. Consult the transistor datasheet to
obtain these parameters for different transistors.
Step 3: Calculate the feedback factor (hre) using the formula: hre = (1 + hfe) / hfe.
Step 4: Calculate the output admittance (hoe) using the formula: hoe = 1 / (hie * hre).
Step 5: Choose suitable resistor values for the emitter resistance (RE) and collector resistor (Rc) to provide
biasing and stabilize the amplifier.
Step 6: Determine the voltage across the collector resistor (Rc) and emitter resistor (R E) to ensure proper
biasing of the transistor.
Step 7: Calculate the required base current (Ib) using the formula: Ib = (Ic) / ( hfe).
Step 8: Calculate the emitter current (Ie) using the formula: Ie = (1 + hfe) * Ib.
Step 9: Calculate the value of the ac emitter resistor (Re) using the formula: Re = (V T / IE), where VT is the
thermal voltage (approximately 26 mV at room temperature).
Step 10: Calculate the collector resistor (Rc) using the formula: Rc = (Vcc - Vc) / Ic, where Vcc is the
supply voltage and Vc is the voltage across the collector resistor.
Step 11: Calculate the voltage gain (Av) using the formula: Av = -hfe * Rc / Re.
Step 12: Finally, connect the circuit with the calculated resistor values and the transistor that
satisfies the desired hfe and hie parameters.]
2. Calculate the current gain, voltage gain and power gain of CE and CB amplifier with load of
3KΩ and justify which amplifier gain is more than the other. (Analyse), 10 Marks
[Hint:
To calculate the current gain (Ai), voltage gain (Av), and power gain (Ap) of a common-emitter (CE)
and common-base (CB) amplifier with a load of 3KΩ, we'll use the following formulas:
For a common-emitter (CE) amplifier: Ai β, Av -β * (Rc||RL) / re; power gain, Ap = Av * Ai = -β^2
* RL / re
For a common-base (CB) amplifier: Ai 1, Av = gm * (Rc||R L), Ap = Av * Ai = gm * RL
Here, β represents the current gain of the transistor in the CE configuration, R L is the load resistance,
and re is the emitter ac resistance. In the CB configuration, gm represents the transconductance of the
transistor.
To determine which amplifier has a higher gain, we'll compare the absolute values of their voltage
gains (|Av|). Let's calculate the gains for both CE and CB amplifiers:
Common-Emitter (CE) Amplifier: Assuming a typical β value of 100 for a transistor, and re can be
approximated as re = 25 mV / IE (where IE is the dc emitter current):
Ai_CE = β = 100, Av_CE = -β * RL / re, Ap_CE = Av_CE * Ai_CE
Common-Base (CB) Amplifier: For a CB amplifier, gm can be approximated as gm = Ic / VT (where
VT is the thermal voltage or volt equivalent of temperature and Ic is the collector current which is
approx. equal to IE):
Ai_CB = 1, Av_CB = gm * RL, Ap_CB = Av_CB * Ai_CB
By comparing the absolute values of the voltage gains (|Av|) of both amplifiers, we can determine
which one has a higher gain.
Keep in mind that the actual values of β, gm, and re may vary depending on the specific
transistor and operating conditions. These calculations provide a general approach to analyze
and compare the gain of CE and CB amplifiers.]
[Hint:
1. Efficiency Analysis: Evaluate the efficiency of your proposed BTL amplifier circuit. Compare
this efficiency to that of a traditional single-ended amplifier driving the same load resistor RL
.
2. Distortion Minimization: Discuss strategies and modifications in your circuit to minimize
distortion. Explain how these modifications improve the performance of the amplifier.
3. Simulation and Evaluation: Suppose you have access to a circuit simulation software. Describe
the steps you would take to simulate your proposed circuit, including what parameters and
outputs you would evaluate to ensure the design meets the requirements. Discuss how you
would interpret the results of your simulation to further refine the circuit design.
Solution:
Circuit Design:
The proposed BTL (Bridged Tied Load) amplifier circuit includes the following components:
Two identical operational amplifiers A1 and A2 with high gain A.
A phase inverter to invert the input signal for A2 .
Feedback resistors to stabilize the gain and reduce distortion.
Capacitors to filter out any high-frequency noise and stabilize the circuit.
Explanation:
Operational Amplifiers A1 and A2 : Ideal op-amps are chosen for their high gain and linearity.
Phase Inverter: Ensures A2 receives the inverted input signal, crucial for BTL configuration.
Feedback Resistors: Feedback resistors Rf and Rin are used to set the closed-loop gain and improve
linearity, reducing harmonic distortion.
Capacitors: Capacitors C1 and C2 are placed at the input and output stages to filter high-frequency
noise, ensuring the amplifier operates efficiently at low frequencies.
Efficiency Analysis:
4. Design the cascade circuit shown below to meet the following specifications
VCE1= VCE2= 2.5V , VBE= 0.7 V , IC1=IC2= 1mA , and IR1=IR2=IR3=0.10 mA.
(Analyse), 10 Marks
[Hint:
To design the cascade circuit with the given specifications, we can use a combination of two common-
emitter amplifiers. Here's the step-by-step process:
1. Choose transistor parameters: Select transistors with suitable characteristics to meet the
specifications. Let's assume we are using NPN transistors with a forward voltage drop of V BE
= 0.7V.
2. Determine the biasing resistor values: To achieve IC1 = IC2 = 1mA, we can use the current
divider formula. Assuming β (current gain) is sufficiently high, the base current (IB) can be
neglected. Therefore, the collector current (IC) of each transistor is equal to the emitter current
(IE).
Given: IC1 = IC2 = 1mA IR1 = IR2 = IR3 = 0.10mA
Since IE = IC + IR, we can write: IE1 = IC1 + IR1 = 1mA + 0.10mA = 1.10mA IE2 = IC2 + IR2 = 1mA +
0.10mA = 1.10mA
We can set up a v capacitors oltage divider biasing scheme using resistors to achieve the desired
collector currents. Let's assume a supply voltage (VCC) of 5V.
Using Ohm's law, we have: VR1 = (VCC - VCE1 - VBE) = (5V - 2.5V - 0.7V) = 1.8V V_R2 = (VCC - VCE2
- VBE) = (5V - 2.5V - 0.7V) = 1.8V
Applying Ohm's law, we get: R1 = VR1 / IR1 = 1.8V / 0.10mA = 18kΩ R2 = VR2 / IR2 = 1.8V / 0.10mA
= 18kΩ
Note that the biasing resistors R1 and R2 are equal.
3. Design the coupling capacitors: To ensure DC isolation between the amplifier stages, coupling
capacitors are used. Since the emitter current of each stage is the same, we can use identical
coupling .
4. Calculate the output resistor (RC2): The output resistor RC2 is chosen to stabilize the circuit and
provide appropriate voltage gain. The value of RC2 is generally larger than RC1 to achieve a
desired voltage gain.
5. Choose the values of the collector resistors (RC1 and RC2): The collector resistors determine the
voltage gain of each stage. Higher values of RC provide higher voltage gain.
Let's assume a desired voltage gain of Av = 100 for each stage.
Using the formula Av = -RC / re, where re is the emitter resistance, we can calculate the values of R C1
and RC2.
For Av = 100, we have: -RC1 / re1 = -100, -RC2 / re2 = -100
The emitter resistance (re) is given by re = 25mV / IE, where IE is the emitter current.
Therefore, re1 = 25mV / 1.10mA = 22.73Ω (approx.) re2 = 25mV / 1.10mA = 22.73Ω (approx.)
We can choose the collector resistors to be larger than the emitter resistance, such as: R C1 = 10kΩ, RC2
= 10kΩ
6. Finalize the circuit: Connect the components as shown in the diagram, with the appropriate
resistor and capacitor values determined in the previous steps.
Here's a summary of the component values for the cascade circuit:
• Transistor: NPN transistor with VBE = 0.7V
• Biasing resistors: R1 = 18kΩ, R2 = 18kΩ
• Coupling capacitors: Identical capacitors for each stage
• Output resistors: RC1 = 10kΩ, RC2 = 10kΩ]
[Solution:
To determine the bandwidth of the CE amplifier, we need to calculate the lower and upper cutoff
frequencies (f_L and f_H) of the amplifier. The bandwidth (BW) is then given by the difference between
these two frequencies (BW = f_H - f_L).
The lower cutoff frequency (fL) is mainly determined by the capacitors and the resistors connected to
the input side of the amplifier. The upper cutoff frequency (fH) is determined by the capacitors and the
resistors connected to the output side of the amplifier.
The formulas to calculate fL and fH are as follows:
1. Lower cutoff frequency (fL): fL = 1 / (2 * π * R_in * C_in) where R_in = R1 || R2 (parallel
combination of R1 and R2) C_in = C1 || C2 (parallel combination of C1 and C2)
2. Upper cutoff frequency (fH): fH = 1 / (2 * π * (R_out + Reff) * C_out) where R_out = RC, Reff
= (rbb' + (hfe + 1) * rb'e) / (hfe + 1), Cout = CE || Cb'e || Cb'c (parallel combination of CE,
Cb'e, and Cb'c)
Let's plug in the given values and calculate the bandwidth:
Given values: R1 = 100kΩ, R2 = 10kΩ, RC = 9kΩ, RE = 2kΩ, C1 = C2 = 25μF, CE = 50μF,
rbb' = 100Ω, rb'e = 1.1kΩ, hfe = 225, Cb'e = 3pF, Cb'c = 100pF
3. Calculate R_in: R_in = R1 || R2 = (R1 * R2) / (R1 + R2) = (100kΩ * 10kΩ) / (100kΩ + 10kΩ)
= 9.09kΩ
4. Calculate C_in: C_in = C1 || C2 = (C1 * C2) / (C1 + C2) = (25μF * 25μF) / (25μF + 25μF) =
12.5μF
5. Calculate Reff: Reff = (rbb' + (hfe + 1) * rb'e) / (hfe + 1) = (100Ω + (225 + 1) * 1.1kΩ) / (225
+ 1) = 335.6Ω
6. Calculate C_out: C_out = CE || Cb'e || Cb'c = (CE * Cb'e * Cb'c) / (CE * Cb'e + CE * Cb'c +
Cb'e * Cb'c) = (50μF * 3pF * 100pF) / (50μF * 3pF + 50μF * 100pF + 3pF * 100pF) ≈ 2.99pF
7. Calculate fL: fL = 1 / (2 * π * R_in * C_in) = 1 / (2 * π * 9.09kΩ * 12.5μF) ≈ 1.40Hz
8. Calculate fH: fH = 1 / (2 * π * (R_out + Reff) * C_out) = 1 / (2 * π * (9kΩ + 335.6Ω) * 2.99pF)
≈ 1.73MHz
Finally, calculate the bandwidth (BW): BW = fH - fL ≈ 1.73MHz - 1.40Hz ≈ 1.73MHz.
So, the bandwidth of the CE amplifier is approximately 1.73 MHz.]
6. An amplifier circuit requires a regulated 5V dc supply for its load current of 10 mA. The
available dc input voltage is 10V with variation of 2V. Design a suitable regulated power
supply for this amplifier. (Create), 5 Marks
[Solution
To design a Zener voltage regulator that meets the specified requirements, we will select
an appropriate Zener diode and calculate the series resistor needed to regulate the output
voltage to 5V and handle the load current of 10mA. Additionally, we will ensure that the
Zener diode's wattage rating is not exceeded.
Step 1: Choose a Zener diode We need to select a Zener diode that has a breakdown voltage
close to the desired output voltage (5V) and can handle the power dissipation. Let's assume
we choose a Zener diode with a breakdown voltage of 5.1V (a common standard value)
and a power rating of 400mW as specified.
Step 2: Calculate the series resistor (R_S) The series resistor is used to limit the current
flowing through the Zener diode and the load. The formula to calculate the series resistor
is:
RS = (VIN - VZ) / IL
Where: VIN = Input voltage (maximum voltage) = 10V + 2V = 12V (assuming the upper
limit of the input voltage range). VZ = Zener diode voltage = 5.1V. IL = Load current =
10mA = 0.01A.
RS = (12V - 5.1V) / 0.01A RS = 690 ohms (approximately)
Step 3: Check Zener diode power dissipation The power dissipation across the Zener diode
can be calculated using the formula:
PZener = VZ * IL
PZener = 5.1V * 0.01A, PZener = 0.051W (51mW)
Since the calculated power dissipation is less than the Zener's power rating (400mW), the
selected Zener diode can handle the load current without any issues.
Step 4: Choose the nearest standard resistor value In practice, you will use a standard
resistor value for R_S. In this case, you can select the nearest standard resistor value of 680
ohms, which is commonly available.
So, the final design would use a 680-ohm series resistor along with a 5.1V Zener diode to
achieve the desired output voltage of 5V while handling a load current of 10mA and staying
within the specified Zener wattage rating of 400mW.]
7. A system needs to be powered with 9V dc source of max current 100mA. Design a circuit
to supply power with the available domestic ac line. Assume any data required but
reasonable. Provide short circuit protection. (Create), 10 Marks
[Solution:
To design a circuit that supplies 9V DC power from the domestic AC line with short circuit protection,
we can use a step-down transformer, a bridge rectifier, a voltage regulator, and a current-limiting
resistor. The voltage regulator will also act as short circuit protection for the circuit.
Here's the step-by-step explanation of the circuit:
i. Step-down transformer: Use a transformer to step down the domestic AC voltage (usually
120V or 230V) to a lower voltage suitable for rectification and regulation. We'll use a 9V-0V-
9V transformer.
ii. Bridge rectifier: The output of the transformer is AC voltage. We need to convert it to DC
voltage. A bridge rectifier can be used to convert the AC voltage to pulsating DC voltage.
iii. Capacitor filter: Place a capacitor at the output of the bridge rectifier to smoothen the pulsating
DC and convert it into a relatively stable DC voltage.
iv. Voltage regulator: Use a 9V voltage regulator (such as LM7809) to regulate the voltage to a
constant 9V DC.
v. Current-limiting resistor: To provide short circuit protection, we'll add a current-limiting
resistor in series with the output of the voltage regulator. In case of a short circuit, the resistor
will limit the current flow, protecting the circuit from damage.
vi. Output filtering: Add another capacitor at the output of the voltage regulator to further reduce
any remaining ripples and provide a cleaner output.
8. Determine the resistor values for the network of following figure for the indicated
operating point and supply voltage. (Analyse), 5 Marks
[Hint:
]
9. Determine the resistor values for the network of figure for the indicated operating point
and supply voltage. (Analyse), 10 Marks
[Hint:
10. An amplifier has an open circuit voltage gain of 1000, an output resistance of 15Ω and an
input resistance of 7kΩ. It is supplied from a signal source of 10mV rms and internal
resistance 3kΩ. The amplifier feeds a load of 35 Ω. Evaluate the power gain of this
amplifier. (Evaluate), 10 Marks
[Hint
]
11. A system with variation of load current from 100 mA to 500 mA requires a 5V dc supply.
The available dc input voltage is 12V. Design a voltage regulator for this system.
(Create), 10 Marks
[Solution:
12. In the silicon BJT circuit shown below, assume that the emitter area of transistor Q1
is half that of transistor Q2. Find the approximate value of current I 0.
(Evaluate), 5 Marks
[Solution:
13. Assuming the diodes D1 and D2 of the circuit shown in the figure to be ideal ones,
Draw the transfer characteristics. (Evaluate), 5 Marks
[ Hint:
To draw the transfer characteristics of the circuit with ideal diodes D1and D 2, we need to
analyze the behavior of the circuit in different regions of the input voltage Vi.
Circuit Analysis
1. Region 1: Vi<5V
• When Vi is less than 5V, D1 will be reverse-biased (since the voltage across it is
negative), and D2 will be forward-biased (since the voltage across it is positive).
• Therefore, Vo will be clamped at 5V because the ideal diode D2 will conduct and
maintain Vo=5V.
2. Region 2: Vi≥5V
• When Vi is equal to or greater than 5V, D1 becomes forward-biased and will start
conducting.
• At the same time, D2 will be reverse-biased since the voltage across it will be zero or
negative.
• The voltage Vo will be equal to Vi as ideal diode D1 is conducting and the voltage drop
across it is zero.
Transfer Characteristics
]
14. For a sinusoidal input of 12V to the given circuit, what is the minimum value of the
output waveform? Consider diode is ideal. (Evaluate)
15. For the given circuit input is a sinusoidal waveform of 20v p-p, What will be the peak
value of output waveform? (Evaluate)
Module 2
1. For the DC analysis of the Common-Emitter amplifier shown, neglect the base
current and assume that the emitter and collector currents are equal. Given that V T
= 25 mV, VBE = 0.7 V, and the BJT output resistance ro is practically infinite. If the
load resistance is made half then what will be the change in gain? (Analyse)
2. An Amplifier has an open-loop gain of 100 and its lower and upper-cut-off frequency
of 100 Hz and 100 kHz respectively. A feedback network is now connected to the
amplifier. If the feedback factor in the feedback network is changed from 0.99 to 0.78,
how it will affect the overall bandwidth? (Analyse)
3. A cascade connection of two voltage amplifiers A1, and A2 is shown in the figure. The
open-loop gain AVO, input resistance Rin, and output resistance Ro for A1 and A2 are
as follows: A1 : Avo = 10, Rin = 10 kohm, Ro = 1 kohm; A2 : Avo = 5, Rin = 5 kohm,
Ro = 200 kohm.
i) What is the approximate overall voltage gain vout/vin ?
ii) Under which condition the overall gain becomes A1 x A2= 50?
(Evaluate)
4. The circuit in the figure employs positive feedback and is intended to generate
sinusoidal oscillation. If at a frequency f0, the feedback factor β = 1/6 with a phase
difference equal to 0o. then what should be the ratio of R2 and R1 ? (Evaluate)
5. c (Analyse)
[Hint : derive the expression for time period and show that it depends on R2]
[ Hint:
A single-tuned amplifier and a double-tuned amplifier serve distinct purposes in RF and communication
systems. Evaluating their performance requires a deep understanding of their characteristics, benefits, and
limitations.
Single-Tuned Amplifier:
1. Selectivity:
• Definition: Selectivity refers to the ability of the amplifier to select a specific frequency and reject
others.
• Performance: Single-tuned amplifiers have moderate selectivity. They use a single resonant LC
circuit tuned to a specific frequency, which allows them to filter out frequencies that are not close
to the desired frequency. However, the selectivity is limited by the quality factor (Q) of the resonant
circuit.
2. Bandwidth:
• Definition: Bandwidth is the range of frequencies that the amplifier can effectively amplify.
• Performance: The bandwidth of a single-tuned amplifier is inversely related to the quality factor.
A higher Q results in narrower bandwidth, which improves selectivity but limits the range of
frequencies amplified. Conversely, a lower Q increases the bandwidth but reduces selectivity.
3. Gain:
• Definition: Gain is the ratio of the output signal amplitude to the input signal amplitude.
• Performance: The gain of a single-tuned amplifier is typically high at the resonant frequency but
drops off sharply outside the resonant bandwidth. The gain at resonance is determined by the circuit
parameters, including the inductor and capacitor values, as well as the transistor's characteristics.
Double-Tuned Amplifier:
1. Selectivity:
2. Bandwidth:
3. Gain:
• Performance: The gain of a double-tuned amplifier is typically higher and more consistent across
the desired bandwidth compared to a single-tuned amplifier. The dual resonant circuits work
together to maintain a higher gain over a broader range of frequencies, reducing the sharp drop-off
seen in single-tuned amplifiers.
Comparison and Analysis:
• Selectivity: Double-tuned amplifiers are superior to single-tuned amplifiers in terms of selectivity.
The presence of two resonant circuits provides a sharper and more selective response, which is
crucial for applications like RF receivers where filtering out adjacent channel interference is
critical.
• Bandwidth: While single-tuned amplifiers can achieve narrow bandwidths with high Q factors,
double-tuned amplifiers offer a more flexible bandwidth control without sacrificing selectivity.
This makes double-tuned amplifiers more versatile and better suited for applications requiring a
specific bandwidth range.
• Gain: Double-tuned amplifiers generally exhibit higher and more uniform gain across the operating
bandwidth. This is particularly advantageous in communication systems where maintaining a
consistent signal strength is important for reliable data transmission.
]
7. Design a double-tuned amplifier circuit to operate at a center frequency of 10 MHz with a
bandwidth of 500 kHz. Include all necessary calculations, component selections, and a
detailed schematic. Additionally, justify your design choices and discuss how you would
optimize the circuit for maximum gain and stability. (Create)
Component Selection:
• Inductors (L1 and L2): Choose high-Q inductors to minimize losses, such as air-core or ferrite-
core inductors.
• Capacitors (C1 and C2): Use precision capacitors with low temperature coefficients to ensure
stability.
• Coupling Method: For simplicity, use mutual inductance with adjustable spacing to fine-tune
the coupling coefficient.
Justification of Design Choices:
• Inductor and Capacitor Values: The selected values ensure resonance at the desired
frequency and a quality factor that provides the necessary selectivity.
• Coupling Coefficient: By setting k=0.025k = 0.025k=0.025, the desired bandwidth is achieved
while maintaining good selectivity.
• High-Q Components: These reduce losses and ensure the amplifier has a high gain.
Optimization for Maximum Gain and Stability:
8. Maximize Q: Use high-quality components with minimal parasitic elements.
9. Stability: Ensure the circuit is free from parasitic oscillations by properly grounding and shielding
the components.
10. Fine-Tuning: Use variable capacitors or inductors to precisely adjust the resonant frequency and
coupling coefficient.
11. Temperature Stability: Select components with low temperature coefficients to maintain
performance across a range of temperatures.
8. Analyze the impact of varying the quality factor (Q) of the resonant circuit on the
performance of a single-tuned amplifier. Discuss how changes in Q affect the amplifier's
selectivity, bandwidth, and gain, and provide a detailed explanation with appropriate graphs
or equations. (Analyse)
Graph:
The bandwidth decreases as Q increases, illustrating the inverse relationsh
Topic: Operational Amplifier: Ideal OP AMP, CMRR, Open & Closed loop circuits,
importance of feedback loop (positive & negative)
What is an Op amp?
Operational amplifiers (Op-amp) are analog circuit blocks that take differential voltage inputs
and produce single-ended voltage outputs. The input stage of an operational amplifier is usually
a differential amplifier.
It consists of three terminals: two high-impedance inputs and a low-impedance output port. A
minus sign denotes the inverting input (-), while the non-inverting input is denoted by a positive
sign (+).
Block Diagram of Op amp
An ideal and a practical Op-amp are shown in the figure below.
Op-amp is a voltage-amplifying device with differential inputs and normal outputs with external
feedback components via resistors and capacitors. They are high-gain electronic voltage
amplifiers with differential inputs.
Differential Amplifier
The circuit operates from a dual supply +Vcc and -Vee which ensures a constant supply. The
voltage that appears at the output, Vout of the amplifier is the difference between the two input
signals as the two base inputs are in anti-phase with each other.
So as the forward bias of transistor, TR1 is increased, the forward bias of transistor TR2 is
reduced and vice versa. Then if the two transistors are perfectly matched, the current flowing
through the common emitter resistor, Re will remain constant.
Like the input signal, the output signal is also balanced and since the collector voltages either
swing in opposite directions (anti-phase) or in the same direction (in-phase) the output voltage
signal, taken from between the two collectors is, assuming a perfectly balanced circuit the zero
difference between the two collector voltages.
This is known as the Common Mode of Operation with the common mode gain of the amplifier
being the output gain when the input is zero.
Operational Amplifiers also have one output (although there are ones with an additional
differential output) of low impedance that is referenced to a common ground terminal and it should
ignore any common mode signals that is, if an identical signal is applied to both the inverting and
non-inverting inputs there should no change to the output.
However, in real amplifiers there is always some variation, and the ratio of the change to the output
voltage regarding the change in the common mode input voltage is called the Common Mode
Rejection Ratio or CMRR for short.
Operational Amplifiers on their own have a very high open loop DC gain and by applying some
form of Negative Feedback we can produce an operational amplifier circuit that has a very precise
gain characteristic that is dependant only on the feedback used. Note that the term “open loop”
means that there are no feedback components used around the amplifier so the feedback path or
loop is open.
An operational amplifier only responds to the difference between the voltages on its two input
terminals, known commonly as the “Differential Input Voltage” and not to their common
potential. Then if the same voltage potential is applied to both terminals the resultant output will
be zero. An Operational Amplifiers gain is commonly known as the Open Loop Differential
Gain, and is given the symbol (Ao).
Equivalent Circuit of an Ideal Operational Amplifier
From this frequency response curve we can see that the product of the gain against frequency is
constant at any point along the curve. Also that the unity gain (0dB) frequency also determines
the gain of the amplifier at any point along the curve. This constant is generally known as the
Gain Bandwidth Product or GBP. Therefore:
GBP = Gain x Bandwidth = A x BW
For example, from the graph above the gain of the amplifier at 100kHz is given as 20dB or 10,
then the gain bandwidth product is calculated as:
GBP = A x BW = 10 x 100,000Hz = 1,000,000.
Similarly, the operational amplifiers gain at 1kHz = 60dB or 1000, therefore the GBP is given as:
GBP = A x BW = 1,000 x 1,000Hz = 1,000,000. The same!.
The Voltage Gain (AV) of the operational amplifier can be found using the following formula:
and in Decibels or (dB) is given as:
Here we have used the 40dB line as an example. The -3dB or 70.7% of Vmax down point from
the frequency response curve is given as 37dB. Taking a line across until it intersects with the
main GBP curve gives us a frequency point just above the 10kHz line at about 12 to 15kHz. We
can now calculate this more accurately as we already know the GBP of the amplifier, in this
particular case 1MHz.
Circuit diagram symbol for an op amp with inverting (-) and non-inverting (+) inputs.
12. The Current Rule: No current flows into the inputs of the op amp. (I+=I-=0)
13. The Voltage Rule: The output of the op amp attempts to ensure that the voltage
difference between the two inputs is zero (V+=V-)
Consider the inverting op amp circuit shown above. Since the inverting input is tied to ground,
by the Voltage Rule, the non-inverting input must also be at (virtual) ground.
The current flowing through R1 is I=Vin/R1,and since the Current Rule states that the inputs
draw no current, all of that current must then flow through R2.
Since the inverting input is at virtual ground, the output of the inverting op amp is V out=-IR2=-
VinR2/R1.
This makes the gain of the inverting op amp circuit -R2/R1.The gain is negative, meaning the
output is out of phase with the input.
Op amp inverter
An op amp inverter is an inverting buffer constructed with an operational amplifier. An inverting
buffer changes the direction of the signal without amplifying it, so the gain of the circuit is -1.
We can see above that the inverting op amp circuit has a gain of -1 when the two resistors are
equal, so an op amp inverter is an inverting op amp with R1=R2.
Non-inverting Operational Amplifier Configuration
In the previous Inverting Amplifier tutorial, we said that for an ideal op-amp “No current flows
into the input terminal” of the amplifier and that “V1 always equals V2”. This was because the
junction of the input and feedback signal ( V1 ) are at the same potential.
In other words the junction is a “virtual earth” summing point. Because of this virtual earth node
the resistors, Rƒ and R2 form a simple potential divider network across the non-inverting
amplifier with the voltage gain of the circuit being determined by the ratios of R2 and Rƒ as
shown below.
Equivalent Potential Divider Network
Then using the formula to calculate the output voltage of a potential divider network, we can
calculate the closed-loop voltage gain ( AV ) of the Non-inverting Amplifier as follows:
Non-inverting Operational Amplifier Gain
Then the closed loop voltage gain of a Non-inverting Operational Amplifier will be given as:
We can see from the equation above, that the overall closed-loop gain of a non-inverting amplifier
will always be greater but never less than one (unity), it is positive in nature and is determined by
the ratio of the values of Rƒ and R2.
If the value of the feedback resistor Rƒ is zero, the gain of the amplifier will be exactly equal to
one (unity). If resistor R2 is zero the gain will approach infinity, but in practice it will be limited
to the operational amplifiers open-loop differential gain, ( AO ).
We can easily convert an inverting operational amplifier configuration into a non-inverting
amplifier configuration by simply changing the input connections as shown.
In this non-inverting circuit configuration, the input impedance Rin has increased to infinity and
the feedback impedance Rƒ reduced to zero. The output is connected directly back to the negative
inverting input, so the feedback is 100% and Vin is exactly equal to Vout giving it a fixed gain of
1 or unity. As the input voltage Vin is applied to the non-inverting input, the voltage gain of the
amplifier is therefore given as:
Since no current flows into the non-inverting input terminal the input impedance is infinite (ideal
conditions) so zero current will flow through the feedback loop. Thus, any value of resistance may
be placed in the feedback loop without affecting the characteristics of the circuit as no current
flows through it so there is zero voltage drop across it is resulting in zero power loss.
As the input impedance is extremely high, the unity gain buffer (voltage follower) can be used to
provide a large power gain as the extra power comes from the op-amps supply rails and through
the op-amps output to the load and not directly from the input. However, in most real unity gain
buffer circuits there are leakage currents and parasitic capacitances present, so a low value
(typically 1kΩ) resistor is required in the feedback loop to help reduce the effects of these leakage
currents providing stability especially if the operational amplifier is of a current feedback type.
The voltage follower or unity gain buffer is a special and very useful type of non-inverting
amplifier circuit that is commonly used in electronics to isolated circuits from each other
especially in High-order state variable or Sallen-Key type active filters to separate one filter stage
from the other. Typical digital buffer IC’s available are the 74LS125 Quad 3-state buffer or the
more common 74LS244 Octal buffer.
One final thought, the closed loop voltage gain of a voltage follower circuit is “1” or Unity. The
open loop voltage gain of an operational amplifier with no feedback is Infinite. Then by carefully
selecting the feedback components we can control the amount of gain produced by a non-inverting
operational amplifier anywhere from one to infinity.
Thus far we have analyzed an inverting and non-inverting amplifier circuit that has just one input
signal, Vin. In the next tutorial about Operational Amplifiers, we will examine the effect of the
output voltage, Vout by connecting more inputs to the amplifier. This then produces another
common type of operational amplifier circuit called a Summing Amplifier which can be used to
“add” together the voltages present on its inputs.
Assignments:
1. Design the circuit to implement division and square root functions using the log and
anti-log amplifier to implement division and square root functions. BL6, (10 Marks)
Hint: If the two inputs are tied together and fed from a single input, the result will be a squaring
circuit.
Hint:
4. (BL4), 10 Marks
5. Calculate the output voltage, Vout, of the ideal OPAMP as shown in the following figure.
(BL4), 5 Marks
Hint:
Apply KCL at inverting terminal
The input voltage of the above OPAMP is represented by the following graph: (BL5, 10 Marks)
Hint:
V0 = -2Vi + 1
7. In an electronic system it is required to design a signal conditioning circuit with proper gain. The
input signal has a peak-to-peak voltage of 2V. The peak to peak output of the signal conditioning
circuit should have a maximum voltage swing of 12V. Choose appropriate resistance value for the
feedback and input resistor, ensuring that the output voltage does not exceed the op amp maximum
voltage. (BL 4), 10 Marks
Hint: to apply knowledge of voltage divider and relation between feedback and input resistance.
8. An ideal OP-AMP circuit with a sinusoidal input is shown in the figure. The 3 dB frequency is the
frequency at which the magnitude of the voltage gain decreases by 3 dB from the maximum value.
Find out whether the circuit is acting as a LPF or HPF and find out the 3dB cut off frequency? (BL
4), 5 Marks
9. A circuit with an ideal OP-AMP is shown. The Bode plot for the magnitude (in dB) of the gain
transfer function (Av(j𝜔) = Vout(j𝜔)/Vin(j𝜔)) of the circuit is also provided (here, 𝜔 is the angular
frequency in rad/s). Find out the values of R and C. (BL 5), 10 Marks
Hint:
Topic: Applications of Operational Amplifiers: adder, integrator & differentiator,
comparator.
Adder:
An adder is an electronic circuit that produces an output, which is equal to the sum of the applied
inputs. This section discusses the op-amp based adder circuit.
An op-amp based adder produces an output equal to the sum of the input voltages applied at its
inverting terminal. It is also called a summing amplifier, since the output is an amplified one.
The circuit diagram of an op-amp based adder is shown in the following figure −
In the above circuit, the non-inverting input terminal of the op-amp is connected to ground. That
means zero volts are applied at its non-inverting input terminal.
According to the virtual short concept, the voltage at the inverting input terminal of an op-amp
is same as that of the voltage at its non-inverting input terminal. So, the voltage at the inverting
input terminal of the op-amp will be zero volts.
The nodal equation at the inverting input terminal's node is
Therefore, the op-amp based adder circuit discussed above will produce the sum of the two input
voltages v1 and v2, as the output, when all the resistors present in the circuit are of same value.
Note that the output voltage V0 of an adder circuit is having a negative sign, which indicates that
there exists a 1800 phase difference between the input and the output.
Subtractor
A subtractor is an electronic circuit that produces an output, which is equal to the difference of the
applied inputs. This section discusses about the op-amp based subtractor circuit.
An op-amp based subtractor produces an output equal to the difference of the input voltages
applied at its inverting and non-inverting terminals. It is also called as a difference amplifier since
the output is an amplified one.
The circuit diagram of an op-amp based subtractor is shown in the following figure −
As its name implies, the Op-amp Integrator is an operational amplifier circuit that performs the
mathematical operation of Integration, that is we can cause the output to respond to changes in
the input voltage over time as the op-amp integrator produces an output voltage which is
proportional to the integral of the input voltage.
In other words, the magnitude of the output signal is determined by the length of time a voltage is
present at its input as the current through the feedback loop charges or discharges the capacitor as
the required negative feedback occurs through the capacitor.
When a step voltage, Vin is firstly applied to the input of an integrating amplifier, the uncharged
capacitor C has very little resistance and acts a bit like a short circuit allowing maximum current
to flow via the input resistor, Rin as potential difference exists between the two plates. No current
flows into the amplifiers input and point X are a virtual earth resulting in zero output. As the
impedance of the capacitor at this point is very low, the gain ratio of XC/RIN is also very small
giving an overall voltage gain of less than one, (voltage follower circuit).
As the feedback capacitor, C begins to charge up due to the influence of the input voltage, its
impedance Xc slowly increases in proportion to its rate of charge. The capacitor charges up at a
rate determined by the RC time constant, ( τ ) of the series RC network. Negative feedback forces
the op-amp to produce an output voltage that maintains a virtual earth at the op-amp’s inverting
input.
Since the capacitor is connected between the op-amp’s inverting input (which is at virtual ground
potential) and the op-amp’s output (which is now negative), the potential voltage, Vc developed
across the capacitor slowly increases causing the charging current to decrease as the impedance of
the capacitor increases. This results in the ratio of Xc/Rin increasing producing a linearly
increasing ramp output voltage that continues to increase until the capacitor is fully charged.
At this point the capacitor acts as an open circuit, blocking any more flow of DC current. The ratio
of feedback capacitor to input resistor ( XC/RIN ) is now infinite resulting in infinite gain. The result
of this high gain (similar to the op-amps open-loop gain) is that the output of the amplifier goes
into saturation as shown below. (Saturation occurs when the output voltage of the amplifier swings
heavily to one voltage supply rail or the other with little or no control in between).
The rate at which the output voltage increases (the rate of change) is determined by the value of
the resistor and the capacitor, “RC time constant“. By changing this RC time constant value, either
by changing the value of the Capacitor, C or the Resistor, R, the time in which it takes the output
voltage to reach saturation can also be changed for example.
If we apply a constantly changing input signal such as a square wave to the input of an Integrator
Amplifier, then the capacitor will charge and discharge in response to changes in the input signal.
This results in the output signal being that of a sawtooth waveform whose output is affected by the
RC time constant of the resistor/capacitor combination because at higher frequencies, the capacitor
has less time to fully charge. This type of circuit is also known as a Ramp Generator and the
transfer function is given below.
Ramp Generator
Op-amp Differentiator Circuit
The input signal to the differentiator is applied to the capacitor. The capacitor blocks any DC
content so there is no current flow to the amplifier summing point X resulting in zero output
voltage. The capacitor only allows AC type input voltage changes to pass through and whose
frequency is dependent on the rate of change of the input signal.
At low frequencies the reactance of the capacitor is “High” resulting in a low gain ( Rƒ/Xc ) and
low output voltage from the op-amp. At higher frequencies the reactance of the capacitor is much
lower resulting in a higher gain and higher output voltage from the differentiator amplifier.
However, at high frequencies an op-amp differentiator circuit becomes unstable and will start to
oscillate. This is due mainly to the first-order effect, which determines the frequency response of
the op-amp circuit causing a second-order response which, at high frequencies, gives an output
voltage far higher than what would be expected. To avoid this the high frequency gain of the circuit
needs to be reduced by adding an additional small value capacitor across the feedback resistor Rƒ.
Ok, some math’s to explain what’s going on! Since the node voltage of the operational amplifier
at its inverting input terminal is zero, the current, i flowing through the capacitor will be given as:
The charge on the capacitor equals Capacitance times Voltage across the capacitor
Therefore, the output voltage Vout is a constant –Rƒ*C times the derivative of the input voltage
Vin with respect to time. The minus sign (–) indicates a 180o phase shift because the input signal
is connected to the inverting input terminal of the operational amplifier.
One final point to mention, the Op-amp Differentiator circuit in its basic form has two main
disadvantages compared to the previous operational amplifier integrator circuit. One is that it
suffers from instability at high frequencies as mentioned above, and the other is that the capacitive
input makes it very susceptible to random noise signals and any noise or harmonics present in the
source circuit will be amplified more than the input signal itself. This is because the output is
proportional to the input voltage slope, so some means of limiting the bandwidth to achieve closed-
loop stability is required.
Assignments
Q No. Question
1 Analyze the circuit diagram of an op amp configured as an adder. Explain the
function of each resistor and the input voltages' contributions to the output
voltage. [BL4], 5 Marks
5 Design an op amp adder circuit with variable gain coefficients for each input.
Justify your design choices and explain how the adjustable gains can be
beneficial in specific applications. [BL6], 5 Marks
6 Design a multi-stage amplifier circuit using operational amplifiers to achieve a specific
gain of 1000. The input signal is a small sinusoidal signal with a peak amplitude of 1
mV, and the output should be a sinusoidal signal with a peak amplitude of 1 V. Ensure
that the design maintains stability and minimizes noise. Provide a detailed explanation
of your design choices, including the selection of each component and the configuration
of each stage. Additionally, explain how you would test and validate the performance
of your designed circuit in a real-world scenario. (Create), 10 Marks
7
You are given a non-inverting amplifier circuit with an op-amp, a resistor Rf (feedback
resistor), and a resistor Ri (input resistor). The input voltage Vin is applied to the non-
inverting input of the op-amp. Analyze and critically evaluate how changes in the values
of Rf and Ri would affect the gain, bandwidth, and stability of the amplifier. Consider
practical limitations such as the op-amp’s slew rate, bandwidth limitations, and
potential noise issues. Provide a detailed explanation and justify your evaluation with
appropriate theoretical principles.
(Evaluate), 10 Marks
Module 4
1. An astable multi-vibrator circuit using IC 555 timer is shown below. Assume that the
circuit is oscillating steadily. What is the voltage VC across the capacitor? Draw the
waveform. (BTL 4), 5 Marks
2. In the astable multivibrator circuit shown in the figure, find the frequency of oscillation (in
kHz) at the output pin 3. (BTL 4), 5 Marks
3. Design a scheme for an application, where you want the outdoor passage light to turn on at
night when you arrive at the outdoor gate of your house and remain ON for about one minute.
After that time duration it is assumed that you have reached the door of your house and
unlocked it, so the light can be turned off. (BTL 6), 10 Marks
[Hint : The scheme to include sensor to detect darkness (night time), sensor for detecting you
when you arrive at the outdoor gate and an astable multi-vibrator which has an ON time of 1
min. ]
4. Design an astable multivibrator with 555 Timer which has an ON time of 0.6 secs and OFF
time of 0.4 sec. Explain its operation. What modification needs to be done in the circuit to
get equal ON and OFF times. (BTL 5), 10 Marks
[ Hint: Capacitor charging and discharging should happen at the same rate.]
5. Analyze the impact of temperature variations on the timing accuracy of monostable timer
circuits. Explain how temperature compensation techniques can be employed to mitigate
these effects.
(BTL 5), 5 Marks
6. Analyze the operational characteristics of a bistable timer circuit and explain how it can be
used as a flip-flop in digital logic circuits. (BTL 5), 5 Marks
[ Hint: A bistable timer circuit, also known as a flip-flop or a latch, can hold its output in one of
two stable states until a triggering signal is received. This characteristic allows it to be used as a basic
building block for storing and transferring binary information in digital logic
circuits